2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
32 #include "brw_fs_surface_builder.h"
33 #include "brw_vec4_gs_visitor.h"
36 using namespace brw::surface_access
;
39 fs_visitor::emit_nir_code()
41 /* emit the arrays used for inputs and outputs - load/store intrinsics will
42 * be converted to reads/writes of these arrays
47 nir_emit_system_values();
49 /* get the main function and emit it */
50 nir_foreach_overload(nir
, overload
) {
51 assert(strcmp(overload
->function
->name
, "main") == 0);
52 assert(overload
->impl
);
53 nir_emit_impl(overload
->impl
);
58 fs_visitor::nir_setup_inputs()
60 if (stage
!= MESA_SHADER_FRAGMENT
)
63 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
65 nir_foreach_variable(var
, &nir
->inputs
) {
66 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
69 if (var
->data
.location
== VARYING_SLOT_POS
) {
70 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
71 var
->data
.origin_upper_left
);
72 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
75 emit_general_interpolation(input
, var
->name
, var
->type
,
76 (glsl_interp_qualifier
) var
->data
.interpolation
,
77 var
->data
.location
, var
->data
.centroid
,
84 fs_visitor::nir_setup_outputs()
86 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
88 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
90 nir_foreach_variable(var
, &nir
->outputs
) {
91 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
93 int vector_elements
= var
->type
->without_array()->vector_elements
;
96 case MESA_SHADER_VERTEX
:
97 for (unsigned int i
= 0; i
< ALIGN(type_size_scalar(var
->type
), 4) / 4; i
++) {
98 int output
= var
->data
.location
+ i
;
99 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
100 this->output_components
[output
] = vector_elements
;
103 case MESA_SHADER_FRAGMENT
:
104 if (var
->data
.index
> 0) {
105 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
106 assert(var
->data
.index
== 1);
107 this->dual_src_output
= reg
;
108 this->do_dual_src
= true;
109 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
110 /* Writing gl_FragColor outputs to all color regions. */
111 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
112 this->outputs
[i
] = reg
;
113 this->output_components
[i
] = 4;
115 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
116 this->frag_depth
= reg
;
117 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
118 this->sample_mask
= reg
;
120 /* gl_FragData or a user-defined FS output */
121 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
122 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
124 /* General color output. */
125 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
126 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
127 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
128 this->output_components
[output
] = vector_elements
;
133 unreachable("unhandled shader stage");
139 fs_visitor::nir_setup_uniforms()
141 if (dispatch_width
!= 8)
144 uniforms
= nir
->num_uniforms
;
146 nir_foreach_variable(var
, &nir
->uniforms
) {
147 /* UBO's and atomics don't take up space in the uniform file */
148 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
151 if (type_size_scalar(var
->type
) > 0)
152 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
157 emit_system_values_block(nir_block
*block
, void *void_visitor
)
159 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
162 nir_foreach_instr(block
, instr
) {
163 if (instr
->type
!= nir_instr_type_intrinsic
)
166 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
167 switch (intrin
->intrinsic
) {
168 case nir_intrinsic_load_vertex_id
:
169 unreachable("should be lowered by lower_vertex_id().");
171 case nir_intrinsic_load_vertex_id_zero_base
:
172 assert(v
->stage
== MESA_SHADER_VERTEX
);
173 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
174 if (reg
->file
== BAD_FILE
)
175 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
178 case nir_intrinsic_load_base_vertex
:
179 assert(v
->stage
== MESA_SHADER_VERTEX
);
180 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
181 if (reg
->file
== BAD_FILE
)
182 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
185 case nir_intrinsic_load_instance_id
:
186 assert(v
->stage
== MESA_SHADER_VERTEX
);
187 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
188 if (reg
->file
== BAD_FILE
)
189 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
192 case nir_intrinsic_load_invocation_id
:
193 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
194 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
195 if (reg
->file
== BAD_FILE
) {
196 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
197 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
198 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
199 abld
.SHR(iid
, g1
, fs_reg(27u));
204 case nir_intrinsic_load_sample_pos
:
205 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
207 if (reg
->file
== BAD_FILE
)
208 *reg
= *v
->emit_samplepos_setup();
211 case nir_intrinsic_load_sample_id
:
212 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
213 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
214 if (reg
->file
== BAD_FILE
)
215 *reg
= *v
->emit_sampleid_setup();
218 case nir_intrinsic_load_sample_mask_in
:
219 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
220 assert(v
->devinfo
->gen
>= 7);
221 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
222 if (reg
->file
== BAD_FILE
)
223 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
224 BRW_REGISTER_TYPE_D
));
227 case nir_intrinsic_load_local_invocation_id
:
228 assert(v
->stage
== MESA_SHADER_COMPUTE
);
229 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
230 if (reg
->file
== BAD_FILE
)
231 *reg
= *v
->emit_cs_local_invocation_id_setup();
234 case nir_intrinsic_load_work_group_id
:
235 assert(v
->stage
== MESA_SHADER_COMPUTE
);
236 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
237 if (reg
->file
== BAD_FILE
)
238 *reg
= *v
->emit_cs_work_group_id_setup();
250 fs_visitor::nir_emit_system_values()
252 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
253 nir_foreach_overload(nir
, overload
) {
254 assert(strcmp(overload
->function
->name
, "main") == 0);
255 assert(overload
->impl
);
256 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
261 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
263 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
264 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
265 unsigned array_elems
=
266 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
267 unsigned size
= array_elems
* reg
->num_components
;
268 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
271 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
274 nir_emit_cf_list(&impl
->body
);
278 fs_visitor::nir_emit_cf_list(exec_list
*list
)
280 exec_list_validate(list
);
281 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
282 switch (node
->type
) {
284 nir_emit_if(nir_cf_node_as_if(node
));
287 case nir_cf_node_loop
:
288 nir_emit_loop(nir_cf_node_as_loop(node
));
291 case nir_cf_node_block
:
292 nir_emit_block(nir_cf_node_as_block(node
));
296 unreachable("Invalid CFG node block");
302 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
304 /* first, put the condition into f0 */
305 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
306 retype(get_nir_src(if_stmt
->condition
),
307 BRW_REGISTER_TYPE_D
));
308 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
310 bld
.IF(BRW_PREDICATE_NORMAL
);
312 nir_emit_cf_list(&if_stmt
->then_list
);
314 /* note: if the else is empty, dead CF elimination will remove it */
315 bld
.emit(BRW_OPCODE_ELSE
);
317 nir_emit_cf_list(&if_stmt
->else_list
);
319 bld
.emit(BRW_OPCODE_ENDIF
);
323 fs_visitor::nir_emit_loop(nir_loop
*loop
)
325 bld
.emit(BRW_OPCODE_DO
);
327 nir_emit_cf_list(&loop
->body
);
329 bld
.emit(BRW_OPCODE_WHILE
);
333 fs_visitor::nir_emit_block(nir_block
*block
)
335 nir_foreach_instr(block
, instr
) {
336 nir_emit_instr(instr
);
341 fs_visitor::nir_emit_instr(nir_instr
*instr
)
343 const fs_builder abld
= bld
.annotate(NULL
, instr
);
345 switch (instr
->type
) {
346 case nir_instr_type_alu
:
347 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
350 case nir_instr_type_intrinsic
:
351 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
354 case nir_instr_type_tex
:
355 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
358 case nir_instr_type_load_const
:
359 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
362 case nir_instr_type_ssa_undef
:
363 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
366 case nir_instr_type_jump
:
367 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
371 unreachable("unknown instruction type");
376 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
377 const fs_reg
&result
)
379 if (!instr
->src
[0].src
.is_ssa
||
380 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
383 nir_intrinsic_instr
*src0
=
384 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
386 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
389 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
390 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
393 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
394 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
397 fs_reg tmp
= vgrf(glsl_type::int_type
);
399 if (devinfo
->gen
>= 6) {
400 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
401 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
403 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
405 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
406 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
408 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
410 * This negation looks like it's safe in practice, because bits 0:4 will
411 * surely be TRIANGLES
414 if (value1
->f
[0] == -1.0f
) {
418 tmp
.type
= BRW_REGISTER_TYPE_W
;
419 tmp
.subreg_offset
= 2;
422 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
423 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
425 tmp
.type
= BRW_REGISTER_TYPE_D
;
426 tmp
.subreg_offset
= 0;
429 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
430 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
432 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
434 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
435 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
437 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
439 * This negation looks like it's safe in practice, because bits 0:4 will
440 * surely be TRIANGLES
443 if (value1
->f
[0] == -1.0f
) {
447 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
449 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
455 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
457 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
460 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
461 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
464 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
465 op
[i
] = get_nir_src(instr
->src
[i
].src
);
466 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
467 op
[i
].abs
= instr
->src
[i
].abs
;
468 op
[i
].negate
= instr
->src
[i
].negate
;
471 /* We get a bunch of mov's out of the from_ssa pass and they may still
472 * be vectorized. We'll handle them as a special-case. We'll also
473 * handle vecN here because it's basically the same thing.
481 fs_reg temp
= result
;
482 bool need_extra_copy
= false;
483 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
484 if (!instr
->src
[i
].src
.is_ssa
&&
485 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
486 need_extra_copy
= true;
487 temp
= bld
.vgrf(result
.type
, 4);
492 for (unsigned i
= 0; i
< 4; i
++) {
493 if (!(instr
->dest
.write_mask
& (1 << i
)))
496 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
497 inst
= bld
.MOV(offset(temp
, bld
, i
),
498 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
500 inst
= bld
.MOV(offset(temp
, bld
, i
),
501 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
503 inst
->saturate
= instr
->dest
.saturate
;
506 /* In this case the source and destination registers were the same,
507 * so we need to insert an extra set of moves in order to deal with
510 if (need_extra_copy
) {
511 for (unsigned i
= 0; i
< 4; i
++) {
512 if (!(instr
->dest
.write_mask
& (1 << i
)))
515 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
524 /* At this point, we have dealt with any instruction that operates on
525 * more than a single channel. Therefore, we can just adjust the source
526 * and destination registers for that channel and emit the instruction.
528 unsigned channel
= 0;
529 if (nir_op_infos
[instr
->op
].output_size
== 0) {
530 /* Since NIR is doing the scalarizing for us, we should only ever see
531 * vectorized operations with a single channel.
533 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
534 channel
= ffs(instr
->dest
.write_mask
) - 1;
536 result
= offset(result
, bld
, channel
);
539 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
540 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
541 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
547 inst
= bld
.MOV(result
, op
[0]);
548 inst
->saturate
= instr
->dest
.saturate
;
553 bld
.MOV(result
, op
[0]);
557 /* AND(val, 0x80000000) gives the sign bit.
559 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
562 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
564 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
565 op
[0].type
= BRW_REGISTER_TYPE_UD
;
566 result
.type
= BRW_REGISTER_TYPE_UD
;
567 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
569 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
570 inst
->predicate
= BRW_PREDICATE_NORMAL
;
571 if (instr
->dest
.saturate
) {
572 inst
= bld
.MOV(result
, result
);
573 inst
->saturate
= true;
579 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
580 * -> non-negative val generates 0x00000000.
581 * Predicated OR sets 1 if val is positive.
583 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
584 bld
.ASR(result
, op
[0], fs_reg(31));
585 inst
= bld
.OR(result
, result
, fs_reg(1));
586 inst
->predicate
= BRW_PREDICATE_NORMAL
;
590 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
591 inst
->saturate
= instr
->dest
.saturate
;
595 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
596 inst
->saturate
= instr
->dest
.saturate
;
600 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
601 inst
->saturate
= instr
->dest
.saturate
;
605 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
606 inst
->saturate
= instr
->dest
.saturate
;
610 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
611 inst
->saturate
= instr
->dest
.saturate
;
615 if (fs_key
->high_quality_derivatives
) {
616 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
618 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
620 inst
->saturate
= instr
->dest
.saturate
;
622 case nir_op_fddx_fine
:
623 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
624 inst
->saturate
= instr
->dest
.saturate
;
626 case nir_op_fddx_coarse
:
627 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
628 inst
->saturate
= instr
->dest
.saturate
;
631 if (fs_key
->high_quality_derivatives
) {
632 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
633 fs_reg(fs_key
->render_to_fbo
));
635 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
636 fs_reg(fs_key
->render_to_fbo
));
638 inst
->saturate
= instr
->dest
.saturate
;
640 case nir_op_fddy_fine
:
641 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
642 fs_reg(fs_key
->render_to_fbo
));
643 inst
->saturate
= instr
->dest
.saturate
;
645 case nir_op_fddy_coarse
:
646 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
647 fs_reg(fs_key
->render_to_fbo
));
648 inst
->saturate
= instr
->dest
.saturate
;
653 inst
= bld
.ADD(result
, op
[0], op
[1]);
654 inst
->saturate
= instr
->dest
.saturate
;
658 inst
= bld
.MUL(result
, op
[0], op
[1]);
659 inst
->saturate
= instr
->dest
.saturate
;
663 bld
.MUL(result
, op
[0], op
[1]);
666 case nir_op_imul_high
:
667 case nir_op_umul_high
:
668 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
673 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
676 case nir_op_uadd_carry
:
677 unreachable("Should have been lowered by carry_to_arith().");
679 case nir_op_usub_borrow
:
680 unreachable("Should have been lowered by borrow_to_arith().");
683 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
689 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
695 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
700 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
705 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
709 if (devinfo
->gen
>= 8) {
710 op
[0] = resolve_source_modifiers(op
[0]);
712 bld
.NOT(result
, op
[0]);
715 if (devinfo
->gen
>= 8) {
716 op
[0] = resolve_source_modifiers(op
[0]);
717 op
[1] = resolve_source_modifiers(op
[1]);
719 bld
.XOR(result
, op
[0], op
[1]);
722 if (devinfo
->gen
>= 8) {
723 op
[0] = resolve_source_modifiers(op
[0]);
724 op
[1] = resolve_source_modifiers(op
[1]);
726 bld
.OR(result
, op
[0], op
[1]);
729 if (devinfo
->gen
>= 8) {
730 op
[0] = resolve_source_modifiers(op
[0]);
731 op
[1] = resolve_source_modifiers(op
[1]);
733 bld
.AND(result
, op
[0], op
[1]);
745 case nir_op_ball_fequal2
:
746 case nir_op_ball_iequal2
:
747 case nir_op_ball_fequal3
:
748 case nir_op_ball_iequal3
:
749 case nir_op_ball_fequal4
:
750 case nir_op_ball_iequal4
:
751 case nir_op_bany_fnequal2
:
752 case nir_op_bany_inequal2
:
753 case nir_op_bany_fnequal3
:
754 case nir_op_bany_inequal3
:
755 case nir_op_bany_fnequal4
:
756 case nir_op_bany_inequal4
:
757 unreachable("Lowered by nir_lower_alu_reductions");
759 case nir_op_fnoise1_1
:
760 case nir_op_fnoise1_2
:
761 case nir_op_fnoise1_3
:
762 case nir_op_fnoise1_4
:
763 case nir_op_fnoise2_1
:
764 case nir_op_fnoise2_2
:
765 case nir_op_fnoise2_3
:
766 case nir_op_fnoise2_4
:
767 case nir_op_fnoise3_1
:
768 case nir_op_fnoise3_2
:
769 case nir_op_fnoise3_3
:
770 case nir_op_fnoise3_4
:
771 case nir_op_fnoise4_1
:
772 case nir_op_fnoise4_2
:
773 case nir_op_fnoise4_3
:
774 case nir_op_fnoise4_4
:
775 unreachable("not reached: should be handled by lower_noise");
778 unreachable("not reached: should be handled by ldexp_to_arith()");
781 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
782 inst
->saturate
= instr
->dest
.saturate
;
786 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
787 inst
->saturate
= instr
->dest
.saturate
;
792 bld
.MOV(result
, negate(op
[0]));
796 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
799 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
803 inst
= bld
.RNDZ(result
, op
[0]);
804 inst
->saturate
= instr
->dest
.saturate
;
808 op
[0].negate
= !op
[0].negate
;
809 fs_reg temp
= vgrf(glsl_type::float_type
);
810 bld
.RNDD(temp
, op
[0]);
812 inst
= bld
.MOV(result
, temp
);
813 inst
->saturate
= instr
->dest
.saturate
;
817 inst
= bld
.RNDD(result
, op
[0]);
818 inst
->saturate
= instr
->dest
.saturate
;
821 inst
= bld
.FRC(result
, op
[0]);
822 inst
->saturate
= instr
->dest
.saturate
;
824 case nir_op_fround_even
:
825 inst
= bld
.RNDE(result
, op
[0]);
826 inst
->saturate
= instr
->dest
.saturate
;
832 if (devinfo
->gen
>= 6) {
833 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
834 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
836 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
837 inst
= bld
.SEL(result
, op
[0], op
[1]);
838 inst
->predicate
= BRW_PREDICATE_NORMAL
;
840 inst
->saturate
= instr
->dest
.saturate
;
846 if (devinfo
->gen
>= 6) {
847 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
848 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
850 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
851 inst
= bld
.SEL(result
, op
[0], op
[1]);
852 inst
->predicate
= BRW_PREDICATE_NORMAL
;
854 inst
->saturate
= instr
->dest
.saturate
;
857 case nir_op_pack_snorm_2x16
:
858 case nir_op_pack_snorm_4x8
:
859 case nir_op_pack_unorm_2x16
:
860 case nir_op_pack_unorm_4x8
:
861 case nir_op_unpack_snorm_2x16
:
862 case nir_op_unpack_snorm_4x8
:
863 case nir_op_unpack_unorm_2x16
:
864 case nir_op_unpack_unorm_4x8
:
865 case nir_op_unpack_half_2x16
:
866 case nir_op_pack_half_2x16
:
867 unreachable("not reached: should be handled by lower_packing_builtins");
869 case nir_op_unpack_half_2x16_split_x
:
870 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
873 case nir_op_unpack_half_2x16_split_y
:
874 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
875 inst
->saturate
= instr
->dest
.saturate
;
879 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
880 inst
->saturate
= instr
->dest
.saturate
;
883 case nir_op_bitfield_reverse
:
884 bld
.BFREV(result
, op
[0]);
887 case nir_op_bit_count
:
888 bld
.CBIT(result
, op
[0]);
891 case nir_op_ufind_msb
:
892 case nir_op_ifind_msb
: {
893 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
895 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
896 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
897 * subtract the result from 31 to convert the MSB count into an LSB count.
900 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
901 fs_reg
neg_result(result
);
902 neg_result
.negate
= true;
903 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
904 inst
->predicate
= BRW_PREDICATE_NORMAL
;
908 case nir_op_find_lsb
:
909 bld
.FBL(result
, op
[0]);
912 case nir_op_ubitfield_extract
:
913 case nir_op_ibitfield_extract
:
914 bld
.BFE(result
, op
[2], op
[1], op
[0]);
917 bld
.BFI1(result
, op
[0], op
[1]);
920 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
923 case nir_op_bitfield_insert
:
924 unreachable("not reached: should be handled by "
925 "lower_instructions::bitfield_insert_to_bfm_bfi");
928 bld
.SHL(result
, op
[0], op
[1]);
931 bld
.ASR(result
, op
[0], op
[1]);
934 bld
.SHR(result
, op
[0], op
[1]);
937 case nir_op_pack_half_2x16_split
:
938 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
942 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
947 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
948 inst
->saturate
= instr
->dest
.saturate
;
952 if (optimize_frontfacing_ternary(instr
, result
))
955 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
956 inst
= bld
.SEL(result
, op
[1], op
[2]);
957 inst
->predicate
= BRW_PREDICATE_NORMAL
;
961 unreachable("unhandled instruction");
964 /* If we need to do a boolean resolve, replace the result with -(x & 1)
965 * to sign extend the low bit to 0/~0
967 if (devinfo
->gen
<= 5 &&
968 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
969 fs_reg masked
= vgrf(glsl_type::int_type
);
970 bld
.AND(masked
, result
, fs_reg(1));
971 masked
.negate
= true;
972 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
977 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
978 nir_load_const_instr
*instr
)
980 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
982 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
983 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
985 nir_ssa_values
[instr
->def
.index
] = reg
;
989 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
991 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
992 instr
->def
.num_components
);
996 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
997 unsigned base_offset
, nir_src
*indirect
)
1001 assert(!nir_reg
->is_global
);
1003 reg
= v
->nir_locals
[nir_reg
->index
];
1005 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1007 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1009 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1010 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1011 fs_reg(multiplier
));
1018 fs_visitor::get_nir_src(nir_src src
)
1022 reg
= nir_ssa_values
[src
.ssa
->index
];
1024 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1028 /* to avoid floating-point denorm flushing problems, set the type by
1029 * default to D - instructions that need floating point semantics will set
1030 * this to F if they need to
1032 return retype(reg
, BRW_REGISTER_TYPE_D
);
1036 fs_visitor::get_nir_dest(nir_dest dest
)
1039 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1040 dest
.ssa
.num_components
);
1041 return nir_ssa_values
[dest
.ssa
.index
];
1044 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1049 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1051 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1052 BRW_REGISTER_TYPE_UD
);
1054 if (deref
->deref
.child
) {
1055 const nir_deref_array
*deref_array
=
1056 nir_deref_as_array(deref
->deref
.child
);
1057 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1058 deref_array
->deref
.child
== NULL
);
1059 const unsigned size
= glsl_get_length(deref
->var
->type
);
1060 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1062 image
= offset(image
, bld
, base
* BRW_IMAGE_PARAM_SIZE
);
1064 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1065 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1067 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1068 /* IVB hangs when trying to access an invalid surface index with
1069 * the dataport. According to the spec "if the index used to
1070 * select an individual element is negative or greater than or
1071 * equal to the size of the array, the results of the operation
1072 * are undefined but may not lead to termination" -- which is one
1073 * of the possible outcomes of the hang. Clamp the index to
1074 * prevent access outside of the array bounds.
1076 bld
.emit_minmax(*tmp
, retype(get_nir_src(deref_array
->indirect
),
1077 BRW_REGISTER_TYPE_UD
),
1078 fs_reg(size
- base
- 1), BRW_CONDITIONAL_L
);
1080 bld
.MOV(*tmp
, get_nir_src(deref_array
->indirect
));
1083 bld
.MUL(*tmp
, *tmp
, fs_reg(BRW_IMAGE_PARAM_SIZE
));
1084 image
.reladdr
= tmp
;
1092 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1095 for (unsigned i
= 0; i
< 4; i
++) {
1096 if (!((wr_mask
>> i
) & 1))
1099 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1100 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1101 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1102 if (new_inst
->src
[j
].file
== GRF
)
1103 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1110 * Get the matching channel register datatype for an image intrinsic of the
1111 * specified GLSL image type.
1114 get_image_base_type(const glsl_type
*type
)
1116 switch ((glsl_base_type
)type
->sampler_type
) {
1117 case GLSL_TYPE_UINT
:
1118 return BRW_REGISTER_TYPE_UD
;
1120 return BRW_REGISTER_TYPE_D
;
1121 case GLSL_TYPE_FLOAT
:
1122 return BRW_REGISTER_TYPE_F
;
1124 unreachable("Not reached.");
1129 * Get the appropriate atomic op for an image atomic intrinsic.
1132 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1135 case nir_intrinsic_image_atomic_add
:
1137 case nir_intrinsic_image_atomic_min
:
1138 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1139 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1140 case nir_intrinsic_image_atomic_max
:
1141 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1142 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1143 case nir_intrinsic_image_atomic_and
:
1145 case nir_intrinsic_image_atomic_or
:
1147 case nir_intrinsic_image_atomic_xor
:
1149 case nir_intrinsic_image_atomic_exchange
:
1151 case nir_intrinsic_image_atomic_comp_swap
:
1152 return BRW_AOP_CMPWR
;
1154 unreachable("Not reachable.");
1159 emit_pixel_interpolater_send(const fs_builder
&bld
,
1164 glsl_interp_qualifier interpolation
)
1170 if (src
.file
== BAD_FILE
) {
1172 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1176 mlen
= 2 * bld
.dispatch_width() / 8;
1179 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1181 /* 2 floats per slot returned */
1182 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1183 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1189 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1192 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1193 dest
= get_nir_dest(instr
->dest
);
1195 bool has_indirect
= false;
1197 switch (instr
->intrinsic
) {
1198 case nir_intrinsic_discard
:
1199 case nir_intrinsic_discard_if
: {
1200 /* We track our discarded pixels in f0.1. By predicating on it, we can
1201 * update just the flag bits that aren't yet discarded. If there's no
1202 * condition, we emit a CMP of g0 != g0, so all currently executing
1203 * channels will get turned off.
1206 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1207 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1208 fs_reg(0), BRW_CONDITIONAL_Z
);
1210 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1211 BRW_REGISTER_TYPE_UW
));
1212 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1214 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1215 cmp
->flag_subreg
= 1;
1217 if (devinfo
->gen
>= 6) {
1218 emit_discard_jump();
1223 case nir_intrinsic_atomic_counter_inc
:
1224 case nir_intrinsic_atomic_counter_dec
:
1225 case nir_intrinsic_atomic_counter_read
: {
1226 using namespace surface_access
;
1228 /* Get the arguments of the atomic intrinsic. */
1229 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1230 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1231 instr
->const_index
[0]);
1234 /* Emit a surface read or atomic op. */
1235 switch (instr
->intrinsic
) {
1236 case nir_intrinsic_atomic_counter_read
:
1237 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1240 case nir_intrinsic_atomic_counter_inc
:
1241 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1242 fs_reg(), 1, 1, BRW_AOP_INC
);
1245 case nir_intrinsic_atomic_counter_dec
:
1246 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1247 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1251 unreachable("Unreachable");
1254 /* Assign the result. */
1255 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1257 /* Mark the surface as used. */
1258 brw_mark_surface_used(stage_prog_data
, surface
);
1262 case nir_intrinsic_image_load
:
1263 case nir_intrinsic_image_store
:
1264 case nir_intrinsic_image_atomic_add
:
1265 case nir_intrinsic_image_atomic_min
:
1266 case nir_intrinsic_image_atomic_max
:
1267 case nir_intrinsic_image_atomic_and
:
1268 case nir_intrinsic_image_atomic_or
:
1269 case nir_intrinsic_image_atomic_xor
:
1270 case nir_intrinsic_image_atomic_exchange
:
1271 case nir_intrinsic_image_atomic_comp_swap
: {
1272 using namespace image_access
;
1274 /* Get the referenced image variable and type. */
1275 const nir_variable
*var
= instr
->variables
[0]->var
;
1276 const glsl_type
*type
= var
->type
->without_array();
1277 const brw_reg_type base_type
= get_image_base_type(type
);
1279 /* Get some metadata from the image intrinsic. */
1280 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1281 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
1282 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
1283 const mesa_format format
=
1284 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
1285 _mesa_get_shader_image_format(var
->data
.image
.format
));
1287 /* Get the arguments of the image intrinsic. */
1288 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1289 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
1290 BRW_REGISTER_TYPE_UD
);
1291 const fs_reg src0
= (info
->num_srcs
>= 3 ?
1292 retype(get_nir_src(instr
->src
[2]), base_type
) :
1294 const fs_reg src1
= (info
->num_srcs
>= 4 ?
1295 retype(get_nir_src(instr
->src
[3]), base_type
) :
1299 /* Emit an image load, store or atomic op. */
1300 if (instr
->intrinsic
== nir_intrinsic_image_load
)
1301 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
1303 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
1304 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
1307 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
1308 surf_dims
, arr_dims
, info
->dest_components
,
1309 get_image_atomic_op(instr
->intrinsic
, type
));
1311 /* Assign the result. */
1312 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
1313 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
1314 offset(tmp
, bld
, c
));
1318 case nir_intrinsic_memory_barrier
: {
1319 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1320 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1325 case nir_intrinsic_image_size
: {
1326 /* Get the referenced image variable and type. */
1327 const nir_variable
*var
= instr
->variables
[0]->var
;
1328 const glsl_type
*type
= var
->type
->without_array();
1330 /* Get the size of the image. */
1331 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1332 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
1334 /* For 1DArray image types, the array index is stored in the Z component.
1335 * Fix this by swizzling the Z component to the Y component.
1337 const bool is_1d_array_image
=
1338 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
1339 type
->sampler_array
;
1341 /* For CubeArray images, we should count the number of cubes instead
1342 * of the number of faces. Fix it by dividing the (Z component) by 6.
1344 const bool is_cube_array_image
=
1345 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1346 type
->sampler_array
;
1348 /* Copy all the components. */
1349 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1350 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
1351 if ((int)c
>= type
->coordinate_components()) {
1352 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1354 } else if (c
== 1 && is_1d_array_image
) {
1355 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1356 offset(size
, bld
, 2));
1357 } else if (c
== 2 && is_cube_array_image
) {
1358 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
1359 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1360 offset(size
, bld
, c
), fs_reg(6));
1362 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1363 offset(size
, bld
, c
));
1370 case nir_intrinsic_image_samples
:
1371 /* The driver does not support multi-sampled images. */
1372 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), fs_reg(1));
1375 case nir_intrinsic_load_front_face
:
1376 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1377 *emit_frontfacing_interpolation());
1380 case nir_intrinsic_load_vertex_id
:
1381 unreachable("should be lowered by lower_vertex_id()");
1383 case nir_intrinsic_load_primitive_id
:
1384 assert(stage
== MESA_SHADER_GEOMETRY
);
1385 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1386 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1387 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1390 case nir_intrinsic_load_vertex_id_zero_base
:
1391 case nir_intrinsic_load_base_vertex
:
1392 case nir_intrinsic_load_instance_id
:
1393 case nir_intrinsic_load_invocation_id
:
1394 case nir_intrinsic_load_sample_mask_in
:
1395 case nir_intrinsic_load_sample_id
: {
1396 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1397 fs_reg val
= nir_system_values
[sv
];
1398 assert(val
.file
!= BAD_FILE
);
1399 dest
.type
= val
.type
;
1404 case nir_intrinsic_load_sample_pos
: {
1405 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1406 assert(sample_pos
.file
!= BAD_FILE
);
1407 dest
.type
= sample_pos
.type
;
1408 bld
.MOV(dest
, sample_pos
);
1409 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1413 case nir_intrinsic_load_uniform_indirect
:
1414 has_indirect
= true;
1416 case nir_intrinsic_load_uniform
: {
1417 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
1418 uniform_reg
.reg_offset
= instr
->const_index
[1];
1420 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1421 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
1423 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1426 dest
= offset(dest
, bld
, 1);
1431 case nir_intrinsic_load_ubo_indirect
:
1432 has_indirect
= true;
1434 case nir_intrinsic_load_ubo
: {
1435 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1439 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1442 /* The block index is not a constant. Evaluate the index expression
1443 * per-channel and add the base UBO index; we have to select a value
1444 * from any live channel.
1446 surf_index
= vgrf(glsl_type::uint_type
);
1447 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1448 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1449 surf_index
= bld
.emit_uniformize(surf_index
);
1451 /* Assume this may touch any UBO. It would be nice to provide
1452 * a tighter bound, but the array information is already lowered away.
1454 brw_mark_surface_used(prog_data
,
1455 stage_prog_data
->binding_table
.ubo_start
+
1456 nir
->info
.num_ubos
- 1);
1460 /* Turn the byte offset into a dword offset. */
1461 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1462 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1463 BRW_REGISTER_TYPE_D
),
1466 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1467 for (int i
= 0; i
< instr
->num_components
; i
++)
1468 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1469 base_offset
, vec4_offset
+ i
);
1471 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1472 packed_consts
.type
= dest
.type
;
1474 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1475 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1476 surf_index
, const_offset_reg
);
1478 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1479 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1481 /* The std140 packing rules don't allow vectors to cross 16-byte
1482 * boundaries, and a reg is 32 bytes.
1484 assert(packed_consts
.subreg_offset
< 32);
1486 bld
.MOV(dest
, packed_consts
);
1487 dest
= offset(dest
, bld
, 1);
1493 case nir_intrinsic_load_ssbo_indirect
:
1494 has_indirect
= true;
1496 case nir_intrinsic_load_ssbo
: {
1497 assert(devinfo
->gen
>= 7);
1499 nir_const_value
*const_uniform_block
=
1500 nir_src_as_const_value(instr
->src
[0]);
1503 if (const_uniform_block
) {
1504 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
1505 const_uniform_block
->u
[0];
1506 surf_index
= fs_reg(index
);
1507 brw_mark_surface_used(prog_data
, index
);
1509 surf_index
= vgrf(glsl_type::uint_type
);
1510 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1511 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1512 surf_index
= bld
.emit_uniformize(surf_index
);
1514 /* Assume this may touch any UBO. It would be nice to provide
1515 * a tighter bound, but the array information is already lowered away.
1517 brw_mark_surface_used(prog_data
,
1518 stage_prog_data
->binding_table
.ssbo_start
+
1519 nir
->info
.num_ssbos
- 1);
1522 /* Get the offset to read from */
1523 fs_reg offset_reg
= vgrf(glsl_type::uint_type
);
1524 unsigned const_offset_bytes
= 0;
1526 bld
.MOV(offset_reg
, get_nir_src(instr
->src
[1]));
1528 const_offset_bytes
= instr
->const_index
[0];
1529 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1532 /* Read the vector */
1533 for (int i
= 0; i
< instr
->num_components
; i
++) {
1534 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
1535 1 /* dims */, 1 /* size */,
1536 BRW_PREDICATE_NONE
);
1537 read_result
.type
= dest
.type
;
1538 bld
.MOV(dest
, read_result
);
1539 dest
= offset(dest
, bld
, 1);
1541 /* Vector components are stored contiguous in memory */
1542 if (i
< instr
->num_components
) {
1543 if (!has_indirect
) {
1544 const_offset_bytes
+= 4;
1545 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1547 bld
.ADD(offset_reg
, offset_reg
, brw_imm_ud(4));
1555 case nir_intrinsic_load_input_indirect
:
1556 has_indirect
= true;
1558 case nir_intrinsic_load_input
: {
1560 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1562 if (stage
== MESA_SHADER_VERTEX
) {
1563 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
1565 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1566 instr
->const_index
[0] + index
);
1569 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1573 dest
= offset(dest
, bld
, 1);
1578 /* Handle ARB_gpu_shader5 interpolation intrinsics
1580 * It's worth a quick word of explanation as to why we handle the full
1581 * variable-based interpolation intrinsic rather than a lowered version
1582 * with like we do for other inputs. We have to do that because the way
1583 * we set up inputs doesn't allow us to use the already setup inputs for
1584 * interpolation. At the beginning of the shader, we go through all of
1585 * the input variables and do the initial interpolation and put it in
1586 * the nir_inputs array based on its location as determined in
1587 * nir_lower_io. If the input isn't used, dead code cleans up and
1588 * everything works fine. However, when we get to the ARB_gpu_shader5
1589 * interpolation intrinsics, we need to reinterpolate the input
1590 * differently. If we used an intrinsic that just had an index it would
1591 * only give us the offset into the nir_inputs array. However, this is
1592 * useless because that value is post-interpolation and we need
1593 * pre-interpolation. In order to get the actual location of the bits
1594 * we get from the vertex fetching hardware, we need the variable.
1596 case nir_intrinsic_interp_var_at_centroid
:
1597 case nir_intrinsic_interp_var_at_sample
:
1598 case nir_intrinsic_interp_var_at_offset
: {
1599 assert(stage
== MESA_SHADER_FRAGMENT
);
1601 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1603 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1604 const glsl_interp_qualifier interpolation
=
1605 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1607 switch (instr
->intrinsic
) {
1608 case nir_intrinsic_interp_var_at_centroid
:
1609 emit_pixel_interpolater_send(bld
,
1610 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1617 case nir_intrinsic_interp_var_at_sample
: {
1618 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1621 unsigned msg_data
= const_sample
->i
[0] << 4;
1623 emit_pixel_interpolater_send(bld
,
1624 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1630 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1631 BRW_REGISTER_TYPE_UD
);
1633 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1634 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1635 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1636 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1637 emit_pixel_interpolater_send(bld
,
1638 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1644 /* Make a loop that sends a message to the pixel interpolater
1645 * for the sample number in each live channel. If there are
1646 * multiple channels with the same sample number then these
1647 * will be handled simultaneously with a single interation of
1650 bld
.emit(BRW_OPCODE_DO
);
1652 /* Get the next live sample number into sample_id_reg */
1653 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1655 /* Set the flag register so that we can perform the send
1656 * message on all channels that have the same sample number
1658 bld
.CMP(bld
.null_reg_ud(),
1659 sample_src
, sample_id
,
1660 BRW_CONDITIONAL_EQ
);
1661 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1662 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1664 emit_pixel_interpolater_send(bld
,
1665 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1670 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1672 /* Continue the loop if there are any live channels left */
1673 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1675 bld
.emit(BRW_OPCODE_WHILE
));
1682 case nir_intrinsic_interp_var_at_offset
: {
1683 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1686 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1687 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1689 emit_pixel_interpolater_send(bld
,
1690 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1693 fs_reg(off_x
| (off_y
<< 4)),
1696 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1697 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1698 BRW_REGISTER_TYPE_F
);
1699 for (int i
= 0; i
< 2; i
++) {
1700 fs_reg temp
= vgrf(glsl_type::float_type
);
1701 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1702 fs_reg itemp
= vgrf(glsl_type::int_type
);
1703 bld
.MOV(itemp
, temp
); /* float to int */
1705 /* Clamp the upper end of the range to +7/16.
1706 * ARB_gpu_shader5 requires that we support a maximum offset
1707 * of +0.5, which isn't representable in a S0.4 value -- if
1708 * we didn't clamp it, we'd end up with -8/16, which is the
1709 * opposite of what the shader author wanted.
1711 * This is legal due to ARB_gpu_shader5's quantization
1714 * "Not all values of <offset> may be supported; x and y
1715 * offsets may be rounded to fixed-point values with the
1716 * number of fraction bits given by the
1717 * implementation-dependent constant
1718 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1720 set_condmod(BRW_CONDITIONAL_L
,
1721 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1724 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
1725 emit_pixel_interpolater_send(bld
,
1736 unreachable("Invalid intrinsic");
1739 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1740 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1741 src
.type
= dest
.type
;
1743 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1744 dest
= offset(dest
, bld
, 1);
1749 case nir_intrinsic_store_ssbo_indirect
:
1750 has_indirect
= true;
1752 case nir_intrinsic_store_ssbo
: {
1753 assert(devinfo
->gen
>= 7);
1757 nir_const_value
*const_uniform_block
=
1758 nir_src_as_const_value(instr
->src
[1]);
1759 if (const_uniform_block
) {
1760 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
1761 const_uniform_block
->u
[0];
1762 surf_index
= fs_reg(index
);
1763 brw_mark_surface_used(prog_data
, index
);
1765 surf_index
= vgrf(glsl_type::uint_type
);
1766 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
1767 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1768 surf_index
= bld
.emit_uniformize(surf_index
);
1770 brw_mark_surface_used(prog_data
,
1771 stage_prog_data
->binding_table
.ssbo_start
+
1772 nir
->info
.num_ssbos
- 1);
1776 fs_reg offset_reg
= vgrf(glsl_type::uint_type
);
1777 unsigned const_offset_bytes
= 0;
1779 bld
.MOV(offset_reg
, get_nir_src(instr
->src
[2]));
1781 const_offset_bytes
= instr
->const_index
[0];
1782 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1786 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
1789 unsigned writemask
= instr
->const_index
[1];
1791 /* Write each component present in the writemask */
1792 unsigned skipped_channels
= 0;
1793 for (int i
= 0; i
< instr
->num_components
; i
++) {
1794 int component_mask
= 1 << i
;
1795 if (writemask
& component_mask
) {
1796 if (skipped_channels
) {
1797 if (!has_indirect
) {
1798 const_offset_bytes
+= 4 * skipped_channels
;
1799 bld
.MOV(offset_reg
, fs_reg(const_offset_bytes
));
1801 bld
.ADD(offset_reg
, offset_reg
,
1802 brw_imm_ud(4 * skipped_channels
));
1804 skipped_channels
= 0;
1807 emit_untyped_write(bld
, surf_index
, offset_reg
,
1808 offset(val_reg
, bld
, i
),
1809 1 /* dims */, 1 /* size */,
1810 BRW_PREDICATE_NONE
);
1818 case nir_intrinsic_store_output_indirect
:
1819 has_indirect
= true;
1821 case nir_intrinsic_store_output
: {
1822 fs_reg src
= get_nir_src(instr
->src
[0]);
1824 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1825 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1826 instr
->const_index
[0] + index
);
1828 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1830 bld
.MOV(new_dest
, src
);
1831 src
= offset(src
, bld
, 1);
1836 case nir_intrinsic_barrier
:
1838 if (stage
== MESA_SHADER_COMPUTE
)
1839 ((struct brw_cs_prog_data
*) prog_data
)->uses_barrier
= true;
1842 case nir_intrinsic_load_local_invocation_id
:
1843 case nir_intrinsic_load_work_group_id
: {
1844 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1845 fs_reg val
= nir_system_values
[sv
];
1846 assert(val
.file
!= BAD_FILE
);
1847 dest
.type
= val
.type
;
1848 for (unsigned i
= 0; i
< 3; i
++)
1849 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
1853 case nir_intrinsic_ssbo_atomic_add
:
1854 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
1856 case nir_intrinsic_ssbo_atomic_imin
:
1857 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
1859 case nir_intrinsic_ssbo_atomic_umin
:
1860 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
1862 case nir_intrinsic_ssbo_atomic_imax
:
1863 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
1865 case nir_intrinsic_ssbo_atomic_umax
:
1866 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
1868 case nir_intrinsic_ssbo_atomic_and
:
1869 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
1871 case nir_intrinsic_ssbo_atomic_or
:
1872 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
1874 case nir_intrinsic_ssbo_atomic_xor
:
1875 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
1877 case nir_intrinsic_ssbo_atomic_exchange
:
1878 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
1880 case nir_intrinsic_ssbo_atomic_comp_swap
:
1881 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
1884 case nir_intrinsic_get_buffer_size
: {
1885 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
1886 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
1887 int reg_width
= dispatch_width
/ 8;
1890 fs_reg source
= fs_reg(0);
1892 int mlen
= 1 * reg_width
;
1893 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1894 BRW_REGISTER_TYPE_UD
);
1895 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
1897 fs_reg surf_index
= fs_reg(prog_data
->binding_table
.ssbo_start
+ ssbo_index
);
1898 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, dest
,
1899 src_payload
, surf_index
);
1900 inst
->header_size
= 0;
1906 case nir_intrinsic_load_num_work_groups
: {
1907 assert(devinfo
->gen
>= 7);
1908 assert(stage
== MESA_SHADER_COMPUTE
);
1910 struct brw_cs_prog_data
*cs_prog_data
=
1911 (struct brw_cs_prog_data
*) prog_data
;
1912 const unsigned surface
=
1913 cs_prog_data
->binding_table
.work_groups_start
;
1915 cs_prog_data
->uses_num_work_groups
= true;
1917 fs_reg surf_index
= fs_reg(surface
);
1918 brw_mark_surface_used(prog_data
, surface
);
1920 /* Read the 3 GLuint components of gl_NumWorkGroups */
1921 for (unsigned i
= 0; i
< 3; i
++) {
1922 fs_reg read_result
=
1923 emit_untyped_read(bld
, surf_index
,
1925 1 /* dims */, 1 /* size */,
1926 BRW_PREDICATE_NONE
);
1927 read_result
.type
= dest
.type
;
1928 bld
.MOV(dest
, read_result
);
1929 dest
= offset(dest
, bld
, 1);
1935 unreachable("unknown intrinsic");
1940 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
1941 int op
, nir_intrinsic_instr
*instr
)
1944 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1945 dest
= get_nir_dest(instr
->dest
);
1948 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
1949 if (const_surface
) {
1950 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
1951 const_surface
->u
[0];
1952 surface
= fs_reg(surf_index
);
1953 brw_mark_surface_used(prog_data
, surf_index
);
1955 surface
= vgrf(glsl_type::uint_type
);
1956 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
1957 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1959 /* Assume this may touch any SSBO. This is the same we do for other
1960 * UBO/SSBO accesses with non-constant surface.
1962 brw_mark_surface_used(prog_data
,
1963 stage_prog_data
->binding_table
.ssbo_start
+
1964 nir
->info
.num_ssbos
- 1);
1967 fs_reg offset
= get_nir_src(instr
->src
[1]);
1968 fs_reg data1
= get_nir_src(instr
->src
[2]);
1970 if (op
== BRW_AOP_CMPWR
)
1971 data2
= get_nir_src(instr
->src
[3]);
1973 /* Emit the actual atomic operation operation */
1975 fs_reg atomic_result
=
1976 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
1978 1 /* dims */, 1 /* rsize */,
1980 BRW_PREDICATE_NONE
);
1981 dest
.type
= atomic_result
.type
;
1982 bld
.MOV(dest
, atomic_result
);
1986 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1988 unsigned sampler
= instr
->sampler_index
;
1989 fs_reg
sampler_reg(sampler
);
1991 int gather_component
= instr
->component
;
1993 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1995 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1998 int lod_components
= 0;
1999 int UNUSED offset_components
= 0;
2001 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2003 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2004 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2005 switch (instr
->src
[i
].src_type
) {
2006 case nir_tex_src_bias
:
2007 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2009 case nir_tex_src_comparitor
:
2010 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2012 case nir_tex_src_coord
:
2013 switch (instr
->op
) {
2015 case nir_texop_txf_ms
:
2016 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2019 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2023 case nir_tex_src_ddx
:
2024 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2025 lod_components
= nir_tex_instr_src_size(instr
, i
);
2027 case nir_tex_src_ddy
:
2028 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2030 case nir_tex_src_lod
:
2031 switch (instr
->op
) {
2033 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2036 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2039 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2043 case nir_tex_src_ms_index
:
2044 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2046 case nir_tex_src_offset
:
2047 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2048 if (instr
->is_array
)
2049 offset_components
= instr
->coord_components
- 1;
2051 offset_components
= instr
->coord_components
;
2053 case nir_tex_src_projector
:
2054 unreachable("should be lowered");
2056 case nir_tex_src_sampler_offset
: {
2057 /* Figure out the highest possible sampler index and mark it as used */
2058 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2059 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2060 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2062 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2064 brw_mark_surface_used(prog_data
, max_used
);
2066 /* Emit code to evaluate the actual indexing expression */
2067 sampler_reg
= vgrf(glsl_type::uint_type
);
2068 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
2069 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2074 unreachable("unknown texture source");
2078 if (instr
->op
== nir_texop_txf_ms
) {
2079 if (devinfo
->gen
>= 7 &&
2080 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2081 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2087 for (unsigned i
= 0; i
< 3; i
++) {
2088 if (instr
->const_offset
[i
] != 0) {
2089 assert(offset_components
== 0);
2090 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
2095 enum glsl_base_type dest_base_type
=
2096 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2098 const glsl_type
*dest_type
=
2099 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2102 ir_texture_opcode op
;
2103 switch (instr
->op
) {
2104 case nir_texop_lod
: op
= ir_lod
; break;
2105 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2106 case nir_texop_tex
: op
= ir_tex
; break;
2107 case nir_texop_tg4
: op
= ir_tg4
; break;
2108 case nir_texop_txb
: op
= ir_txb
; break;
2109 case nir_texop_txd
: op
= ir_txd
; break;
2110 case nir_texop_txf
: op
= ir_txf
; break;
2111 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2112 case nir_texop_txl
: op
= ir_txl
; break;
2113 case nir_texop_txs
: op
= ir_txs
; break;
2114 case nir_texop_texture_samples
: {
2115 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2116 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2117 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2120 inst
->header_size
= 1;
2121 inst
->base_mrf
= -1;
2125 unreachable("unknown texture opcode");
2128 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2129 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2130 tex_offset
, mcs
, gather_component
,
2131 is_cube_array
, is_rect
, sampler
, sampler_reg
);
2133 fs_reg dest
= get_nir_dest(instr
->dest
);
2134 dest
.type
= this->result
.type
;
2135 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2136 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2137 dest
, this->result
),
2138 (1 << num_components
) - 1);
2142 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2144 switch (instr
->type
) {
2145 case nir_jump_break
:
2146 bld
.emit(BRW_OPCODE_BREAK
);
2148 case nir_jump_continue
:
2149 bld
.emit(BRW_OPCODE_CONTINUE
);
2151 case nir_jump_return
:
2153 unreachable("unknown jump");