2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (key
->force_dual_color_blend
&&
134 var
->data
.location
== FRAG_RESULT_DATA1
) {
135 this->dual_src_output
= reg
;
136 this->do_dual_src
= true;
137 } else if (var
->data
.index
> 0) {
138 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
139 assert(var
->data
.index
== 1);
140 this->dual_src_output
= reg
;
141 this->do_dual_src
= true;
142 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
143 /* Writing gl_FragColor outputs to all color regions. */
144 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
145 this->outputs
[i
] = reg
;
146 this->output_components
[i
] = 4;
148 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
149 this->frag_depth
= reg
;
150 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
151 this->frag_stencil
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
153 this->sample_mask
= reg
;
155 int vector_elements
= var
->type
->without_array()->vector_elements
;
157 /* gl_FragData or a user-defined FS output */
158 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
159 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
161 /* General color output. */
162 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
163 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
164 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
165 this->output_components
[output
] = vector_elements
;
170 unreachable("unhandled shader stage");
176 fs_visitor::nir_setup_uniforms()
178 if (dispatch_width
!= 8)
181 uniforms
= nir
->num_uniforms
/ 4;
183 nir_foreach_variable(var
, &nir
->uniforms
) {
184 /* UBO's and atomics don't take up space in the uniform file */
185 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
188 if (type_size_scalar(var
->type
) > 0)
189 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
194 emit_system_values_block(nir_block
*block
, void *void_visitor
)
196 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
199 nir_foreach_instr(block
, instr
) {
200 if (instr
->type
!= nir_instr_type_intrinsic
)
203 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
204 switch (intrin
->intrinsic
) {
205 case nir_intrinsic_load_vertex_id
:
206 unreachable("should be lowered by lower_vertex_id().");
208 case nir_intrinsic_load_vertex_id_zero_base
:
209 assert(v
->stage
== MESA_SHADER_VERTEX
);
210 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
211 if (reg
->file
== BAD_FILE
)
212 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
215 case nir_intrinsic_load_base_vertex
:
216 assert(v
->stage
== MESA_SHADER_VERTEX
);
217 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
218 if (reg
->file
== BAD_FILE
)
219 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
222 case nir_intrinsic_load_instance_id
:
223 assert(v
->stage
== MESA_SHADER_VERTEX
);
224 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
225 if (reg
->file
== BAD_FILE
)
226 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
229 case nir_intrinsic_load_base_instance
:
230 assert(v
->stage
== MESA_SHADER_VERTEX
);
231 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
232 if (reg
->file
== BAD_FILE
)
233 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
236 case nir_intrinsic_load_draw_id
:
237 assert(v
->stage
== MESA_SHADER_VERTEX
);
238 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
239 if (reg
->file
== BAD_FILE
)
240 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
243 case nir_intrinsic_load_invocation_id
:
244 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
245 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
246 if (reg
->file
== BAD_FILE
) {
247 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
248 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
249 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
250 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
255 case nir_intrinsic_load_sample_pos
:
256 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
257 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
258 if (reg
->file
== BAD_FILE
)
259 *reg
= *v
->emit_samplepos_setup();
262 case nir_intrinsic_load_sample_id
:
263 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
264 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
265 if (reg
->file
== BAD_FILE
)
266 *reg
= *v
->emit_sampleid_setup();
269 case nir_intrinsic_load_sample_mask_in
:
270 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
271 assert(v
->devinfo
->gen
>= 7);
272 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
273 if (reg
->file
== BAD_FILE
)
274 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
275 BRW_REGISTER_TYPE_D
));
278 case nir_intrinsic_load_local_invocation_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_local_invocation_id_setup();
285 case nir_intrinsic_load_work_group_id
:
286 assert(v
->stage
== MESA_SHADER_COMPUTE
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
288 if (reg
->file
== BAD_FILE
)
289 *reg
= *v
->emit_cs_work_group_id_setup();
292 case nir_intrinsic_load_helper_invocation
:
293 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
294 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
295 if (reg
->file
== BAD_FILE
) {
296 const fs_builder abld
=
297 v
->bld
.annotate("gl_HelperInvocation", NULL
);
299 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
300 * pixel mask is in g1.7 of the thread payload.
302 * We move the per-channel pixel enable bit to the low bit of each
303 * channel by shifting the byte containing the pixel mask by the
304 * vector immediate 0x76543210UV.
306 * The region of <1,8,0> reads only 1 byte (the pixel masks for
307 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
308 * masks for 2 and 3) in SIMD16.
310 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
312 stride(byte_offset(retype(brw_vec1_grf(1, 0),
313 BRW_REGISTER_TYPE_UB
), 28),
315 brw_imm_uv(0x76543210));
317 /* A set bit in the pixel mask means the channel is enabled, but
318 * that is the opposite of gl_HelperInvocation so we need to invert
321 * The negate source-modifier bit of logical instructions on Gen8+
322 * performs 1's complement negation, so we can use that instead of
325 fs_reg inverted
= negate(shifted
);
326 if (v
->devinfo
->gen
< 8) {
327 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
328 abld
.NOT(inverted
, shifted
);
331 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
332 * with 1 and negating.
334 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
335 abld
.AND(anded
, inverted
, brw_imm_uw(1));
337 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
338 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
352 fs_visitor::nir_emit_system_values()
354 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
355 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
356 nir_system_values
[i
] = fs_reg();
359 nir_foreach_function(nir
, function
) {
360 assert(strcmp(function
->name
, "main") == 0);
361 assert(function
->impl
);
362 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
367 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
369 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
370 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
371 nir_locals
[i
] = fs_reg();
374 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
375 unsigned array_elems
=
376 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
377 unsigned size
= array_elems
* reg
->num_components
;
378 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
381 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
384 nir_emit_cf_list(&impl
->body
);
388 fs_visitor::nir_emit_cf_list(exec_list
*list
)
390 exec_list_validate(list
);
391 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
392 switch (node
->type
) {
394 nir_emit_if(nir_cf_node_as_if(node
));
397 case nir_cf_node_loop
:
398 nir_emit_loop(nir_cf_node_as_loop(node
));
401 case nir_cf_node_block
:
402 nir_emit_block(nir_cf_node_as_block(node
));
406 unreachable("Invalid CFG node block");
412 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
414 /* first, put the condition into f0 */
415 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
416 retype(get_nir_src(if_stmt
->condition
),
417 BRW_REGISTER_TYPE_D
));
418 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
420 bld
.IF(BRW_PREDICATE_NORMAL
);
422 nir_emit_cf_list(&if_stmt
->then_list
);
424 /* note: if the else is empty, dead CF elimination will remove it */
425 bld
.emit(BRW_OPCODE_ELSE
);
427 nir_emit_cf_list(&if_stmt
->else_list
);
429 bld
.emit(BRW_OPCODE_ENDIF
);
433 fs_visitor::nir_emit_loop(nir_loop
*loop
)
435 bld
.emit(BRW_OPCODE_DO
);
437 nir_emit_cf_list(&loop
->body
);
439 bld
.emit(BRW_OPCODE_WHILE
);
443 fs_visitor::nir_emit_block(nir_block
*block
)
445 nir_foreach_instr(block
, instr
) {
446 nir_emit_instr(instr
);
451 fs_visitor::nir_emit_instr(nir_instr
*instr
)
453 const fs_builder abld
= bld
.annotate(NULL
, instr
);
455 switch (instr
->type
) {
456 case nir_instr_type_alu
:
457 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
460 case nir_instr_type_intrinsic
:
462 case MESA_SHADER_VERTEX
:
463 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_EVAL
:
466 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_GEOMETRY
:
469 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_FRAGMENT
:
472 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_COMPUTE
:
475 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 unreachable("unsupported shader stage");
482 case nir_instr_type_tex
:
483 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
486 case nir_instr_type_load_const
:
487 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
490 case nir_instr_type_ssa_undef
:
491 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
494 case nir_instr_type_jump
:
495 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
499 unreachable("unknown instruction type");
504 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
508 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
509 const fs_reg
&result
)
511 if (!instr
->src
[0].src
.is_ssa
||
512 !instr
->src
[0].src
.ssa
->parent_instr
)
515 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
518 nir_alu_instr
*src0
=
519 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
521 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
522 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
525 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
526 assert(element
!= NULL
);
528 enum opcode extract_op
;
529 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
530 assert(element
->u32
[0] <= 1);
531 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
533 assert(element
->u32
[0] <= 3);
534 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
537 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
538 op0
.type
= brw_type_for_nir_type(nir_op_infos
[src0
->op
].input_types
[0]);
539 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
541 set_saturate(instr
->dest
.saturate
,
542 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
547 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
548 const fs_reg
&result
)
550 if (!instr
->src
[0].src
.is_ssa
||
551 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
554 nir_intrinsic_instr
*src0
=
555 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
557 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
560 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
561 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
564 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
565 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
568 fs_reg tmp
= vgrf(glsl_type::int_type
);
570 if (devinfo
->gen
>= 6) {
571 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
572 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
574 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
576 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
577 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
579 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
581 * This negation looks like it's safe in practice, because bits 0:4 will
582 * surely be TRIANGLES
585 if (value1
->f32
[0] == -1.0f
) {
589 tmp
.type
= BRW_REGISTER_TYPE_W
;
590 tmp
.subreg_offset
= 2;
593 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
595 tmp
.type
= BRW_REGISTER_TYPE_D
;
596 tmp
.subreg_offset
= 0;
599 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
600 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
602 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
604 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
605 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
607 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
609 * This negation looks like it's safe in practice, because bits 0:4 will
610 * surely be TRIANGLES
613 if (value1
->f32
[0] == -1.0f
) {
617 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
619 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
625 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
627 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
630 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
631 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
634 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
635 op
[i
] = get_nir_src(instr
->src
[i
].src
);
636 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
637 op
[i
].abs
= instr
->src
[i
].abs
;
638 op
[i
].negate
= instr
->src
[i
].negate
;
641 /* We get a bunch of mov's out of the from_ssa pass and they may still
642 * be vectorized. We'll handle them as a special-case. We'll also
643 * handle vecN here because it's basically the same thing.
651 fs_reg temp
= result
;
652 bool need_extra_copy
= false;
653 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
654 if (!instr
->src
[i
].src
.is_ssa
&&
655 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
656 need_extra_copy
= true;
657 temp
= bld
.vgrf(result
.type
, 4);
662 for (unsigned i
= 0; i
< 4; i
++) {
663 if (!(instr
->dest
.write_mask
& (1 << i
)))
666 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
667 inst
= bld
.MOV(offset(temp
, bld
, i
),
668 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
670 inst
= bld
.MOV(offset(temp
, bld
, i
),
671 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
673 inst
->saturate
= instr
->dest
.saturate
;
676 /* In this case the source and destination registers were the same,
677 * so we need to insert an extra set of moves in order to deal with
680 if (need_extra_copy
) {
681 for (unsigned i
= 0; i
< 4; i
++) {
682 if (!(instr
->dest
.write_mask
& (1 << i
)))
685 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
694 /* At this point, we have dealt with any instruction that operates on
695 * more than a single channel. Therefore, we can just adjust the source
696 * and destination registers for that channel and emit the instruction.
698 unsigned channel
= 0;
699 if (nir_op_infos
[instr
->op
].output_size
== 0) {
700 /* Since NIR is doing the scalarizing for us, we should only ever see
701 * vectorized operations with a single channel.
703 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
704 channel
= ffs(instr
->dest
.write_mask
) - 1;
706 result
= offset(result
, bld
, channel
);
709 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
710 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
711 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
717 if (optimize_extract_to_float(instr
, result
))
720 inst
= bld
.MOV(result
, op
[0]);
721 inst
->saturate
= instr
->dest
.saturate
;
726 bld
.MOV(result
, op
[0]);
730 /* AND(val, 0x80000000) gives the sign bit.
732 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
735 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
737 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
738 op
[0].type
= BRW_REGISTER_TYPE_UD
;
739 result
.type
= BRW_REGISTER_TYPE_UD
;
740 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
742 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
743 inst
->predicate
= BRW_PREDICATE_NORMAL
;
744 if (instr
->dest
.saturate
) {
745 inst
= bld
.MOV(result
, result
);
746 inst
->saturate
= true;
752 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
753 * -> non-negative val generates 0x00000000.
754 * Predicated OR sets 1 if val is positive.
756 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
757 bld
.ASR(result
, op
[0], brw_imm_d(31));
758 inst
= bld
.OR(result
, result
, brw_imm_d(1));
759 inst
->predicate
= BRW_PREDICATE_NORMAL
;
763 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
764 inst
->saturate
= instr
->dest
.saturate
;
768 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
769 inst
->saturate
= instr
->dest
.saturate
;
773 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
774 inst
->saturate
= instr
->dest
.saturate
;
778 if (!compiler
->precise_trig
) {
779 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
781 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
782 inst
= bld
.emit(SHADER_OPCODE_SIN
, tmp
, op
[0]);
783 inst
= bld
.MUL(result
, tmp
, brw_imm_f(0.99997));
785 inst
->saturate
= instr
->dest
.saturate
;
789 if (!compiler
->precise_trig
) {
790 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
792 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
793 inst
= bld
.emit(SHADER_OPCODE_COS
, tmp
, op
[0]);
794 inst
= bld
.MUL(result
, tmp
, brw_imm_f(0.99997));
796 inst
->saturate
= instr
->dest
.saturate
;
800 if (fs_key
->high_quality_derivatives
) {
801 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
803 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
805 inst
->saturate
= instr
->dest
.saturate
;
807 case nir_op_fddx_fine
:
808 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
809 inst
->saturate
= instr
->dest
.saturate
;
811 case nir_op_fddx_coarse
:
812 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
813 inst
->saturate
= instr
->dest
.saturate
;
816 if (fs_key
->high_quality_derivatives
) {
817 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
818 brw_imm_d(fs_key
->render_to_fbo
));
820 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
821 brw_imm_d(fs_key
->render_to_fbo
));
823 inst
->saturate
= instr
->dest
.saturate
;
825 case nir_op_fddy_fine
:
826 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
827 brw_imm_d(fs_key
->render_to_fbo
));
828 inst
->saturate
= instr
->dest
.saturate
;
830 case nir_op_fddy_coarse
:
831 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
832 brw_imm_d(fs_key
->render_to_fbo
));
833 inst
->saturate
= instr
->dest
.saturate
;
838 inst
= bld
.ADD(result
, op
[0], op
[1]);
839 inst
->saturate
= instr
->dest
.saturate
;
843 inst
= bld
.MUL(result
, op
[0], op
[1]);
844 inst
->saturate
= instr
->dest
.saturate
;
848 bld
.MUL(result
, op
[0], op
[1]);
851 case nir_op_imul_high
:
852 case nir_op_umul_high
:
853 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
858 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
861 case nir_op_uadd_carry
:
862 unreachable("Should have been lowered by carry_to_arith().");
864 case nir_op_usub_borrow
:
865 unreachable("Should have been lowered by borrow_to_arith().");
868 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
874 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
880 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
885 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
890 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
894 if (devinfo
->gen
>= 8) {
895 op
[0] = resolve_source_modifiers(op
[0]);
897 bld
.NOT(result
, op
[0]);
900 if (devinfo
->gen
>= 8) {
901 op
[0] = resolve_source_modifiers(op
[0]);
902 op
[1] = resolve_source_modifiers(op
[1]);
904 bld
.XOR(result
, op
[0], op
[1]);
907 if (devinfo
->gen
>= 8) {
908 op
[0] = resolve_source_modifiers(op
[0]);
909 op
[1] = resolve_source_modifiers(op
[1]);
911 bld
.OR(result
, op
[0], op
[1]);
914 if (devinfo
->gen
>= 8) {
915 op
[0] = resolve_source_modifiers(op
[0]);
916 op
[1] = resolve_source_modifiers(op
[1]);
918 bld
.AND(result
, op
[0], op
[1]);
924 case nir_op_ball_fequal2
:
925 case nir_op_ball_iequal2
:
926 case nir_op_ball_fequal3
:
927 case nir_op_ball_iequal3
:
928 case nir_op_ball_fequal4
:
929 case nir_op_ball_iequal4
:
930 case nir_op_bany_fnequal2
:
931 case nir_op_bany_inequal2
:
932 case nir_op_bany_fnequal3
:
933 case nir_op_bany_inequal3
:
934 case nir_op_bany_fnequal4
:
935 case nir_op_bany_inequal4
:
936 unreachable("Lowered by nir_lower_alu_reductions");
938 case nir_op_fnoise1_1
:
939 case nir_op_fnoise1_2
:
940 case nir_op_fnoise1_3
:
941 case nir_op_fnoise1_4
:
942 case nir_op_fnoise2_1
:
943 case nir_op_fnoise2_2
:
944 case nir_op_fnoise2_3
:
945 case nir_op_fnoise2_4
:
946 case nir_op_fnoise3_1
:
947 case nir_op_fnoise3_2
:
948 case nir_op_fnoise3_3
:
949 case nir_op_fnoise3_4
:
950 case nir_op_fnoise4_1
:
951 case nir_op_fnoise4_2
:
952 case nir_op_fnoise4_3
:
953 case nir_op_fnoise4_4
:
954 unreachable("not reached: should be handled by lower_noise");
957 unreachable("not reached: should be handled by ldexp_to_arith()");
960 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
961 inst
->saturate
= instr
->dest
.saturate
;
965 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
966 inst
->saturate
= instr
->dest
.saturate
;
971 bld
.MOV(result
, negate(op
[0]));
975 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
978 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
982 inst
= bld
.RNDZ(result
, op
[0]);
983 inst
->saturate
= instr
->dest
.saturate
;
987 op
[0].negate
= !op
[0].negate
;
988 fs_reg temp
= vgrf(glsl_type::float_type
);
989 bld
.RNDD(temp
, op
[0]);
991 inst
= bld
.MOV(result
, temp
);
992 inst
->saturate
= instr
->dest
.saturate
;
996 inst
= bld
.RNDD(result
, op
[0]);
997 inst
->saturate
= instr
->dest
.saturate
;
1000 inst
= bld
.FRC(result
, op
[0]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1003 case nir_op_fround_even
:
1004 inst
= bld
.RNDE(result
, op
[0]);
1005 inst
->saturate
= instr
->dest
.saturate
;
1008 case nir_op_fquantize2f16
: {
1009 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1010 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1011 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1013 /* The destination stride must be at least as big as the source stride. */
1014 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1017 /* Check for denormal */
1018 fs_reg abs_src0
= op
[0];
1019 abs_src0
.abs
= true;
1020 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1022 /* Get the appropriately signed zero */
1023 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1024 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1025 brw_imm_ud(0x80000000));
1026 /* Do the actual F32 -> F16 -> F32 conversion */
1027 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1028 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1029 /* Select that or zero based on normal status */
1030 inst
= bld
.SEL(result
, zero
, tmp32
);
1031 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1032 inst
->saturate
= instr
->dest
.saturate
;
1039 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1040 inst
->saturate
= instr
->dest
.saturate
;
1046 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1047 inst
->saturate
= instr
->dest
.saturate
;
1050 case nir_op_pack_snorm_2x16
:
1051 case nir_op_pack_snorm_4x8
:
1052 case nir_op_pack_unorm_2x16
:
1053 case nir_op_pack_unorm_4x8
:
1054 case nir_op_unpack_snorm_2x16
:
1055 case nir_op_unpack_snorm_4x8
:
1056 case nir_op_unpack_unorm_2x16
:
1057 case nir_op_unpack_unorm_4x8
:
1058 case nir_op_unpack_half_2x16
:
1059 case nir_op_pack_half_2x16
:
1060 unreachable("not reached: should be handled by lower_packing_builtins");
1062 case nir_op_unpack_half_2x16_split_x
:
1063 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1064 inst
->saturate
= instr
->dest
.saturate
;
1066 case nir_op_unpack_half_2x16_split_y
:
1067 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1068 inst
->saturate
= instr
->dest
.saturate
;
1072 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1073 inst
->saturate
= instr
->dest
.saturate
;
1076 case nir_op_bitfield_reverse
:
1077 bld
.BFREV(result
, op
[0]);
1080 case nir_op_bit_count
:
1081 bld
.CBIT(result
, op
[0]);
1084 case nir_op_ufind_msb
:
1085 case nir_op_ifind_msb
: {
1086 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1088 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1089 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1090 * subtract the result from 31 to convert the MSB count into an LSB count.
1092 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1094 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1095 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1096 inst
->src
[0].negate
= true;
1100 case nir_op_find_lsb
:
1101 bld
.FBL(result
, op
[0]);
1104 case nir_op_ubitfield_extract
:
1105 case nir_op_ibitfield_extract
:
1106 unreachable("should have been lowered");
1109 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1112 bld
.BFI1(result
, op
[0], op
[1]);
1115 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1118 case nir_op_bitfield_insert
:
1119 unreachable("not reached: should have been lowered");
1122 bld
.SHL(result
, op
[0], op
[1]);
1125 bld
.ASR(result
, op
[0], op
[1]);
1128 bld
.SHR(result
, op
[0], op
[1]);
1131 case nir_op_pack_half_2x16_split
:
1132 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1136 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1137 inst
->saturate
= instr
->dest
.saturate
;
1141 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1142 inst
->saturate
= instr
->dest
.saturate
;
1146 if (optimize_frontfacing_ternary(instr
, result
))
1149 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1150 inst
= bld
.SEL(result
, op
[1], op
[2]);
1151 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1154 case nir_op_extract_u8
:
1155 case nir_op_extract_i8
: {
1156 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1157 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1158 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1162 case nir_op_extract_u16
:
1163 case nir_op_extract_i16
: {
1164 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1165 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1166 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1171 unreachable("unhandled instruction");
1174 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1175 * to sign extend the low bit to 0/~0
1177 if (devinfo
->gen
<= 5 &&
1178 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1179 fs_reg masked
= vgrf(glsl_type::int_type
);
1180 bld
.AND(masked
, result
, brw_imm_d(1));
1181 masked
.negate
= true;
1182 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1187 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1188 nir_load_const_instr
*instr
)
1190 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1192 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1193 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1195 nir_ssa_values
[instr
->def
.index
] = reg
;
1199 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1201 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1202 instr
->def
.num_components
);
1206 fs_visitor::get_nir_src(nir_src src
)
1210 reg
= nir_ssa_values
[src
.ssa
->index
];
1212 /* We don't handle indirects on locals */
1213 assert(src
.reg
.indirect
== NULL
);
1214 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1215 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1218 /* to avoid floating-point denorm flushing problems, set the type by
1219 * default to D - instructions that need floating point semantics will set
1220 * this to F if they need to
1222 return retype(reg
, BRW_REGISTER_TYPE_D
);
1226 fs_visitor::get_nir_dest(nir_dest dest
)
1229 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1230 dest
.ssa
.num_components
);
1231 return nir_ssa_values
[dest
.ssa
.index
];
1233 /* We don't handle indirects on locals */
1234 assert(dest
.reg
.indirect
== NULL
);
1235 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1236 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1241 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1243 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1244 BRW_REGISTER_TYPE_UD
);
1246 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1247 tail
= tail
->child
) {
1248 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1249 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1250 const unsigned size
= glsl_get_length(tail
->type
);
1251 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1252 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1253 image
= offset(image
, bld
, base
* element_size
);
1255 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1256 fs_reg tmp
= vgrf(glsl_type::int_type
);
1258 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1259 /* IVB hangs when trying to access an invalid surface index with
1260 * the dataport. According to the spec "if the index used to
1261 * select an individual element is negative or greater than or
1262 * equal to the size of the array, the results of the operation
1263 * are undefined but may not lead to termination" -- which is one
1264 * of the possible outcomes of the hang. Clamp the index to
1265 * prevent access outside of the array bounds.
1267 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1268 BRW_REGISTER_TYPE_UD
),
1269 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1271 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1274 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1276 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1278 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1286 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1289 for (unsigned i
= 0; i
< 4; i
++) {
1290 if (!((wr_mask
>> i
) & 1))
1293 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1294 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1295 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1296 if (new_inst
->src
[j
].file
== VGRF
)
1297 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1304 * Get the matching channel register datatype for an image intrinsic of the
1305 * specified GLSL image type.
1308 get_image_base_type(const glsl_type
*type
)
1310 switch ((glsl_base_type
)type
->sampled_type
) {
1311 case GLSL_TYPE_UINT
:
1312 return BRW_REGISTER_TYPE_UD
;
1314 return BRW_REGISTER_TYPE_D
;
1315 case GLSL_TYPE_FLOAT
:
1316 return BRW_REGISTER_TYPE_F
;
1318 unreachable("Not reached.");
1323 * Get the appropriate atomic op for an image atomic intrinsic.
1326 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1329 case nir_intrinsic_image_atomic_add
:
1331 case nir_intrinsic_image_atomic_min
:
1332 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1333 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1334 case nir_intrinsic_image_atomic_max
:
1335 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1336 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1337 case nir_intrinsic_image_atomic_and
:
1339 case nir_intrinsic_image_atomic_or
:
1341 case nir_intrinsic_image_atomic_xor
:
1343 case nir_intrinsic_image_atomic_exchange
:
1345 case nir_intrinsic_image_atomic_comp_swap
:
1346 return BRW_AOP_CMPWR
;
1348 unreachable("Not reachable.");
1353 emit_pixel_interpolater_send(const fs_builder
&bld
,
1358 glsl_interp_qualifier interpolation
)
1364 if (src
.file
== BAD_FILE
) {
1366 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1370 mlen
= 2 * bld
.dispatch_width() / 8;
1373 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1375 /* 2 floats per slot returned */
1376 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1377 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1383 * Computes 1 << x, given a D/UD register containing some value x.
1386 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1388 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1390 fs_reg result
= bld
.vgrf(x
.type
, 1);
1391 fs_reg one
= bld
.vgrf(x
.type
, 1);
1393 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1394 bld
.SHL(result
, one
, x
);
1399 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1401 assert(stage
== MESA_SHADER_GEOMETRY
);
1403 struct brw_gs_prog_data
*gs_prog_data
=
1404 (struct brw_gs_prog_data
*) prog_data
;
1406 /* We can only do EndPrimitive() functionality when the control data
1407 * consists of cut bits. Fortunately, the only time it isn't is when the
1408 * output type is points, in which case EndPrimitive() is a no-op.
1410 if (gs_prog_data
->control_data_format
!=
1411 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1415 /* Cut bits use one bit per vertex. */
1416 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1418 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1419 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1421 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1422 * vertex n, 0 otherwise. So all we need to do here is mark bit
1423 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1424 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1425 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1427 * Note that if EndPrimitive() is called before emitting any vertices, this
1428 * will cause us to set bit 31 of the control_data_bits register to 1.
1429 * That's fine because:
1431 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1432 * output, so the hardware will ignore cut bit 31.
1434 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1435 * last vertex, so setting cut bit 31 has no effect (since the primitive
1436 * is automatically ended when the GS terminates).
1438 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1439 * control_data_bits register to 0 when the first vertex is emitted.
1442 const fs_builder abld
= bld
.annotate("end primitive");
1444 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1445 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1446 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1447 fs_reg mask
= intexp2(abld
, prev_count
);
1448 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1449 * attention to the lower 5 bits of its second source argument, so on this
1450 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1451 * ((vertex_count - 1) % 32).
1453 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1457 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1459 assert(stage
== MESA_SHADER_GEOMETRY
);
1460 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1462 struct brw_gs_prog_data
*gs_prog_data
=
1463 (struct brw_gs_prog_data
*) prog_data
;
1465 const fs_builder abld
= bld
.annotate("emit control data bits");
1466 const fs_builder fwa_bld
= bld
.exec_all();
1468 /* We use a single UD register to accumulate control data bits (32 bits
1469 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1472 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1473 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1474 * use the Channel Mask phase to enable/disable which DWord within that
1475 * group to write. (Remember, different SIMD8 channels may have emitted
1476 * different numbers of vertices, so we may need per-slot offsets.)
1478 * Channel masking presents an annoying problem: we may have to replicate
1479 * the data up to 4 times:
1481 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1483 * To avoid penalizing shaders that emit a small number of vertices, we
1484 * can avoid these sometimes: if the size of the control data header is
1485 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1486 * land in the same 128-bit group, so we can skip per-slot offsets.
1488 * Similarly, if the control data header is <= 32 bits, there is only one
1489 * DWord, so we can skip channel masks.
1491 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1493 fs_reg channel_mask
, per_slot_offset
;
1495 if (gs_compile
->control_data_header_size_bits
> 32) {
1496 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1497 channel_mask
= vgrf(glsl_type::uint_type
);
1500 if (gs_compile
->control_data_header_size_bits
> 128) {
1501 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1502 per_slot_offset
= vgrf(glsl_type::uint_type
);
1505 /* Figure out which DWord we're trying to write to using the formula:
1507 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1509 * Since bits_per_vertex is a power of two, and is known at compile
1510 * time, this can be optimized to:
1512 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1514 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1515 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1516 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1517 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1518 unsigned log2_bits_per_vertex
=
1519 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1520 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1522 if (per_slot_offset
.file
!= BAD_FILE
) {
1523 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1524 * the appropriate OWord within the control data header.
1526 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1529 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1530 * write to the appropriate DWORD within the OWORD.
1532 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1533 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1534 channel_mask
= intexp2(fwa_bld
, channel
);
1535 /* Then the channel masks need to be in bits 23:16. */
1536 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1539 /* Store the control data bits in the message payload and send it. */
1541 if (channel_mask
.file
!= BAD_FILE
)
1542 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1543 if (per_slot_offset
.file
!= BAD_FILE
)
1546 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1547 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1549 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1550 if (per_slot_offset
.file
!= BAD_FILE
)
1551 sources
[i
++] = per_slot_offset
;
1552 if (channel_mask
.file
!= BAD_FILE
)
1553 sources
[i
++] = channel_mask
;
1555 sources
[i
++] = this->control_data_bits
;
1558 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1559 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1561 /* We need to increment Global Offset by 256-bits to make room for
1562 * Broadwell's extra "Vertex Count" payload at the beginning of the
1563 * URB entry. Since this is an OWord message, Global Offset is counted
1564 * in 128-bit units, so we must set it to 2.
1566 if (gs_prog_data
->static_vertex_count
== -1)
1571 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1574 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1576 /* Note: we are calling this *before* increasing vertex_count, so
1577 * this->vertex_count == vertex_count - 1 in the formula above.
1580 /* Stream mode uses 2 bits per vertex */
1581 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1583 /* Must be a valid stream */
1584 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1586 /* Control data bits are initialized to 0 so we don't have to set any
1587 * bits when sending vertices to stream 0.
1592 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1594 /* reg::sid = stream_id */
1595 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1596 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1598 /* reg:shift_count = 2 * (vertex_count - 1) */
1599 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1600 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1602 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1603 * attention to the lower 5 bits of its second source argument, so on this
1604 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1605 * stream_id << ((2 * (vertex_count - 1)) % 32).
1607 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1608 abld
.SHL(mask
, sid
, shift_count
);
1609 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1613 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1616 assert(stage
== MESA_SHADER_GEOMETRY
);
1618 struct brw_gs_prog_data
*gs_prog_data
=
1619 (struct brw_gs_prog_data
*) prog_data
;
1621 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1622 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1624 /* Haswell and later hardware ignores the "Render Stream Select" bits
1625 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1626 * and instead sends all primitives down the pipeline for rasterization.
1627 * If the SOL stage is enabled, "Render Stream Select" is honored and
1628 * primitives bound to non-zero streams are discarded after stream output.
1630 * Since the only purpose of primives sent to non-zero streams is to
1631 * be recorded by transform feedback, we can simply discard all geometry
1632 * bound to these streams when transform feedback is disabled.
1634 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1637 /* If we're outputting 32 control data bits or less, then we can wait
1638 * until the shader is over to output them all. Otherwise we need to
1639 * output them as we go. Now is the time to do it, since we're about to
1640 * output the vertex_count'th vertex, so it's guaranteed that the
1641 * control data bits associated with the (vertex_count - 1)th vertex are
1644 if (gs_compile
->control_data_header_size_bits
> 32) {
1645 const fs_builder abld
=
1646 bld
.annotate("emit vertex: emit control data bits");
1648 /* Only emit control data bits if we've finished accumulating a batch
1649 * of 32 bits. This is the case when:
1651 * (vertex_count * bits_per_vertex) % 32 == 0
1653 * (in other words, when the last 5 bits of vertex_count *
1654 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1655 * integer n (which is always the case, since bits_per_vertex is
1656 * always 1 or 2), this is equivalent to requiring that the last 5-n
1657 * bits of vertex_count are 0:
1659 * vertex_count & (2^(5-n) - 1) == 0
1661 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1664 * vertex_count & (32 / bits_per_vertex - 1) == 0
1666 * TODO: If vertex_count is an immediate, we could do some of this math
1667 * at compile time...
1670 abld
.AND(bld
.null_reg_d(), vertex_count
,
1671 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1672 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1674 abld
.IF(BRW_PREDICATE_NORMAL
);
1675 /* If vertex_count is 0, then no control data bits have been
1676 * accumulated yet, so we can skip emitting them.
1678 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1679 BRW_CONDITIONAL_NEQ
);
1680 abld
.IF(BRW_PREDICATE_NORMAL
);
1681 emit_gs_control_data_bits(vertex_count
);
1682 abld
.emit(BRW_OPCODE_ENDIF
);
1684 /* Reset control_data_bits to 0 so we can start accumulating a new
1687 * Note: in the case where vertex_count == 0, this neutralizes the
1688 * effect of any call to EndPrimitive() that the shader may have
1689 * made before outputting its first vertex.
1691 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1692 inst
->force_writemask_all
= true;
1693 abld
.emit(BRW_OPCODE_ENDIF
);
1696 emit_urb_writes(vertex_count
);
1698 /* In stream mode we have to set control data bits for all vertices
1699 * unless we have disabled control data bits completely (which we do
1700 * do for GL_POINTS outputs that don't use streams).
1702 if (gs_compile
->control_data_header_size_bits
> 0 &&
1703 gs_prog_data
->control_data_format
==
1704 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1705 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1710 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1711 const nir_src
&vertex_src
,
1712 unsigned base_offset
,
1713 const nir_src
&offset_src
,
1714 unsigned num_components
)
1716 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1718 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1719 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1720 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1722 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1723 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1724 * gl_PointSize is available as a GS input, however, so it must be that.
1726 const bool is_point_size
= (base_offset
== 0);
1728 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1729 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1730 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1731 vertex_const
->u32
[0] * push_reg_count
;
1732 /* This input was pushed into registers. */
1733 if (is_point_size
) {
1734 /* gl_PointSize comes in .w */
1735 assert(imm_offset
== 0);
1736 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1738 for (unsigned i
= 0; i
< num_components
; i
++) {
1739 bld
.MOV(offset(dst
, bld
, i
),
1740 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1744 /* Resort to the pull model. Ensure the VUE handles are provided. */
1745 gs_prog_data
->base
.include_vue_handles
= true;
1747 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1751 /* The vertex index is constant; just select the proper URB handle. */
1753 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1754 BRW_REGISTER_TYPE_UD
);
1756 /* The vertex index is non-constant. We need to use indirect
1757 * addressing to fetch the proper URB handle.
1759 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1760 * indicating that channel <n> should read the handle from
1761 * DWord <n>. We convert that to bytes by multiplying by 4.
1763 * Next, we convert the vertex index to bytes by multiplying
1764 * by 32 (shifting by 5), and add the two together. This is
1765 * the final indirect byte offset.
1767 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1768 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1769 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1770 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1771 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1773 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1774 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1775 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1776 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1777 /* Convert vertex_index to bytes (multiply by 32) */
1778 bld
.SHL(vertex_offset_bytes
,
1779 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1781 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1783 /* Use first_icp_handle as the base offset. There is one register
1784 * of URB handles per vertex, so inform the register allocator that
1785 * we might read up to nir->info.gs.vertices_in registers.
1787 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1788 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1789 fs_reg(icp_offset_bytes
),
1790 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1795 /* Constant indexing - use global offset. */
1796 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1797 inst
->offset
= base_offset
+ offset_const
->u32
[0];
1798 inst
->base_mrf
= -1;
1800 inst
->regs_written
= num_components
;
1802 /* Indirect indexing - use per-slot offsets as well. */
1803 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1804 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1805 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1807 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1808 inst
->offset
= base_offset
;
1809 inst
->base_mrf
= -1;
1811 inst
->regs_written
= num_components
;
1814 if (is_point_size
) {
1815 /* Read the whole VUE header (because of alignment) and read .w. */
1816 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1818 inst
->regs_written
= 4;
1819 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1825 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1827 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1828 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1831 /* The only constant offset we should find is 0. brw_nir.c's
1832 * add_const_offset_to_base() will fold other constant offsets
1833 * into instr->const_index[0].
1835 assert(const_value
->u32
[0] == 0);
1839 return get_nir_src(*offset_src
);
1843 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1844 nir_intrinsic_instr
*instr
)
1846 assert(stage
== MESA_SHADER_VERTEX
);
1849 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1850 dest
= get_nir_dest(instr
->dest
);
1852 switch (instr
->intrinsic
) {
1853 case nir_intrinsic_load_vertex_id
:
1854 unreachable("should be lowered by lower_vertex_id()");
1856 case nir_intrinsic_load_vertex_id_zero_base
:
1857 case nir_intrinsic_load_base_vertex
:
1858 case nir_intrinsic_load_instance_id
:
1859 case nir_intrinsic_load_base_instance
:
1860 case nir_intrinsic_load_draw_id
: {
1861 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1862 fs_reg val
= nir_system_values
[sv
];
1863 assert(val
.file
!= BAD_FILE
);
1864 dest
.type
= val
.type
;
1870 nir_emit_intrinsic(bld
, instr
);
1876 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1877 nir_intrinsic_instr
*instr
)
1879 assert(stage
== MESA_SHADER_TESS_EVAL
);
1880 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1883 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1884 dest
= get_nir_dest(instr
->dest
);
1886 switch (instr
->intrinsic
) {
1887 case nir_intrinsic_load_primitive_id
:
1888 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1890 case nir_intrinsic_load_tess_coord
:
1891 /* gl_TessCoord is part of the payload in g1-3 */
1892 for (unsigned i
= 0; i
< 3; i
++) {
1893 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1897 case nir_intrinsic_load_tess_level_outer
:
1898 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1899 * appears as a push-model input. So, we can simply use the ATTR file
1900 * rather than issuing URB read messages. The data is stored in the
1901 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1904 switch (tes_prog_data
->domain
) {
1905 case BRW_TESS_DOMAIN_QUAD
:
1906 for (unsigned i
= 0; i
< 4; i
++)
1907 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1909 case BRW_TESS_DOMAIN_TRI
:
1910 for (unsigned i
= 0; i
< 3; i
++)
1911 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1913 case BRW_TESS_DOMAIN_ISOLINE
:
1914 for (unsigned i
= 0; i
< 2; i
++)
1915 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1920 case nir_intrinsic_load_tess_level_inner
:
1921 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1922 * appears as a push-model input. So, we can simply use the ATTR file
1923 * rather than issuing URB read messages.
1925 switch (tes_prog_data
->domain
) {
1926 case BRW_TESS_DOMAIN_QUAD
:
1927 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1928 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1930 case BRW_TESS_DOMAIN_TRI
:
1931 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1933 case BRW_TESS_DOMAIN_ISOLINE
:
1934 /* ignore - value is undefined */
1939 case nir_intrinsic_load_input
:
1940 case nir_intrinsic_load_per_vertex_input
: {
1941 fs_reg indirect_offset
= get_indirect_offset(instr
);
1942 unsigned imm_offset
= instr
->const_index
[0];
1945 if (indirect_offset
.file
== BAD_FILE
) {
1946 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1947 * which is 16 registers (since each holds 2 vec4 slots).
1949 const unsigned max_push_slots
= 32;
1950 if (imm_offset
< max_push_slots
) {
1951 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1952 for (int i
= 0; i
< instr
->num_components
; i
++) {
1953 bld
.MOV(offset(dest
, bld
, i
),
1954 component(src
, 4 * (imm_offset
% 2) + i
));
1956 tes_prog_data
->base
.urb_read_length
=
1957 MAX2(tes_prog_data
->base
.urb_read_length
,
1958 DIV_ROUND_UP(imm_offset
+ 1, 2));
1960 /* Replicate the patch handle to all enabled channels */
1961 const fs_reg srcs
[] = {
1962 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1964 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1965 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1967 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1969 inst
->offset
= imm_offset
;
1970 inst
->base_mrf
= -1;
1971 inst
->regs_written
= instr
->num_components
;
1974 /* Indirect indexing - use per-slot offsets as well. */
1975 const fs_reg srcs
[] = {
1976 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1979 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1980 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1982 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1984 inst
->offset
= imm_offset
;
1985 inst
->base_mrf
= -1;
1986 inst
->regs_written
= instr
->num_components
;
1991 nir_emit_intrinsic(bld
, instr
);
1997 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1998 nir_intrinsic_instr
*instr
)
2000 assert(stage
== MESA_SHADER_GEOMETRY
);
2001 fs_reg indirect_offset
;
2004 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2005 dest
= get_nir_dest(instr
->dest
);
2007 switch (instr
->intrinsic
) {
2008 case nir_intrinsic_load_primitive_id
:
2009 assert(stage
== MESA_SHADER_GEOMETRY
);
2010 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2011 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2012 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2015 case nir_intrinsic_load_input
:
2016 unreachable("load_input intrinsics are invalid for the GS stage");
2018 case nir_intrinsic_load_per_vertex_input
:
2019 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2020 instr
->src
[1], instr
->num_components
);
2023 case nir_intrinsic_emit_vertex_with_counter
:
2024 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2027 case nir_intrinsic_end_primitive_with_counter
:
2028 emit_gs_end_primitive(instr
->src
[0]);
2031 case nir_intrinsic_set_vertex_count
:
2032 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2035 case nir_intrinsic_load_invocation_id
: {
2036 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2037 assert(val
.file
!= BAD_FILE
);
2038 dest
.type
= val
.type
;
2044 nir_emit_intrinsic(bld
, instr
);
2050 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2051 nir_intrinsic_instr
*instr
)
2053 assert(stage
== MESA_SHADER_FRAGMENT
);
2054 struct brw_wm_prog_data
*wm_prog_data
=
2055 (struct brw_wm_prog_data
*) prog_data
;
2058 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2059 dest
= get_nir_dest(instr
->dest
);
2061 switch (instr
->intrinsic
) {
2062 case nir_intrinsic_load_front_face
:
2063 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2064 *emit_frontfacing_interpolation());
2067 case nir_intrinsic_load_sample_pos
: {
2068 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2069 assert(sample_pos
.file
!= BAD_FILE
);
2070 dest
.type
= sample_pos
.type
;
2071 bld
.MOV(dest
, sample_pos
);
2072 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2076 case nir_intrinsic_load_helper_invocation
:
2077 case nir_intrinsic_load_sample_mask_in
:
2078 case nir_intrinsic_load_sample_id
: {
2079 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2080 fs_reg val
= nir_system_values
[sv
];
2081 assert(val
.file
!= BAD_FILE
);
2082 dest
.type
= val
.type
;
2087 case nir_intrinsic_discard
:
2088 case nir_intrinsic_discard_if
: {
2089 /* We track our discarded pixels in f0.1. By predicating on it, we can
2090 * update just the flag bits that aren't yet discarded. If there's no
2091 * condition, we emit a CMP of g0 != g0, so all currently executing
2092 * channels will get turned off.
2095 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2096 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2097 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2099 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2100 BRW_REGISTER_TYPE_UW
));
2101 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2103 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2104 cmp
->flag_subreg
= 1;
2106 if (devinfo
->gen
>= 6) {
2107 emit_discard_jump();
2112 case nir_intrinsic_interp_var_at_centroid
:
2113 case nir_intrinsic_interp_var_at_sample
:
2114 case nir_intrinsic_interp_var_at_offset
: {
2115 /* Handle ARB_gpu_shader5 interpolation intrinsics
2117 * It's worth a quick word of explanation as to why we handle the full
2118 * variable-based interpolation intrinsic rather than a lowered version
2119 * with like we do for other inputs. We have to do that because the way
2120 * we set up inputs doesn't allow us to use the already setup inputs for
2121 * interpolation. At the beginning of the shader, we go through all of
2122 * the input variables and do the initial interpolation and put it in
2123 * the nir_inputs array based on its location as determined in
2124 * nir_lower_io. If the input isn't used, dead code cleans up and
2125 * everything works fine. However, when we get to the ARB_gpu_shader5
2126 * interpolation intrinsics, we need to reinterpolate the input
2127 * differently. If we used an intrinsic that just had an index it would
2128 * only give us the offset into the nir_inputs array. However, this is
2129 * useless because that value is post-interpolation and we need
2130 * pre-interpolation. In order to get the actual location of the bits
2131 * we get from the vertex fetching hardware, we need the variable.
2133 wm_prog_data
->pulls_bary
= true;
2135 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2136 const glsl_interp_qualifier interpolation
=
2137 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2139 switch (instr
->intrinsic
) {
2140 case nir_intrinsic_interp_var_at_centroid
:
2141 emit_pixel_interpolater_send(bld
,
2142 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2149 case nir_intrinsic_interp_var_at_sample
: {
2150 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2153 unsigned msg_data
= const_sample
->i32
[0] << 4;
2155 emit_pixel_interpolater_send(bld
,
2156 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2159 brw_imm_ud(msg_data
),
2162 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2163 BRW_REGISTER_TYPE_UD
);
2165 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2166 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2167 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2168 bld
.exec_all().group(1, 0)
2169 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2170 emit_pixel_interpolater_send(bld
,
2171 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2177 /* Make a loop that sends a message to the pixel interpolater
2178 * for the sample number in each live channel. If there are
2179 * multiple channels with the same sample number then these
2180 * will be handled simultaneously with a single interation of
2183 bld
.emit(BRW_OPCODE_DO
);
2185 /* Get the next live sample number into sample_id_reg */
2186 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2188 /* Set the flag register so that we can perform the send
2189 * message on all channels that have the same sample number
2191 bld
.CMP(bld
.null_reg_ud(),
2192 sample_src
, sample_id
,
2193 BRW_CONDITIONAL_EQ
);
2194 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2195 bld
.exec_all().group(1, 0)
2196 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2198 emit_pixel_interpolater_send(bld
,
2199 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2204 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2206 /* Continue the loop if there are any live channels left */
2207 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2209 bld
.emit(BRW_OPCODE_WHILE
));
2216 case nir_intrinsic_interp_var_at_offset
: {
2217 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2220 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2221 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2223 emit_pixel_interpolater_send(bld
,
2224 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2227 brw_imm_ud(off_x
| (off_y
<< 4)),
2230 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2231 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2232 BRW_REGISTER_TYPE_F
);
2233 for (int i
= 0; i
< 2; i
++) {
2234 fs_reg temp
= vgrf(glsl_type::float_type
);
2235 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2236 fs_reg itemp
= vgrf(glsl_type::int_type
);
2237 bld
.MOV(itemp
, temp
); /* float to int */
2239 /* Clamp the upper end of the range to +7/16.
2240 * ARB_gpu_shader5 requires that we support a maximum offset
2241 * of +0.5, which isn't representable in a S0.4 value -- if
2242 * we didn't clamp it, we'd end up with -8/16, which is the
2243 * opposite of what the shader author wanted.
2245 * This is legal due to ARB_gpu_shader5's quantization
2248 * "Not all values of <offset> may be supported; x and y
2249 * offsets may be rounded to fixed-point values with the
2250 * number of fraction bits given by the
2251 * implementation-dependent constant
2252 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2254 set_condmod(BRW_CONDITIONAL_L
,
2255 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2258 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2259 emit_pixel_interpolater_send(bld
,
2270 unreachable("Invalid intrinsic");
2273 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2274 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2275 src
.type
= dest
.type
;
2277 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2278 dest
= offset(dest
, bld
, 1);
2283 nir_emit_intrinsic(bld
, instr
);
2289 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2290 nir_intrinsic_instr
*instr
)
2292 assert(stage
== MESA_SHADER_COMPUTE
);
2293 struct brw_cs_prog_data
*cs_prog_data
=
2294 (struct brw_cs_prog_data
*) prog_data
;
2297 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2298 dest
= get_nir_dest(instr
->dest
);
2300 switch (instr
->intrinsic
) {
2301 case nir_intrinsic_barrier
:
2303 cs_prog_data
->uses_barrier
= true;
2306 case nir_intrinsic_load_local_invocation_id
:
2307 case nir_intrinsic_load_work_group_id
: {
2308 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2309 fs_reg val
= nir_system_values
[sv
];
2310 assert(val
.file
!= BAD_FILE
);
2311 dest
.type
= val
.type
;
2312 for (unsigned i
= 0; i
< 3; i
++)
2313 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2317 case nir_intrinsic_load_num_work_groups
: {
2318 const unsigned surface
=
2319 cs_prog_data
->binding_table
.work_groups_start
;
2321 cs_prog_data
->uses_num_work_groups
= true;
2323 fs_reg surf_index
= brw_imm_ud(surface
);
2324 brw_mark_surface_used(prog_data
, surface
);
2326 /* Read the 3 GLuint components of gl_NumWorkGroups */
2327 for (unsigned i
= 0; i
< 3; i
++) {
2328 fs_reg read_result
=
2329 emit_untyped_read(bld
, surf_index
,
2331 1 /* dims */, 1 /* size */,
2332 BRW_PREDICATE_NONE
);
2333 read_result
.type
= dest
.type
;
2334 bld
.MOV(dest
, read_result
);
2335 dest
= offset(dest
, bld
, 1);
2340 case nir_intrinsic_shared_atomic_add
:
2341 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2343 case nir_intrinsic_shared_atomic_imin
:
2344 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2346 case nir_intrinsic_shared_atomic_umin
:
2347 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2349 case nir_intrinsic_shared_atomic_imax
:
2350 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2352 case nir_intrinsic_shared_atomic_umax
:
2353 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2355 case nir_intrinsic_shared_atomic_and
:
2356 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2358 case nir_intrinsic_shared_atomic_or
:
2359 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2361 case nir_intrinsic_shared_atomic_xor
:
2362 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2364 case nir_intrinsic_shared_atomic_exchange
:
2365 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2367 case nir_intrinsic_shared_atomic_comp_swap
:
2368 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2371 case nir_intrinsic_load_shared
: {
2372 assert(devinfo
->gen
>= 7);
2374 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2376 /* Get the offset to read from */
2378 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2380 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
2382 offset_reg
= vgrf(glsl_type::uint_type
);
2384 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2385 brw_imm_ud(instr
->const_index
[0]));
2388 /* Read the vector */
2389 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2391 instr
->num_components
,
2392 BRW_PREDICATE_NONE
);
2393 read_result
.type
= dest
.type
;
2394 for (int i
= 0; i
< instr
->num_components
; i
++)
2395 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2400 case nir_intrinsic_store_shared
: {
2401 assert(devinfo
->gen
>= 7);
2404 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2407 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2410 unsigned writemask
= instr
->const_index
[1];
2412 /* Combine groups of consecutive enabled channels in one write
2413 * message. We use ffs to find the first enabled channel and then ffs on
2414 * the bit-inverse, down-shifted writemask to determine the length of
2415 * the block of enabled bits.
2418 unsigned first_component
= ffs(writemask
) - 1;
2419 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2422 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2424 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
2425 4 * first_component
);
2427 offset_reg
= vgrf(glsl_type::uint_type
);
2429 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2430 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2433 emit_untyped_write(bld
, surf_index
, offset_reg
,
2434 offset(val_reg
, bld
, first_component
),
2435 1 /* dims */, length
,
2436 BRW_PREDICATE_NONE
);
2438 /* Clear the bits in the writemask that we just wrote, then try
2439 * again to see if more channels are left.
2441 writemask
&= (15 << (first_component
+ length
));
2448 nir_emit_intrinsic(bld
, instr
);
2454 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2457 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2458 dest
= get_nir_dest(instr
->dest
);
2460 switch (instr
->intrinsic
) {
2461 case nir_intrinsic_atomic_counter_inc
:
2462 case nir_intrinsic_atomic_counter_dec
:
2463 case nir_intrinsic_atomic_counter_read
: {
2464 /* Get the arguments of the atomic intrinsic. */
2465 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2466 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2467 instr
->const_index
[0]);
2470 /* Emit a surface read or atomic op. */
2471 switch (instr
->intrinsic
) {
2472 case nir_intrinsic_atomic_counter_read
:
2473 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2476 case nir_intrinsic_atomic_counter_inc
:
2477 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2478 fs_reg(), 1, 1, BRW_AOP_INC
);
2481 case nir_intrinsic_atomic_counter_dec
:
2482 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2483 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2487 unreachable("Unreachable");
2490 /* Assign the result. */
2491 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2493 /* Mark the surface as used. */
2494 brw_mark_surface_used(stage_prog_data
, surface
);
2498 case nir_intrinsic_image_load
:
2499 case nir_intrinsic_image_store
:
2500 case nir_intrinsic_image_atomic_add
:
2501 case nir_intrinsic_image_atomic_min
:
2502 case nir_intrinsic_image_atomic_max
:
2503 case nir_intrinsic_image_atomic_and
:
2504 case nir_intrinsic_image_atomic_or
:
2505 case nir_intrinsic_image_atomic_xor
:
2506 case nir_intrinsic_image_atomic_exchange
:
2507 case nir_intrinsic_image_atomic_comp_swap
: {
2508 using namespace image_access
;
2510 /* Get the referenced image variable and type. */
2511 const nir_variable
*var
= instr
->variables
[0]->var
;
2512 const glsl_type
*type
= var
->type
->without_array();
2513 const brw_reg_type base_type
= get_image_base_type(type
);
2515 /* Get some metadata from the image intrinsic. */
2516 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2517 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2518 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2519 const mesa_format format
=
2520 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2521 _mesa_get_shader_image_format(var
->data
.image
.format
));
2523 /* Get the arguments of the image intrinsic. */
2524 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2525 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2526 BRW_REGISTER_TYPE_UD
);
2527 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2528 retype(get_nir_src(instr
->src
[2]), base_type
) :
2530 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2531 retype(get_nir_src(instr
->src
[3]), base_type
) :
2535 /* Emit an image load, store or atomic op. */
2536 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2537 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2539 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2540 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2543 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2544 surf_dims
, arr_dims
, info
->dest_components
,
2545 get_image_atomic_op(instr
->intrinsic
, type
));
2547 /* Assign the result. */
2548 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2549 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2550 offset(tmp
, bld
, c
));
2554 case nir_intrinsic_memory_barrier_atomic_counter
:
2555 case nir_intrinsic_memory_barrier_buffer
:
2556 case nir_intrinsic_memory_barrier_image
:
2557 case nir_intrinsic_memory_barrier
: {
2558 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2559 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2564 case nir_intrinsic_group_memory_barrier
:
2565 case nir_intrinsic_memory_barrier_shared
:
2566 /* We treat these workgroup-level barriers as no-ops. This should be
2567 * safe at present and as long as:
2569 * - Memory access instructions are not subsequently reordered by the
2570 * compiler back-end.
2572 * - All threads from a given compute shader workgroup fit within a
2573 * single subslice and therefore talk to the same HDC shared unit
2574 * what supposedly guarantees ordering and coherency between threads
2575 * from the same workgroup. This may change in the future when we
2576 * start splitting workgroups across multiple subslices.
2578 * - The context is not in fault-and-stream mode, which could cause
2579 * memory transactions (including to SLM) prior to the barrier to be
2580 * replayed after the barrier if a pagefault occurs. This shouldn't
2581 * be a problem up to and including SKL because fault-and-stream is
2582 * not usable due to hardware issues, but that's likely to change in
2587 case nir_intrinsic_shader_clock
: {
2588 /* We cannot do anything if there is an event, so ignore it for now */
2589 fs_reg shader_clock
= get_timestamp(bld
);
2590 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2592 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2596 case nir_intrinsic_image_size
: {
2597 /* Get the referenced image variable and type. */
2598 const nir_variable
*var
= instr
->variables
[0]->var
;
2599 const glsl_type
*type
= var
->type
->without_array();
2601 /* Get the size of the image. */
2602 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2603 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2605 /* For 1DArray image types, the array index is stored in the Z component.
2606 * Fix this by swizzling the Z component to the Y component.
2608 const bool is_1d_array_image
=
2609 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2610 type
->sampler_array
;
2612 /* For CubeArray images, we should count the number of cubes instead
2613 * of the number of faces. Fix it by dividing the (Z component) by 6.
2615 const bool is_cube_array_image
=
2616 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2617 type
->sampler_array
;
2619 /* Copy all the components. */
2620 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2621 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2622 if ((int)c
>= type
->coordinate_components()) {
2623 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2625 } else if (c
== 1 && is_1d_array_image
) {
2626 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2627 offset(size
, bld
, 2));
2628 } else if (c
== 2 && is_cube_array_image
) {
2629 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2630 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2631 offset(size
, bld
, c
), brw_imm_d(6));
2633 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2634 offset(size
, bld
, c
));
2641 case nir_intrinsic_image_samples
:
2642 /* The driver does not support multi-sampled images. */
2643 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2646 case nir_intrinsic_load_uniform
: {
2647 /* Offsets are in bytes but they should always be multiples of 4 */
2648 assert(instr
->const_index
[0] % 4 == 0);
2650 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2652 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2654 /* Offsets are in bytes but they should always be multiples of 4 */
2655 assert(const_offset
->u32
[0] % 4 == 0);
2656 src
.reg_offset
= const_offset
->u32
[0] / 4;
2658 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2661 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2662 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2667 case nir_intrinsic_load_ubo
: {
2668 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2672 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2673 const_index
->u32
[0];
2674 surf_index
= brw_imm_ud(index
);
2675 brw_mark_surface_used(prog_data
, index
);
2677 /* The block index is not a constant. Evaluate the index expression
2678 * per-channel and add the base UBO index; we have to select a value
2679 * from any live channel.
2681 surf_index
= vgrf(glsl_type::uint_type
);
2682 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2683 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2684 surf_index
= bld
.emit_uniformize(surf_index
);
2686 /* Assume this may touch any UBO. It would be nice to provide
2687 * a tighter bound, but the array information is already lowered away.
2689 brw_mark_surface_used(prog_data
,
2690 stage_prog_data
->binding_table
.ubo_start
+
2691 nir
->info
.num_ubos
- 1);
2694 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2695 if (const_offset
== NULL
) {
2696 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2697 BRW_REGISTER_TYPE_D
);
2699 for (int i
= 0; i
< instr
->num_components
; i
++)
2700 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2701 base_offset
, i
* 4);
2703 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2704 packed_consts
.type
= dest
.type
;
2706 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
2707 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2708 surf_index
, const_offset_reg
);
2710 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2711 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
2713 /* The std140 packing rules don't allow vectors to cross 16-byte
2714 * boundaries, and a reg is 32 bytes.
2716 assert(packed_consts
.subreg_offset
< 32);
2718 bld
.MOV(dest
, packed_consts
);
2719 dest
= offset(dest
, bld
, 1);
2725 case nir_intrinsic_load_ssbo
: {
2726 assert(devinfo
->gen
>= 7);
2728 nir_const_value
*const_uniform_block
=
2729 nir_src_as_const_value(instr
->src
[0]);
2732 if (const_uniform_block
) {
2733 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2734 const_uniform_block
->u32
[0];
2735 surf_index
= brw_imm_ud(index
);
2736 brw_mark_surface_used(prog_data
, index
);
2738 surf_index
= vgrf(glsl_type::uint_type
);
2739 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2740 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2742 /* Assume this may touch any UBO. It would be nice to provide
2743 * a tighter bound, but the array information is already lowered away.
2745 brw_mark_surface_used(prog_data
,
2746 stage_prog_data
->binding_table
.ssbo_start
+
2747 nir
->info
.num_ssbos
- 1);
2751 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2753 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
2755 offset_reg
= get_nir_src(instr
->src
[1]);
2758 /* Read the vector */
2759 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2761 instr
->num_components
,
2762 BRW_PREDICATE_NONE
);
2763 read_result
.type
= dest
.type
;
2764 for (int i
= 0; i
< instr
->num_components
; i
++)
2765 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2770 case nir_intrinsic_load_input
: {
2772 if (stage
== MESA_SHADER_VERTEX
) {
2773 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2775 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2776 instr
->const_index
[0]);
2779 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2780 assert(const_offset
&& "Indirect input loads not allowed");
2781 src
= offset(src
, bld
, const_offset
->u32
[0]);
2783 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2784 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2789 case nir_intrinsic_store_ssbo
: {
2790 assert(devinfo
->gen
>= 7);
2794 nir_const_value
*const_uniform_block
=
2795 nir_src_as_const_value(instr
->src
[1]);
2796 if (const_uniform_block
) {
2797 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2798 const_uniform_block
->u32
[0];
2799 surf_index
= brw_imm_ud(index
);
2800 brw_mark_surface_used(prog_data
, index
);
2802 surf_index
= vgrf(glsl_type::uint_type
);
2803 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2804 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2806 brw_mark_surface_used(prog_data
,
2807 stage_prog_data
->binding_table
.ssbo_start
+
2808 nir
->info
.num_ssbos
- 1);
2812 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2815 unsigned writemask
= instr
->const_index
[0];
2817 /* Combine groups of consecutive enabled channels in one write
2818 * message. We use ffs to find the first enabled channel and then ffs on
2819 * the bit-inverse, down-shifted writemask to determine the length of
2820 * the block of enabled bits.
2823 unsigned first_component
= ffs(writemask
) - 1;
2824 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2827 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2829 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
2831 offset_reg
= vgrf(glsl_type::uint_type
);
2833 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2834 brw_imm_ud(4 * first_component
));
2837 emit_untyped_write(bld
, surf_index
, offset_reg
,
2838 offset(val_reg
, bld
, first_component
),
2839 1 /* dims */, length
,
2840 BRW_PREDICATE_NONE
);
2842 /* Clear the bits in the writemask that we just wrote, then try
2843 * again to see if more channels are left.
2845 writemask
&= (15 << (first_component
+ length
));
2850 case nir_intrinsic_store_output
: {
2851 fs_reg src
= get_nir_src(instr
->src
[0]);
2852 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2853 instr
->const_index
[0]);
2855 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2856 assert(const_offset
&& "Indirect output stores not allowed");
2857 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
2859 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2860 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2865 case nir_intrinsic_ssbo_atomic_add
:
2866 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2868 case nir_intrinsic_ssbo_atomic_imin
:
2869 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2871 case nir_intrinsic_ssbo_atomic_umin
:
2872 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2874 case nir_intrinsic_ssbo_atomic_imax
:
2875 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2877 case nir_intrinsic_ssbo_atomic_umax
:
2878 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2880 case nir_intrinsic_ssbo_atomic_and
:
2881 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2883 case nir_intrinsic_ssbo_atomic_or
:
2884 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2886 case nir_intrinsic_ssbo_atomic_xor
:
2887 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2889 case nir_intrinsic_ssbo_atomic_exchange
:
2890 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2892 case nir_intrinsic_ssbo_atomic_comp_swap
:
2893 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2896 case nir_intrinsic_get_buffer_size
: {
2897 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2898 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
2899 int reg_width
= dispatch_width
/ 8;
2902 fs_reg source
= brw_imm_d(0);
2904 int mlen
= 1 * reg_width
;
2906 /* A resinfo's sampler message is used to get the buffer size.
2907 * The SIMD8's writeback message consists of four registers and
2908 * SIMD16's writeback message consists of 8 destination registers
2909 * (two per each component), although we are only interested on the
2910 * first component, where resinfo returns the buffer size for
2913 int regs_written
= 4 * mlen
;
2914 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2915 BRW_REGISTER_TYPE_UD
);
2916 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2917 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2918 BRW_REGISTER_TYPE_UD
);
2919 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2920 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2921 src_payload
, brw_imm_ud(index
));
2922 inst
->header_size
= 0;
2924 inst
->regs_written
= regs_written
;
2926 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2928 brw_mark_surface_used(prog_data
, index
);
2933 unreachable("unknown intrinsic");
2938 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2939 int op
, nir_intrinsic_instr
*instr
)
2942 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2943 dest
= get_nir_dest(instr
->dest
);
2946 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2947 if (const_surface
) {
2948 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2949 const_surface
->u32
[0];
2950 surface
= brw_imm_ud(surf_index
);
2951 brw_mark_surface_used(prog_data
, surf_index
);
2953 surface
= vgrf(glsl_type::uint_type
);
2954 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2955 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2957 /* Assume this may touch any SSBO. This is the same we do for other
2958 * UBO/SSBO accesses with non-constant surface.
2960 brw_mark_surface_used(prog_data
,
2961 stage_prog_data
->binding_table
.ssbo_start
+
2962 nir
->info
.num_ssbos
- 1);
2965 fs_reg offset
= get_nir_src(instr
->src
[1]);
2966 fs_reg data1
= get_nir_src(instr
->src
[2]);
2968 if (op
== BRW_AOP_CMPWR
)
2969 data2
= get_nir_src(instr
->src
[3]);
2971 /* Emit the actual atomic operation operation */
2973 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
2975 1 /* dims */, 1 /* rsize */,
2977 BRW_PREDICATE_NONE
);
2978 dest
.type
= atomic_result
.type
;
2979 bld
.MOV(dest
, atomic_result
);
2983 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2984 int op
, nir_intrinsic_instr
*instr
)
2987 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2988 dest
= get_nir_dest(instr
->dest
);
2990 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2991 fs_reg offset
= get_nir_src(instr
->src
[0]);
2992 fs_reg data1
= get_nir_src(instr
->src
[1]);
2994 if (op
== BRW_AOP_CMPWR
)
2995 data2
= get_nir_src(instr
->src
[2]);
2997 /* Emit the actual atomic operation operation */
2999 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3001 1 /* dims */, 1 /* rsize */,
3003 BRW_PREDICATE_NONE
);
3004 dest
.type
= atomic_result
.type
;
3005 bld
.MOV(dest
, atomic_result
);
3009 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3011 unsigned texture
= instr
->texture_index
;
3012 unsigned sampler
= instr
->sampler_index
;
3013 fs_reg
texture_reg(brw_imm_ud(texture
));
3014 fs_reg
sampler_reg(brw_imm_ud(sampler
));
3016 int gather_component
= instr
->component
;
3018 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3021 int lod_components
= 0;
3023 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
3025 /* The hardware requires a LOD for buffer textures */
3026 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3029 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3030 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3031 switch (instr
->src
[i
].src_type
) {
3032 case nir_tex_src_bias
:
3033 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3035 case nir_tex_src_comparitor
:
3036 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
3038 case nir_tex_src_coord
:
3039 switch (instr
->op
) {
3041 case nir_texop_txf_ms
:
3042 case nir_texop_samples_identical
:
3043 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
3046 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
3050 case nir_tex_src_ddx
:
3051 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3052 lod_components
= nir_tex_instr_src_size(instr
, i
);
3054 case nir_tex_src_ddy
:
3055 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
3057 case nir_tex_src_lod
:
3058 switch (instr
->op
) {
3060 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
3063 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
3066 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3070 case nir_tex_src_ms_index
:
3071 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
3074 case nir_tex_src_offset
: {
3075 nir_const_value
*const_offset
=
3076 nir_src_as_const_value(instr
->src
[i
].src
);
3078 tex_offset
= brw_imm_ud(brw_texture_offset(const_offset
->i32
, 3));
3080 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
3085 case nir_tex_src_projector
:
3086 unreachable("should be lowered");
3088 case nir_tex_src_texture_offset
: {
3089 /* Figure out the highest possible texture index and mark it as used */
3090 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3091 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3092 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3094 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3096 brw_mark_surface_used(prog_data
, max_used
);
3098 /* Emit code to evaluate the actual indexing expression */
3099 texture_reg
= vgrf(glsl_type::uint_type
);
3100 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3101 texture_reg
= bld
.emit_uniformize(texture_reg
);
3105 case nir_tex_src_sampler_offset
: {
3106 /* Emit code to evaluate the actual indexing expression */
3107 sampler_reg
= vgrf(glsl_type::uint_type
);
3108 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3109 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3114 unreachable("unknown texture source");
3118 if (instr
->op
== nir_texop_txf_ms
||
3119 instr
->op
== nir_texop_samples_identical
) {
3120 if (devinfo
->gen
>= 7 &&
3121 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3122 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3124 mcs
= brw_imm_ud(0u);
3128 enum glsl_base_type dest_base_type
=
3129 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3131 const glsl_type
*dest_type
=
3132 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3135 ir_texture_opcode op
;
3136 switch (instr
->op
) {
3137 case nir_texop_lod
: op
= ir_lod
; break;
3138 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3139 case nir_texop_tex
: op
= ir_tex
; break;
3140 case nir_texop_tg4
: op
= ir_tg4
; break;
3141 case nir_texop_txb
: op
= ir_txb
; break;
3142 case nir_texop_txd
: op
= ir_txd
; break;
3143 case nir_texop_txf
: op
= ir_txf
; break;
3144 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3145 case nir_texop_txl
: op
= ir_txl
; break;
3146 case nir_texop_txs
: op
= ir_txs
; break;
3147 case nir_texop_texture_samples
: {
3148 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3149 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3150 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3151 texture_reg
, texture_reg
);
3153 inst
->header_size
= 1;
3154 inst
->base_mrf
= -1;
3157 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3159 unreachable("unknown texture opcode");
3162 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3163 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3164 tex_offset
, mcs
, gather_component
, is_cube_array
,
3165 texture
, texture_reg
, sampler
, sampler_reg
);
3167 fs_reg dest
= get_nir_dest(instr
->dest
);
3168 dest
.type
= this->result
.type
;
3169 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3170 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3171 dest
, this->result
),
3172 (1 << num_components
) - 1);
3176 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3178 switch (instr
->type
) {
3179 case nir_jump_break
:
3180 bld
.emit(BRW_OPCODE_BREAK
);
3182 case nir_jump_continue
:
3183 bld
.emit(BRW_OPCODE_CONTINUE
);
3185 case nir_jump_return
:
3187 unreachable("unknown jump");