2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
36 fs_visitor::emit_nir_code()
38 nir_shader
*nir
= prog
->nir
;
40 /* emit the arrays used for inputs and outputs - load/store intrinsics will
41 * be converted to reads/writes of these arrays
43 nir_setup_inputs(nir
);
44 nir_setup_outputs(nir
);
45 nir_setup_uniforms(nir
);
46 nir_emit_system_values(nir
);
48 /* get the main function and emit it */
49 nir_foreach_overload(nir
, overload
) {
50 assert(strcmp(overload
->function
->name
, "main") == 0);
51 assert(overload
->impl
);
52 nir_emit_impl(overload
->impl
);
57 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_inputs
);
61 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
62 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
63 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
67 case MESA_SHADER_VERTEX
: {
68 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
69 * stored in nir_variable::location.
71 * However, NIR's load_input intrinsics use a different index - an
72 * offset into a single contiguous array containing all inputs.
73 * This index corresponds to the nir_variable::driver_location field.
75 * So, we need to copy from fs_reg(ATTR, var->location) to
76 * offset(nir_inputs, var->data.driver_location).
78 const glsl_type
*const t
= var
->type
->without_array();
79 const unsigned components
= t
->components();
80 const unsigned cols
= t
->matrix_columns
;
81 const unsigned elts
= t
->vector_elements
;
82 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
83 for (unsigned i
= 0; i
< array_length
; i
++) {
84 for (unsigned j
= 0; j
< cols
; j
++) {
85 for (unsigned k
= 0; k
< elts
; k
++) {
86 bld
.MOV(offset(retype(input
, type
), bld
,
87 components
* i
+ elts
* j
+ k
),
88 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
95 case MESA_SHADER_GEOMETRY
:
96 case MESA_SHADER_COMPUTE
:
97 case MESA_SHADER_TESS_CTRL
:
98 case MESA_SHADER_TESS_EVAL
:
99 unreachable("fs_visitor not used for these stages yet.");
101 case MESA_SHADER_FRAGMENT
:
102 if (var
->data
.location
== VARYING_SLOT_POS
) {
103 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
104 var
->data
.origin_upper_left
);
105 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
108 emit_general_interpolation(input
, var
->name
, var
->type
,
109 (glsl_interp_qualifier
) var
->data
.interpolation
,
110 var
->data
.location
, var
->data
.centroid
,
119 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
121 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
123 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_outputs
);
125 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
126 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
128 int vector_elements
=
129 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
130 : var
->type
->vector_elements
;
133 case MESA_SHADER_VERTEX
:
134 for (int i
= 0; i
< ALIGN(type_size_scalar(var
->type
), 4) / 4; i
++) {
135 int output
= var
->data
.location
+ i
;
136 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
137 this->output_components
[output
] = vector_elements
;
140 case MESA_SHADER_FRAGMENT
:
141 if (var
->data
.index
> 0) {
142 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
143 assert(var
->data
.index
== 1);
144 this->dual_src_output
= reg
;
145 this->do_dual_src
= true;
146 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
147 /* Writing gl_FragColor outputs to all color regions. */
148 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
149 this->outputs
[i
] = reg
;
150 this->output_components
[i
] = 4;
152 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
153 this->frag_depth
= reg
;
154 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
155 this->sample_mask
= reg
;
157 /* gl_FragData or a user-defined FS output */
158 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
159 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
161 /* General color output. */
162 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
163 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
164 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
165 this->output_components
[output
] = vector_elements
;
170 unreachable("unhandled shader stage");
176 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
178 num_direct_uniforms
= shader
->num_direct_uniforms
;
180 if (dispatch_width
!= 8)
183 /* We split the uniform register file in half. The first half is
184 * entirely direct uniforms. The second half is indirect.
186 if (num_direct_uniforms
> 0)
187 param_size
[0] = num_direct_uniforms
;
188 if (shader
->num_uniforms
> num_direct_uniforms
)
189 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
191 uniforms
= shader
->num_uniforms
;
194 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
195 /* UBO's and atomics don't take up space in the uniform file */
196 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
199 if (strncmp(var
->name
, "gl_", 3) == 0)
200 nir_setup_builtin_uniform(var
);
202 nir_setup_uniform(var
);
205 /* prog_to_nir doesn't create uniform variables; set param up directly. */
206 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
207 for (unsigned int i
= 0; i
< 4; i
++) {
208 stage_prog_data
->param
[4 * p
+ i
] =
209 &prog
->Parameters
->ParameterValues
[p
][i
];
216 fs_visitor::nir_setup_uniform(nir_variable
*var
)
218 int namelen
= strlen(var
->name
);
220 /* The data for our (non-builtin) uniforms is stored in a series of
221 * gl_uniform_driver_storage structs for each subcomponent that
222 * glGetUniformLocation() could name. We know it's been set up in the
223 * same order we'd walk the type, so walk the list of storage and find
224 * anything with our name, or the prefix of a component that starts with
227 unsigned index
= var
->data
.driver_location
;
228 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
229 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
231 if (storage
->builtin
)
234 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
235 (storage
->name
[namelen
] != 0 &&
236 storage
->name
[namelen
] != '.' &&
237 storage
->name
[namelen
] != '[')) {
241 if (storage
->type
->is_image()) {
242 /* Images don't get a valid location assigned by nir_lower_io()
243 * because their size is driver-specific, so we need to allocate
244 * space for them here at the end of the parameter array.
246 var
->data
.driver_location
= uniforms
;
248 BRW_IMAGE_PARAM_SIZE
* MAX2(storage
->array_elements
, 1);
250 setup_image_uniform_values(uniforms
, storage
);
252 param_size
[uniforms
] = size
;
255 unsigned slots
= storage
->type
->component_slots();
256 if (storage
->array_elements
)
257 slots
*= storage
->array_elements
;
259 for (unsigned i
= 0; i
< slots
; i
++) {
260 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
267 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
269 const nir_state_slot
*const slots
= var
->state_slots
;
270 assert(var
->state_slots
!= NULL
);
272 unsigned uniform_index
= var
->data
.driver_location
;
273 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
274 /* This state reference has already been setup by ir_to_mesa, but we'll
275 * get the same index back here.
277 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
278 (gl_state_index
*)slots
[i
].tokens
);
280 /* Add each of the unique swizzles of the element as a parameter.
281 * This'll end up matching the expected layout of the
282 * array/matrix/structure we're trying to fill in.
285 for (unsigned int j
= 0; j
< 4; j
++) {
286 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
287 if (swiz
== last_swiz
)
291 stage_prog_data
->param
[uniform_index
++] =
292 &prog
->Parameters
->ParameterValues
[index
][swiz
];
298 emit_system_values_block(nir_block
*block
, void *void_visitor
)
300 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
303 nir_foreach_instr(block
, instr
) {
304 if (instr
->type
!= nir_instr_type_intrinsic
)
307 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
308 switch (intrin
->intrinsic
) {
309 case nir_intrinsic_load_vertex_id
:
310 unreachable("should be lowered by lower_vertex_id().");
312 case nir_intrinsic_load_vertex_id_zero_base
:
313 assert(v
->stage
== MESA_SHADER_VERTEX
);
314 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
315 if (reg
->file
== BAD_FILE
)
316 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
319 case nir_intrinsic_load_base_vertex
:
320 assert(v
->stage
== MESA_SHADER_VERTEX
);
321 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
322 if (reg
->file
== BAD_FILE
)
323 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
326 case nir_intrinsic_load_instance_id
:
327 assert(v
->stage
== MESA_SHADER_VERTEX
);
328 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
329 if (reg
->file
== BAD_FILE
)
330 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
333 case nir_intrinsic_load_sample_pos
:
334 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
335 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
336 if (reg
->file
== BAD_FILE
)
337 *reg
= *v
->emit_samplepos_setup();
340 case nir_intrinsic_load_sample_id
:
341 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
342 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
343 if (reg
->file
== BAD_FILE
)
344 *reg
= *v
->emit_sampleid_setup();
347 case nir_intrinsic_load_sample_mask_in
:
348 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
349 assert(v
->devinfo
->gen
>= 7);
350 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
351 if (reg
->file
== BAD_FILE
)
352 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
353 BRW_REGISTER_TYPE_D
));
365 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
367 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
368 nir_foreach_overload(shader
, overload
) {
369 assert(strcmp(overload
->function
->name
, "main") == 0);
370 assert(overload
->impl
);
371 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
376 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
378 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
379 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
380 unsigned array_elems
=
381 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
382 unsigned size
= array_elems
* reg
->num_components
;
383 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
386 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
389 nir_emit_cf_list(&impl
->body
);
393 fs_visitor::nir_emit_cf_list(exec_list
*list
)
395 exec_list_validate(list
);
396 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
397 switch (node
->type
) {
399 nir_emit_if(nir_cf_node_as_if(node
));
402 case nir_cf_node_loop
:
403 nir_emit_loop(nir_cf_node_as_loop(node
));
406 case nir_cf_node_block
:
407 nir_emit_block(nir_cf_node_as_block(node
));
411 unreachable("Invalid CFG node block");
417 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
419 /* first, put the condition into f0 */
420 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
421 retype(get_nir_src(if_stmt
->condition
),
422 BRW_REGISTER_TYPE_D
));
423 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
425 bld
.IF(BRW_PREDICATE_NORMAL
);
427 nir_emit_cf_list(&if_stmt
->then_list
);
429 /* note: if the else is empty, dead CF elimination will remove it */
430 bld
.emit(BRW_OPCODE_ELSE
);
432 nir_emit_cf_list(&if_stmt
->else_list
);
434 bld
.emit(BRW_OPCODE_ENDIF
);
436 try_replace_with_sel();
440 fs_visitor::nir_emit_loop(nir_loop
*loop
)
442 bld
.emit(BRW_OPCODE_DO
);
444 nir_emit_cf_list(&loop
->body
);
446 bld
.emit(BRW_OPCODE_WHILE
);
450 fs_visitor::nir_emit_block(nir_block
*block
)
452 nir_foreach_instr(block
, instr
) {
453 nir_emit_instr(instr
);
458 fs_visitor::nir_emit_instr(nir_instr
*instr
)
460 const fs_builder abld
= bld
.annotate(NULL
, instr
);
462 switch (instr
->type
) {
463 case nir_instr_type_alu
:
464 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
467 case nir_instr_type_intrinsic
:
468 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case nir_instr_type_tex
:
472 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
475 case nir_instr_type_load_const
:
476 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
479 case nir_instr_type_ssa_undef
:
480 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
483 case nir_instr_type_jump
:
484 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
488 unreachable("unknown instruction type");
493 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
494 const fs_reg
&result
)
496 if (!instr
->src
[0].src
.is_ssa
||
497 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
500 nir_intrinsic_instr
*src0
=
501 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
503 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
506 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
507 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
510 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
511 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
514 fs_reg tmp
= vgrf(glsl_type::int_type
);
516 if (devinfo
->gen
>= 6) {
517 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
518 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
520 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
522 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
523 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
525 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
527 * This negation looks like it's safe in practice, because bits 0:4 will
528 * surely be TRIANGLES
531 if (value1
->f
[0] == -1.0f
) {
535 tmp
.type
= BRW_REGISTER_TYPE_W
;
536 tmp
.subreg_offset
= 2;
539 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
540 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
542 tmp
.type
= BRW_REGISTER_TYPE_D
;
543 tmp
.subreg_offset
= 0;
546 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
547 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
549 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
551 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
552 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
554 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
556 * This negation looks like it's safe in practice, because bits 0:4 will
557 * surely be TRIANGLES
560 if (value1
->f
[0] == -1.0f
) {
564 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
566 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
572 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
574 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
577 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
578 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
581 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
582 op
[i
] = get_nir_src(instr
->src
[i
].src
);
583 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
584 op
[i
].abs
= instr
->src
[i
].abs
;
585 op
[i
].negate
= instr
->src
[i
].negate
;
588 /* We get a bunch of mov's out of the from_ssa pass and they may still
589 * be vectorized. We'll handle them as a special-case. We'll also
590 * handle vecN here because it's basically the same thing.
598 fs_reg temp
= result
;
599 bool need_extra_copy
= false;
600 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
601 if (!instr
->src
[i
].src
.is_ssa
&&
602 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
603 need_extra_copy
= true;
604 temp
= bld
.vgrf(result
.type
, 4);
609 for (unsigned i
= 0; i
< 4; i
++) {
610 if (!(instr
->dest
.write_mask
& (1 << i
)))
613 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
614 inst
= bld
.MOV(offset(temp
, bld
, i
),
615 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
617 inst
= bld
.MOV(offset(temp
, bld
, i
),
618 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
620 inst
->saturate
= instr
->dest
.saturate
;
623 /* In this case the source and destination registers were the same,
624 * so we need to insert an extra set of moves in order to deal with
627 if (need_extra_copy
) {
628 for (unsigned i
= 0; i
< 4; i
++) {
629 if (!(instr
->dest
.write_mask
& (1 << i
)))
632 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
641 /* At this point, we have dealt with any instruction that operates on
642 * more than a single channel. Therefore, we can just adjust the source
643 * and destination registers for that channel and emit the instruction.
645 unsigned channel
= 0;
646 if (nir_op_infos
[instr
->op
].output_size
== 0) {
647 /* Since NIR is doing the scalarizing for us, we should only ever see
648 * vectorized operations with a single channel.
650 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
651 channel
= ffs(instr
->dest
.write_mask
) - 1;
653 result
= offset(result
, bld
, channel
);
656 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
657 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
658 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
664 inst
= bld
.MOV(result
, op
[0]);
665 inst
->saturate
= instr
->dest
.saturate
;
670 bld
.MOV(result
, op
[0]);
674 /* AND(val, 0x80000000) gives the sign bit.
676 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
679 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
681 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
682 op
[0].type
= BRW_REGISTER_TYPE_UD
;
683 result
.type
= BRW_REGISTER_TYPE_UD
;
684 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
686 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
687 inst
->predicate
= BRW_PREDICATE_NORMAL
;
688 if (instr
->dest
.saturate
) {
689 inst
= bld
.MOV(result
, result
);
690 inst
->saturate
= true;
696 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
697 * -> non-negative val generates 0x00000000.
698 * Predicated OR sets 1 if val is positive.
700 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
701 bld
.ASR(result
, op
[0], fs_reg(31));
702 inst
= bld
.OR(result
, result
, fs_reg(1));
703 inst
->predicate
= BRW_PREDICATE_NORMAL
;
707 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
708 inst
->saturate
= instr
->dest
.saturate
;
712 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
713 inst
->saturate
= instr
->dest
.saturate
;
717 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
718 inst
->saturate
= instr
->dest
.saturate
;
722 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
723 inst
->saturate
= instr
->dest
.saturate
;
727 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
728 inst
->saturate
= instr
->dest
.saturate
;
732 if (fs_key
->high_quality_derivatives
) {
733 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
735 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
737 inst
->saturate
= instr
->dest
.saturate
;
739 case nir_op_fddx_fine
:
740 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
741 inst
->saturate
= instr
->dest
.saturate
;
743 case nir_op_fddx_coarse
:
744 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
745 inst
->saturate
= instr
->dest
.saturate
;
748 if (fs_key
->high_quality_derivatives
) {
749 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
750 fs_reg(fs_key
->render_to_fbo
));
752 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
753 fs_reg(fs_key
->render_to_fbo
));
755 inst
->saturate
= instr
->dest
.saturate
;
757 case nir_op_fddy_fine
:
758 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
759 fs_reg(fs_key
->render_to_fbo
));
760 inst
->saturate
= instr
->dest
.saturate
;
762 case nir_op_fddy_coarse
:
763 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
764 fs_reg(fs_key
->render_to_fbo
));
765 inst
->saturate
= instr
->dest
.saturate
;
770 inst
= bld
.ADD(result
, op
[0], op
[1]);
771 inst
->saturate
= instr
->dest
.saturate
;
775 inst
= bld
.MUL(result
, op
[0], op
[1]);
776 inst
->saturate
= instr
->dest
.saturate
;
780 bld
.MUL(result
, op
[0], op
[1]);
783 case nir_op_imul_high
:
784 case nir_op_umul_high
:
785 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
790 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
793 case nir_op_uadd_carry
:
794 unreachable("Should have been lowered by carry_to_arith().");
796 case nir_op_usub_borrow
:
797 unreachable("Should have been lowered by borrow_to_arith().");
800 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
806 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
812 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
817 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
822 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
826 if (devinfo
->gen
>= 8) {
827 op
[0] = resolve_source_modifiers(op
[0]);
829 bld
.NOT(result
, op
[0]);
832 if (devinfo
->gen
>= 8) {
833 op
[0] = resolve_source_modifiers(op
[0]);
834 op
[1] = resolve_source_modifiers(op
[1]);
836 bld
.XOR(result
, op
[0], op
[1]);
839 if (devinfo
->gen
>= 8) {
840 op
[0] = resolve_source_modifiers(op
[0]);
841 op
[1] = resolve_source_modifiers(op
[1]);
843 bld
.OR(result
, op
[0], op
[1]);
846 if (devinfo
->gen
>= 8) {
847 op
[0] = resolve_source_modifiers(op
[0]);
848 op
[1] = resolve_source_modifiers(op
[1]);
850 bld
.AND(result
, op
[0], op
[1]);
862 case nir_op_ball_fequal2
:
863 case nir_op_ball_iequal2
:
864 case nir_op_ball_fequal3
:
865 case nir_op_ball_iequal3
:
866 case nir_op_ball_fequal4
:
867 case nir_op_ball_iequal4
:
868 case nir_op_bany_fnequal2
:
869 case nir_op_bany_inequal2
:
870 case nir_op_bany_fnequal3
:
871 case nir_op_bany_inequal3
:
872 case nir_op_bany_fnequal4
:
873 case nir_op_bany_inequal4
:
874 unreachable("Lowered by nir_lower_alu_reductions");
876 case nir_op_fnoise1_1
:
877 case nir_op_fnoise1_2
:
878 case nir_op_fnoise1_3
:
879 case nir_op_fnoise1_4
:
880 case nir_op_fnoise2_1
:
881 case nir_op_fnoise2_2
:
882 case nir_op_fnoise2_3
:
883 case nir_op_fnoise2_4
:
884 case nir_op_fnoise3_1
:
885 case nir_op_fnoise3_2
:
886 case nir_op_fnoise3_3
:
887 case nir_op_fnoise3_4
:
888 case nir_op_fnoise4_1
:
889 case nir_op_fnoise4_2
:
890 case nir_op_fnoise4_3
:
891 case nir_op_fnoise4_4
:
892 unreachable("not reached: should be handled by lower_noise");
895 unreachable("not reached: should be handled by ldexp_to_arith()");
898 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
903 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
904 inst
->saturate
= instr
->dest
.saturate
;
909 bld
.MOV(result
, negate(op
[0]));
913 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
916 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
920 inst
= bld
.RNDZ(result
, op
[0]);
921 inst
->saturate
= instr
->dest
.saturate
;
925 op
[0].negate
= !op
[0].negate
;
926 fs_reg temp
= vgrf(glsl_type::float_type
);
927 bld
.RNDD(temp
, op
[0]);
929 inst
= bld
.MOV(result
, temp
);
930 inst
->saturate
= instr
->dest
.saturate
;
934 inst
= bld
.RNDD(result
, op
[0]);
935 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.FRC(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
941 case nir_op_fround_even
:
942 inst
= bld
.RNDE(result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
949 if (devinfo
->gen
>= 6) {
950 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
951 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
953 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
954 inst
= bld
.SEL(result
, op
[0], op
[1]);
955 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 inst
->saturate
= instr
->dest
.saturate
;
963 if (devinfo
->gen
>= 6) {
964 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
965 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
967 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
968 inst
= bld
.SEL(result
, op
[0], op
[1]);
969 inst
->predicate
= BRW_PREDICATE_NORMAL
;
971 inst
->saturate
= instr
->dest
.saturate
;
974 case nir_op_pack_snorm_2x16
:
975 case nir_op_pack_snorm_4x8
:
976 case nir_op_pack_unorm_2x16
:
977 case nir_op_pack_unorm_4x8
:
978 case nir_op_unpack_snorm_2x16
:
979 case nir_op_unpack_snorm_4x8
:
980 case nir_op_unpack_unorm_2x16
:
981 case nir_op_unpack_unorm_4x8
:
982 case nir_op_unpack_half_2x16
:
983 case nir_op_pack_half_2x16
:
984 unreachable("not reached: should be handled by lower_packing_builtins");
986 case nir_op_unpack_half_2x16_split_x
:
987 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
988 inst
->saturate
= instr
->dest
.saturate
;
990 case nir_op_unpack_half_2x16_split_y
:
991 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
992 inst
->saturate
= instr
->dest
.saturate
;
996 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
997 inst
->saturate
= instr
->dest
.saturate
;
1000 case nir_op_bitfield_reverse
:
1001 bld
.BFREV(result
, op
[0]);
1004 case nir_op_bit_count
:
1005 bld
.CBIT(result
, op
[0]);
1008 case nir_op_ufind_msb
:
1009 case nir_op_ifind_msb
: {
1010 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1012 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1013 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1014 * subtract the result from 31 to convert the MSB count into an LSB count.
1017 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1018 fs_reg
neg_result(result
);
1019 neg_result
.negate
= true;
1020 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1021 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1025 case nir_op_find_lsb
:
1026 bld
.FBL(result
, op
[0]);
1029 case nir_op_ubitfield_extract
:
1030 case nir_op_ibitfield_extract
:
1031 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1034 bld
.BFI1(result
, op
[0], op
[1]);
1037 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1040 case nir_op_bitfield_insert
:
1041 unreachable("not reached: should be handled by "
1042 "lower_instructions::bitfield_insert_to_bfm_bfi");
1045 bld
.SHL(result
, op
[0], op
[1]);
1048 bld
.ASR(result
, op
[0], op
[1]);
1051 bld
.SHR(result
, op
[0], op
[1]);
1054 case nir_op_pack_half_2x16_split
:
1055 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1059 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1060 inst
->saturate
= instr
->dest
.saturate
;
1064 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1065 inst
->saturate
= instr
->dest
.saturate
;
1069 if (optimize_frontfacing_ternary(instr
, result
))
1072 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1073 inst
= bld
.SEL(result
, op
[1], op
[2]);
1074 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1078 unreachable("unhandled instruction");
1081 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1082 * to sign extend the low bit to 0/~0
1084 if (devinfo
->gen
<= 5 &&
1085 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1086 fs_reg masked
= vgrf(glsl_type::int_type
);
1087 bld
.AND(masked
, result
, fs_reg(1));
1088 masked
.negate
= true;
1089 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1094 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1095 nir_load_const_instr
*instr
)
1097 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1099 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1100 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1102 nir_ssa_values
[instr
->def
.index
] = reg
;
1106 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1108 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1109 instr
->def
.num_components
);
1113 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1114 unsigned base_offset
, nir_src
*indirect
)
1118 assert(!nir_reg
->is_global
);
1120 reg
= v
->nir_locals
[nir_reg
->index
];
1122 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1124 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1126 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1127 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1128 fs_reg(multiplier
));
1135 fs_visitor::get_nir_src(nir_src src
)
1139 reg
= nir_ssa_values
[src
.ssa
->index
];
1141 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1145 /* to avoid floating-point denorm flushing problems, set the type by
1146 * default to D - instructions that need floating point semantics will set
1147 * this to F if they need to
1149 return retype(reg
, BRW_REGISTER_TYPE_D
);
1153 fs_visitor::get_nir_dest(nir_dest dest
)
1156 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1157 dest
.ssa
.num_components
);
1158 return nir_ssa_values
[dest
.ssa
.index
];
1161 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1166 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1168 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1169 BRW_REGISTER_TYPE_UD
);
1171 if (deref
->deref
.child
) {
1172 const nir_deref_array
*deref_array
=
1173 nir_deref_as_array(deref
->deref
.child
);
1174 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1175 deref_array
->deref
.child
== NULL
);
1176 const unsigned size
= glsl_get_length(deref
->var
->type
);
1177 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1179 image
= offset(image
, bld
, base
* BRW_IMAGE_PARAM_SIZE
);
1181 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1182 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1184 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1185 /* IVB hangs when trying to access an invalid surface index with
1186 * the dataport. According to the spec "if the index used to
1187 * select an individual element is negative or greater than or
1188 * equal to the size of the array, the results of the operation
1189 * are undefined but may not lead to termination" -- which is one
1190 * of the possible outcomes of the hang. Clamp the index to
1191 * prevent access outside of the array bounds.
1193 bld
.emit_minmax(*tmp
, retype(get_nir_src(deref_array
->indirect
),
1194 BRW_REGISTER_TYPE_UD
),
1195 fs_reg(size
- base
- 1), BRW_CONDITIONAL_L
);
1197 bld
.MOV(*tmp
, get_nir_src(deref_array
->indirect
));
1200 bld
.MUL(*tmp
, *tmp
, fs_reg(BRW_IMAGE_PARAM_SIZE
));
1201 image
.reladdr
= tmp
;
1209 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1212 for (unsigned i
= 0; i
< 4; i
++) {
1213 if (!((wr_mask
>> i
) & 1))
1216 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1217 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1218 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1219 if (new_inst
->src
[j
].file
== GRF
)
1220 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1227 * Get the matching channel register datatype for an image intrinsic of the
1228 * specified GLSL image type.
1231 get_image_base_type(const glsl_type
*type
)
1233 switch ((glsl_base_type
)type
->sampler_type
) {
1234 case GLSL_TYPE_UINT
:
1235 return BRW_REGISTER_TYPE_UD
;
1237 return BRW_REGISTER_TYPE_D
;
1238 case GLSL_TYPE_FLOAT
:
1239 return BRW_REGISTER_TYPE_F
;
1241 unreachable("Not reached.");
1246 * Get the appropriate atomic op for an image atomic intrinsic.
1249 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1252 case nir_intrinsic_image_atomic_add
:
1254 case nir_intrinsic_image_atomic_min
:
1255 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1256 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1257 case nir_intrinsic_image_atomic_max
:
1258 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1259 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1260 case nir_intrinsic_image_atomic_and
:
1262 case nir_intrinsic_image_atomic_or
:
1264 case nir_intrinsic_image_atomic_xor
:
1266 case nir_intrinsic_image_atomic_exchange
:
1268 case nir_intrinsic_image_atomic_comp_swap
:
1269 return BRW_AOP_CMPWR
;
1271 unreachable("Not reachable.");
1276 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1279 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1280 dest
= get_nir_dest(instr
->dest
);
1282 bool has_indirect
= false;
1284 switch (instr
->intrinsic
) {
1285 case nir_intrinsic_discard
:
1286 case nir_intrinsic_discard_if
: {
1287 /* We track our discarded pixels in f0.1. By predicating on it, we can
1288 * update just the flag bits that aren't yet discarded. If there's no
1289 * condition, we emit a CMP of g0 != g0, so all currently executing
1290 * channels will get turned off.
1293 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1294 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1295 fs_reg(0), BRW_CONDITIONAL_Z
);
1297 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1298 BRW_REGISTER_TYPE_UW
));
1299 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1301 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1302 cmp
->flag_subreg
= 1;
1304 if (devinfo
->gen
>= 6) {
1305 emit_discard_jump();
1310 case nir_intrinsic_atomic_counter_inc
:
1311 case nir_intrinsic_atomic_counter_dec
:
1312 case nir_intrinsic_atomic_counter_read
: {
1313 using namespace surface_access
;
1315 /* Get the arguments of the atomic intrinsic. */
1316 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1317 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1318 instr
->const_index
[0]);
1321 /* Emit a surface read or atomic op. */
1322 switch (instr
->intrinsic
) {
1323 case nir_intrinsic_atomic_counter_read
:
1324 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1327 case nir_intrinsic_atomic_counter_inc
:
1328 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1329 fs_reg(), 1, 1, BRW_AOP_INC
);
1332 case nir_intrinsic_atomic_counter_dec
:
1333 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1334 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1338 unreachable("Unreachable");
1341 /* Assign the result. */
1342 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1344 /* Mark the surface as used. */
1345 brw_mark_surface_used(stage_prog_data
, surface
);
1349 case nir_intrinsic_image_load
:
1350 case nir_intrinsic_image_store
:
1351 case nir_intrinsic_image_atomic_add
:
1352 case nir_intrinsic_image_atomic_min
:
1353 case nir_intrinsic_image_atomic_max
:
1354 case nir_intrinsic_image_atomic_and
:
1355 case nir_intrinsic_image_atomic_or
:
1356 case nir_intrinsic_image_atomic_xor
:
1357 case nir_intrinsic_image_atomic_exchange
:
1358 case nir_intrinsic_image_atomic_comp_swap
: {
1359 using namespace image_access
;
1361 /* Get the referenced image variable and type. */
1362 const nir_variable
*var
= instr
->variables
[0]->var
;
1363 const glsl_type
*type
= var
->type
->without_array();
1364 const brw_reg_type base_type
= get_image_base_type(type
);
1366 /* Get some metadata from the image intrinsic. */
1367 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1368 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
1369 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
1370 const mesa_format format
=
1371 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
1372 _mesa_get_shader_image_format(var
->data
.image
.format
));
1374 /* Get the arguments of the image intrinsic. */
1375 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1376 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
1377 BRW_REGISTER_TYPE_UD
);
1378 const fs_reg src0
= (info
->num_srcs
>= 3 ?
1379 retype(get_nir_src(instr
->src
[2]), base_type
) :
1381 const fs_reg src1
= (info
->num_srcs
>= 4 ?
1382 retype(get_nir_src(instr
->src
[3]), base_type
) :
1386 /* Emit an image load, store or atomic op. */
1387 if (instr
->intrinsic
== nir_intrinsic_image_load
)
1388 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
1390 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
1391 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
1394 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
1395 surf_dims
, arr_dims
, info
->dest_components
,
1396 get_image_atomic_op(instr
->intrinsic
, type
));
1398 /* Assign the result. */
1399 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
1400 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
1401 offset(tmp
, bld
, c
));
1405 case nir_intrinsic_memory_barrier
: {
1406 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1407 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1412 case nir_intrinsic_image_size
: {
1413 /* Get the referenced image variable and type. */
1414 const nir_variable
*var
= instr
->variables
[0]->var
;
1415 const glsl_type
*type
= var
->type
->without_array();
1417 /* Get the size of the image. */
1418 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1419 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
1421 /* For 1DArray image types, the array index is stored in the Z component.
1422 * Fix this by swizzling the Z component to the Y component.
1424 const bool is_1d_array_image
=
1425 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
1426 type
->sampler_array
;
1428 /* For CubeArray images, we should count the number of cubes instead
1429 * of the number of faces. Fix it by dividing the (Z component) by 6.
1431 const bool is_cube_array_image
=
1432 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1433 type
->sampler_array
;
1435 /* Copy all the components. */
1436 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1437 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
1438 if ((int)c
>= type
->coordinate_components()) {
1439 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1441 } else if (c
== 1 && is_1d_array_image
) {
1442 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1443 offset(size
, bld
, 2));
1444 } else if (c
== 2 && is_cube_array_image
) {
1445 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
1446 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1447 offset(size
, bld
, c
), fs_reg(6));
1449 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1450 offset(size
, bld
, c
));
1457 case nir_intrinsic_load_front_face
:
1458 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1459 *emit_frontfacing_interpolation());
1462 case nir_intrinsic_load_vertex_id
:
1463 unreachable("should be lowered by lower_vertex_id()");
1465 case nir_intrinsic_load_vertex_id_zero_base
: {
1466 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1467 assert(vertex_id
.file
!= BAD_FILE
);
1468 dest
.type
= vertex_id
.type
;
1469 bld
.MOV(dest
, vertex_id
);
1473 case nir_intrinsic_load_base_vertex
: {
1474 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1475 assert(base_vertex
.file
!= BAD_FILE
);
1476 dest
.type
= base_vertex
.type
;
1477 bld
.MOV(dest
, base_vertex
);
1481 case nir_intrinsic_load_instance_id
: {
1482 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1483 assert(instance_id
.file
!= BAD_FILE
);
1484 dest
.type
= instance_id
.type
;
1485 bld
.MOV(dest
, instance_id
);
1489 case nir_intrinsic_load_sample_mask_in
: {
1490 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1491 assert(sample_mask_in
.file
!= BAD_FILE
);
1492 dest
.type
= sample_mask_in
.type
;
1493 bld
.MOV(dest
, sample_mask_in
);
1497 case nir_intrinsic_load_sample_pos
: {
1498 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1499 assert(sample_pos
.file
!= BAD_FILE
);
1500 dest
.type
= sample_pos
.type
;
1501 bld
.MOV(dest
, sample_pos
);
1502 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1506 case nir_intrinsic_load_sample_id
: {
1507 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1508 assert(sample_id
.file
!= BAD_FILE
);
1509 dest
.type
= sample_id
.type
;
1510 bld
.MOV(dest
, sample_id
);
1514 case nir_intrinsic_load_uniform_indirect
:
1515 has_indirect
= true;
1517 case nir_intrinsic_load_uniform
: {
1518 unsigned index
= instr
->const_index
[0];
1521 if (index
< num_direct_uniforms
) {
1522 uniform_reg
= fs_reg(UNIFORM
, 0);
1524 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1525 index
-= num_direct_uniforms
;
1528 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1529 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1531 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1535 dest
= offset(dest
, bld
, 1);
1540 case nir_intrinsic_load_ubo_indirect
:
1541 has_indirect
= true;
1543 case nir_intrinsic_load_ubo
: {
1544 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1548 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1551 /* The block index is not a constant. Evaluate the index expression
1552 * per-channel and add the base UBO index; we have to select a value
1553 * from any live channel.
1555 surf_index
= vgrf(glsl_type::uint_type
);
1556 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1557 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1558 surf_index
= bld
.emit_uniformize(surf_index
);
1560 /* Assume this may touch any UBO. It would be nice to provide
1561 * a tighter bound, but the array information is already lowered away.
1563 brw_mark_surface_used(prog_data
,
1564 stage_prog_data
->binding_table
.ubo_start
+
1565 shader_prog
->NumUniformBlocks
- 1);
1569 /* Turn the byte offset into a dword offset. */
1570 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1571 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1572 BRW_REGISTER_TYPE_D
),
1575 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1576 for (int i
= 0; i
< instr
->num_components
; i
++)
1577 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1578 base_offset
, vec4_offset
+ i
);
1580 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1581 packed_consts
.type
= dest
.type
;
1583 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1584 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1585 surf_index
, const_offset_reg
);
1587 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1588 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1590 /* The std140 packing rules don't allow vectors to cross 16-byte
1591 * boundaries, and a reg is 32 bytes.
1593 assert(packed_consts
.subreg_offset
< 32);
1595 bld
.MOV(dest
, packed_consts
);
1596 dest
= offset(dest
, bld
, 1);
1602 case nir_intrinsic_load_input_indirect
:
1603 has_indirect
= true;
1605 case nir_intrinsic_load_input
: {
1607 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1608 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1609 instr
->const_index
[0] + index
);
1611 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1615 dest
= offset(dest
, bld
, 1);
1620 /* Handle ARB_gpu_shader5 interpolation intrinsics
1622 * It's worth a quick word of explanation as to why we handle the full
1623 * variable-based interpolation intrinsic rather than a lowered version
1624 * with like we do for other inputs. We have to do that because the way
1625 * we set up inputs doesn't allow us to use the already setup inputs for
1626 * interpolation. At the beginning of the shader, we go through all of
1627 * the input variables and do the initial interpolation and put it in
1628 * the nir_inputs array based on its location as determined in
1629 * nir_lower_io. If the input isn't used, dead code cleans up and
1630 * everything works fine. However, when we get to the ARB_gpu_shader5
1631 * interpolation intrinsics, we need to reinterpolate the input
1632 * differently. If we used an intrinsic that just had an index it would
1633 * only give us the offset into the nir_inputs array. However, this is
1634 * useless because that value is post-interpolation and we need
1635 * pre-interpolation. In order to get the actual location of the bits
1636 * we get from the vertex fetching hardware, we need the variable.
1638 case nir_intrinsic_interp_var_at_centroid
:
1639 case nir_intrinsic_interp_var_at_sample
:
1640 case nir_intrinsic_interp_var_at_offset
: {
1641 assert(stage
== MESA_SHADER_FRAGMENT
);
1643 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1645 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1647 /* For most messages, we need one reg of ignored data; the hardware
1648 * requires mlen==1 even when there is no payload. in the per-slot
1649 * offset case, we'll replace this with the proper source data.
1651 fs_reg src
= vgrf(glsl_type::float_type
);
1652 int mlen
= 1; /* one reg unless overriden */
1655 switch (instr
->intrinsic
) {
1656 case nir_intrinsic_interp_var_at_centroid
:
1657 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1658 dst_xy
, src
, fs_reg(0u));
1661 case nir_intrinsic_interp_var_at_sample
: {
1662 /* XXX: We should probably handle non-constant sample id's */
1663 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1664 assert(const_sample
);
1665 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1666 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1671 case nir_intrinsic_interp_var_at_offset
: {
1672 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1675 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1676 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1678 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1679 fs_reg(off_x
| (off_y
<< 4)));
1681 src
= vgrf(glsl_type::ivec2_type
);
1682 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1683 BRW_REGISTER_TYPE_F
);
1684 for (int i
= 0; i
< 2; i
++) {
1685 fs_reg temp
= vgrf(glsl_type::float_type
);
1686 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1687 fs_reg itemp
= vgrf(glsl_type::int_type
);
1688 bld
.MOV(itemp
, temp
); /* float to int */
1690 /* Clamp the upper end of the range to +7/16.
1691 * ARB_gpu_shader5 requires that we support a maximum offset
1692 * of +0.5, which isn't representable in a S0.4 value -- if
1693 * we didn't clamp it, we'd end up with -8/16, which is the
1694 * opposite of what the shader author wanted.
1696 * This is legal due to ARB_gpu_shader5's quantization
1699 * "Not all values of <offset> may be supported; x and y
1700 * offsets may be rounded to fixed-point values with the
1701 * number of fraction bits given by the
1702 * implementation-dependent constant
1703 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1705 set_condmod(BRW_CONDITIONAL_L
,
1706 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1709 mlen
= 2 * dispatch_width
/ 8;
1710 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1717 unreachable("Invalid intrinsic");
1721 /* 2 floats per slot returned */
1722 inst
->regs_written
= 2 * dispatch_width
/ 8;
1723 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1724 INTERP_QUALIFIER_NOPERSPECTIVE
;
1726 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1727 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1728 src
.type
= dest
.type
;
1730 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1731 dest
= offset(dest
, bld
, 1);
1736 case nir_intrinsic_store_output_indirect
:
1737 has_indirect
= true;
1739 case nir_intrinsic_store_output
: {
1740 fs_reg src
= get_nir_src(instr
->src
[0]);
1742 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1743 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1744 instr
->const_index
[0] + index
);
1746 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1748 bld
.MOV(new_dest
, src
);
1749 src
= offset(src
, bld
, 1);
1754 case nir_intrinsic_barrier
:
1759 unreachable("unknown intrinsic");
1764 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1766 unsigned sampler
= instr
->sampler_index
;
1767 fs_reg
sampler_reg(sampler
);
1769 /* FINISHME: We're failing to recompile our programs when the sampler is
1770 * updated. This only matters for the texture rectangle scale parameters
1771 * (pre-gen6, or gen6+ with GL_CLAMP).
1773 int texunit
= prog
->SamplerUnits
[sampler
];
1775 int gather_component
= instr
->component
;
1777 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1779 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1782 int lod_components
= 0;
1783 int UNUSED offset_components
= 0;
1785 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1787 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1788 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1789 switch (instr
->src
[i
].src_type
) {
1790 case nir_tex_src_bias
:
1791 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1793 case nir_tex_src_comparitor
:
1794 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1796 case nir_tex_src_coord
:
1797 switch (instr
->op
) {
1799 case nir_texop_txf_ms
:
1800 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1803 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1807 case nir_tex_src_ddx
:
1808 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1809 lod_components
= nir_tex_instr_src_size(instr
, i
);
1811 case nir_tex_src_ddy
:
1812 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1814 case nir_tex_src_lod
:
1815 switch (instr
->op
) {
1817 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1820 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1823 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1827 case nir_tex_src_ms_index
:
1828 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1830 case nir_tex_src_offset
:
1831 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1832 if (instr
->is_array
)
1833 offset_components
= instr
->coord_components
- 1;
1835 offset_components
= instr
->coord_components
;
1837 case nir_tex_src_projector
:
1838 unreachable("should be lowered");
1840 case nir_tex_src_sampler_offset
: {
1841 /* Figure out the highest possible sampler index and mark it as used */
1842 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1843 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1844 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1846 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1848 brw_mark_surface_used(prog_data
, max_used
);
1850 /* Emit code to evaluate the actual indexing expression */
1851 sampler_reg
= vgrf(glsl_type::uint_type
);
1852 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1853 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1858 unreachable("unknown texture source");
1862 if (instr
->op
== nir_texop_txf_ms
) {
1863 if (devinfo
->gen
>= 7 &&
1864 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1865 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1871 for (unsigned i
= 0; i
< 3; i
++) {
1872 if (instr
->const_offset
[i
] != 0) {
1873 assert(offset_components
== 0);
1874 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1879 enum glsl_base_type dest_base_type
=
1880 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
1882 const glsl_type
*dest_type
=
1883 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1886 ir_texture_opcode op
;
1887 switch (instr
->op
) {
1888 case nir_texop_lod
: op
= ir_lod
; break;
1889 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1890 case nir_texop_tex
: op
= ir_tex
; break;
1891 case nir_texop_tg4
: op
= ir_tg4
; break;
1892 case nir_texop_txb
: op
= ir_txb
; break;
1893 case nir_texop_txd
: op
= ir_txd
; break;
1894 case nir_texop_txf
: op
= ir_txf
; break;
1895 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1896 case nir_texop_txl
: op
= ir_txl
; break;
1897 case nir_texop_txs
: op
= ir_txs
; break;
1899 unreachable("unknown texture opcode");
1902 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1903 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1904 tex_offset
, mcs
, gather_component
,
1905 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1907 fs_reg dest
= get_nir_dest(instr
->dest
);
1908 dest
.type
= this->result
.type
;
1909 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1910 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1911 dest
, this->result
),
1912 (1 << num_components
) - 1);
1916 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1918 switch (instr
->type
) {
1919 case nir_jump_break
:
1920 bld
.emit(BRW_OPCODE_BREAK
);
1922 case nir_jump_continue
:
1923 bld
.emit(BRW_OPCODE_CONTINUE
);
1925 case nir_jump_return
:
1927 unreachable("unknown jump");