2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (var
->data
.index
> 0) {
134 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
135 assert(var
->data
.index
== 1);
136 this->dual_src_output
= reg
;
137 this->do_dual_src
= true;
138 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
139 /* Writing gl_FragColor outputs to all color regions. */
140 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
141 this->outputs
[i
] = reg
;
142 this->output_components
[i
] = 4;
144 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
145 this->frag_depth
= reg
;
146 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
147 this->frag_stencil
= reg
;
148 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
149 this->sample_mask
= reg
;
151 int vector_elements
= var
->type
->without_array()->vector_elements
;
153 /* gl_FragData or a user-defined FS output */
154 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
155 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
157 /* General color output. */
158 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
159 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
160 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
161 this->output_components
[output
] = vector_elements
;
166 unreachable("unhandled shader stage");
172 fs_visitor::nir_setup_uniforms()
174 if (dispatch_width
!= 8)
177 uniforms
= nir
->num_uniforms
/ 4;
179 nir_foreach_variable(var
, &nir
->uniforms
) {
180 /* UBO's and atomics don't take up space in the uniform file */
181 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
184 if (type_size_scalar(var
->type
) > 0)
185 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
190 emit_system_values_block(nir_block
*block
, void *void_visitor
)
192 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
195 nir_foreach_instr(block
, instr
) {
196 if (instr
->type
!= nir_instr_type_intrinsic
)
199 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
200 switch (intrin
->intrinsic
) {
201 case nir_intrinsic_load_vertex_id
:
202 unreachable("should be lowered by lower_vertex_id().");
204 case nir_intrinsic_load_vertex_id_zero_base
:
205 assert(v
->stage
== MESA_SHADER_VERTEX
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
207 if (reg
->file
== BAD_FILE
)
208 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
211 case nir_intrinsic_load_base_vertex
:
212 assert(v
->stage
== MESA_SHADER_VERTEX
);
213 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
214 if (reg
->file
== BAD_FILE
)
215 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
218 case nir_intrinsic_load_instance_id
:
219 assert(v
->stage
== MESA_SHADER_VERTEX
);
220 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
221 if (reg
->file
== BAD_FILE
)
222 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
225 case nir_intrinsic_load_base_instance
:
226 assert(v
->stage
== MESA_SHADER_VERTEX
);
227 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
228 if (reg
->file
== BAD_FILE
)
229 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
232 case nir_intrinsic_load_draw_id
:
233 assert(v
->stage
== MESA_SHADER_VERTEX
);
234 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
235 if (reg
->file
== BAD_FILE
)
236 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
239 case nir_intrinsic_load_invocation_id
:
240 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
241 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
242 if (reg
->file
== BAD_FILE
) {
243 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
244 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
245 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
246 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
251 case nir_intrinsic_load_sample_pos
:
252 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
253 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
254 if (reg
->file
== BAD_FILE
)
255 *reg
= *v
->emit_samplepos_setup();
258 case nir_intrinsic_load_sample_id
:
259 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
260 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
261 if (reg
->file
== BAD_FILE
)
262 *reg
= *v
->emit_sampleid_setup();
265 case nir_intrinsic_load_sample_mask_in
:
266 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
267 assert(v
->devinfo
->gen
>= 7);
268 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
269 if (reg
->file
== BAD_FILE
)
270 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
271 BRW_REGISTER_TYPE_D
));
274 case nir_intrinsic_load_local_invocation_id
:
275 assert(v
->stage
== MESA_SHADER_COMPUTE
);
276 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
277 if (reg
->file
== BAD_FILE
)
278 *reg
= *v
->emit_cs_local_invocation_id_setup();
281 case nir_intrinsic_load_work_group_id
:
282 assert(v
->stage
== MESA_SHADER_COMPUTE
);
283 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
284 if (reg
->file
== BAD_FILE
)
285 *reg
= *v
->emit_cs_work_group_id_setup();
288 case nir_intrinsic_load_helper_invocation
:
289 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
290 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
291 if (reg
->file
== BAD_FILE
) {
292 const fs_builder abld
=
293 v
->bld
.annotate("gl_HelperInvocation", NULL
);
295 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
296 * pixel mask is in g1.7 of the thread payload.
298 * We move the per-channel pixel enable bit to the low bit of each
299 * channel by shifting the byte containing the pixel mask by the
300 * vector immediate 0x76543210UV.
302 * The region of <1,8,0> reads only 1 byte (the pixel masks for
303 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
304 * masks for 2 and 3) in SIMD16.
306 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
308 stride(byte_offset(retype(brw_vec1_grf(1, 0),
309 BRW_REGISTER_TYPE_UB
), 28),
311 brw_imm_uv(0x76543210));
313 /* A set bit in the pixel mask means the channel is enabled, but
314 * that is the opposite of gl_HelperInvocation so we need to invert
317 * The negate source-modifier bit of logical instructions on Gen8+
318 * performs 1's complement negation, so we can use that instead of
321 fs_reg inverted
= negate(shifted
);
322 if (v
->devinfo
->gen
< 8) {
323 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
324 abld
.NOT(inverted
, shifted
);
327 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
328 * with 1 and negating.
330 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
331 abld
.AND(anded
, inverted
, brw_imm_uw(1));
333 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
334 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
348 fs_visitor::nir_emit_system_values()
350 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
351 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
352 nir_system_values
[i
] = fs_reg();
355 nir_foreach_function(nir
, function
) {
356 assert(strcmp(function
->name
, "main") == 0);
357 assert(function
->impl
);
358 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
363 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
365 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
366 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
367 nir_locals
[i
] = fs_reg();
370 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
371 unsigned array_elems
=
372 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
373 unsigned size
= array_elems
* reg
->num_components
;
374 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
377 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
380 nir_emit_cf_list(&impl
->body
);
384 fs_visitor::nir_emit_cf_list(exec_list
*list
)
386 exec_list_validate(list
);
387 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
388 switch (node
->type
) {
390 nir_emit_if(nir_cf_node_as_if(node
));
393 case nir_cf_node_loop
:
394 nir_emit_loop(nir_cf_node_as_loop(node
));
397 case nir_cf_node_block
:
398 nir_emit_block(nir_cf_node_as_block(node
));
402 unreachable("Invalid CFG node block");
408 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
410 /* first, put the condition into f0 */
411 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
412 retype(get_nir_src(if_stmt
->condition
),
413 BRW_REGISTER_TYPE_D
));
414 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
416 bld
.IF(BRW_PREDICATE_NORMAL
);
418 nir_emit_cf_list(&if_stmt
->then_list
);
420 /* note: if the else is empty, dead CF elimination will remove it */
421 bld
.emit(BRW_OPCODE_ELSE
);
423 nir_emit_cf_list(&if_stmt
->else_list
);
425 bld
.emit(BRW_OPCODE_ENDIF
);
429 fs_visitor::nir_emit_loop(nir_loop
*loop
)
431 bld
.emit(BRW_OPCODE_DO
);
433 nir_emit_cf_list(&loop
->body
);
435 bld
.emit(BRW_OPCODE_WHILE
);
439 fs_visitor::nir_emit_block(nir_block
*block
)
441 nir_foreach_instr(block
, instr
) {
442 nir_emit_instr(instr
);
447 fs_visitor::nir_emit_instr(nir_instr
*instr
)
449 const fs_builder abld
= bld
.annotate(NULL
, instr
);
451 switch (instr
->type
) {
452 case nir_instr_type_alu
:
453 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
456 case nir_instr_type_intrinsic
:
458 case MESA_SHADER_VERTEX
:
459 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_TESS_EVAL
:
462 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case MESA_SHADER_GEOMETRY
:
465 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_FRAGMENT
:
468 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_COMPUTE
:
471 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 unreachable("unsupported shader stage");
478 case nir_instr_type_tex
:
479 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
482 case nir_instr_type_load_const
:
483 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
486 case nir_instr_type_ssa_undef
:
487 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
490 case nir_instr_type_jump
:
491 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
495 unreachable("unknown instruction type");
500 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
501 const fs_reg
&result
)
503 if (!instr
->src
[0].src
.is_ssa
||
504 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
507 nir_intrinsic_instr
*src0
=
508 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
510 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
513 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
514 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
517 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
518 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
521 fs_reg tmp
= vgrf(glsl_type::int_type
);
523 if (devinfo
->gen
>= 6) {
524 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
525 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
527 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
529 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
530 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
532 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
534 * This negation looks like it's safe in practice, because bits 0:4 will
535 * surely be TRIANGLES
538 if (value1
->f
[0] == -1.0f
) {
542 tmp
.type
= BRW_REGISTER_TYPE_W
;
543 tmp
.subreg_offset
= 2;
546 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
548 tmp
.type
= BRW_REGISTER_TYPE_D
;
549 tmp
.subreg_offset
= 0;
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
566 if (value1
->f
[0] == -1.0f
) {
570 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
572 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
578 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
580 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
583 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
584 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
587 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
588 op
[i
] = get_nir_src(instr
->src
[i
].src
);
589 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
590 op
[i
].abs
= instr
->src
[i
].abs
;
591 op
[i
].negate
= instr
->src
[i
].negate
;
594 /* We get a bunch of mov's out of the from_ssa pass and they may still
595 * be vectorized. We'll handle them as a special-case. We'll also
596 * handle vecN here because it's basically the same thing.
604 fs_reg temp
= result
;
605 bool need_extra_copy
= false;
606 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
607 if (!instr
->src
[i
].src
.is_ssa
&&
608 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
609 need_extra_copy
= true;
610 temp
= bld
.vgrf(result
.type
, 4);
615 for (unsigned i
= 0; i
< 4; i
++) {
616 if (!(instr
->dest
.write_mask
& (1 << i
)))
619 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
620 inst
= bld
.MOV(offset(temp
, bld
, i
),
621 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
623 inst
= bld
.MOV(offset(temp
, bld
, i
),
624 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
626 inst
->saturate
= instr
->dest
.saturate
;
629 /* In this case the source and destination registers were the same,
630 * so we need to insert an extra set of moves in order to deal with
633 if (need_extra_copy
) {
634 for (unsigned i
= 0; i
< 4; i
++) {
635 if (!(instr
->dest
.write_mask
& (1 << i
)))
638 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
647 /* At this point, we have dealt with any instruction that operates on
648 * more than a single channel. Therefore, we can just adjust the source
649 * and destination registers for that channel and emit the instruction.
651 unsigned channel
= 0;
652 if (nir_op_infos
[instr
->op
].output_size
== 0) {
653 /* Since NIR is doing the scalarizing for us, we should only ever see
654 * vectorized operations with a single channel.
656 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
657 channel
= ffs(instr
->dest
.write_mask
) - 1;
659 result
= offset(result
, bld
, channel
);
662 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
663 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
664 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
670 inst
= bld
.MOV(result
, op
[0]);
671 inst
->saturate
= instr
->dest
.saturate
;
676 bld
.MOV(result
, op
[0]);
680 /* AND(val, 0x80000000) gives the sign bit.
682 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
685 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
687 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
688 op
[0].type
= BRW_REGISTER_TYPE_UD
;
689 result
.type
= BRW_REGISTER_TYPE_UD
;
690 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
692 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
693 inst
->predicate
= BRW_PREDICATE_NORMAL
;
694 if (instr
->dest
.saturate
) {
695 inst
= bld
.MOV(result
, result
);
696 inst
->saturate
= true;
702 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
703 * -> non-negative val generates 0x00000000.
704 * Predicated OR sets 1 if val is positive.
706 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
707 bld
.ASR(result
, op
[0], brw_imm_d(31));
708 inst
= bld
.OR(result
, result
, brw_imm_d(1));
709 inst
->predicate
= BRW_PREDICATE_NORMAL
;
713 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
714 inst
->saturate
= instr
->dest
.saturate
;
718 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
719 inst
->saturate
= instr
->dest
.saturate
;
723 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
728 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
729 inst
->saturate
= instr
->dest
.saturate
;
733 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
734 inst
->saturate
= instr
->dest
.saturate
;
738 if (fs_key
->high_quality_derivatives
) {
739 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
741 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
743 inst
->saturate
= instr
->dest
.saturate
;
745 case nir_op_fddx_fine
:
746 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
749 case nir_op_fddx_coarse
:
750 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
751 inst
->saturate
= instr
->dest
.saturate
;
754 if (fs_key
->high_quality_derivatives
) {
755 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
756 brw_imm_d(fs_key
->render_to_fbo
));
758 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
759 brw_imm_d(fs_key
->render_to_fbo
));
761 inst
->saturate
= instr
->dest
.saturate
;
763 case nir_op_fddy_fine
:
764 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
765 brw_imm_d(fs_key
->render_to_fbo
));
766 inst
->saturate
= instr
->dest
.saturate
;
768 case nir_op_fddy_coarse
:
769 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
770 brw_imm_d(fs_key
->render_to_fbo
));
771 inst
->saturate
= instr
->dest
.saturate
;
776 inst
= bld
.ADD(result
, op
[0], op
[1]);
777 inst
->saturate
= instr
->dest
.saturate
;
781 inst
= bld
.MUL(result
, op
[0], op
[1]);
782 inst
->saturate
= instr
->dest
.saturate
;
786 bld
.MUL(result
, op
[0], op
[1]);
789 case nir_op_imul_high
:
790 case nir_op_umul_high
:
791 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
796 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
799 case nir_op_uadd_carry
:
800 unreachable("Should have been lowered by carry_to_arith().");
802 case nir_op_usub_borrow
:
803 unreachable("Should have been lowered by borrow_to_arith().");
806 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
812 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
818 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
823 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
828 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
832 if (devinfo
->gen
>= 8) {
833 op
[0] = resolve_source_modifiers(op
[0]);
835 bld
.NOT(result
, op
[0]);
838 if (devinfo
->gen
>= 8) {
839 op
[0] = resolve_source_modifiers(op
[0]);
840 op
[1] = resolve_source_modifiers(op
[1]);
842 bld
.XOR(result
, op
[0], op
[1]);
845 if (devinfo
->gen
>= 8) {
846 op
[0] = resolve_source_modifiers(op
[0]);
847 op
[1] = resolve_source_modifiers(op
[1]);
849 bld
.OR(result
, op
[0], op
[1]);
852 if (devinfo
->gen
>= 8) {
853 op
[0] = resolve_source_modifiers(op
[0]);
854 op
[1] = resolve_source_modifiers(op
[1]);
856 bld
.AND(result
, op
[0], op
[1]);
862 case nir_op_ball_fequal2
:
863 case nir_op_ball_iequal2
:
864 case nir_op_ball_fequal3
:
865 case nir_op_ball_iequal3
:
866 case nir_op_ball_fequal4
:
867 case nir_op_ball_iequal4
:
868 case nir_op_bany_fnequal2
:
869 case nir_op_bany_inequal2
:
870 case nir_op_bany_fnequal3
:
871 case nir_op_bany_inequal3
:
872 case nir_op_bany_fnequal4
:
873 case nir_op_bany_inequal4
:
874 unreachable("Lowered by nir_lower_alu_reductions");
876 case nir_op_fnoise1_1
:
877 case nir_op_fnoise1_2
:
878 case nir_op_fnoise1_3
:
879 case nir_op_fnoise1_4
:
880 case nir_op_fnoise2_1
:
881 case nir_op_fnoise2_2
:
882 case nir_op_fnoise2_3
:
883 case nir_op_fnoise2_4
:
884 case nir_op_fnoise3_1
:
885 case nir_op_fnoise3_2
:
886 case nir_op_fnoise3_3
:
887 case nir_op_fnoise3_4
:
888 case nir_op_fnoise4_1
:
889 case nir_op_fnoise4_2
:
890 case nir_op_fnoise4_3
:
891 case nir_op_fnoise4_4
:
892 unreachable("not reached: should be handled by lower_noise");
895 unreachable("not reached: should be handled by ldexp_to_arith()");
898 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
903 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
904 inst
->saturate
= instr
->dest
.saturate
;
909 bld
.MOV(result
, negate(op
[0]));
913 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
916 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
920 inst
= bld
.RNDZ(result
, op
[0]);
921 inst
->saturate
= instr
->dest
.saturate
;
925 op
[0].negate
= !op
[0].negate
;
926 fs_reg temp
= vgrf(glsl_type::float_type
);
927 bld
.RNDD(temp
, op
[0]);
929 inst
= bld
.MOV(result
, temp
);
930 inst
->saturate
= instr
->dest
.saturate
;
934 inst
= bld
.RNDD(result
, op
[0]);
935 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.FRC(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
941 case nir_op_fround_even
:
942 inst
= bld
.RNDE(result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
949 if (devinfo
->gen
>= 6) {
950 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
951 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
953 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
954 inst
= bld
.SEL(result
, op
[0], op
[1]);
955 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 inst
->saturate
= instr
->dest
.saturate
;
963 if (devinfo
->gen
>= 6) {
964 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
965 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
967 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
968 inst
= bld
.SEL(result
, op
[0], op
[1]);
969 inst
->predicate
= BRW_PREDICATE_NORMAL
;
971 inst
->saturate
= instr
->dest
.saturate
;
974 case nir_op_pack_snorm_2x16
:
975 case nir_op_pack_snorm_4x8
:
976 case nir_op_pack_unorm_2x16
:
977 case nir_op_pack_unorm_4x8
:
978 case nir_op_unpack_snorm_2x16
:
979 case nir_op_unpack_snorm_4x8
:
980 case nir_op_unpack_unorm_2x16
:
981 case nir_op_unpack_unorm_4x8
:
982 case nir_op_unpack_half_2x16
:
983 case nir_op_pack_half_2x16
:
984 unreachable("not reached: should be handled by lower_packing_builtins");
986 case nir_op_unpack_half_2x16_split_x
:
987 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
988 inst
->saturate
= instr
->dest
.saturate
;
990 case nir_op_unpack_half_2x16_split_y
:
991 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
992 inst
->saturate
= instr
->dest
.saturate
;
996 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
997 inst
->saturate
= instr
->dest
.saturate
;
1000 case nir_op_bitfield_reverse
:
1001 bld
.BFREV(result
, op
[0]);
1004 case nir_op_bit_count
:
1005 bld
.CBIT(result
, op
[0]);
1008 case nir_op_ufind_msb
:
1009 case nir_op_ifind_msb
: {
1010 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1012 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1013 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1014 * subtract the result from 31 to convert the MSB count into an LSB count.
1016 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1018 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1019 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1020 inst
->src
[0].negate
= true;
1024 case nir_op_find_lsb
:
1025 bld
.FBL(result
, op
[0]);
1028 case nir_op_ubitfield_extract
:
1029 case nir_op_ibitfield_extract
:
1030 unreachable("should have been lowered");
1033 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1036 bld
.BFI1(result
, op
[0], op
[1]);
1039 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1042 case nir_op_bitfield_insert
:
1043 unreachable("not reached: should have been lowered");
1046 bld
.SHL(result
, op
[0], op
[1]);
1049 bld
.ASR(result
, op
[0], op
[1]);
1052 bld
.SHR(result
, op
[0], op
[1]);
1055 case nir_op_pack_half_2x16_split
:
1056 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1060 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1061 inst
->saturate
= instr
->dest
.saturate
;
1065 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1066 inst
->saturate
= instr
->dest
.saturate
;
1070 if (optimize_frontfacing_ternary(instr
, result
))
1073 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1074 inst
= bld
.SEL(result
, op
[1], op
[2]);
1075 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1078 case nir_op_extract_ubyte
:
1079 case nir_op_extract_ibyte
: {
1080 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1081 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1082 result
, op
[0], brw_imm_ud(byte
->u
[0]));
1086 case nir_op_extract_uword
:
1087 case nir_op_extract_iword
: {
1088 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1089 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1090 result
, op
[0], brw_imm_ud(word
->u
[0]));
1095 unreachable("unhandled instruction");
1098 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1099 * to sign extend the low bit to 0/~0
1101 if (devinfo
->gen
<= 5 &&
1102 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1103 fs_reg masked
= vgrf(glsl_type::int_type
);
1104 bld
.AND(masked
, result
, brw_imm_d(1));
1105 masked
.negate
= true;
1106 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1111 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1112 nir_load_const_instr
*instr
)
1114 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1116 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1117 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1119 nir_ssa_values
[instr
->def
.index
] = reg
;
1123 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1125 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1126 instr
->def
.num_components
);
1130 fs_visitor::get_nir_src(nir_src src
)
1134 reg
= nir_ssa_values
[src
.ssa
->index
];
1136 /* We don't handle indirects on locals */
1137 assert(src
.reg
.indirect
== NULL
);
1138 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1139 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1142 /* to avoid floating-point denorm flushing problems, set the type by
1143 * default to D - instructions that need floating point semantics will set
1144 * this to F if they need to
1146 return retype(reg
, BRW_REGISTER_TYPE_D
);
1150 fs_visitor::get_nir_dest(nir_dest dest
)
1153 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1154 dest
.ssa
.num_components
);
1155 return nir_ssa_values
[dest
.ssa
.index
];
1157 /* We don't handle indirects on locals */
1158 assert(dest
.reg
.indirect
== NULL
);
1159 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1160 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1165 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1167 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1168 BRW_REGISTER_TYPE_UD
);
1170 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1171 tail
= tail
->child
) {
1172 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1173 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1174 const unsigned size
= glsl_get_length(tail
->type
);
1175 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1176 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1177 image
= offset(image
, bld
, base
* element_size
);
1179 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1180 fs_reg tmp
= vgrf(glsl_type::int_type
);
1182 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1183 /* IVB hangs when trying to access an invalid surface index with
1184 * the dataport. According to the spec "if the index used to
1185 * select an individual element is negative or greater than or
1186 * equal to the size of the array, the results of the operation
1187 * are undefined but may not lead to termination" -- which is one
1188 * of the possible outcomes of the hang. Clamp the index to
1189 * prevent access outside of the array bounds.
1191 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1192 BRW_REGISTER_TYPE_UD
),
1193 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1195 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1198 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1200 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1202 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1210 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1213 for (unsigned i
= 0; i
< 4; i
++) {
1214 if (!((wr_mask
>> i
) & 1))
1217 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1218 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1219 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1220 if (new_inst
->src
[j
].file
== VGRF
)
1221 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1228 * Get the matching channel register datatype for an image intrinsic of the
1229 * specified GLSL image type.
1232 get_image_base_type(const glsl_type
*type
)
1234 switch ((glsl_base_type
)type
->sampler_type
) {
1235 case GLSL_TYPE_UINT
:
1236 return BRW_REGISTER_TYPE_UD
;
1238 return BRW_REGISTER_TYPE_D
;
1239 case GLSL_TYPE_FLOAT
:
1240 return BRW_REGISTER_TYPE_F
;
1242 unreachable("Not reached.");
1247 * Get the appropriate atomic op for an image atomic intrinsic.
1250 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1253 case nir_intrinsic_image_atomic_add
:
1255 case nir_intrinsic_image_atomic_min
:
1256 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1257 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1258 case nir_intrinsic_image_atomic_max
:
1259 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1260 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1261 case nir_intrinsic_image_atomic_and
:
1263 case nir_intrinsic_image_atomic_or
:
1265 case nir_intrinsic_image_atomic_xor
:
1267 case nir_intrinsic_image_atomic_exchange
:
1269 case nir_intrinsic_image_atomic_comp_swap
:
1270 return BRW_AOP_CMPWR
;
1272 unreachable("Not reachable.");
1277 emit_pixel_interpolater_send(const fs_builder
&bld
,
1282 glsl_interp_qualifier interpolation
)
1288 if (src
.file
== BAD_FILE
) {
1290 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1294 mlen
= 2 * bld
.dispatch_width() / 8;
1297 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1299 /* 2 floats per slot returned */
1300 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1301 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1307 * Computes 1 << x, given a D/UD register containing some value x.
1310 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1312 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1314 fs_reg result
= bld
.vgrf(x
.type
, 1);
1315 fs_reg one
= bld
.vgrf(x
.type
, 1);
1317 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1318 bld
.SHL(result
, one
, x
);
1323 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1325 assert(stage
== MESA_SHADER_GEOMETRY
);
1327 struct brw_gs_prog_data
*gs_prog_data
=
1328 (struct brw_gs_prog_data
*) prog_data
;
1330 /* We can only do EndPrimitive() functionality when the control data
1331 * consists of cut bits. Fortunately, the only time it isn't is when the
1332 * output type is points, in which case EndPrimitive() is a no-op.
1334 if (gs_prog_data
->control_data_format
!=
1335 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1339 /* Cut bits use one bit per vertex. */
1340 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1342 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1343 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1345 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1346 * vertex n, 0 otherwise. So all we need to do here is mark bit
1347 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1348 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1349 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1351 * Note that if EndPrimitive() is called before emitting any vertices, this
1352 * will cause us to set bit 31 of the control_data_bits register to 1.
1353 * That's fine because:
1355 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1356 * output, so the hardware will ignore cut bit 31.
1358 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1359 * last vertex, so setting cut bit 31 has no effect (since the primitive
1360 * is automatically ended when the GS terminates).
1362 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1363 * control_data_bits register to 0 when the first vertex is emitted.
1366 const fs_builder abld
= bld
.annotate("end primitive");
1368 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1369 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1370 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1371 fs_reg mask
= intexp2(abld
, prev_count
);
1372 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1373 * attention to the lower 5 bits of its second source argument, so on this
1374 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1375 * ((vertex_count - 1) % 32).
1377 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1381 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1383 assert(stage
== MESA_SHADER_GEOMETRY
);
1384 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1386 struct brw_gs_prog_data
*gs_prog_data
=
1387 (struct brw_gs_prog_data
*) prog_data
;
1389 const fs_builder abld
= bld
.annotate("emit control data bits");
1390 const fs_builder fwa_bld
= bld
.exec_all();
1392 /* We use a single UD register to accumulate control data bits (32 bits
1393 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1396 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1397 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1398 * use the Channel Mask phase to enable/disable which DWord within that
1399 * group to write. (Remember, different SIMD8 channels may have emitted
1400 * different numbers of vertices, so we may need per-slot offsets.)
1402 * Channel masking presents an annoying problem: we may have to replicate
1403 * the data up to 4 times:
1405 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1407 * To avoid penalizing shaders that emit a small number of vertices, we
1408 * can avoid these sometimes: if the size of the control data header is
1409 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1410 * land in the same 128-bit group, so we can skip per-slot offsets.
1412 * Similarly, if the control data header is <= 32 bits, there is only one
1413 * DWord, so we can skip channel masks.
1415 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1417 fs_reg channel_mask
, per_slot_offset
;
1419 if (gs_compile
->control_data_header_size_bits
> 32) {
1420 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1421 channel_mask
= vgrf(glsl_type::uint_type
);
1424 if (gs_compile
->control_data_header_size_bits
> 128) {
1425 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1426 per_slot_offset
= vgrf(glsl_type::uint_type
);
1429 /* Figure out which DWord we're trying to write to using the formula:
1431 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1433 * Since bits_per_vertex is a power of two, and is known at compile
1434 * time, this can be optimized to:
1436 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1438 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1439 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1440 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1441 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1442 unsigned log2_bits_per_vertex
=
1443 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1444 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1446 if (per_slot_offset
.file
!= BAD_FILE
) {
1447 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1448 * the appropriate OWord within the control data header.
1450 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1453 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1454 * write to the appropriate DWORD within the OWORD.
1456 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1457 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1458 channel_mask
= intexp2(fwa_bld
, channel
);
1459 /* Then the channel masks need to be in bits 23:16. */
1460 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1463 /* Store the control data bits in the message payload and send it. */
1465 if (channel_mask
.file
!= BAD_FILE
)
1466 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1467 if (per_slot_offset
.file
!= BAD_FILE
)
1470 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1471 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1473 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1474 if (per_slot_offset
.file
!= BAD_FILE
)
1475 sources
[i
++] = per_slot_offset
;
1476 if (channel_mask
.file
!= BAD_FILE
)
1477 sources
[i
++] = channel_mask
;
1479 sources
[i
++] = this->control_data_bits
;
1482 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1483 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1485 /* We need to increment Global Offset by 256-bits to make room for
1486 * Broadwell's extra "Vertex Count" payload at the beginning of the
1487 * URB entry. Since this is an OWord message, Global Offset is counted
1488 * in 128-bit units, so we must set it to 2.
1490 if (gs_prog_data
->static_vertex_count
== -1)
1495 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1498 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1500 /* Note: we are calling this *before* increasing vertex_count, so
1501 * this->vertex_count == vertex_count - 1 in the formula above.
1504 /* Stream mode uses 2 bits per vertex */
1505 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1507 /* Must be a valid stream */
1508 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1510 /* Control data bits are initialized to 0 so we don't have to set any
1511 * bits when sending vertices to stream 0.
1516 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1518 /* reg::sid = stream_id */
1519 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1520 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1522 /* reg:shift_count = 2 * (vertex_count - 1) */
1523 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1524 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1526 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1527 * attention to the lower 5 bits of its second source argument, so on this
1528 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1529 * stream_id << ((2 * (vertex_count - 1)) % 32).
1531 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1532 abld
.SHL(mask
, sid
, shift_count
);
1533 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1537 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1540 assert(stage
== MESA_SHADER_GEOMETRY
);
1542 struct brw_gs_prog_data
*gs_prog_data
=
1543 (struct brw_gs_prog_data
*) prog_data
;
1545 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1546 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1548 /* Haswell and later hardware ignores the "Render Stream Select" bits
1549 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1550 * and instead sends all primitives down the pipeline for rasterization.
1551 * If the SOL stage is enabled, "Render Stream Select" is honored and
1552 * primitives bound to non-zero streams are discarded after stream output.
1554 * Since the only purpose of primives sent to non-zero streams is to
1555 * be recorded by transform feedback, we can simply discard all geometry
1556 * bound to these streams when transform feedback is disabled.
1558 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1561 /* If we're outputting 32 control data bits or less, then we can wait
1562 * until the shader is over to output them all. Otherwise we need to
1563 * output them as we go. Now is the time to do it, since we're about to
1564 * output the vertex_count'th vertex, so it's guaranteed that the
1565 * control data bits associated with the (vertex_count - 1)th vertex are
1568 if (gs_compile
->control_data_header_size_bits
> 32) {
1569 const fs_builder abld
=
1570 bld
.annotate("emit vertex: emit control data bits");
1572 /* Only emit control data bits if we've finished accumulating a batch
1573 * of 32 bits. This is the case when:
1575 * (vertex_count * bits_per_vertex) % 32 == 0
1577 * (in other words, when the last 5 bits of vertex_count *
1578 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1579 * integer n (which is always the case, since bits_per_vertex is
1580 * always 1 or 2), this is equivalent to requiring that the last 5-n
1581 * bits of vertex_count are 0:
1583 * vertex_count & (2^(5-n) - 1) == 0
1585 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1588 * vertex_count & (32 / bits_per_vertex - 1) == 0
1590 * TODO: If vertex_count is an immediate, we could do some of this math
1591 * at compile time...
1594 abld
.AND(bld
.null_reg_d(), vertex_count
,
1595 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1596 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1598 abld
.IF(BRW_PREDICATE_NORMAL
);
1599 /* If vertex_count is 0, then no control data bits have been
1600 * accumulated yet, so we can skip emitting them.
1602 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1603 BRW_CONDITIONAL_NEQ
);
1604 abld
.IF(BRW_PREDICATE_NORMAL
);
1605 emit_gs_control_data_bits(vertex_count
);
1606 abld
.emit(BRW_OPCODE_ENDIF
);
1608 /* Reset control_data_bits to 0 so we can start accumulating a new
1611 * Note: in the case where vertex_count == 0, this neutralizes the
1612 * effect of any call to EndPrimitive() that the shader may have
1613 * made before outputting its first vertex.
1615 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1616 inst
->force_writemask_all
= true;
1617 abld
.emit(BRW_OPCODE_ENDIF
);
1620 emit_urb_writes(vertex_count
);
1622 /* In stream mode we have to set control data bits for all vertices
1623 * unless we have disabled control data bits completely (which we do
1624 * do for GL_POINTS outputs that don't use streams).
1626 if (gs_compile
->control_data_header_size_bits
> 0 &&
1627 gs_prog_data
->control_data_format
==
1628 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1629 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1634 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1635 const nir_src
&vertex_src
,
1636 unsigned base_offset
,
1637 const nir_src
&offset_src
,
1638 unsigned num_components
)
1640 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1642 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1643 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1644 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1646 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1647 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1648 * gl_PointSize is available as a GS input, however, so it must be that.
1650 const bool is_point_size
= (base_offset
== 0);
1652 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1653 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1654 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1655 vertex_const
->u
[0] * push_reg_count
;
1656 /* This input was pushed into registers. */
1657 if (is_point_size
) {
1658 /* gl_PointSize comes in .w */
1659 assert(imm_offset
== 0);
1660 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1662 for (unsigned i
= 0; i
< num_components
; i
++) {
1663 bld
.MOV(offset(dst
, bld
, i
),
1664 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1668 /* Resort to the pull model. Ensure the VUE handles are provided. */
1669 gs_prog_data
->base
.include_vue_handles
= true;
1671 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1675 /* The vertex index is constant; just select the proper URB handle. */
1677 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1678 BRW_REGISTER_TYPE_UD
);
1680 /* The vertex index is non-constant. We need to use indirect
1681 * addressing to fetch the proper URB handle.
1683 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1684 * indicating that channel <n> should read the handle from
1685 * DWord <n>. We convert that to bytes by multiplying by 4.
1687 * Next, we convert the vertex index to bytes by multiplying
1688 * by 32 (shifting by 5), and add the two together. This is
1689 * the final indirect byte offset.
1691 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1692 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1693 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1694 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1695 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1697 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1698 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1699 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1700 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1701 /* Convert vertex_index to bytes (multiply by 32) */
1702 bld
.SHL(vertex_offset_bytes
,
1703 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1705 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1707 /* Use first_icp_handle as the base offset. There is one register
1708 * of URB handles per vertex, so inform the register allocator that
1709 * we might read up to nir->info.gs.vertices_in registers.
1711 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1712 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1713 fs_reg(icp_offset_bytes
),
1714 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1719 /* Constant indexing - use global offset. */
1720 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1721 inst
->offset
= base_offset
+ offset_const
->u
[0];
1722 inst
->base_mrf
= -1;
1724 inst
->regs_written
= num_components
;
1726 /* Indirect indexing - use per-slot offsets as well. */
1727 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1728 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1729 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1731 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1732 inst
->offset
= base_offset
;
1733 inst
->base_mrf
= -1;
1735 inst
->regs_written
= num_components
;
1738 if (is_point_size
) {
1739 /* Read the whole VUE header (because of alignment) and read .w. */
1740 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1742 inst
->regs_written
= 4;
1743 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1749 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1751 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1752 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1755 /* The only constant offset we should find is 0. brw_nir.c's
1756 * add_const_offset_to_base() will fold other constant offsets
1757 * into instr->const_index[0].
1759 assert(const_value
->u
[0] == 0);
1763 return get_nir_src(*offset_src
);
1767 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1768 nir_intrinsic_instr
*instr
)
1770 assert(stage
== MESA_SHADER_VERTEX
);
1773 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1774 dest
= get_nir_dest(instr
->dest
);
1776 switch (instr
->intrinsic
) {
1777 case nir_intrinsic_load_vertex_id
:
1778 unreachable("should be lowered by lower_vertex_id()");
1780 case nir_intrinsic_load_vertex_id_zero_base
:
1781 case nir_intrinsic_load_base_vertex
:
1782 case nir_intrinsic_load_instance_id
:
1783 case nir_intrinsic_load_base_instance
:
1784 case nir_intrinsic_load_draw_id
: {
1785 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1786 fs_reg val
= nir_system_values
[sv
];
1787 assert(val
.file
!= BAD_FILE
);
1788 dest
.type
= val
.type
;
1794 nir_emit_intrinsic(bld
, instr
);
1800 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1801 nir_intrinsic_instr
*instr
)
1803 assert(stage
== MESA_SHADER_TESS_EVAL
);
1804 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1807 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1808 dest
= get_nir_dest(instr
->dest
);
1810 switch (instr
->intrinsic
) {
1811 case nir_intrinsic_load_primitive_id
:
1812 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1814 case nir_intrinsic_load_tess_coord
:
1815 /* gl_TessCoord is part of the payload in g1-3 */
1816 for (unsigned i
= 0; i
< 3; i
++) {
1817 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1821 case nir_intrinsic_load_tess_level_outer
:
1822 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1823 * appears as a push-model input. So, we can simply use the ATTR file
1824 * rather than issuing URB read messages. The data is stored in the
1825 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1828 switch (tes_prog_data
->domain
) {
1829 case BRW_TESS_DOMAIN_QUAD
:
1830 for (unsigned i
= 0; i
< 4; i
++)
1831 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1833 case BRW_TESS_DOMAIN_TRI
:
1834 for (unsigned i
= 0; i
< 3; i
++)
1835 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1837 case BRW_TESS_DOMAIN_ISOLINE
:
1838 for (unsigned i
= 0; i
< 2; i
++)
1839 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1844 case nir_intrinsic_load_tess_level_inner
:
1845 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1846 * appears as a push-model input. So, we can simply use the ATTR file
1847 * rather than issuing URB read messages.
1849 switch (tes_prog_data
->domain
) {
1850 case BRW_TESS_DOMAIN_QUAD
:
1851 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1852 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1854 case BRW_TESS_DOMAIN_TRI
:
1855 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1857 case BRW_TESS_DOMAIN_ISOLINE
:
1858 /* ignore - value is undefined */
1863 case nir_intrinsic_load_input
:
1864 case nir_intrinsic_load_per_vertex_input
: {
1865 fs_reg indirect_offset
= get_indirect_offset(instr
);
1866 unsigned imm_offset
= instr
->const_index
[0];
1869 if (indirect_offset
.file
== BAD_FILE
) {
1870 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1871 * which is 16 registers (since each holds 2 vec4 slots).
1873 const unsigned max_push_slots
= 32;
1874 if (imm_offset
< max_push_slots
) {
1875 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1876 for (int i
= 0; i
< instr
->num_components
; i
++) {
1877 bld
.MOV(offset(dest
, bld
, i
),
1878 component(src
, 4 * (imm_offset
% 2) + i
));
1880 tes_prog_data
->base
.urb_read_length
=
1881 MAX2(tes_prog_data
->base
.urb_read_length
,
1882 DIV_ROUND_UP(imm_offset
+ 1, 2));
1884 /* Replicate the patch handle to all enabled channels */
1885 const fs_reg srcs
[] = {
1886 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1888 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1889 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1891 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1893 inst
->offset
= imm_offset
;
1894 inst
->base_mrf
= -1;
1895 inst
->regs_written
= instr
->num_components
;
1898 /* Indirect indexing - use per-slot offsets as well. */
1899 const fs_reg srcs
[] = {
1900 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1903 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1904 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1906 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1908 inst
->offset
= imm_offset
;
1909 inst
->base_mrf
= -1;
1910 inst
->regs_written
= instr
->num_components
;
1915 nir_emit_intrinsic(bld
, instr
);
1921 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1922 nir_intrinsic_instr
*instr
)
1924 assert(stage
== MESA_SHADER_GEOMETRY
);
1925 fs_reg indirect_offset
;
1928 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1929 dest
= get_nir_dest(instr
->dest
);
1931 switch (instr
->intrinsic
) {
1932 case nir_intrinsic_load_primitive_id
:
1933 assert(stage
== MESA_SHADER_GEOMETRY
);
1934 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1935 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1936 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1939 case nir_intrinsic_load_input
:
1940 unreachable("load_input intrinsics are invalid for the GS stage");
1942 case nir_intrinsic_load_per_vertex_input
:
1943 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1944 instr
->src
[1], instr
->num_components
);
1947 case nir_intrinsic_emit_vertex_with_counter
:
1948 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1951 case nir_intrinsic_end_primitive_with_counter
:
1952 emit_gs_end_primitive(instr
->src
[0]);
1955 case nir_intrinsic_set_vertex_count
:
1956 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1959 case nir_intrinsic_load_invocation_id
: {
1960 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1961 assert(val
.file
!= BAD_FILE
);
1962 dest
.type
= val
.type
;
1968 nir_emit_intrinsic(bld
, instr
);
1974 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1975 nir_intrinsic_instr
*instr
)
1977 assert(stage
== MESA_SHADER_FRAGMENT
);
1978 struct brw_wm_prog_data
*wm_prog_data
=
1979 (struct brw_wm_prog_data
*) prog_data
;
1982 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1983 dest
= get_nir_dest(instr
->dest
);
1985 switch (instr
->intrinsic
) {
1986 case nir_intrinsic_load_front_face
:
1987 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1988 *emit_frontfacing_interpolation());
1991 case nir_intrinsic_load_sample_pos
: {
1992 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1993 assert(sample_pos
.file
!= BAD_FILE
);
1994 dest
.type
= sample_pos
.type
;
1995 bld
.MOV(dest
, sample_pos
);
1996 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2000 case nir_intrinsic_load_helper_invocation
:
2001 case nir_intrinsic_load_sample_mask_in
:
2002 case nir_intrinsic_load_sample_id
: {
2003 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2004 fs_reg val
= nir_system_values
[sv
];
2005 assert(val
.file
!= BAD_FILE
);
2006 dest
.type
= val
.type
;
2011 case nir_intrinsic_discard
:
2012 case nir_intrinsic_discard_if
: {
2013 /* We track our discarded pixels in f0.1. By predicating on it, we can
2014 * update just the flag bits that aren't yet discarded. If there's no
2015 * condition, we emit a CMP of g0 != g0, so all currently executing
2016 * channels will get turned off.
2019 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2020 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2021 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2023 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2024 BRW_REGISTER_TYPE_UW
));
2025 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2027 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2028 cmp
->flag_subreg
= 1;
2030 if (devinfo
->gen
>= 6) {
2031 emit_discard_jump();
2036 case nir_intrinsic_interp_var_at_centroid
:
2037 case nir_intrinsic_interp_var_at_sample
:
2038 case nir_intrinsic_interp_var_at_offset
: {
2039 /* Handle ARB_gpu_shader5 interpolation intrinsics
2041 * It's worth a quick word of explanation as to why we handle the full
2042 * variable-based interpolation intrinsic rather than a lowered version
2043 * with like we do for other inputs. We have to do that because the way
2044 * we set up inputs doesn't allow us to use the already setup inputs for
2045 * interpolation. At the beginning of the shader, we go through all of
2046 * the input variables and do the initial interpolation and put it in
2047 * the nir_inputs array based on its location as determined in
2048 * nir_lower_io. If the input isn't used, dead code cleans up and
2049 * everything works fine. However, when we get to the ARB_gpu_shader5
2050 * interpolation intrinsics, we need to reinterpolate the input
2051 * differently. If we used an intrinsic that just had an index it would
2052 * only give us the offset into the nir_inputs array. However, this is
2053 * useless because that value is post-interpolation and we need
2054 * pre-interpolation. In order to get the actual location of the bits
2055 * we get from the vertex fetching hardware, we need the variable.
2057 wm_prog_data
->pulls_bary
= true;
2059 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2060 const glsl_interp_qualifier interpolation
=
2061 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2063 switch (instr
->intrinsic
) {
2064 case nir_intrinsic_interp_var_at_centroid
:
2065 emit_pixel_interpolater_send(bld
,
2066 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2073 case nir_intrinsic_interp_var_at_sample
: {
2074 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2077 unsigned msg_data
= const_sample
->i
[0] << 4;
2079 emit_pixel_interpolater_send(bld
,
2080 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2083 brw_imm_ud(msg_data
),
2086 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2087 BRW_REGISTER_TYPE_UD
);
2089 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2090 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2091 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2092 bld
.exec_all().group(1, 0)
2093 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2094 emit_pixel_interpolater_send(bld
,
2095 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2101 /* Make a loop that sends a message to the pixel interpolater
2102 * for the sample number in each live channel. If there are
2103 * multiple channels with the same sample number then these
2104 * will be handled simultaneously with a single interation of
2107 bld
.emit(BRW_OPCODE_DO
);
2109 /* Get the next live sample number into sample_id_reg */
2110 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2112 /* Set the flag register so that we can perform the send
2113 * message on all channels that have the same sample number
2115 bld
.CMP(bld
.null_reg_ud(),
2116 sample_src
, sample_id
,
2117 BRW_CONDITIONAL_EQ
);
2118 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2119 bld
.exec_all().group(1, 0)
2120 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2122 emit_pixel_interpolater_send(bld
,
2123 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2128 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2130 /* Continue the loop if there are any live channels left */
2131 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2133 bld
.emit(BRW_OPCODE_WHILE
));
2140 case nir_intrinsic_interp_var_at_offset
: {
2141 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2144 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2145 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2147 emit_pixel_interpolater_send(bld
,
2148 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2151 brw_imm_ud(off_x
| (off_y
<< 4)),
2154 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2155 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2156 BRW_REGISTER_TYPE_F
);
2157 for (int i
= 0; i
< 2; i
++) {
2158 fs_reg temp
= vgrf(glsl_type::float_type
);
2159 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2160 fs_reg itemp
= vgrf(glsl_type::int_type
);
2161 bld
.MOV(itemp
, temp
); /* float to int */
2163 /* Clamp the upper end of the range to +7/16.
2164 * ARB_gpu_shader5 requires that we support a maximum offset
2165 * of +0.5, which isn't representable in a S0.4 value -- if
2166 * we didn't clamp it, we'd end up with -8/16, which is the
2167 * opposite of what the shader author wanted.
2169 * This is legal due to ARB_gpu_shader5's quantization
2172 * "Not all values of <offset> may be supported; x and y
2173 * offsets may be rounded to fixed-point values with the
2174 * number of fraction bits given by the
2175 * implementation-dependent constant
2176 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2178 set_condmod(BRW_CONDITIONAL_L
,
2179 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2182 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2183 emit_pixel_interpolater_send(bld
,
2194 unreachable("Invalid intrinsic");
2197 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2198 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2199 src
.type
= dest
.type
;
2201 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2202 dest
= offset(dest
, bld
, 1);
2207 nir_emit_intrinsic(bld
, instr
);
2213 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2214 nir_intrinsic_instr
*instr
)
2216 assert(stage
== MESA_SHADER_COMPUTE
);
2217 struct brw_cs_prog_data
*cs_prog_data
=
2218 (struct brw_cs_prog_data
*) prog_data
;
2221 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2222 dest
= get_nir_dest(instr
->dest
);
2224 switch (instr
->intrinsic
) {
2225 case nir_intrinsic_barrier
:
2227 cs_prog_data
->uses_barrier
= true;
2230 case nir_intrinsic_load_local_invocation_id
:
2231 case nir_intrinsic_load_work_group_id
: {
2232 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2233 fs_reg val
= nir_system_values
[sv
];
2234 assert(val
.file
!= BAD_FILE
);
2235 dest
.type
= val
.type
;
2236 for (unsigned i
= 0; i
< 3; i
++)
2237 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2241 case nir_intrinsic_load_num_work_groups
: {
2242 const unsigned surface
=
2243 cs_prog_data
->binding_table
.work_groups_start
;
2245 cs_prog_data
->uses_num_work_groups
= true;
2247 fs_reg surf_index
= brw_imm_ud(surface
);
2248 brw_mark_surface_used(prog_data
, surface
);
2250 /* Read the 3 GLuint components of gl_NumWorkGroups */
2251 for (unsigned i
= 0; i
< 3; i
++) {
2252 fs_reg read_result
=
2253 emit_untyped_read(bld
, surf_index
,
2255 1 /* dims */, 1 /* size */,
2256 BRW_PREDICATE_NONE
);
2257 read_result
.type
= dest
.type
;
2258 bld
.MOV(dest
, read_result
);
2259 dest
= offset(dest
, bld
, 1);
2264 case nir_intrinsic_shared_atomic_add
:
2265 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2267 case nir_intrinsic_shared_atomic_imin
:
2268 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2270 case nir_intrinsic_shared_atomic_umin
:
2271 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2273 case nir_intrinsic_shared_atomic_imax
:
2274 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2276 case nir_intrinsic_shared_atomic_umax
:
2277 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2279 case nir_intrinsic_shared_atomic_and
:
2280 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2282 case nir_intrinsic_shared_atomic_or
:
2283 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2285 case nir_intrinsic_shared_atomic_xor
:
2286 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2288 case nir_intrinsic_shared_atomic_exchange
:
2289 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2291 case nir_intrinsic_shared_atomic_comp_swap
:
2292 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2296 nir_emit_intrinsic(bld
, instr
);
2302 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2305 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2306 dest
= get_nir_dest(instr
->dest
);
2308 switch (instr
->intrinsic
) {
2309 case nir_intrinsic_atomic_counter_inc
:
2310 case nir_intrinsic_atomic_counter_dec
:
2311 case nir_intrinsic_atomic_counter_read
: {
2312 using namespace surface_access
;
2314 /* Get the arguments of the atomic intrinsic. */
2315 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2316 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2317 instr
->const_index
[0]);
2320 /* Emit a surface read or atomic op. */
2321 switch (instr
->intrinsic
) {
2322 case nir_intrinsic_atomic_counter_read
:
2323 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2326 case nir_intrinsic_atomic_counter_inc
:
2327 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2328 fs_reg(), 1, 1, BRW_AOP_INC
);
2331 case nir_intrinsic_atomic_counter_dec
:
2332 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2333 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2337 unreachable("Unreachable");
2340 /* Assign the result. */
2341 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2343 /* Mark the surface as used. */
2344 brw_mark_surface_used(stage_prog_data
, surface
);
2348 case nir_intrinsic_image_load
:
2349 case nir_intrinsic_image_store
:
2350 case nir_intrinsic_image_atomic_add
:
2351 case nir_intrinsic_image_atomic_min
:
2352 case nir_intrinsic_image_atomic_max
:
2353 case nir_intrinsic_image_atomic_and
:
2354 case nir_intrinsic_image_atomic_or
:
2355 case nir_intrinsic_image_atomic_xor
:
2356 case nir_intrinsic_image_atomic_exchange
:
2357 case nir_intrinsic_image_atomic_comp_swap
: {
2358 using namespace image_access
;
2360 /* Get the referenced image variable and type. */
2361 const nir_variable
*var
= instr
->variables
[0]->var
;
2362 const glsl_type
*type
= var
->type
->without_array();
2363 const brw_reg_type base_type
= get_image_base_type(type
);
2365 /* Get some metadata from the image intrinsic. */
2366 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2367 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2368 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2369 const mesa_format format
=
2370 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2371 _mesa_get_shader_image_format(var
->data
.image
.format
));
2373 /* Get the arguments of the image intrinsic. */
2374 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2375 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2376 BRW_REGISTER_TYPE_UD
);
2377 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2378 retype(get_nir_src(instr
->src
[2]), base_type
) :
2380 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2381 retype(get_nir_src(instr
->src
[3]), base_type
) :
2385 /* Emit an image load, store or atomic op. */
2386 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2387 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2389 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2390 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2393 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2394 surf_dims
, arr_dims
, info
->dest_components
,
2395 get_image_atomic_op(instr
->intrinsic
, type
));
2397 /* Assign the result. */
2398 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2399 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2400 offset(tmp
, bld
, c
));
2404 case nir_intrinsic_memory_barrier_atomic_counter
:
2405 case nir_intrinsic_memory_barrier_buffer
:
2406 case nir_intrinsic_memory_barrier_image
:
2407 case nir_intrinsic_memory_barrier
: {
2408 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2409 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2414 case nir_intrinsic_group_memory_barrier
:
2415 case nir_intrinsic_memory_barrier_shared
:
2416 /* We treat these workgroup-level barriers as no-ops. This should be
2417 * safe at present and as long as:
2419 * - Memory access instructions are not subsequently reordered by the
2420 * compiler back-end.
2422 * - All threads from a given compute shader workgroup fit within a
2423 * single subslice and therefore talk to the same HDC shared unit
2424 * what supposedly guarantees ordering and coherency between threads
2425 * from the same workgroup. This may change in the future when we
2426 * start splitting workgroups across multiple subslices.
2428 * - The context is not in fault-and-stream mode, which could cause
2429 * memory transactions (including to SLM) prior to the barrier to be
2430 * replayed after the barrier if a pagefault occurs. This shouldn't
2431 * be a problem up to and including SKL because fault-and-stream is
2432 * not usable due to hardware issues, but that's likely to change in
2437 case nir_intrinsic_shader_clock
: {
2438 /* We cannot do anything if there is an event, so ignore it for now */
2439 fs_reg shader_clock
= get_timestamp(bld
);
2440 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2442 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2446 case nir_intrinsic_image_size
: {
2447 /* Get the referenced image variable and type. */
2448 const nir_variable
*var
= instr
->variables
[0]->var
;
2449 const glsl_type
*type
= var
->type
->without_array();
2451 /* Get the size of the image. */
2452 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2453 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2455 /* For 1DArray image types, the array index is stored in the Z component.
2456 * Fix this by swizzling the Z component to the Y component.
2458 const bool is_1d_array_image
=
2459 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2460 type
->sampler_array
;
2462 /* For CubeArray images, we should count the number of cubes instead
2463 * of the number of faces. Fix it by dividing the (Z component) by 6.
2465 const bool is_cube_array_image
=
2466 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2467 type
->sampler_array
;
2469 /* Copy all the components. */
2470 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2471 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2472 if ((int)c
>= type
->coordinate_components()) {
2473 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2475 } else if (c
== 1 && is_1d_array_image
) {
2476 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2477 offset(size
, bld
, 2));
2478 } else if (c
== 2 && is_cube_array_image
) {
2479 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2480 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2481 offset(size
, bld
, c
), brw_imm_d(6));
2483 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2484 offset(size
, bld
, c
));
2491 case nir_intrinsic_image_samples
:
2492 /* The driver does not support multi-sampled images. */
2493 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2496 case nir_intrinsic_load_uniform
: {
2497 /* Offsets are in bytes but they should always be multiples of 4 */
2498 assert(instr
->const_index
[0] % 4 == 0);
2500 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2502 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2504 /* Offsets are in bytes but they should always be multiples of 4 */
2505 assert(const_offset
->u
[0] % 4 == 0);
2506 src
.reg_offset
= const_offset
->u
[0] / 4;
2508 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2511 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2512 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2517 case nir_intrinsic_load_ubo
: {
2518 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2522 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2524 surf_index
= brw_imm_ud(index
);
2525 brw_mark_surface_used(prog_data
, index
);
2527 /* The block index is not a constant. Evaluate the index expression
2528 * per-channel and add the base UBO index; we have to select a value
2529 * from any live channel.
2531 surf_index
= vgrf(glsl_type::uint_type
);
2532 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2533 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2534 surf_index
= bld
.emit_uniformize(surf_index
);
2536 /* Assume this may touch any UBO. It would be nice to provide
2537 * a tighter bound, but the array information is already lowered away.
2539 brw_mark_surface_used(prog_data
,
2540 stage_prog_data
->binding_table
.ubo_start
+
2541 nir
->info
.num_ubos
- 1);
2544 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2545 if (const_offset
== NULL
) {
2546 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2547 BRW_REGISTER_TYPE_D
);
2549 for (int i
= 0; i
< instr
->num_components
; i
++)
2550 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2551 base_offset
, i
* 4);
2553 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2554 packed_consts
.type
= dest
.type
;
2556 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2557 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2558 surf_index
, const_offset_reg
);
2560 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2561 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2563 /* The std140 packing rules don't allow vectors to cross 16-byte
2564 * boundaries, and a reg is 32 bytes.
2566 assert(packed_consts
.subreg_offset
< 32);
2568 bld
.MOV(dest
, packed_consts
);
2569 dest
= offset(dest
, bld
, 1);
2575 case nir_intrinsic_load_ssbo
: {
2576 assert(devinfo
->gen
>= 7);
2578 nir_const_value
*const_uniform_block
=
2579 nir_src_as_const_value(instr
->src
[0]);
2582 if (const_uniform_block
) {
2583 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2584 const_uniform_block
->u
[0];
2585 surf_index
= brw_imm_ud(index
);
2586 brw_mark_surface_used(prog_data
, index
);
2588 surf_index
= vgrf(glsl_type::uint_type
);
2589 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2590 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2592 /* Assume this may touch any UBO. It would be nice to provide
2593 * a tighter bound, but the array information is already lowered away.
2595 brw_mark_surface_used(prog_data
,
2596 stage_prog_data
->binding_table
.ssbo_start
+
2597 nir
->info
.num_ssbos
- 1);
2601 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2603 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2605 offset_reg
= get_nir_src(instr
->src
[1]);
2608 /* Read the vector */
2609 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2611 instr
->num_components
,
2612 BRW_PREDICATE_NONE
);
2613 read_result
.type
= dest
.type
;
2614 for (int i
= 0; i
< instr
->num_components
; i
++)
2615 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2620 case nir_intrinsic_load_shared
: {
2621 assert(devinfo
->gen
>= 7);
2623 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2625 /* Get the offset to read from */
2627 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2629 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2631 offset_reg
= vgrf(glsl_type::uint_type
);
2633 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2634 brw_imm_ud(instr
->const_index
[0]));
2637 /* Read the vector */
2638 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2640 instr
->num_components
,
2641 BRW_PREDICATE_NONE
);
2642 read_result
.type
= dest
.type
;
2643 for (int i
= 0; i
< instr
->num_components
; i
++)
2644 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2649 case nir_intrinsic_store_shared
: {
2650 assert(devinfo
->gen
>= 7);
2653 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2656 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2659 unsigned writemask
= instr
->const_index
[1];
2661 /* Combine groups of consecutive enabled channels in one write
2662 * message. We use ffs to find the first enabled channel and then ffs on
2663 * the bit-inverse, down-shifted writemask to determine the length of
2664 * the block of enabled bits.
2667 unsigned first_component
= ffs(writemask
) - 1;
2668 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2671 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2673 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2674 4 * first_component
);
2676 offset_reg
= vgrf(glsl_type::uint_type
);
2678 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2679 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2682 emit_untyped_write(bld
, surf_index
, offset_reg
,
2683 offset(val_reg
, bld
, first_component
),
2684 1 /* dims */, length
,
2685 BRW_PREDICATE_NONE
);
2687 /* Clear the bits in the writemask that we just wrote, then try
2688 * again to see if more channels are left.
2690 writemask
&= (15 << (first_component
+ length
));
2696 case nir_intrinsic_load_input
: {
2698 if (stage
== MESA_SHADER_VERTEX
) {
2699 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2701 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2702 instr
->const_index
[0]);
2705 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2706 assert(const_offset
&& "Indirect input loads not allowed");
2707 src
= offset(src
, bld
, const_offset
->u
[0]);
2709 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2710 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2715 case nir_intrinsic_store_ssbo
: {
2716 assert(devinfo
->gen
>= 7);
2720 nir_const_value
*const_uniform_block
=
2721 nir_src_as_const_value(instr
->src
[1]);
2722 if (const_uniform_block
) {
2723 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2724 const_uniform_block
->u
[0];
2725 surf_index
= brw_imm_ud(index
);
2726 brw_mark_surface_used(prog_data
, index
);
2728 surf_index
= vgrf(glsl_type::uint_type
);
2729 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2730 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2732 brw_mark_surface_used(prog_data
,
2733 stage_prog_data
->binding_table
.ssbo_start
+
2734 nir
->info
.num_ssbos
- 1);
2738 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2741 unsigned writemask
= instr
->const_index
[0];
2743 /* Combine groups of consecutive enabled channels in one write
2744 * message. We use ffs to find the first enabled channel and then ffs on
2745 * the bit-inverse, down-shifted writemask to determine the length of
2746 * the block of enabled bits.
2749 unsigned first_component
= ffs(writemask
) - 1;
2750 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2753 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2755 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2757 offset_reg
= vgrf(glsl_type::uint_type
);
2759 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2760 brw_imm_ud(4 * first_component
));
2763 emit_untyped_write(bld
, surf_index
, offset_reg
,
2764 offset(val_reg
, bld
, first_component
),
2765 1 /* dims */, length
,
2766 BRW_PREDICATE_NONE
);
2768 /* Clear the bits in the writemask that we just wrote, then try
2769 * again to see if more channels are left.
2771 writemask
&= (15 << (first_component
+ length
));
2776 case nir_intrinsic_store_output
: {
2777 fs_reg src
= get_nir_src(instr
->src
[0]);
2778 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2779 instr
->const_index
[0]);
2781 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2782 assert(const_offset
&& "Indirect output stores not allowed");
2783 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2785 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2786 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2791 case nir_intrinsic_ssbo_atomic_add
:
2792 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2794 case nir_intrinsic_ssbo_atomic_imin
:
2795 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2797 case nir_intrinsic_ssbo_atomic_umin
:
2798 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2800 case nir_intrinsic_ssbo_atomic_imax
:
2801 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2803 case nir_intrinsic_ssbo_atomic_umax
:
2804 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2806 case nir_intrinsic_ssbo_atomic_and
:
2807 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2809 case nir_intrinsic_ssbo_atomic_or
:
2810 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2812 case nir_intrinsic_ssbo_atomic_xor
:
2813 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2815 case nir_intrinsic_ssbo_atomic_exchange
:
2816 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2818 case nir_intrinsic_ssbo_atomic_comp_swap
:
2819 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2822 case nir_intrinsic_get_buffer_size
: {
2823 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2824 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2825 int reg_width
= dispatch_width
/ 8;
2828 fs_reg source
= brw_imm_d(0);
2830 int mlen
= 1 * reg_width
;
2832 /* A resinfo's sampler message is used to get the buffer size.
2833 * The SIMD8's writeback message consists of four registers and
2834 * SIMD16's writeback message consists of 8 destination registers
2835 * (two per each component), although we are only interested on the
2836 * first component, where resinfo returns the buffer size for
2839 int regs_written
= 4 * mlen
;
2840 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2841 BRW_REGISTER_TYPE_UD
);
2842 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2843 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2844 BRW_REGISTER_TYPE_UD
);
2845 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2846 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2847 src_payload
, brw_imm_ud(index
));
2848 inst
->header_size
= 0;
2850 inst
->regs_written
= regs_written
;
2852 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2854 brw_mark_surface_used(prog_data
, index
);
2859 unreachable("unknown intrinsic");
2864 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2865 int op
, nir_intrinsic_instr
*instr
)
2868 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2869 dest
= get_nir_dest(instr
->dest
);
2872 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2873 if (const_surface
) {
2874 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2875 const_surface
->u
[0];
2876 surface
= brw_imm_ud(surf_index
);
2877 brw_mark_surface_used(prog_data
, surf_index
);
2879 surface
= vgrf(glsl_type::uint_type
);
2880 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2881 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2883 /* Assume this may touch any SSBO. This is the same we do for other
2884 * UBO/SSBO accesses with non-constant surface.
2886 brw_mark_surface_used(prog_data
,
2887 stage_prog_data
->binding_table
.ssbo_start
+
2888 nir
->info
.num_ssbos
- 1);
2891 fs_reg offset
= get_nir_src(instr
->src
[1]);
2892 fs_reg data1
= get_nir_src(instr
->src
[2]);
2894 if (op
== BRW_AOP_CMPWR
)
2895 data2
= get_nir_src(instr
->src
[3]);
2897 /* Emit the actual atomic operation operation */
2899 fs_reg atomic_result
=
2900 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2902 1 /* dims */, 1 /* rsize */,
2904 BRW_PREDICATE_NONE
);
2905 dest
.type
= atomic_result
.type
;
2906 bld
.MOV(dest
, atomic_result
);
2910 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2911 int op
, nir_intrinsic_instr
*instr
)
2914 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2915 dest
= get_nir_dest(instr
->dest
);
2917 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2918 fs_reg offset
= get_nir_src(instr
->src
[0]);
2919 fs_reg data1
= get_nir_src(instr
->src
[1]);
2921 if (op
== BRW_AOP_CMPWR
)
2922 data2
= get_nir_src(instr
->src
[2]);
2924 /* Emit the actual atomic operation operation */
2926 fs_reg atomic_result
=
2927 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2929 1 /* dims */, 1 /* rsize */,
2931 BRW_PREDICATE_NONE
);
2932 dest
.type
= atomic_result
.type
;
2933 bld
.MOV(dest
, atomic_result
);
2937 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2939 unsigned sampler
= instr
->sampler_index
;
2940 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2942 int gather_component
= instr
->component
;
2944 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2947 int lod_components
= 0;
2948 int UNUSED offset_components
= 0;
2950 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2952 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2953 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2954 switch (instr
->src
[i
].src_type
) {
2955 case nir_tex_src_bias
:
2956 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2958 case nir_tex_src_comparitor
:
2959 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2961 case nir_tex_src_coord
:
2962 switch (instr
->op
) {
2964 case nir_texop_txf_ms
:
2965 case nir_texop_samples_identical
:
2966 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2969 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2973 case nir_tex_src_ddx
:
2974 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2975 lod_components
= nir_tex_instr_src_size(instr
, i
);
2977 case nir_tex_src_ddy
:
2978 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2980 case nir_tex_src_lod
:
2981 switch (instr
->op
) {
2983 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2986 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2989 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2993 case nir_tex_src_ms_index
:
2994 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2996 case nir_tex_src_offset
:
2997 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2998 if (instr
->is_array
)
2999 offset_components
= instr
->coord_components
- 1;
3001 offset_components
= instr
->coord_components
;
3003 case nir_tex_src_projector
:
3004 unreachable("should be lowered");
3006 case nir_tex_src_sampler_offset
: {
3007 /* Figure out the highest possible sampler index and mark it as used */
3008 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
3009 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3010 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3012 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3014 brw_mark_surface_used(prog_data
, max_used
);
3016 /* Emit code to evaluate the actual indexing expression */
3017 sampler_reg
= vgrf(glsl_type::uint_type
);
3018 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3019 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3024 unreachable("unknown texture source");
3028 if (instr
->op
== nir_texop_txf_ms
||
3029 instr
->op
== nir_texop_samples_identical
) {
3030 if (devinfo
->gen
>= 7 &&
3031 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
3032 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
3034 mcs
= brw_imm_ud(0u);
3038 for (unsigned i
= 0; i
< 3; i
++) {
3039 if (instr
->const_offset
[i
] != 0) {
3040 assert(offset_components
== 0);
3041 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
3046 enum glsl_base_type dest_base_type
=
3047 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3049 const glsl_type
*dest_type
=
3050 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3053 ir_texture_opcode op
;
3054 switch (instr
->op
) {
3055 case nir_texop_lod
: op
= ir_lod
; break;
3056 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3057 case nir_texop_tex
: op
= ir_tex
; break;
3058 case nir_texop_tg4
: op
= ir_tg4
; break;
3059 case nir_texop_txb
: op
= ir_txb
; break;
3060 case nir_texop_txd
: op
= ir_txd
; break;
3061 case nir_texop_txf
: op
= ir_txf
; break;
3062 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3063 case nir_texop_txl
: op
= ir_txl
; break;
3064 case nir_texop_txs
: op
= ir_txs
; break;
3065 case nir_texop_texture_samples
: {
3066 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3067 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3068 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3071 inst
->header_size
= 1;
3072 inst
->base_mrf
= -1;
3075 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3077 unreachable("unknown texture opcode");
3080 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3081 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3082 tex_offset
, mcs
, gather_component
,
3083 is_cube_array
, sampler
, sampler_reg
);
3085 fs_reg dest
= get_nir_dest(instr
->dest
);
3086 dest
.type
= this->result
.type
;
3087 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3088 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3089 dest
, this->result
),
3090 (1 << num_components
) - 1);
3094 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3096 switch (instr
->type
) {
3097 case nir_jump_break
:
3098 bld
.emit(BRW_OPCODE_BREAK
);
3100 case nir_jump_continue
:
3101 bld
.emit(BRW_OPCODE_CONTINUE
);
3103 case nir_jump_return
:
3105 unreachable("unknown jump");