2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
31 #include "brw_vec4_gs_visitor.h"
33 #include "brw_fs_surface_builder.h"
34 #include "brw_vec4_gs_visitor.h"
37 using namespace brw::surface_access
;
40 fs_visitor::emit_nir_code()
42 /* emit the arrays used for inputs and outputs - load/store intrinsics will
43 * be converted to reads/writes of these arrays
48 nir_emit_system_values();
50 /* get the main function and emit it */
51 nir_foreach_overload(nir
, overload
) {
52 assert(strcmp(overload
->function
->name
, "main") == 0);
53 assert(overload
->impl
);
54 nir_emit_impl(overload
->impl
);
59 fs_visitor::nir_setup_inputs()
61 if (stage
!= MESA_SHADER_FRAGMENT
)
64 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
66 nir_foreach_variable(var
, &nir
->inputs
) {
67 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
70 if (var
->data
.location
== VARYING_SLOT_POS
) {
71 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
72 var
->data
.origin_upper_left
);
73 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
75 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
76 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
77 reg
.type
= BRW_REGISTER_TYPE_D
;
78 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
80 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
81 reg
.type
= BRW_REGISTER_TYPE_D
;
82 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
84 emit_general_interpolation(input
, var
->name
, var
->type
,
85 (glsl_interp_qualifier
) var
->data
.interpolation
,
86 var
->data
.location
, var
->data
.centroid
,
93 fs_visitor::nir_setup_outputs()
95 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
97 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
99 nir_foreach_variable(var
, &nir
->outputs
) {
100 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
102 int vector_elements
= var
->type
->without_array()->vector_elements
;
105 case MESA_SHADER_VERTEX
:
106 case MESA_SHADER_GEOMETRY
:
107 for (int i
= 0; i
< type_size_vec4(var
->type
); i
++) {
108 int output
= var
->data
.location
+ i
;
109 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
110 this->output_components
[output
] = vector_elements
;
113 case MESA_SHADER_FRAGMENT
:
114 if (var
->data
.index
> 0) {
115 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
116 assert(var
->data
.index
== 1);
117 this->dual_src_output
= reg
;
118 this->do_dual_src
= true;
119 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
120 /* Writing gl_FragColor outputs to all color regions. */
121 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
122 this->outputs
[i
] = reg
;
123 this->output_components
[i
] = 4;
125 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
126 this->frag_depth
= reg
;
127 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
128 this->frag_stencil
= reg
;
129 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
130 this->sample_mask
= reg
;
132 /* gl_FragData or a user-defined FS output */
133 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
134 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
136 /* General color output. */
137 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
138 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
139 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
140 this->output_components
[output
] = vector_elements
;
145 unreachable("unhandled shader stage");
151 fs_visitor::nir_setup_uniforms()
153 if (dispatch_width
!= 8)
156 uniforms
= nir
->num_uniforms
;
158 nir_foreach_variable(var
, &nir
->uniforms
) {
159 /* UBO's and atomics don't take up space in the uniform file */
160 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
163 if (type_size_scalar(var
->type
) > 0)
164 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
169 emit_system_values_block(nir_block
*block
, void *void_visitor
)
171 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
174 nir_foreach_instr(block
, instr
) {
175 if (instr
->type
!= nir_instr_type_intrinsic
)
178 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
179 switch (intrin
->intrinsic
) {
180 case nir_intrinsic_load_vertex_id
:
181 unreachable("should be lowered by lower_vertex_id().");
183 case nir_intrinsic_load_vertex_id_zero_base
:
184 assert(v
->stage
== MESA_SHADER_VERTEX
);
185 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
186 if (reg
->file
== BAD_FILE
)
187 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
190 case nir_intrinsic_load_base_vertex
:
191 assert(v
->stage
== MESA_SHADER_VERTEX
);
192 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
193 if (reg
->file
== BAD_FILE
)
194 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
197 case nir_intrinsic_load_instance_id
:
198 assert(v
->stage
== MESA_SHADER_VERTEX
);
199 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
200 if (reg
->file
== BAD_FILE
)
201 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
204 case nir_intrinsic_load_invocation_id
:
205 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
207 if (reg
->file
== BAD_FILE
) {
208 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
209 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
210 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
211 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
216 case nir_intrinsic_load_sample_pos
:
217 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
218 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
219 if (reg
->file
== BAD_FILE
)
220 *reg
= *v
->emit_samplepos_setup();
223 case nir_intrinsic_load_sample_id
:
224 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
225 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
226 if (reg
->file
== BAD_FILE
)
227 *reg
= *v
->emit_sampleid_setup();
230 case nir_intrinsic_load_sample_mask_in
:
231 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
232 assert(v
->devinfo
->gen
>= 7);
233 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
234 if (reg
->file
== BAD_FILE
)
235 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
236 BRW_REGISTER_TYPE_D
));
239 case nir_intrinsic_load_local_invocation_id
:
240 assert(v
->stage
== MESA_SHADER_COMPUTE
);
241 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
242 if (reg
->file
== BAD_FILE
)
243 *reg
= *v
->emit_cs_local_invocation_id_setup();
246 case nir_intrinsic_load_work_group_id
:
247 assert(v
->stage
== MESA_SHADER_COMPUTE
);
248 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
249 if (reg
->file
== BAD_FILE
)
250 *reg
= *v
->emit_cs_work_group_id_setup();
253 case nir_intrinsic_load_helper_invocation
:
254 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
255 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
256 if (reg
->file
== BAD_FILE
) {
257 const fs_builder abld
=
258 v
->bld
.annotate("gl_HelperInvocation", NULL
);
260 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
261 * pixel mask is in g1.7 of the thread payload.
263 * We move the per-channel pixel enable bit to the low bit of each
264 * channel by shifting the byte containing the pixel mask by the
265 * vector immediate 0x76543210UV.
267 * The region of <1,8,0> reads only 1 byte (the pixel masks for
268 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
269 * masks for 2 and 3) in SIMD16.
271 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
273 stride(byte_offset(retype(brw_vec1_grf(1, 0),
274 BRW_REGISTER_TYPE_UB
), 28),
276 brw_imm_uv(0x76543210));
278 /* A set bit in the pixel mask means the channel is enabled, but
279 * that is the opposite of gl_HelperInvocation so we need to invert
282 * The negate source-modifier bit of logical instructions on Gen8+
283 * performs 1's complement negation, so we can use that instead of
286 fs_reg inverted
= negate(shifted
);
287 if (v
->devinfo
->gen
< 8) {
288 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
289 abld
.NOT(inverted
, shifted
);
292 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
293 * with 1 and negating.
295 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
296 abld
.AND(anded
, inverted
, brw_imm_uw(1));
298 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
299 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
313 fs_visitor::nir_emit_system_values()
315 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
316 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
317 nir_system_values
[i
] = fs_reg();
320 nir_foreach_overload(nir
, overload
) {
321 assert(strcmp(overload
->function
->name
, "main") == 0);
322 assert(overload
->impl
);
323 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
328 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
330 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
331 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
332 nir_locals
[i
] = fs_reg();
335 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
336 unsigned array_elems
=
337 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
338 unsigned size
= array_elems
* reg
->num_components
;
339 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
342 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
345 nir_emit_cf_list(&impl
->body
);
349 fs_visitor::nir_emit_cf_list(exec_list
*list
)
351 exec_list_validate(list
);
352 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
353 switch (node
->type
) {
355 nir_emit_if(nir_cf_node_as_if(node
));
358 case nir_cf_node_loop
:
359 nir_emit_loop(nir_cf_node_as_loop(node
));
362 case nir_cf_node_block
:
363 nir_emit_block(nir_cf_node_as_block(node
));
367 unreachable("Invalid CFG node block");
373 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
375 /* first, put the condition into f0 */
376 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
377 retype(get_nir_src(if_stmt
->condition
),
378 BRW_REGISTER_TYPE_D
));
379 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
381 bld
.IF(BRW_PREDICATE_NORMAL
);
383 nir_emit_cf_list(&if_stmt
->then_list
);
385 /* note: if the else is empty, dead CF elimination will remove it */
386 bld
.emit(BRW_OPCODE_ELSE
);
388 nir_emit_cf_list(&if_stmt
->else_list
);
390 bld
.emit(BRW_OPCODE_ENDIF
);
394 fs_visitor::nir_emit_loop(nir_loop
*loop
)
396 bld
.emit(BRW_OPCODE_DO
);
398 nir_emit_cf_list(&loop
->body
);
400 bld
.emit(BRW_OPCODE_WHILE
);
404 fs_visitor::nir_emit_block(nir_block
*block
)
406 nir_foreach_instr(block
, instr
) {
407 nir_emit_instr(instr
);
412 fs_visitor::nir_emit_instr(nir_instr
*instr
)
414 const fs_builder abld
= bld
.annotate(NULL
, instr
);
416 switch (instr
->type
) {
417 case nir_instr_type_alu
:
418 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
421 case nir_instr_type_intrinsic
:
423 case MESA_SHADER_VERTEX
:
424 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
426 case MESA_SHADER_GEOMETRY
:
427 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
429 case MESA_SHADER_FRAGMENT
:
430 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
432 case MESA_SHADER_COMPUTE
:
433 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
436 unreachable("unsupported shader stage");
440 case nir_instr_type_tex
:
441 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
444 case nir_instr_type_load_const
:
445 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
448 case nir_instr_type_ssa_undef
:
449 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
452 case nir_instr_type_jump
:
453 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
457 unreachable("unknown instruction type");
462 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
463 const fs_reg
&result
)
465 if (!instr
->src
[0].src
.is_ssa
||
466 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
469 nir_intrinsic_instr
*src0
=
470 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
472 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
475 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
476 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
479 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
480 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
483 fs_reg tmp
= vgrf(glsl_type::int_type
);
485 if (devinfo
->gen
>= 6) {
486 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
487 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
489 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
491 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
492 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
494 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
496 * This negation looks like it's safe in practice, because bits 0:4 will
497 * surely be TRIANGLES
500 if (value1
->f
[0] == -1.0f
) {
504 tmp
.type
= BRW_REGISTER_TYPE_W
;
505 tmp
.subreg_offset
= 2;
508 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
510 tmp
.type
= BRW_REGISTER_TYPE_D
;
511 tmp
.subreg_offset
= 0;
514 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
515 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
517 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
519 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
520 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
522 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
524 * This negation looks like it's safe in practice, because bits 0:4 will
525 * surely be TRIANGLES
528 if (value1
->f
[0] == -1.0f
) {
532 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
534 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
540 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
542 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
545 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
546 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
549 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
550 op
[i
] = get_nir_src(instr
->src
[i
].src
);
551 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
552 op
[i
].abs
= instr
->src
[i
].abs
;
553 op
[i
].negate
= instr
->src
[i
].negate
;
556 /* We get a bunch of mov's out of the from_ssa pass and they may still
557 * be vectorized. We'll handle them as a special-case. We'll also
558 * handle vecN here because it's basically the same thing.
566 fs_reg temp
= result
;
567 bool need_extra_copy
= false;
568 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
569 if (!instr
->src
[i
].src
.is_ssa
&&
570 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
571 need_extra_copy
= true;
572 temp
= bld
.vgrf(result
.type
, 4);
577 for (unsigned i
= 0; i
< 4; i
++) {
578 if (!(instr
->dest
.write_mask
& (1 << i
)))
581 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
582 inst
= bld
.MOV(offset(temp
, bld
, i
),
583 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
585 inst
= bld
.MOV(offset(temp
, bld
, i
),
586 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
588 inst
->saturate
= instr
->dest
.saturate
;
591 /* In this case the source and destination registers were the same,
592 * so we need to insert an extra set of moves in order to deal with
595 if (need_extra_copy
) {
596 for (unsigned i
= 0; i
< 4; i
++) {
597 if (!(instr
->dest
.write_mask
& (1 << i
)))
600 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
609 /* At this point, we have dealt with any instruction that operates on
610 * more than a single channel. Therefore, we can just adjust the source
611 * and destination registers for that channel and emit the instruction.
613 unsigned channel
= 0;
614 if (nir_op_infos
[instr
->op
].output_size
== 0) {
615 /* Since NIR is doing the scalarizing for us, we should only ever see
616 * vectorized operations with a single channel.
618 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
619 channel
= ffs(instr
->dest
.write_mask
) - 1;
621 result
= offset(result
, bld
, channel
);
624 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
625 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
626 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
632 inst
= bld
.MOV(result
, op
[0]);
633 inst
->saturate
= instr
->dest
.saturate
;
638 bld
.MOV(result
, op
[0]);
642 /* AND(val, 0x80000000) gives the sign bit.
644 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
647 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
649 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
650 op
[0].type
= BRW_REGISTER_TYPE_UD
;
651 result
.type
= BRW_REGISTER_TYPE_UD
;
652 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
654 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
655 inst
->predicate
= BRW_PREDICATE_NORMAL
;
656 if (instr
->dest
.saturate
) {
657 inst
= bld
.MOV(result
, result
);
658 inst
->saturate
= true;
664 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
665 * -> non-negative val generates 0x00000000.
666 * Predicated OR sets 1 if val is positive.
668 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
669 bld
.ASR(result
, op
[0], brw_imm_d(31));
670 inst
= bld
.OR(result
, result
, brw_imm_d(1));
671 inst
->predicate
= BRW_PREDICATE_NORMAL
;
675 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
676 inst
->saturate
= instr
->dest
.saturate
;
680 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
681 inst
->saturate
= instr
->dest
.saturate
;
685 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
686 inst
->saturate
= instr
->dest
.saturate
;
690 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
691 inst
->saturate
= instr
->dest
.saturate
;
695 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
696 inst
->saturate
= instr
->dest
.saturate
;
700 if (fs_key
->high_quality_derivatives
) {
701 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
703 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
705 inst
->saturate
= instr
->dest
.saturate
;
707 case nir_op_fddx_fine
:
708 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
709 inst
->saturate
= instr
->dest
.saturate
;
711 case nir_op_fddx_coarse
:
712 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
713 inst
->saturate
= instr
->dest
.saturate
;
716 if (fs_key
->high_quality_derivatives
) {
717 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
718 brw_imm_d(fs_key
->render_to_fbo
));
720 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
721 brw_imm_d(fs_key
->render_to_fbo
));
723 inst
->saturate
= instr
->dest
.saturate
;
725 case nir_op_fddy_fine
:
726 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
727 brw_imm_d(fs_key
->render_to_fbo
));
728 inst
->saturate
= instr
->dest
.saturate
;
730 case nir_op_fddy_coarse
:
731 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
732 brw_imm_d(fs_key
->render_to_fbo
));
733 inst
->saturate
= instr
->dest
.saturate
;
738 inst
= bld
.ADD(result
, op
[0], op
[1]);
739 inst
->saturate
= instr
->dest
.saturate
;
743 inst
= bld
.MUL(result
, op
[0], op
[1]);
744 inst
->saturate
= instr
->dest
.saturate
;
748 bld
.MUL(result
, op
[0], op
[1]);
751 case nir_op_imul_high
:
752 case nir_op_umul_high
:
753 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
758 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
761 case nir_op_uadd_carry
:
762 unreachable("Should have been lowered by carry_to_arith().");
764 case nir_op_usub_borrow
:
765 unreachable("Should have been lowered by borrow_to_arith().");
768 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
774 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
780 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
785 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
790 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
794 if (devinfo
->gen
>= 8) {
795 op
[0] = resolve_source_modifiers(op
[0]);
797 bld
.NOT(result
, op
[0]);
800 if (devinfo
->gen
>= 8) {
801 op
[0] = resolve_source_modifiers(op
[0]);
802 op
[1] = resolve_source_modifiers(op
[1]);
804 bld
.XOR(result
, op
[0], op
[1]);
807 if (devinfo
->gen
>= 8) {
808 op
[0] = resolve_source_modifiers(op
[0]);
809 op
[1] = resolve_source_modifiers(op
[1]);
811 bld
.OR(result
, op
[0], op
[1]);
814 if (devinfo
->gen
>= 8) {
815 op
[0] = resolve_source_modifiers(op
[0]);
816 op
[1] = resolve_source_modifiers(op
[1]);
818 bld
.AND(result
, op
[0], op
[1]);
830 case nir_op_ball_fequal2
:
831 case nir_op_ball_iequal2
:
832 case nir_op_ball_fequal3
:
833 case nir_op_ball_iequal3
:
834 case nir_op_ball_fequal4
:
835 case nir_op_ball_iequal4
:
836 case nir_op_bany_fnequal2
:
837 case nir_op_bany_inequal2
:
838 case nir_op_bany_fnequal3
:
839 case nir_op_bany_inequal3
:
840 case nir_op_bany_fnequal4
:
841 case nir_op_bany_inequal4
:
842 unreachable("Lowered by nir_lower_alu_reductions");
844 case nir_op_fnoise1_1
:
845 case nir_op_fnoise1_2
:
846 case nir_op_fnoise1_3
:
847 case nir_op_fnoise1_4
:
848 case nir_op_fnoise2_1
:
849 case nir_op_fnoise2_2
:
850 case nir_op_fnoise2_3
:
851 case nir_op_fnoise2_4
:
852 case nir_op_fnoise3_1
:
853 case nir_op_fnoise3_2
:
854 case nir_op_fnoise3_3
:
855 case nir_op_fnoise3_4
:
856 case nir_op_fnoise4_1
:
857 case nir_op_fnoise4_2
:
858 case nir_op_fnoise4_3
:
859 case nir_op_fnoise4_4
:
860 unreachable("not reached: should be handled by lower_noise");
863 unreachable("not reached: should be handled by ldexp_to_arith()");
866 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
867 inst
->saturate
= instr
->dest
.saturate
;
871 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
872 inst
->saturate
= instr
->dest
.saturate
;
877 bld
.MOV(result
, negate(op
[0]));
881 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
884 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
888 inst
= bld
.RNDZ(result
, op
[0]);
889 inst
->saturate
= instr
->dest
.saturate
;
893 op
[0].negate
= !op
[0].negate
;
894 fs_reg temp
= vgrf(glsl_type::float_type
);
895 bld
.RNDD(temp
, op
[0]);
897 inst
= bld
.MOV(result
, temp
);
898 inst
->saturate
= instr
->dest
.saturate
;
902 inst
= bld
.RNDD(result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
906 inst
= bld
.FRC(result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
909 case nir_op_fround_even
:
910 inst
= bld
.RNDE(result
, op
[0]);
911 inst
->saturate
= instr
->dest
.saturate
;
917 if (devinfo
->gen
>= 6) {
918 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
919 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
921 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
922 inst
= bld
.SEL(result
, op
[0], op
[1]);
923 inst
->predicate
= BRW_PREDICATE_NORMAL
;
925 inst
->saturate
= instr
->dest
.saturate
;
931 if (devinfo
->gen
>= 6) {
932 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
933 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
935 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
936 inst
= bld
.SEL(result
, op
[0], op
[1]);
937 inst
->predicate
= BRW_PREDICATE_NORMAL
;
939 inst
->saturate
= instr
->dest
.saturate
;
942 case nir_op_pack_snorm_2x16
:
943 case nir_op_pack_snorm_4x8
:
944 case nir_op_pack_unorm_2x16
:
945 case nir_op_pack_unorm_4x8
:
946 case nir_op_unpack_snorm_2x16
:
947 case nir_op_unpack_snorm_4x8
:
948 case nir_op_unpack_unorm_2x16
:
949 case nir_op_unpack_unorm_4x8
:
950 case nir_op_unpack_half_2x16
:
951 case nir_op_pack_half_2x16
:
952 unreachable("not reached: should be handled by lower_packing_builtins");
954 case nir_op_unpack_half_2x16_split_x
:
955 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
956 inst
->saturate
= instr
->dest
.saturate
;
958 case nir_op_unpack_half_2x16_split_y
:
959 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
964 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
965 inst
->saturate
= instr
->dest
.saturate
;
968 case nir_op_bitfield_reverse
:
969 bld
.BFREV(result
, op
[0]);
972 case nir_op_bit_count
:
973 bld
.CBIT(result
, op
[0]);
976 case nir_op_ufind_msb
:
977 case nir_op_ifind_msb
: {
978 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
980 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
981 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
982 * subtract the result from 31 to convert the MSB count into an LSB count.
984 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
986 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
987 inst
->predicate
= BRW_PREDICATE_NORMAL
;
988 inst
->src
[0].negate
= true;
992 case nir_op_find_lsb
:
993 bld
.FBL(result
, op
[0]);
996 case nir_op_ubitfield_extract
:
997 case nir_op_ibitfield_extract
:
998 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1001 bld
.BFI1(result
, op
[0], op
[1]);
1004 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1007 case nir_op_bitfield_insert
:
1008 unreachable("not reached: should be handled by "
1009 "lower_instructions::bitfield_insert_to_bfm_bfi");
1012 bld
.SHL(result
, op
[0], op
[1]);
1015 bld
.ASR(result
, op
[0], op
[1]);
1018 bld
.SHR(result
, op
[0], op
[1]);
1021 case nir_op_pack_half_2x16_split
:
1022 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1026 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1027 inst
->saturate
= instr
->dest
.saturate
;
1031 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1032 inst
->saturate
= instr
->dest
.saturate
;
1036 if (optimize_frontfacing_ternary(instr
, result
))
1039 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1040 inst
= bld
.SEL(result
, op
[1], op
[2]);
1041 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1045 unreachable("unhandled instruction");
1048 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1049 * to sign extend the low bit to 0/~0
1051 if (devinfo
->gen
<= 5 &&
1052 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1053 fs_reg masked
= vgrf(glsl_type::int_type
);
1054 bld
.AND(masked
, result
, brw_imm_d(1));
1055 masked
.negate
= true;
1056 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1061 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1062 nir_load_const_instr
*instr
)
1064 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1066 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1067 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1069 nir_ssa_values
[instr
->def
.index
] = reg
;
1073 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1075 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1076 instr
->def
.num_components
);
1080 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1081 unsigned base_offset
, nir_src
*indirect
)
1085 assert(!nir_reg
->is_global
);
1087 reg
= v
->nir_locals
[nir_reg
->index
];
1089 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1091 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1093 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1094 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1095 brw_imm_d(multiplier
));
1102 fs_visitor::get_nir_src(nir_src src
)
1106 reg
= nir_ssa_values
[src
.ssa
->index
];
1108 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1112 /* to avoid floating-point denorm flushing problems, set the type by
1113 * default to D - instructions that need floating point semantics will set
1114 * this to F if they need to
1116 return retype(reg
, BRW_REGISTER_TYPE_D
);
1120 fs_visitor::get_nir_dest(nir_dest dest
)
1123 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1124 dest
.ssa
.num_components
);
1125 return nir_ssa_values
[dest
.ssa
.index
];
1128 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1133 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1135 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1136 BRW_REGISTER_TYPE_UD
);
1138 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1139 tail
= tail
->child
) {
1140 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1141 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1142 const unsigned size
= glsl_get_length(tail
->type
);
1143 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1144 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1145 image
= offset(image
, bld
, base
* element_size
);
1147 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1148 fs_reg tmp
= vgrf(glsl_type::int_type
);
1150 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1151 /* IVB hangs when trying to access an invalid surface index with
1152 * the dataport. According to the spec "if the index used to
1153 * select an individual element is negative or greater than or
1154 * equal to the size of the array, the results of the operation
1155 * are undefined but may not lead to termination" -- which is one
1156 * of the possible outcomes of the hang. Clamp the index to
1157 * prevent access outside of the array bounds.
1159 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1160 BRW_REGISTER_TYPE_UD
),
1161 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1163 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1166 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
));
1168 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1170 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1178 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1181 for (unsigned i
= 0; i
< 4; i
++) {
1182 if (!((wr_mask
>> i
) & 1))
1185 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1186 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1187 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1188 if (new_inst
->src
[j
].file
== VGRF
)
1189 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1196 * Get the matching channel register datatype for an image intrinsic of the
1197 * specified GLSL image type.
1200 get_image_base_type(const glsl_type
*type
)
1202 switch ((glsl_base_type
)type
->sampler_type
) {
1203 case GLSL_TYPE_UINT
:
1204 return BRW_REGISTER_TYPE_UD
;
1206 return BRW_REGISTER_TYPE_D
;
1207 case GLSL_TYPE_FLOAT
:
1208 return BRW_REGISTER_TYPE_F
;
1210 unreachable("Not reached.");
1215 * Get the appropriate atomic op for an image atomic intrinsic.
1218 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1221 case nir_intrinsic_image_atomic_add
:
1223 case nir_intrinsic_image_atomic_min
:
1224 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1225 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1226 case nir_intrinsic_image_atomic_max
:
1227 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1228 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1229 case nir_intrinsic_image_atomic_and
:
1231 case nir_intrinsic_image_atomic_or
:
1233 case nir_intrinsic_image_atomic_xor
:
1235 case nir_intrinsic_image_atomic_exchange
:
1237 case nir_intrinsic_image_atomic_comp_swap
:
1238 return BRW_AOP_CMPWR
;
1240 unreachable("Not reachable.");
1245 emit_pixel_interpolater_send(const fs_builder
&bld
,
1250 glsl_interp_qualifier interpolation
)
1256 if (src
.file
== BAD_FILE
) {
1258 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1262 mlen
= 2 * bld
.dispatch_width() / 8;
1265 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1267 /* 2 floats per slot returned */
1268 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1269 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1275 * Computes 1 << x, given a D/UD register containing some value x.
1278 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1280 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1282 fs_reg result
= bld
.vgrf(x
.type
, 1);
1283 fs_reg one
= bld
.vgrf(x
.type
, 1);
1285 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1286 bld
.SHL(result
, one
, x
);
1291 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1293 assert(stage
== MESA_SHADER_GEOMETRY
);
1295 struct brw_gs_prog_data
*gs_prog_data
=
1296 (struct brw_gs_prog_data
*) prog_data
;
1298 /* We can only do EndPrimitive() functionality when the control data
1299 * consists of cut bits. Fortunately, the only time it isn't is when the
1300 * output type is points, in which case EndPrimitive() is a no-op.
1302 if (gs_prog_data
->control_data_format
!=
1303 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1307 /* Cut bits use one bit per vertex. */
1308 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1310 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1311 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1313 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1314 * vertex n, 0 otherwise. So all we need to do here is mark bit
1315 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1316 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1317 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1319 * Note that if EndPrimitive() is called before emitting any vertices, this
1320 * will cause us to set bit 31 of the control_data_bits register to 1.
1321 * That's fine because:
1323 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1324 * output, so the hardware will ignore cut bit 31.
1326 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1327 * last vertex, so setting cut bit 31 has no effect (since the primitive
1328 * is automatically ended when the GS terminates).
1330 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1331 * control_data_bits register to 0 when the first vertex is emitted.
1334 const fs_builder abld
= bld
.annotate("end primitive");
1336 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1337 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1338 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1339 fs_reg mask
= intexp2(abld
, prev_count
);
1340 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1341 * attention to the lower 5 bits of its second source argument, so on this
1342 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1343 * ((vertex_count - 1) % 32).
1345 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1349 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1351 assert(stage
== MESA_SHADER_GEOMETRY
);
1352 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1354 struct brw_gs_prog_data
*gs_prog_data
=
1355 (struct brw_gs_prog_data
*) prog_data
;
1357 const fs_builder abld
= bld
.annotate("emit control data bits");
1358 const fs_builder fwa_bld
= bld
.exec_all();
1360 /* We use a single UD register to accumulate control data bits (32 bits
1361 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1364 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1365 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1366 * use the Channel Mask phase to enable/disable which DWord within that
1367 * group to write. (Remember, different SIMD8 channels may have emitted
1368 * different numbers of vertices, so we may need per-slot offsets.)
1370 * Channel masking presents an annoying problem: we may have to replicate
1371 * the data up to 4 times:
1373 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1375 * To avoid penalizing shaders that emit a small number of vertices, we
1376 * can avoid these sometimes: if the size of the control data header is
1377 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1378 * land in the same 128-bit group, so we can skip per-slot offsets.
1380 * Similarly, if the control data header is <= 32 bits, there is only one
1381 * DWord, so we can skip channel masks.
1383 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1385 fs_reg channel_mask
, per_slot_offset
;
1387 if (gs_compile
->control_data_header_size_bits
> 32) {
1388 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1389 channel_mask
= vgrf(glsl_type::uint_type
);
1392 if (gs_compile
->control_data_header_size_bits
> 128) {
1393 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1394 per_slot_offset
= vgrf(glsl_type::uint_type
);
1397 /* Figure out which DWord we're trying to write to using the formula:
1399 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1401 * Since bits_per_vertex is a power of two, and is known at compile
1402 * time, this can be optimized to:
1404 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1406 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1407 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1408 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1409 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1410 unsigned log2_bits_per_vertex
=
1411 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1412 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1414 if (per_slot_offset
.file
!= BAD_FILE
) {
1415 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1416 * the appropriate OWord within the control data header.
1418 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1421 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1422 * write to the appropriate DWORD within the OWORD.
1424 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1425 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1426 channel_mask
= intexp2(fwa_bld
, channel
);
1427 /* Then the channel masks need to be in bits 23:16. */
1428 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1431 /* Store the control data bits in the message payload and send it. */
1433 if (channel_mask
.file
!= BAD_FILE
)
1434 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1435 if (per_slot_offset
.file
!= BAD_FILE
)
1438 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1439 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1441 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1442 if (per_slot_offset
.file
!= BAD_FILE
)
1443 sources
[i
++] = per_slot_offset
;
1444 if (channel_mask
.file
!= BAD_FILE
)
1445 sources
[i
++] = channel_mask
;
1447 sources
[i
++] = this->control_data_bits
;
1450 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1451 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1453 /* We need to increment Global Offset by 256-bits to make room for
1454 * Broadwell's extra "Vertex Count" payload at the beginning of the
1455 * URB entry. Since this is an OWord message, Global Offset is counted
1456 * in 128-bit units, so we must set it to 2.
1458 if (gs_prog_data
->static_vertex_count
== -1)
1463 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1466 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1468 /* Note: we are calling this *before* increasing vertex_count, so
1469 * this->vertex_count == vertex_count - 1 in the formula above.
1472 /* Stream mode uses 2 bits per vertex */
1473 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1475 /* Must be a valid stream */
1476 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1478 /* Control data bits are initialized to 0 so we don't have to set any
1479 * bits when sending vertices to stream 0.
1484 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1486 /* reg::sid = stream_id */
1487 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1488 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1490 /* reg:shift_count = 2 * (vertex_count - 1) */
1491 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1492 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1494 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1495 * attention to the lower 5 bits of its second source argument, so on this
1496 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1497 * stream_id << ((2 * (vertex_count - 1)) % 32).
1499 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1500 abld
.SHL(mask
, sid
, shift_count
);
1501 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1505 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1508 assert(stage
== MESA_SHADER_GEOMETRY
);
1510 struct brw_gs_prog_data
*gs_prog_data
=
1511 (struct brw_gs_prog_data
*) prog_data
;
1513 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1514 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1516 /* Haswell and later hardware ignores the "Render Stream Select" bits
1517 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1518 * and instead sends all primitives down the pipeline for rasterization.
1519 * If the SOL stage is enabled, "Render Stream Select" is honored and
1520 * primitives bound to non-zero streams are discarded after stream output.
1522 * Since the only purpose of primives sent to non-zero streams is to
1523 * be recorded by transform feedback, we can simply discard all geometry
1524 * bound to these streams when transform feedback is disabled.
1526 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1529 /* If we're outputting 32 control data bits or less, then we can wait
1530 * until the shader is over to output them all. Otherwise we need to
1531 * output them as we go. Now is the time to do it, since we're about to
1532 * output the vertex_count'th vertex, so it's guaranteed that the
1533 * control data bits associated with the (vertex_count - 1)th vertex are
1536 if (gs_compile
->control_data_header_size_bits
> 32) {
1537 const fs_builder abld
=
1538 bld
.annotate("emit vertex: emit control data bits");
1540 /* Only emit control data bits if we've finished accumulating a batch
1541 * of 32 bits. This is the case when:
1543 * (vertex_count * bits_per_vertex) % 32 == 0
1545 * (in other words, when the last 5 bits of vertex_count *
1546 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1547 * integer n (which is always the case, since bits_per_vertex is
1548 * always 1 or 2), this is equivalent to requiring that the last 5-n
1549 * bits of vertex_count are 0:
1551 * vertex_count & (2^(5-n) - 1) == 0
1553 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1556 * vertex_count & (32 / bits_per_vertex - 1) == 0
1558 * TODO: If vertex_count is an immediate, we could do some of this math
1559 * at compile time...
1562 abld
.AND(bld
.null_reg_d(), vertex_count
,
1563 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1564 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1566 abld
.IF(BRW_PREDICATE_NORMAL
);
1567 /* If vertex_count is 0, then no control data bits have been
1568 * accumulated yet, so we can skip emitting them.
1570 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1571 BRW_CONDITIONAL_NEQ
);
1572 abld
.IF(BRW_PREDICATE_NORMAL
);
1573 emit_gs_control_data_bits(vertex_count
);
1574 abld
.emit(BRW_OPCODE_ENDIF
);
1576 /* Reset control_data_bits to 0 so we can start accumulating a new
1579 * Note: in the case where vertex_count == 0, this neutralizes the
1580 * effect of any call to EndPrimitive() that the shader may have
1581 * made before outputting its first vertex.
1583 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1584 inst
->force_writemask_all
= true;
1585 abld
.emit(BRW_OPCODE_ENDIF
);
1588 emit_urb_writes(vertex_count
);
1590 /* In stream mode we have to set control data bits for all vertices
1591 * unless we have disabled control data bits completely (which we do
1592 * do for GL_POINTS outputs that don't use streams).
1594 if (gs_compile
->control_data_header_size_bits
> 0 &&
1595 gs_prog_data
->control_data_format
==
1596 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1597 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1602 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1603 const nir_src
&vertex_src
,
1604 const fs_reg
&indirect_offset
,
1605 unsigned imm_offset
,
1606 unsigned num_components
)
1608 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1610 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1611 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1612 * gl_PointSize is available as a GS input, however, so it must be that.
1614 const bool is_point_size
=
1615 indirect_offset
.file
== BAD_FILE
&& imm_offset
== 0;
1617 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1618 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1620 if (indirect_offset
.file
== BAD_FILE
&& vertex_const
!= NULL
&&
1621 4 * imm_offset
< push_reg_count
) {
1622 imm_offset
= 4 * imm_offset
+ vertex_const
->u
[0] * push_reg_count
;
1623 /* This input was pushed into registers. */
1624 if (is_point_size
) {
1625 /* gl_PointSize comes in .w */
1626 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1628 for (unsigned i
= 0; i
< num_components
; i
++) {
1629 bld
.MOV(offset(dst
, bld
, i
),
1630 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1634 /* Resort to the pull model. Ensure the VUE handles are provided. */
1635 gs_prog_data
->base
.include_vue_handles
= true;
1637 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1641 /* The vertex index is constant; just select the proper URB handle. */
1643 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1644 BRW_REGISTER_TYPE_UD
);
1646 /* The vertex index is non-constant. We need to use indirect
1647 * addressing to fetch the proper URB handle.
1649 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1650 * indicating that channel <n> should read the handle from
1651 * DWord <n>. We convert that to bytes by multiplying by 4.
1653 * Next, we convert the vertex index to bytes by multiplying
1654 * by 32 (shifting by 5), and add the two together. This is
1655 * the final indirect byte offset.
1657 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1658 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1659 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1660 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1661 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1663 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1664 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1665 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1666 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1667 /* Convert vertex_index to bytes (multiply by 32) */
1668 bld
.SHL(vertex_offset_bytes
,
1669 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1671 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1673 /* Use first_icp_handle as the base offset. There is one register
1674 * of URB handles per vertex, so inform the register allocator that
1675 * we might read up to nir->info.gs.vertices_in registers.
1677 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1678 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1679 fs_reg(icp_offset_bytes
),
1680 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1684 if (indirect_offset
.file
== BAD_FILE
) {
1685 /* Constant indexing - use global offset. */
1686 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1687 inst
->offset
= imm_offset
;
1688 inst
->base_mrf
= -1;
1690 inst
->regs_written
= num_components
;
1692 /* Indirect indexing - use per-slot offsets as well. */
1693 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
1694 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1695 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1697 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1698 inst
->offset
= imm_offset
;
1699 inst
->base_mrf
= -1;
1701 inst
->regs_written
= num_components
;
1704 if (is_point_size
) {
1705 /* Read the whole VUE header (because of alignment) and read .w. */
1706 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1708 inst
->regs_written
= 4;
1709 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1715 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1716 nir_intrinsic_instr
*instr
)
1718 assert(stage
== MESA_SHADER_VERTEX
);
1721 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1722 dest
= get_nir_dest(instr
->dest
);
1724 switch (instr
->intrinsic
) {
1725 case nir_intrinsic_load_vertex_id
:
1726 unreachable("should be lowered by lower_vertex_id()");
1728 case nir_intrinsic_load_vertex_id_zero_base
:
1729 case nir_intrinsic_load_base_vertex
:
1730 case nir_intrinsic_load_instance_id
: {
1731 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1732 fs_reg val
= nir_system_values
[sv
];
1733 assert(val
.file
!= BAD_FILE
);
1734 dest
.type
= val
.type
;
1740 nir_emit_intrinsic(bld
, instr
);
1746 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1747 nir_intrinsic_instr
*instr
)
1749 assert(stage
== MESA_SHADER_GEOMETRY
);
1750 fs_reg indirect_offset
;
1753 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1754 dest
= get_nir_dest(instr
->dest
);
1756 switch (instr
->intrinsic
) {
1757 case nir_intrinsic_load_primitive_id
:
1758 assert(stage
== MESA_SHADER_GEOMETRY
);
1759 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1760 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1761 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1764 case nir_intrinsic_load_input_indirect
:
1765 case nir_intrinsic_load_input
:
1766 unreachable("load_input intrinsics are invalid for the GS stage");
1768 case nir_intrinsic_load_per_vertex_input_indirect
:
1769 indirect_offset
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_D
);
1771 case nir_intrinsic_load_per_vertex_input
:
1772 emit_gs_input_load(dest
, instr
->src
[0],
1773 indirect_offset
, instr
->const_index
[0],
1774 instr
->num_components
);
1777 case nir_intrinsic_emit_vertex_with_counter
:
1778 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1781 case nir_intrinsic_end_primitive_with_counter
:
1782 emit_gs_end_primitive(instr
->src
[0]);
1785 case nir_intrinsic_set_vertex_count
:
1786 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1789 case nir_intrinsic_load_invocation_id
: {
1790 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1791 assert(val
.file
!= BAD_FILE
);
1792 dest
.type
= val
.type
;
1798 nir_emit_intrinsic(bld
, instr
);
1804 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1805 nir_intrinsic_instr
*instr
)
1807 assert(stage
== MESA_SHADER_FRAGMENT
);
1808 struct brw_wm_prog_data
*wm_prog_data
=
1809 (struct brw_wm_prog_data
*) prog_data
;
1812 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1813 dest
= get_nir_dest(instr
->dest
);
1815 switch (instr
->intrinsic
) {
1816 case nir_intrinsic_load_front_face
:
1817 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1818 *emit_frontfacing_interpolation());
1821 case nir_intrinsic_load_sample_pos
: {
1822 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1823 assert(sample_pos
.file
!= BAD_FILE
);
1824 dest
.type
= sample_pos
.type
;
1825 bld
.MOV(dest
, sample_pos
);
1826 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1830 case nir_intrinsic_load_helper_invocation
:
1831 case nir_intrinsic_load_sample_mask_in
:
1832 case nir_intrinsic_load_sample_id
: {
1833 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1834 fs_reg val
= nir_system_values
[sv
];
1835 assert(val
.file
!= BAD_FILE
);
1836 dest
.type
= val
.type
;
1841 case nir_intrinsic_discard
:
1842 case nir_intrinsic_discard_if
: {
1843 /* We track our discarded pixels in f0.1. By predicating on it, we can
1844 * update just the flag bits that aren't yet discarded. If there's no
1845 * condition, we emit a CMP of g0 != g0, so all currently executing
1846 * channels will get turned off.
1849 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1850 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1851 brw_imm_d(0), BRW_CONDITIONAL_Z
);
1853 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1854 BRW_REGISTER_TYPE_UW
));
1855 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1857 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1858 cmp
->flag_subreg
= 1;
1860 if (devinfo
->gen
>= 6) {
1861 emit_discard_jump();
1866 case nir_intrinsic_interp_var_at_centroid
:
1867 case nir_intrinsic_interp_var_at_sample
:
1868 case nir_intrinsic_interp_var_at_offset
: {
1869 /* Handle ARB_gpu_shader5 interpolation intrinsics
1871 * It's worth a quick word of explanation as to why we handle the full
1872 * variable-based interpolation intrinsic rather than a lowered version
1873 * with like we do for other inputs. We have to do that because the way
1874 * we set up inputs doesn't allow us to use the already setup inputs for
1875 * interpolation. At the beginning of the shader, we go through all of
1876 * the input variables and do the initial interpolation and put it in
1877 * the nir_inputs array based on its location as determined in
1878 * nir_lower_io. If the input isn't used, dead code cleans up and
1879 * everything works fine. However, when we get to the ARB_gpu_shader5
1880 * interpolation intrinsics, we need to reinterpolate the input
1881 * differently. If we used an intrinsic that just had an index it would
1882 * only give us the offset into the nir_inputs array. However, this is
1883 * useless because that value is post-interpolation and we need
1884 * pre-interpolation. In order to get the actual location of the bits
1885 * we get from the vertex fetching hardware, we need the variable.
1887 wm_prog_data
->pulls_bary
= true;
1889 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1890 const glsl_interp_qualifier interpolation
=
1891 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1893 switch (instr
->intrinsic
) {
1894 case nir_intrinsic_interp_var_at_centroid
:
1895 emit_pixel_interpolater_send(bld
,
1896 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1903 case nir_intrinsic_interp_var_at_sample
: {
1904 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1907 unsigned msg_data
= const_sample
->i
[0] << 4;
1909 emit_pixel_interpolater_send(bld
,
1910 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1913 brw_imm_ud(msg_data
),
1916 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1917 BRW_REGISTER_TYPE_UD
);
1919 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1920 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1921 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1922 bld
.exec_all().group(1, 0)
1923 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1924 emit_pixel_interpolater_send(bld
,
1925 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1931 /* Make a loop that sends a message to the pixel interpolater
1932 * for the sample number in each live channel. If there are
1933 * multiple channels with the same sample number then these
1934 * will be handled simultaneously with a single interation of
1937 bld
.emit(BRW_OPCODE_DO
);
1939 /* Get the next live sample number into sample_id_reg */
1940 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1942 /* Set the flag register so that we can perform the send
1943 * message on all channels that have the same sample number
1945 bld
.CMP(bld
.null_reg_ud(),
1946 sample_src
, sample_id
,
1947 BRW_CONDITIONAL_EQ
);
1948 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1949 bld
.exec_all().group(1, 0)
1950 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1952 emit_pixel_interpolater_send(bld
,
1953 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1958 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1960 /* Continue the loop if there are any live channels left */
1961 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1963 bld
.emit(BRW_OPCODE_WHILE
));
1970 case nir_intrinsic_interp_var_at_offset
: {
1971 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1974 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1975 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1977 emit_pixel_interpolater_send(bld
,
1978 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1981 brw_imm_ud(off_x
| (off_y
<< 4)),
1984 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1985 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1986 BRW_REGISTER_TYPE_F
);
1987 for (int i
= 0; i
< 2; i
++) {
1988 fs_reg temp
= vgrf(glsl_type::float_type
);
1989 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
1990 fs_reg itemp
= vgrf(glsl_type::int_type
);
1991 bld
.MOV(itemp
, temp
); /* float to int */
1993 /* Clamp the upper end of the range to +7/16.
1994 * ARB_gpu_shader5 requires that we support a maximum offset
1995 * of +0.5, which isn't representable in a S0.4 value -- if
1996 * we didn't clamp it, we'd end up with -8/16, which is the
1997 * opposite of what the shader author wanted.
1999 * This is legal due to ARB_gpu_shader5's quantization
2002 * "Not all values of <offset> may be supported; x and y
2003 * offsets may be rounded to fixed-point values with the
2004 * number of fraction bits given by the
2005 * implementation-dependent constant
2006 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2008 set_condmod(BRW_CONDITIONAL_L
,
2009 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2012 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2013 emit_pixel_interpolater_send(bld
,
2024 unreachable("Invalid intrinsic");
2027 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2028 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2029 src
.type
= dest
.type
;
2031 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2032 dest
= offset(dest
, bld
, 1);
2037 nir_emit_intrinsic(bld
, instr
);
2043 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2044 nir_intrinsic_instr
*instr
)
2046 assert(stage
== MESA_SHADER_COMPUTE
);
2047 struct brw_cs_prog_data
*cs_prog_data
=
2048 (struct brw_cs_prog_data
*) prog_data
;
2051 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2052 dest
= get_nir_dest(instr
->dest
);
2054 switch (instr
->intrinsic
) {
2055 case nir_intrinsic_barrier
:
2057 cs_prog_data
->uses_barrier
= true;
2060 case nir_intrinsic_load_local_invocation_id
:
2061 case nir_intrinsic_load_work_group_id
: {
2062 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2063 fs_reg val
= nir_system_values
[sv
];
2064 assert(val
.file
!= BAD_FILE
);
2065 dest
.type
= val
.type
;
2066 for (unsigned i
= 0; i
< 3; i
++)
2067 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2071 case nir_intrinsic_load_num_work_groups
: {
2072 const unsigned surface
=
2073 cs_prog_data
->binding_table
.work_groups_start
;
2075 cs_prog_data
->uses_num_work_groups
= true;
2077 fs_reg surf_index
= brw_imm_ud(surface
);
2078 brw_mark_surface_used(prog_data
, surface
);
2080 /* Read the 3 GLuint components of gl_NumWorkGroups */
2081 for (unsigned i
= 0; i
< 3; i
++) {
2082 fs_reg read_result
=
2083 emit_untyped_read(bld
, surf_index
,
2085 1 /* dims */, 1 /* size */,
2086 BRW_PREDICATE_NONE
);
2087 read_result
.type
= dest
.type
;
2088 bld
.MOV(dest
, read_result
);
2089 dest
= offset(dest
, bld
, 1);
2095 nir_emit_intrinsic(bld
, instr
);
2101 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2104 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2105 dest
= get_nir_dest(instr
->dest
);
2107 bool has_indirect
= false;
2109 switch (instr
->intrinsic
) {
2110 case nir_intrinsic_atomic_counter_inc
:
2111 case nir_intrinsic_atomic_counter_dec
:
2112 case nir_intrinsic_atomic_counter_read
: {
2113 using namespace surface_access
;
2115 /* Get the arguments of the atomic intrinsic. */
2116 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2117 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2118 instr
->const_index
[0]);
2121 /* Emit a surface read or atomic op. */
2122 switch (instr
->intrinsic
) {
2123 case nir_intrinsic_atomic_counter_read
:
2124 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2127 case nir_intrinsic_atomic_counter_inc
:
2128 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2129 fs_reg(), 1, 1, BRW_AOP_INC
);
2132 case nir_intrinsic_atomic_counter_dec
:
2133 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2134 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2138 unreachable("Unreachable");
2141 /* Assign the result. */
2142 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2144 /* Mark the surface as used. */
2145 brw_mark_surface_used(stage_prog_data
, surface
);
2149 case nir_intrinsic_image_load
:
2150 case nir_intrinsic_image_store
:
2151 case nir_intrinsic_image_atomic_add
:
2152 case nir_intrinsic_image_atomic_min
:
2153 case nir_intrinsic_image_atomic_max
:
2154 case nir_intrinsic_image_atomic_and
:
2155 case nir_intrinsic_image_atomic_or
:
2156 case nir_intrinsic_image_atomic_xor
:
2157 case nir_intrinsic_image_atomic_exchange
:
2158 case nir_intrinsic_image_atomic_comp_swap
: {
2159 using namespace image_access
;
2161 /* Get the referenced image variable and type. */
2162 const nir_variable
*var
= instr
->variables
[0]->var
;
2163 const glsl_type
*type
= var
->type
->without_array();
2164 const brw_reg_type base_type
= get_image_base_type(type
);
2166 /* Get some metadata from the image intrinsic. */
2167 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2168 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2169 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2170 const mesa_format format
=
2171 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2172 _mesa_get_shader_image_format(var
->data
.image
.format
));
2174 /* Get the arguments of the image intrinsic. */
2175 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2176 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2177 BRW_REGISTER_TYPE_UD
);
2178 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2179 retype(get_nir_src(instr
->src
[2]), base_type
) :
2181 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2182 retype(get_nir_src(instr
->src
[3]), base_type
) :
2186 /* Emit an image load, store or atomic op. */
2187 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2188 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2190 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2191 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2194 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2195 surf_dims
, arr_dims
, info
->dest_components
,
2196 get_image_atomic_op(instr
->intrinsic
, type
));
2198 /* Assign the result. */
2199 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2200 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2201 offset(tmp
, bld
, c
));
2205 case nir_intrinsic_memory_barrier_atomic_counter
:
2206 case nir_intrinsic_memory_barrier_buffer
:
2207 case nir_intrinsic_memory_barrier_image
:
2208 case nir_intrinsic_memory_barrier
: {
2209 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2210 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2215 case nir_intrinsic_group_memory_barrier
:
2216 case nir_intrinsic_memory_barrier_shared
:
2217 /* We treat these workgroup-level barriers as no-ops. This should be
2218 * safe at present and as long as:
2220 * - Memory access instructions are not subsequently reordered by the
2221 * compiler back-end.
2223 * - All threads from a given compute shader workgroup fit within a
2224 * single subslice and therefore talk to the same HDC shared unit
2225 * what supposedly guarantees ordering and coherency between threads
2226 * from the same workgroup. This may change in the future when we
2227 * start splitting workgroups across multiple subslices.
2229 * - The context is not in fault-and-stream mode, which could cause
2230 * memory transactions (including to SLM) prior to the barrier to be
2231 * replayed after the barrier if a pagefault occurs. This shouldn't
2232 * be a problem up to and including SKL because fault-and-stream is
2233 * not usable due to hardware issues, but that's likely to change in
2238 case nir_intrinsic_shader_clock
: {
2239 /* We cannot do anything if there is an event, so ignore it for now */
2240 fs_reg shader_clock
= get_timestamp(bld
);
2241 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2243 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2247 case nir_intrinsic_image_size
: {
2248 /* Get the referenced image variable and type. */
2249 const nir_variable
*var
= instr
->variables
[0]->var
;
2250 const glsl_type
*type
= var
->type
->without_array();
2252 /* Get the size of the image. */
2253 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2254 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2256 /* For 1DArray image types, the array index is stored in the Z component.
2257 * Fix this by swizzling the Z component to the Y component.
2259 const bool is_1d_array_image
=
2260 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2261 type
->sampler_array
;
2263 /* For CubeArray images, we should count the number of cubes instead
2264 * of the number of faces. Fix it by dividing the (Z component) by 6.
2266 const bool is_cube_array_image
=
2267 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2268 type
->sampler_array
;
2270 /* Copy all the components. */
2271 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2272 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2273 if ((int)c
>= type
->coordinate_components()) {
2274 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2276 } else if (c
== 1 && is_1d_array_image
) {
2277 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2278 offset(size
, bld
, 2));
2279 } else if (c
== 2 && is_cube_array_image
) {
2280 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2281 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2282 offset(size
, bld
, c
), brw_imm_d(6));
2284 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2285 offset(size
, bld
, c
));
2292 case nir_intrinsic_image_samples
:
2293 /* The driver does not support multi-sampled images. */
2294 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2297 case nir_intrinsic_load_uniform_indirect
:
2298 has_indirect
= true;
2300 case nir_intrinsic_load_uniform
: {
2301 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
2302 uniform_reg
.reg_offset
= instr
->const_index
[1];
2304 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2305 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
2307 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2310 dest
= offset(dest
, bld
, 1);
2315 case nir_intrinsic_load_ubo_indirect
:
2316 has_indirect
= true;
2318 case nir_intrinsic_load_ubo
: {
2319 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2323 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2325 surf_index
= brw_imm_ud(index
);
2326 brw_mark_surface_used(prog_data
, index
);
2328 /* The block index is not a constant. Evaluate the index expression
2329 * per-channel and add the base UBO index; we have to select a value
2330 * from any live channel.
2332 surf_index
= vgrf(glsl_type::uint_type
);
2333 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2334 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2335 surf_index
= bld
.emit_uniformize(surf_index
);
2337 /* Assume this may touch any UBO. It would be nice to provide
2338 * a tighter bound, but the array information is already lowered away.
2340 brw_mark_surface_used(prog_data
,
2341 stage_prog_data
->binding_table
.ubo_start
+
2342 nir
->info
.num_ubos
- 1);
2346 /* Turn the byte offset into a dword offset. */
2347 fs_reg base_offset
= vgrf(glsl_type::int_type
);
2348 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
2349 BRW_REGISTER_TYPE_D
),
2352 unsigned vec4_offset
= instr
->const_index
[0] / 4;
2353 for (int i
= 0; i
< instr
->num_components
; i
++)
2354 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2355 base_offset
, vec4_offset
+ i
);
2357 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2358 packed_consts
.type
= dest
.type
;
2360 struct brw_reg const_offset_reg
= brw_imm_ud(instr
->const_index
[0] & ~15);
2361 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2362 surf_index
, const_offset_reg
);
2364 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2365 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
2367 /* The std140 packing rules don't allow vectors to cross 16-byte
2368 * boundaries, and a reg is 32 bytes.
2370 assert(packed_consts
.subreg_offset
< 32);
2372 bld
.MOV(dest
, packed_consts
);
2373 dest
= offset(dest
, bld
, 1);
2379 case nir_intrinsic_load_ssbo_indirect
:
2380 has_indirect
= true;
2382 case nir_intrinsic_load_ssbo
: {
2383 assert(devinfo
->gen
>= 7);
2385 nir_const_value
*const_uniform_block
=
2386 nir_src_as_const_value(instr
->src
[0]);
2389 if (const_uniform_block
) {
2390 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2391 const_uniform_block
->u
[0];
2392 surf_index
= brw_imm_ud(index
);
2393 brw_mark_surface_used(prog_data
, index
);
2395 surf_index
= vgrf(glsl_type::uint_type
);
2396 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2397 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2399 /* Assume this may touch any UBO. It would be nice to provide
2400 * a tighter bound, but the array information is already lowered away.
2402 brw_mark_surface_used(prog_data
,
2403 stage_prog_data
->binding_table
.ssbo_start
+
2404 nir
->info
.num_ssbos
- 1);
2407 /* Get the offset to read from */
2410 offset_reg
= get_nir_src(instr
->src
[1]);
2412 offset_reg
= brw_imm_ud(instr
->const_index
[0]);
2415 /* Read the vector */
2416 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2418 instr
->num_components
,
2419 BRW_PREDICATE_NONE
);
2420 read_result
.type
= dest
.type
;
2421 for (int i
= 0; i
< instr
->num_components
; i
++)
2422 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2427 case nir_intrinsic_load_input_indirect
:
2428 has_indirect
= true;
2430 case nir_intrinsic_load_input
: {
2432 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2434 if (stage
== MESA_SHADER_VERTEX
) {
2435 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
2437 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2438 instr
->const_index
[0] + index
);
2441 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2445 dest
= offset(dest
, bld
, 1);
2450 case nir_intrinsic_store_ssbo_indirect
:
2451 has_indirect
= true;
2453 case nir_intrinsic_store_ssbo
: {
2454 assert(devinfo
->gen
>= 7);
2458 nir_const_value
*const_uniform_block
=
2459 nir_src_as_const_value(instr
->src
[1]);
2460 if (const_uniform_block
) {
2461 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2462 const_uniform_block
->u
[0];
2463 surf_index
= brw_imm_ud(index
);
2464 brw_mark_surface_used(prog_data
, index
);
2466 surf_index
= vgrf(glsl_type::uint_type
);
2467 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2468 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2470 brw_mark_surface_used(prog_data
,
2471 stage_prog_data
->binding_table
.ssbo_start
+
2472 nir
->info
.num_ssbos
- 1);
2476 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2479 unsigned writemask
= instr
->const_index
[1];
2481 /* Combine groups of consecutive enabled channels in one write
2482 * message. We use ffs to find the first enabled channel and then ffs on
2483 * the bit-inverse, down-shifted writemask to determine the length of
2484 * the block of enabled bits.
2487 unsigned first_component
= ffs(writemask
) - 1;
2488 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2491 if (!has_indirect
) {
2492 offset_reg
= brw_imm_ud(instr
->const_index
[0] + 4 * first_component
);
2494 offset_reg
= vgrf(glsl_type::uint_type
);
2496 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2497 brw_imm_ud(4 * first_component
));
2500 emit_untyped_write(bld
, surf_index
, offset_reg
,
2501 offset(val_reg
, bld
, first_component
),
2502 1 /* dims */, length
,
2503 BRW_PREDICATE_NONE
);
2505 /* Clear the bits in the writemask that we just wrote, then try
2506 * again to see if more channels are left.
2508 writemask
&= (15 << (first_component
+ length
));
2513 case nir_intrinsic_store_output_indirect
:
2514 has_indirect
= true;
2516 case nir_intrinsic_store_output
: {
2517 fs_reg src
= get_nir_src(instr
->src
[0]);
2519 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2520 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2521 instr
->const_index
[0] + index
);
2523 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
2525 bld
.MOV(new_dest
, src
);
2526 src
= offset(src
, bld
, 1);
2531 case nir_intrinsic_ssbo_atomic_add
:
2532 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2534 case nir_intrinsic_ssbo_atomic_imin
:
2535 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2537 case nir_intrinsic_ssbo_atomic_umin
:
2538 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2540 case nir_intrinsic_ssbo_atomic_imax
:
2541 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2543 case nir_intrinsic_ssbo_atomic_umax
:
2544 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2546 case nir_intrinsic_ssbo_atomic_and
:
2547 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2549 case nir_intrinsic_ssbo_atomic_or
:
2550 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2552 case nir_intrinsic_ssbo_atomic_xor
:
2553 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2555 case nir_intrinsic_ssbo_atomic_exchange
:
2556 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2558 case nir_intrinsic_ssbo_atomic_comp_swap
:
2559 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2562 case nir_intrinsic_get_buffer_size
: {
2563 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2564 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2565 int reg_width
= dispatch_width
/ 8;
2568 fs_reg source
= brw_imm_d(0);
2570 int mlen
= 1 * reg_width
;
2572 /* A resinfo's sampler message is used to get the buffer size.
2573 * The SIMD8's writeback message consists of four registers and
2574 * SIMD16's writeback message consists of 8 destination registers
2575 * (two per each component), although we are only interested on the
2576 * first component, where resinfo returns the buffer size for
2579 int regs_written
= 4 * mlen
;
2580 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2581 BRW_REGISTER_TYPE_UD
);
2582 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2583 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2584 BRW_REGISTER_TYPE_UD
);
2585 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2586 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2587 src_payload
, brw_imm_ud(index
));
2588 inst
->header_size
= 0;
2590 inst
->regs_written
= regs_written
;
2592 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2594 brw_mark_surface_used(prog_data
, index
);
2599 unreachable("unknown intrinsic");
2604 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2605 int op
, nir_intrinsic_instr
*instr
)
2608 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2609 dest
= get_nir_dest(instr
->dest
);
2612 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2613 if (const_surface
) {
2614 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2615 const_surface
->u
[0];
2616 surface
= brw_imm_ud(surf_index
);
2617 brw_mark_surface_used(prog_data
, surf_index
);
2619 surface
= vgrf(glsl_type::uint_type
);
2620 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2621 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2623 /* Assume this may touch any SSBO. This is the same we do for other
2624 * UBO/SSBO accesses with non-constant surface.
2626 brw_mark_surface_used(prog_data
,
2627 stage_prog_data
->binding_table
.ssbo_start
+
2628 nir
->info
.num_ssbos
- 1);
2631 fs_reg offset
= get_nir_src(instr
->src
[1]);
2632 fs_reg data1
= get_nir_src(instr
->src
[2]);
2634 if (op
== BRW_AOP_CMPWR
)
2635 data2
= get_nir_src(instr
->src
[3]);
2637 /* Emit the actual atomic operation operation */
2639 fs_reg atomic_result
=
2640 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2642 1 /* dims */, 1 /* rsize */,
2644 BRW_PREDICATE_NONE
);
2645 dest
.type
= atomic_result
.type
;
2646 bld
.MOV(dest
, atomic_result
);
2650 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2652 unsigned sampler
= instr
->sampler_index
;
2653 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2655 int gather_component
= instr
->component
;
2657 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2660 int lod_components
= 0;
2661 int UNUSED offset_components
= 0;
2663 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2665 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2666 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2667 switch (instr
->src
[i
].src_type
) {
2668 case nir_tex_src_bias
:
2669 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2671 case nir_tex_src_comparitor
:
2672 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2674 case nir_tex_src_coord
:
2675 switch (instr
->op
) {
2677 case nir_texop_txf_ms
:
2678 case nir_texop_samples_identical
:
2679 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2682 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2686 case nir_tex_src_ddx
:
2687 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2688 lod_components
= nir_tex_instr_src_size(instr
, i
);
2690 case nir_tex_src_ddy
:
2691 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2693 case nir_tex_src_lod
:
2694 switch (instr
->op
) {
2696 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2699 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2702 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2706 case nir_tex_src_ms_index
:
2707 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2709 case nir_tex_src_offset
:
2710 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2711 if (instr
->is_array
)
2712 offset_components
= instr
->coord_components
- 1;
2714 offset_components
= instr
->coord_components
;
2716 case nir_tex_src_projector
:
2717 unreachable("should be lowered");
2719 case nir_tex_src_sampler_offset
: {
2720 /* Figure out the highest possible sampler index and mark it as used */
2721 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2722 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2723 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2725 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2727 brw_mark_surface_used(prog_data
, max_used
);
2729 /* Emit code to evaluate the actual indexing expression */
2730 sampler_reg
= vgrf(glsl_type::uint_type
);
2731 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
2732 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2737 unreachable("unknown texture source");
2741 if (instr
->op
== nir_texop_txf_ms
||
2742 instr
->op
== nir_texop_samples_identical
) {
2743 if (devinfo
->gen
>= 7 &&
2744 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2745 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2747 mcs
= brw_imm_ud(0u);
2751 for (unsigned i
= 0; i
< 3; i
++) {
2752 if (instr
->const_offset
[i
] != 0) {
2753 assert(offset_components
== 0);
2754 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
2759 enum glsl_base_type dest_base_type
=
2760 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2762 const glsl_type
*dest_type
=
2763 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2766 ir_texture_opcode op
;
2767 switch (instr
->op
) {
2768 case nir_texop_lod
: op
= ir_lod
; break;
2769 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2770 case nir_texop_tex
: op
= ir_tex
; break;
2771 case nir_texop_tg4
: op
= ir_tg4
; break;
2772 case nir_texop_txb
: op
= ir_txb
; break;
2773 case nir_texop_txd
: op
= ir_txd
; break;
2774 case nir_texop_txf
: op
= ir_txf
; break;
2775 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2776 case nir_texop_txl
: op
= ir_txl
; break;
2777 case nir_texop_txs
: op
= ir_txs
; break;
2778 case nir_texop_texture_samples
: {
2779 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2780 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2781 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2784 inst
->header_size
= 1;
2785 inst
->base_mrf
= -1;
2788 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2790 unreachable("unknown texture opcode");
2793 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2794 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2795 tex_offset
, mcs
, gather_component
,
2796 is_cube_array
, sampler
, sampler_reg
);
2798 fs_reg dest
= get_nir_dest(instr
->dest
);
2799 dest
.type
= this->result
.type
;
2800 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2801 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2802 dest
, this->result
),
2803 (1 << num_components
) - 1);
2807 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2809 switch (instr
->type
) {
2810 case nir_jump_break
:
2811 bld
.emit(BRW_OPCODE_BREAK
);
2813 case nir_jump_continue
:
2814 bld
.emit(BRW_OPCODE_CONTINUE
);
2816 case nir_jump_return
:
2818 unreachable("unknown jump");