2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
34 fs_visitor::emit_nir_code()
36 nir_shader
*nir
= prog
->nir
;
38 /* emit the arrays used for inputs and outputs - load/store intrinsics will
39 * be converted to reads/writes of these arrays
42 if (nir
->num_inputs
> 0) {
43 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
44 nir_setup_inputs(nir
);
47 if (nir
->num_outputs
> 0) {
48 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
49 nir_setup_outputs(nir
);
52 if (nir
->num_uniforms
> 0) {
53 nir_setup_uniforms(nir
);
56 nir_emit_system_values(nir
);
58 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
59 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
60 unsigned array_elems
=
61 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
62 unsigned size
= array_elems
* reg
->num_components
;
63 nir_globals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
66 /* get the main function and emit it */
67 nir_foreach_overload(nir
, overload
) {
68 assert(strcmp(overload
->function
->name
, "main") == 0);
69 assert(overload
->impl
);
70 nir_emit_impl(overload
->impl
);
75 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
77 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
78 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
79 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
83 case MESA_SHADER_VERTEX
: {
84 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
85 * stored in nir_variable::location.
87 * However, NIR's load_input intrinsics use a different index - an
88 * offset into a single contiguous array containing all inputs.
89 * This index corresponds to the nir_variable::driver_location field.
91 * So, we need to copy from fs_reg(ATTR, var->location) to
92 * offset(nir_inputs, var->data.driver_location).
94 const glsl_type
*const t
= var
->type
->without_array();
95 const unsigned components
= t
->components();
96 const unsigned cols
= t
->matrix_columns
;
97 const unsigned elts
= t
->vector_elements
;
98 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
99 for (unsigned i
= 0; i
< array_length
; i
++) {
100 for (unsigned j
= 0; j
< cols
; j
++) {
101 for (unsigned k
= 0; k
< elts
; k
++) {
102 bld
.MOV(offset(retype(input
, type
), bld
,
103 components
* i
+ elts
* j
+ k
),
104 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
111 case MESA_SHADER_GEOMETRY
:
112 case MESA_SHADER_COMPUTE
:
113 unreachable("fs_visitor not used for these stages yet.");
115 case MESA_SHADER_FRAGMENT
:
116 if (var
->data
.location
== VARYING_SLOT_POS
) {
117 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
118 var
->data
.origin_upper_left
);
119 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
122 emit_general_interpolation(input
, var
->name
, var
->type
,
123 (glsl_interp_qualifier
) var
->data
.interpolation
,
124 var
->data
.location
, var
->data
.centroid
,
133 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
135 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
137 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
138 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
140 int vector_elements
=
141 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
142 : var
->type
->vector_elements
;
144 if (stage
== MESA_SHADER_VERTEX
) {
145 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
146 int output
= var
->data
.location
+ i
;
147 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
148 this->output_components
[output
] = vector_elements
;
150 } else if (var
->data
.index
> 0) {
151 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
152 assert(var
->data
.index
== 1);
153 this->dual_src_output
= reg
;
154 this->do_dual_src
= true;
155 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
156 /* Writing gl_FragColor outputs to all color regions. */
157 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
158 this->outputs
[i
] = reg
;
159 this->output_components
[i
] = 4;
161 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
162 this->frag_depth
= reg
;
163 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
164 this->sample_mask
= reg
;
166 /* gl_FragData or a user-defined FS output */
167 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
168 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
170 /* General color output. */
171 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
172 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
173 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
174 this->output_components
[output
] = vector_elements
;
181 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
183 uniforms
= shader
->num_uniforms
;
184 num_direct_uniforms
= shader
->num_direct_uniforms
;
186 /* We split the uniform register file in half. The first half is
187 * entirely direct uniforms. The second half is indirect.
189 param_size
[0] = num_direct_uniforms
;
190 if (shader
->num_uniforms
> num_direct_uniforms
)
191 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
193 if (dispatch_width
!= 8)
197 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
198 /* UBO's and atomics don't take up space in the uniform file */
199 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
202 if (strncmp(var
->name
, "gl_", 3) == 0)
203 nir_setup_builtin_uniform(var
);
205 nir_setup_uniform(var
);
208 /* prog_to_nir doesn't create uniform variables; set param up directly. */
209 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
210 for (unsigned int i
= 0; i
< 4; i
++) {
211 stage_prog_data
->param
[4 * p
+ i
] =
212 &prog
->Parameters
->ParameterValues
[p
][i
];
219 fs_visitor::nir_setup_uniform(nir_variable
*var
)
221 int namelen
= strlen(var
->name
);
223 /* The data for our (non-builtin) uniforms is stored in a series of
224 * gl_uniform_driver_storage structs for each subcomponent that
225 * glGetUniformLocation() could name. We know it's been set up in the
226 * same order we'd walk the type, so walk the list of storage and find
227 * anything with our name, or the prefix of a component that starts with
230 unsigned index
= var
->data
.driver_location
;
231 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
232 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
234 if (storage
->builtin
)
237 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
238 (storage
->name
[namelen
] != 0 &&
239 storage
->name
[namelen
] != '.' &&
240 storage
->name
[namelen
] != '[')) {
244 unsigned slots
= storage
->type
->component_slots();
245 if (storage
->array_elements
)
246 slots
*= storage
->array_elements
;
248 for (unsigned i
= 0; i
< slots
; i
++) {
249 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
253 /* Make sure we actually initialized the right amount of stuff here. */
254 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
258 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
260 const nir_state_slot
*const slots
= var
->state_slots
;
261 assert(var
->state_slots
!= NULL
);
263 unsigned uniform_index
= var
->data
.driver_location
;
264 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
265 /* This state reference has already been setup by ir_to_mesa, but we'll
266 * get the same index back here.
268 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
269 (gl_state_index
*)slots
[i
].tokens
);
271 /* Add each of the unique swizzles of the element as a parameter.
272 * This'll end up matching the expected layout of the
273 * array/matrix/structure we're trying to fill in.
276 for (unsigned int j
= 0; j
< 4; j
++) {
277 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
278 if (swiz
== last_swiz
)
282 stage_prog_data
->param
[uniform_index
++] =
283 &prog
->Parameters
->ParameterValues
[index
][swiz
];
289 emit_system_values_block(nir_block
*block
, void *void_visitor
)
291 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
294 nir_foreach_instr(block
, instr
) {
295 if (instr
->type
!= nir_instr_type_intrinsic
)
298 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
299 switch (intrin
->intrinsic
) {
300 case nir_intrinsic_load_vertex_id
:
301 unreachable("should be lowered by lower_vertex_id().");
303 case nir_intrinsic_load_vertex_id_zero_base
:
304 assert(v
->stage
== MESA_SHADER_VERTEX
);
305 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
306 if (reg
->file
== BAD_FILE
)
307 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
310 case nir_intrinsic_load_base_vertex
:
311 assert(v
->stage
== MESA_SHADER_VERTEX
);
312 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
313 if (reg
->file
== BAD_FILE
)
314 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
317 case nir_intrinsic_load_instance_id
:
318 assert(v
->stage
== MESA_SHADER_VERTEX
);
319 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
320 if (reg
->file
== BAD_FILE
)
321 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
324 case nir_intrinsic_load_sample_pos
:
325 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
326 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
327 if (reg
->file
== BAD_FILE
)
328 *reg
= *v
->emit_samplepos_setup();
331 case nir_intrinsic_load_sample_id
:
332 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
333 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
334 if (reg
->file
== BAD_FILE
)
335 *reg
= *v
->emit_sampleid_setup();
338 case nir_intrinsic_load_sample_mask_in
:
339 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
340 assert(v
->devinfo
->gen
>= 7);
341 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
342 if (reg
->file
== BAD_FILE
)
343 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
344 BRW_REGISTER_TYPE_D
));
356 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
358 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
359 nir_foreach_overload(shader
, overload
) {
360 assert(strcmp(overload
->function
->name
, "main") == 0);
361 assert(overload
->impl
);
362 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
367 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
369 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
370 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
371 unsigned array_elems
=
372 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
373 unsigned size
= array_elems
* reg
->num_components
;
374 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
377 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
380 nir_emit_cf_list(&impl
->body
);
384 fs_visitor::nir_emit_cf_list(exec_list
*list
)
386 exec_list_validate(list
);
387 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
388 switch (node
->type
) {
390 nir_emit_if(nir_cf_node_as_if(node
));
393 case nir_cf_node_loop
:
394 nir_emit_loop(nir_cf_node_as_loop(node
));
397 case nir_cf_node_block
:
398 nir_emit_block(nir_cf_node_as_block(node
));
402 unreachable("Invalid CFG node block");
408 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
410 /* first, put the condition into f0 */
411 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
412 retype(get_nir_src(if_stmt
->condition
),
413 BRW_REGISTER_TYPE_D
));
414 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
416 bld
.IF(BRW_PREDICATE_NORMAL
);
418 nir_emit_cf_list(&if_stmt
->then_list
);
420 /* note: if the else is empty, dead CF elimination will remove it */
421 bld
.emit(BRW_OPCODE_ELSE
);
423 nir_emit_cf_list(&if_stmt
->else_list
);
425 bld
.emit(BRW_OPCODE_ENDIF
);
427 try_replace_with_sel();
431 fs_visitor::nir_emit_loop(nir_loop
*loop
)
433 bld
.emit(BRW_OPCODE_DO
);
435 nir_emit_cf_list(&loop
->body
);
437 bld
.emit(BRW_OPCODE_WHILE
);
441 fs_visitor::nir_emit_block(nir_block
*block
)
443 nir_foreach_instr(block
, instr
) {
444 nir_emit_instr(instr
);
449 fs_visitor::nir_emit_instr(nir_instr
*instr
)
451 const fs_builder abld
= bld
.annotate(NULL
, instr
);
453 switch (instr
->type
) {
454 case nir_instr_type_alu
:
455 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
458 case nir_instr_type_intrinsic
:
459 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case nir_instr_type_tex
:
463 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
466 case nir_instr_type_load_const
:
467 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
470 case nir_instr_type_ssa_undef
:
471 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
474 case nir_instr_type_jump
:
475 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
479 unreachable("unknown instruction type");
484 brw_type_for_nir_type(nir_alu_type type
)
487 case nir_type_unsigned
:
488 return BRW_REGISTER_TYPE_UD
;
491 return BRW_REGISTER_TYPE_D
;
493 return BRW_REGISTER_TYPE_F
;
495 unreachable("unknown type");
498 return BRW_REGISTER_TYPE_F
;
502 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
503 const fs_reg
&result
)
505 if (!instr
->src
[0].src
.is_ssa
||
506 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
509 nir_intrinsic_instr
*src0
=
510 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
515 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
516 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
519 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
520 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
523 fs_reg tmp
= vgrf(glsl_type::int_type
);
525 if (devinfo
->gen
>= 6) {
526 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
527 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
529 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
531 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
532 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
534 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
536 * This negation looks like it's safe in practice, because bits 0:4 will
537 * surely be TRIANGLES
540 if (value1
->f
[0] == -1.0f
) {
544 tmp
.type
= BRW_REGISTER_TYPE_W
;
545 tmp
.subreg_offset
= 2;
548 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
549 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
551 tmp
.type
= BRW_REGISTER_TYPE_D
;
552 tmp
.subreg_offset
= 0;
555 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
556 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
558 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
560 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
561 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
563 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
565 * This negation looks like it's safe in practice, because bits 0:4 will
566 * surely be TRIANGLES
569 if (value1
->f
[0] == -1.0f
) {
573 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
575 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
581 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
583 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
586 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
587 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
590 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
591 op
[i
] = get_nir_src(instr
->src
[i
].src
);
592 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
593 op
[i
].abs
= instr
->src
[i
].abs
;
594 op
[i
].negate
= instr
->src
[i
].negate
;
597 /* We get a bunch of mov's out of the from_ssa pass and they may still
598 * be vectorized. We'll handle them as a special-case. We'll also
599 * handle vecN here because it's basically the same thing.
607 fs_reg temp
= result
;
608 bool need_extra_copy
= false;
609 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
610 if (!instr
->src
[i
].src
.is_ssa
&&
611 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
612 need_extra_copy
= true;
613 temp
= bld
.vgrf(result
.type
, 4);
618 for (unsigned i
= 0; i
< 4; i
++) {
619 if (!(instr
->dest
.write_mask
& (1 << i
)))
622 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
623 inst
= bld
.MOV(offset(temp
, bld
, i
),
624 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
626 inst
= bld
.MOV(offset(temp
, bld
, i
),
627 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
629 inst
->saturate
= instr
->dest
.saturate
;
632 /* In this case the source and destination registers were the same,
633 * so we need to insert an extra set of moves in order to deal with
636 if (need_extra_copy
) {
637 for (unsigned i
= 0; i
< 4; i
++) {
638 if (!(instr
->dest
.write_mask
& (1 << i
)))
641 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
650 /* At this point, we have dealt with any instruction that operates on
651 * more than a single channel. Therefore, we can just adjust the source
652 * and destination registers for that channel and emit the instruction.
654 unsigned channel
= 0;
655 if (nir_op_infos
[instr
->op
].output_size
== 0) {
656 /* Since NIR is doing the scalarizing for us, we should only ever see
657 * vectorized operations with a single channel.
659 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
660 channel
= ffs(instr
->dest
.write_mask
) - 1;
662 result
= offset(result
, bld
, channel
);
665 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
666 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
667 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
673 inst
= bld
.MOV(result
, op
[0]);
674 inst
->saturate
= instr
->dest
.saturate
;
679 bld
.MOV(result
, op
[0]);
683 /* AND(val, 0x80000000) gives the sign bit.
685 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
688 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
690 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
691 op
[0].type
= BRW_REGISTER_TYPE_UD
;
692 result
.type
= BRW_REGISTER_TYPE_UD
;
693 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
695 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
696 inst
->predicate
= BRW_PREDICATE_NORMAL
;
697 if (instr
->dest
.saturate
) {
698 inst
= bld
.MOV(result
, result
);
699 inst
->saturate
= true;
705 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
706 * -> non-negative val generates 0x00000000.
707 * Predicated OR sets 1 if val is positive.
709 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
710 bld
.ASR(result
, op
[0], fs_reg(31));
711 inst
= bld
.OR(result
, result
, fs_reg(1));
712 inst
->predicate
= BRW_PREDICATE_NORMAL
;
716 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
717 inst
->saturate
= instr
->dest
.saturate
;
721 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
722 inst
->saturate
= instr
->dest
.saturate
;
726 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
727 inst
->saturate
= instr
->dest
.saturate
;
731 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
732 inst
->saturate
= instr
->dest
.saturate
;
736 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
737 inst
->saturate
= instr
->dest
.saturate
;
741 if (fs_key
->high_quality_derivatives
) {
742 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
744 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
746 inst
->saturate
= instr
->dest
.saturate
;
748 case nir_op_fddx_fine
:
749 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
750 inst
->saturate
= instr
->dest
.saturate
;
752 case nir_op_fddx_coarse
:
753 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
754 inst
->saturate
= instr
->dest
.saturate
;
757 if (fs_key
->high_quality_derivatives
) {
758 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
759 fs_reg(fs_key
->render_to_fbo
));
761 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
762 fs_reg(fs_key
->render_to_fbo
));
764 inst
->saturate
= instr
->dest
.saturate
;
766 case nir_op_fddy_fine
:
767 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
768 fs_reg(fs_key
->render_to_fbo
));
769 inst
->saturate
= instr
->dest
.saturate
;
771 case nir_op_fddy_coarse
:
772 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
773 fs_reg(fs_key
->render_to_fbo
));
774 inst
->saturate
= instr
->dest
.saturate
;
779 inst
= bld
.ADD(result
, op
[0], op
[1]);
780 inst
->saturate
= instr
->dest
.saturate
;
784 inst
= bld
.MUL(result
, op
[0], op
[1]);
785 inst
->saturate
= instr
->dest
.saturate
;
789 bld
.MUL(result
, op
[0], op
[1]);
792 case nir_op_imul_high
:
793 case nir_op_umul_high
: {
794 if (devinfo
->gen
>= 7)
795 no16("SIMD16 explicit accumulator operands unsupported\n");
797 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
799 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
800 bld
.MACH(result
, op
[0], op
[1]);
802 /* Until Gen8, integer multiplies read 32-bits from one source, and
803 * 16-bits from the other, and relying on the MACH instruction to
804 * generate the high bits of the result.
806 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
807 * but in order to do a 64x64-bit multiply we have to simulate the
808 * previous behavior and then use a MACH instruction.
810 * FINISHME: Don't use source modifiers on src1.
812 if (devinfo
->gen
>= 8) {
813 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
814 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
815 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
816 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
817 mul
->src
[1].stride
= 2;
819 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
820 mul
->src
[1].stride
= 2;
828 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
831 case nir_op_uadd_carry
: {
832 if (devinfo
->gen
>= 7)
833 no16("SIMD16 explicit accumulator operands unsupported\n");
835 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
836 BRW_REGISTER_TYPE_UD
);
838 bld
.ADDC(bld
.null_reg_ud(), op
[0], op
[1]);
839 bld
.MOV(result
, fs_reg(acc
));
843 case nir_op_usub_borrow
: {
844 if (devinfo
->gen
>= 7)
845 no16("SIMD16 explicit accumulator operands unsupported\n");
847 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
848 BRW_REGISTER_TYPE_UD
);
850 bld
.SUBB(bld
.null_reg_ud(), op
[0], op
[1]);
851 bld
.MOV(result
, fs_reg(acc
));
856 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
862 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
868 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
873 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
878 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
882 if (devinfo
->gen
>= 8) {
883 resolve_source_modifiers(&op
[0]);
885 bld
.NOT(result
, op
[0]);
888 if (devinfo
->gen
>= 8) {
889 resolve_source_modifiers(&op
[0]);
890 resolve_source_modifiers(&op
[1]);
892 bld
.XOR(result
, op
[0], op
[1]);
895 if (devinfo
->gen
>= 8) {
896 resolve_source_modifiers(&op
[0]);
897 resolve_source_modifiers(&op
[1]);
899 bld
.OR(result
, op
[0], op
[1]);
902 if (devinfo
->gen
>= 8) {
903 resolve_source_modifiers(&op
[0]);
904 resolve_source_modifiers(&op
[1]);
906 bld
.AND(result
, op
[0], op
[1]);
918 case nir_op_ball_fequal2
:
919 case nir_op_ball_iequal2
:
920 case nir_op_ball_fequal3
:
921 case nir_op_ball_iequal3
:
922 case nir_op_ball_fequal4
:
923 case nir_op_ball_iequal4
:
924 case nir_op_bany_fnequal2
:
925 case nir_op_bany_inequal2
:
926 case nir_op_bany_fnequal3
:
927 case nir_op_bany_inequal3
:
928 case nir_op_bany_fnequal4
:
929 case nir_op_bany_inequal4
:
930 unreachable("Lowered by nir_lower_alu_reductions");
932 case nir_op_fnoise1_1
:
933 case nir_op_fnoise1_2
:
934 case nir_op_fnoise1_3
:
935 case nir_op_fnoise1_4
:
936 case nir_op_fnoise2_1
:
937 case nir_op_fnoise2_2
:
938 case nir_op_fnoise2_3
:
939 case nir_op_fnoise2_4
:
940 case nir_op_fnoise3_1
:
941 case nir_op_fnoise3_2
:
942 case nir_op_fnoise3_3
:
943 case nir_op_fnoise3_4
:
944 case nir_op_fnoise4_1
:
945 case nir_op_fnoise4_2
:
946 case nir_op_fnoise4_3
:
947 case nir_op_fnoise4_4
:
948 unreachable("not reached: should be handled by lower_noise");
951 unreachable("not reached: should be handled by ldexp_to_arith()");
954 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
955 inst
->saturate
= instr
->dest
.saturate
;
959 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
960 inst
->saturate
= instr
->dest
.saturate
;
964 bld
.AND(result
, op
[0], fs_reg(1));
967 bld
.AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
));
971 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
974 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
978 inst
= bld
.RNDZ(result
, op
[0]);
979 inst
->saturate
= instr
->dest
.saturate
;
983 op
[0].negate
= !op
[0].negate
;
984 fs_reg temp
= vgrf(glsl_type::float_type
);
985 bld
.RNDD(temp
, op
[0]);
987 inst
= bld
.MOV(result
, temp
);
988 inst
->saturate
= instr
->dest
.saturate
;
992 inst
= bld
.RNDD(result
, op
[0]);
993 inst
->saturate
= instr
->dest
.saturate
;
996 inst
= bld
.FRC(result
, op
[0]);
997 inst
->saturate
= instr
->dest
.saturate
;
999 case nir_op_fround_even
:
1000 inst
= bld
.RNDE(result
, op
[0]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1007 if (devinfo
->gen
>= 6) {
1008 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1009 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1011 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
1012 inst
= bld
.SEL(result
, op
[0], op
[1]);
1013 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1015 inst
->saturate
= instr
->dest
.saturate
;
1021 if (devinfo
->gen
>= 6) {
1022 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1023 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1025 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1026 inst
= bld
.SEL(result
, op
[0], op
[1]);
1027 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1029 inst
->saturate
= instr
->dest
.saturate
;
1032 case nir_op_pack_snorm_2x16
:
1033 case nir_op_pack_snorm_4x8
:
1034 case nir_op_pack_unorm_2x16
:
1035 case nir_op_pack_unorm_4x8
:
1036 case nir_op_unpack_snorm_2x16
:
1037 case nir_op_unpack_snorm_4x8
:
1038 case nir_op_unpack_unorm_2x16
:
1039 case nir_op_unpack_unorm_4x8
:
1040 case nir_op_unpack_half_2x16
:
1041 case nir_op_pack_half_2x16
:
1042 unreachable("not reached: should be handled by lower_packing_builtins");
1044 case nir_op_unpack_half_2x16_split_x
:
1045 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1046 inst
->saturate
= instr
->dest
.saturate
;
1048 case nir_op_unpack_half_2x16_split_y
:
1049 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1050 inst
->saturate
= instr
->dest
.saturate
;
1054 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1055 inst
->saturate
= instr
->dest
.saturate
;
1058 case nir_op_bitfield_reverse
:
1059 bld
.BFREV(result
, op
[0]);
1062 case nir_op_bit_count
:
1063 bld
.CBIT(result
, op
[0]);
1066 case nir_op_ufind_msb
:
1067 case nir_op_ifind_msb
: {
1068 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1070 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1071 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1072 * subtract the result from 31 to convert the MSB count into an LSB count.
1075 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1076 fs_reg
neg_result(result
);
1077 neg_result
.negate
= true;
1078 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1079 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1083 case nir_op_find_lsb
:
1084 bld
.FBL(result
, op
[0]);
1087 case nir_op_ubitfield_extract
:
1088 case nir_op_ibitfield_extract
:
1089 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1092 bld
.BFI1(result
, op
[0], op
[1]);
1095 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1098 case nir_op_bitfield_insert
:
1099 unreachable("not reached: should be handled by "
1100 "lower_instructions::bitfield_insert_to_bfm_bfi");
1103 bld
.SHL(result
, op
[0], op
[1]);
1106 bld
.ASR(result
, op
[0], op
[1]);
1109 bld
.SHR(result
, op
[0], op
[1]);
1112 case nir_op_pack_half_2x16_split
:
1113 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1117 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1118 inst
->saturate
= instr
->dest
.saturate
;
1122 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1123 inst
->saturate
= instr
->dest
.saturate
;
1127 if (optimize_frontfacing_ternary(instr
, result
))
1130 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1131 inst
= bld
.SEL(result
, op
[1], op
[2]);
1132 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1136 unreachable("unhandled instruction");
1139 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1140 * to sign extend the low bit to 0/~0
1142 if (devinfo
->gen
<= 5 &&
1143 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1144 fs_reg masked
= vgrf(glsl_type::int_type
);
1145 bld
.AND(masked
, result
, fs_reg(1));
1146 masked
.negate
= true;
1147 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1152 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1153 nir_load_const_instr
*instr
)
1155 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1157 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1158 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1160 nir_ssa_values
[instr
->def
.index
] = reg
;
1164 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1166 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1167 instr
->def
.num_components
);
1171 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1172 unsigned base_offset
, nir_src
*indirect
)
1175 if (nir_reg
->is_global
)
1176 reg
= v
->nir_globals
[nir_reg
->index
];
1178 reg
= v
->nir_locals
[nir_reg
->index
];
1180 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1182 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1184 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1185 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1186 fs_reg(multiplier
));
1193 fs_visitor::get_nir_src(nir_src src
)
1197 reg
= nir_ssa_values
[src
.ssa
->index
];
1199 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1203 /* to avoid floating-point denorm flushing problems, set the type by
1204 * default to D - instructions that need floating point semantics will set
1205 * this to F if they need to
1207 return retype(reg
, BRW_REGISTER_TYPE_D
);
1211 fs_visitor::get_nir_dest(nir_dest dest
)
1214 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1215 dest
.ssa
.num_components
);
1216 return nir_ssa_values
[dest
.ssa
.index
];
1219 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1224 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1227 for (unsigned i
= 0; i
< 4; i
++) {
1228 if (!((wr_mask
>> i
) & 1))
1231 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1232 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1233 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1234 if (new_inst
->src
[j
].file
== GRF
)
1235 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1242 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1245 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1246 dest
= get_nir_dest(instr
->dest
);
1248 bool has_indirect
= false;
1250 switch (instr
->intrinsic
) {
1251 case nir_intrinsic_discard
:
1252 case nir_intrinsic_discard_if
: {
1253 /* We track our discarded pixels in f0.1. By predicating on it, we can
1254 * update just the flag bits that aren't yet discarded. If there's no
1255 * condition, we emit a CMP of g0 != g0, so all currently executing
1256 * channels will get turned off.
1259 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1260 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1261 fs_reg(0), BRW_CONDITIONAL_Z
);
1263 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1264 BRW_REGISTER_TYPE_UW
));
1265 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1267 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1268 cmp
->flag_subreg
= 1;
1270 if (devinfo
->gen
>= 6) {
1271 emit_discard_jump();
1276 case nir_intrinsic_atomic_counter_inc
:
1277 case nir_intrinsic_atomic_counter_dec
:
1278 case nir_intrinsic_atomic_counter_read
: {
1279 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1280 (unsigned) instr
->const_index
[0];
1281 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1283 switch (instr
->intrinsic
) {
1284 case nir_intrinsic_atomic_counter_inc
:
1285 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1286 fs_reg(), fs_reg());
1288 case nir_intrinsic_atomic_counter_dec
:
1289 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1290 fs_reg(), fs_reg());
1292 case nir_intrinsic_atomic_counter_read
:
1293 emit_untyped_surface_read(surf_index
, dest
, offset
);
1296 unreachable("Unreachable");
1301 case nir_intrinsic_load_front_face
:
1302 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1303 *emit_frontfacing_interpolation());
1306 case nir_intrinsic_load_vertex_id
:
1307 unreachable("should be lowered by lower_vertex_id()");
1309 case nir_intrinsic_load_vertex_id_zero_base
: {
1310 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1311 assert(vertex_id
.file
!= BAD_FILE
);
1312 dest
.type
= vertex_id
.type
;
1313 bld
.MOV(dest
, vertex_id
);
1317 case nir_intrinsic_load_base_vertex
: {
1318 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1319 assert(base_vertex
.file
!= BAD_FILE
);
1320 dest
.type
= base_vertex
.type
;
1321 bld
.MOV(dest
, base_vertex
);
1325 case nir_intrinsic_load_instance_id
: {
1326 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1327 assert(instance_id
.file
!= BAD_FILE
);
1328 dest
.type
= instance_id
.type
;
1329 bld
.MOV(dest
, instance_id
);
1333 case nir_intrinsic_load_sample_mask_in
: {
1334 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1335 assert(sample_mask_in
.file
!= BAD_FILE
);
1336 dest
.type
= sample_mask_in
.type
;
1337 bld
.MOV(dest
, sample_mask_in
);
1341 case nir_intrinsic_load_sample_pos
: {
1342 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1343 assert(sample_pos
.file
!= BAD_FILE
);
1344 dest
.type
= sample_pos
.type
;
1345 bld
.MOV(dest
, sample_pos
);
1346 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1350 case nir_intrinsic_load_sample_id
: {
1351 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1352 assert(sample_id
.file
!= BAD_FILE
);
1353 dest
.type
= sample_id
.type
;
1354 bld
.MOV(dest
, sample_id
);
1358 case nir_intrinsic_load_uniform_indirect
:
1359 has_indirect
= true;
1361 case nir_intrinsic_load_uniform
: {
1362 unsigned index
= instr
->const_index
[0];
1365 if (index
< num_direct_uniforms
) {
1366 uniform_reg
= fs_reg(UNIFORM
, 0);
1368 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1369 index
-= num_direct_uniforms
;
1372 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1373 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1375 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1379 dest
= offset(dest
, bld
, 1);
1384 case nir_intrinsic_load_ubo_indirect
:
1385 has_indirect
= true;
1387 case nir_intrinsic_load_ubo
: {
1388 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1392 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1395 /* The block index is not a constant. Evaluate the index expression
1396 * per-channel and add the base UBO index; we have to select a value
1397 * from any live channel.
1399 surf_index
= vgrf(glsl_type::uint_type
);
1400 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1401 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1402 bld
.emit_uniformize(surf_index
, surf_index
);
1404 /* Assume this may touch any UBO. It would be nice to provide
1405 * a tighter bound, but the array information is already lowered away.
1407 brw_mark_surface_used(prog_data
,
1408 stage_prog_data
->binding_table
.ubo_start
+
1409 shader_prog
->NumUniformBlocks
- 1);
1413 /* Turn the byte offset into a dword offset. */
1414 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1415 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1416 BRW_REGISTER_TYPE_D
),
1419 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1420 for (int i
= 0; i
< instr
->num_components
; i
++)
1421 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1422 base_offset
, vec4_offset
+ i
);
1424 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1425 packed_consts
.type
= dest
.type
;
1427 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1428 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1429 surf_index
, const_offset_reg
);
1431 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1432 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1434 /* The std140 packing rules don't allow vectors to cross 16-byte
1435 * boundaries, and a reg is 32 bytes.
1437 assert(packed_consts
.subreg_offset
< 32);
1439 bld
.MOV(dest
, packed_consts
);
1440 dest
= offset(dest
, bld
, 1);
1446 case nir_intrinsic_load_input_indirect
:
1447 has_indirect
= true;
1449 case nir_intrinsic_load_input
: {
1451 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1452 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1453 instr
->const_index
[0] + index
);
1455 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1459 dest
= offset(dest
, bld
, 1);
1464 /* Handle ARB_gpu_shader5 interpolation intrinsics
1466 * It's worth a quick word of explanation as to why we handle the full
1467 * variable-based interpolation intrinsic rather than a lowered version
1468 * with like we do for other inputs. We have to do that because the way
1469 * we set up inputs doesn't allow us to use the already setup inputs for
1470 * interpolation. At the beginning of the shader, we go through all of
1471 * the input variables and do the initial interpolation and put it in
1472 * the nir_inputs array based on its location as determined in
1473 * nir_lower_io. If the input isn't used, dead code cleans up and
1474 * everything works fine. However, when we get to the ARB_gpu_shader5
1475 * interpolation intrinsics, we need to reinterpolate the input
1476 * differently. If we used an intrinsic that just had an index it would
1477 * only give us the offset into the nir_inputs array. However, this is
1478 * useless because that value is post-interpolation and we need
1479 * pre-interpolation. In order to get the actual location of the bits
1480 * we get from the vertex fetching hardware, we need the variable.
1482 case nir_intrinsic_interp_var_at_centroid
:
1483 case nir_intrinsic_interp_var_at_sample
:
1484 case nir_intrinsic_interp_var_at_offset
: {
1485 assert(stage
== MESA_SHADER_FRAGMENT
);
1487 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1489 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1491 /* For most messages, we need one reg of ignored data; the hardware
1492 * requires mlen==1 even when there is no payload. in the per-slot
1493 * offset case, we'll replace this with the proper source data.
1495 fs_reg src
= vgrf(glsl_type::float_type
);
1496 int mlen
= 1; /* one reg unless overriden */
1499 switch (instr
->intrinsic
) {
1500 case nir_intrinsic_interp_var_at_centroid
:
1501 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1502 dst_xy
, src
, fs_reg(0u));
1505 case nir_intrinsic_interp_var_at_sample
: {
1506 /* XXX: We should probably handle non-constant sample id's */
1507 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1508 assert(const_sample
);
1509 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1510 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1515 case nir_intrinsic_interp_var_at_offset
: {
1516 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1519 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1520 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1522 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1523 fs_reg(off_x
| (off_y
<< 4)));
1525 src
= vgrf(glsl_type::ivec2_type
);
1526 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1527 BRW_REGISTER_TYPE_F
);
1528 for (int i
= 0; i
< 2; i
++) {
1529 fs_reg temp
= vgrf(glsl_type::float_type
);
1530 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1531 fs_reg itemp
= vgrf(glsl_type::int_type
);
1532 bld
.MOV(itemp
, temp
); /* float to int */
1534 /* Clamp the upper end of the range to +7/16.
1535 * ARB_gpu_shader5 requires that we support a maximum offset
1536 * of +0.5, which isn't representable in a S0.4 value -- if
1537 * we didn't clamp it, we'd end up with -8/16, which is the
1538 * opposite of what the shader author wanted.
1540 * This is legal due to ARB_gpu_shader5's quantization
1543 * "Not all values of <offset> may be supported; x and y
1544 * offsets may be rounded to fixed-point values with the
1545 * number of fraction bits given by the
1546 * implementation-dependent constant
1547 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1549 set_condmod(BRW_CONDITIONAL_L
,
1550 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1553 mlen
= 2 * dispatch_width
/ 8;
1554 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1561 unreachable("Invalid intrinsic");
1565 /* 2 floats per slot returned */
1566 inst
->regs_written
= 2 * dispatch_width
/ 8;
1567 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1568 INTERP_QUALIFIER_NOPERSPECTIVE
;
1570 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1571 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1572 src
.type
= dest
.type
;
1574 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1575 dest
= offset(dest
, bld
, 1);
1580 case nir_intrinsic_store_output_indirect
:
1581 has_indirect
= true;
1583 case nir_intrinsic_store_output
: {
1584 fs_reg src
= get_nir_src(instr
->src
[0]);
1586 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1587 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1588 instr
->const_index
[0] + index
);
1590 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1592 bld
.MOV(new_dest
, src
);
1593 src
= offset(src
, bld
, 1);
1598 case nir_intrinsic_barrier
:
1603 unreachable("unknown intrinsic");
1608 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1610 unsigned sampler
= instr
->sampler_index
;
1611 fs_reg
sampler_reg(sampler
);
1613 /* FINISHME: We're failing to recompile our programs when the sampler is
1614 * updated. This only matters for the texture rectangle scale parameters
1615 * (pre-gen6, or gen6+ with GL_CLAMP).
1617 int texunit
= prog
->SamplerUnits
[sampler
];
1619 int gather_component
= instr
->component
;
1621 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1623 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1626 int lod_components
= 0;
1627 int UNUSED offset_components
= 0;
1629 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1631 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1632 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1633 switch (instr
->src
[i
].src_type
) {
1634 case nir_tex_src_bias
:
1635 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1637 case nir_tex_src_comparitor
:
1638 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1640 case nir_tex_src_coord
:
1641 switch (instr
->op
) {
1643 case nir_texop_txf_ms
:
1644 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1647 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1651 case nir_tex_src_ddx
:
1652 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1653 lod_components
= nir_tex_instr_src_size(instr
, i
);
1655 case nir_tex_src_ddy
:
1656 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1658 case nir_tex_src_lod
:
1659 switch (instr
->op
) {
1661 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1664 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1667 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1671 case nir_tex_src_ms_index
:
1672 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1674 case nir_tex_src_offset
:
1675 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1676 if (instr
->is_array
)
1677 offset_components
= instr
->coord_components
- 1;
1679 offset_components
= instr
->coord_components
;
1681 case nir_tex_src_projector
:
1682 unreachable("should be lowered");
1684 case nir_tex_src_sampler_offset
: {
1685 /* Figure out the highest possible sampler index and mark it as used */
1686 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1687 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1688 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1690 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1692 brw_mark_surface_used(prog_data
, max_used
);
1694 /* Emit code to evaluate the actual indexing expression */
1695 sampler_reg
= vgrf(glsl_type::uint_type
);
1696 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1697 bld
.emit_uniformize(sampler_reg
, sampler_reg
);
1702 unreachable("unknown texture source");
1706 if (instr
->op
== nir_texop_txf_ms
) {
1707 if (devinfo
->gen
>= 7 &&
1708 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1709 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1715 for (unsigned i
= 0; i
< 3; i
++) {
1716 if (instr
->const_offset
[i
] != 0) {
1717 assert(offset_components
== 0);
1718 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1723 enum glsl_base_type dest_base_type
;
1724 switch (instr
->dest_type
) {
1725 case nir_type_float
:
1726 dest_base_type
= GLSL_TYPE_FLOAT
;
1729 dest_base_type
= GLSL_TYPE_INT
;
1731 case nir_type_unsigned
:
1732 dest_base_type
= GLSL_TYPE_UINT
;
1735 unreachable("bad type");
1738 const glsl_type
*dest_type
=
1739 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1742 ir_texture_opcode op
;
1743 switch (instr
->op
) {
1744 case nir_texop_lod
: op
= ir_lod
; break;
1745 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1746 case nir_texop_tex
: op
= ir_tex
; break;
1747 case nir_texop_tg4
: op
= ir_tg4
; break;
1748 case nir_texop_txb
: op
= ir_txb
; break;
1749 case nir_texop_txd
: op
= ir_txd
; break;
1750 case nir_texop_txf
: op
= ir_txf
; break;
1751 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1752 case nir_texop_txl
: op
= ir_txl
; break;
1753 case nir_texop_txs
: op
= ir_txs
; break;
1755 unreachable("unknown texture opcode");
1758 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1759 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1760 tex_offset
, mcs
, gather_component
,
1761 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1763 fs_reg dest
= get_nir_dest(instr
->dest
);
1764 dest
.type
= this->result
.type
;
1765 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1766 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1767 dest
, this->result
),
1768 (1 << num_components
) - 1);
1772 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1774 switch (instr
->type
) {
1775 case nir_jump_break
:
1776 bld
.emit(BRW_OPCODE_BREAK
);
1778 case nir_jump_continue
:
1779 bld
.emit(BRW_OPCODE_CONTINUE
);
1781 case nir_jump_return
:
1783 unreachable("unknown jump");