2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
66 var
->data
.origin_upper_left
);
67 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
69 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
70 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
71 reg
.type
= BRW_REGISTER_TYPE_D
;
72 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
73 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
74 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
75 reg
.type
= BRW_REGISTER_TYPE_D
;
76 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
78 int location
= var
->data
.location
;
79 emit_general_interpolation(&input
, var
->name
, var
->type
,
80 (glsl_interp_qualifier
) var
->data
.interpolation
,
81 &location
, var
->data
.centroid
,
88 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
89 const glsl_type
*type
,
92 if (type
->is_array() || type
->is_matrix()) {
93 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
94 const unsigned length
= glsl_get_length(type
);
96 for (unsigned i
= 0; i
< length
; i
++) {
97 nir_setup_single_output_varying(reg
, elem_type
, location
);
99 } else if (type
->is_record()) {
100 for (unsigned i
= 0; i
< type
->length
; i
++) {
101 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
102 nir_setup_single_output_varying(reg
, field_type
, location
);
105 assert(type
->is_scalar() || type
->is_vector());
106 this->outputs
[*location
] = *reg
;
107 this->output_components
[*location
] = type
->vector_elements
;
108 *reg
= offset(*reg
, bld
, 4);
114 fs_visitor::nir_setup_outputs()
116 if (stage
== MESA_SHADER_TESS_CTRL
)
119 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
121 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
123 nir_foreach_variable(var
, &nir
->outputs
) {
124 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 case MESA_SHADER_VERTEX
:
128 case MESA_SHADER_TESS_EVAL
:
129 case MESA_SHADER_GEOMETRY
: {
130 unsigned location
= var
->data
.location
;
131 nir_setup_single_output_varying(®
, var
->type
, &location
);
134 case MESA_SHADER_FRAGMENT
:
135 if (key
->force_dual_color_blend
&&
136 var
->data
.location
== FRAG_RESULT_DATA1
) {
137 this->dual_src_output
= reg
;
138 this->do_dual_src
= true;
139 } else if (var
->data
.index
> 0) {
140 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
141 assert(var
->data
.index
== 1);
142 this->dual_src_output
= reg
;
143 this->do_dual_src
= true;
144 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
145 /* Writing gl_FragColor outputs to all color regions. */
146 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
147 this->outputs
[i
] = reg
;
148 this->output_components
[i
] = 4;
150 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
151 this->frag_depth
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
153 this->frag_stencil
= reg
;
154 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
155 this->sample_mask
= reg
;
157 int vector_elements
= var
->type
->without_array()->vector_elements
;
159 /* gl_FragData or a user-defined FS output */
160 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
161 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
163 /* General color output. */
164 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
165 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
166 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
167 this->output_components
[output
] = vector_elements
;
172 unreachable("unhandled shader stage");
178 fs_visitor::nir_setup_uniforms()
180 if (dispatch_width
!= 8)
183 uniforms
= nir
->num_uniforms
/ 4;
187 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
191 nir_foreach_instr(instr
, block
) {
192 if (instr
->type
!= nir_instr_type_intrinsic
)
195 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
196 switch (intrin
->intrinsic
) {
197 case nir_intrinsic_load_vertex_id
:
198 unreachable("should be lowered by lower_vertex_id().");
200 case nir_intrinsic_load_vertex_id_zero_base
:
201 assert(v
->stage
== MESA_SHADER_VERTEX
);
202 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
203 if (reg
->file
== BAD_FILE
)
204 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
207 case nir_intrinsic_load_base_vertex
:
208 assert(v
->stage
== MESA_SHADER_VERTEX
);
209 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
210 if (reg
->file
== BAD_FILE
)
211 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
214 case nir_intrinsic_load_instance_id
:
215 assert(v
->stage
== MESA_SHADER_VERTEX
);
216 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
217 if (reg
->file
== BAD_FILE
)
218 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
221 case nir_intrinsic_load_base_instance
:
222 assert(v
->stage
== MESA_SHADER_VERTEX
);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
228 case nir_intrinsic_load_draw_id
:
229 assert(v
->stage
== MESA_SHADER_VERTEX
);
230 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
231 if (reg
->file
== BAD_FILE
)
232 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
235 case nir_intrinsic_load_invocation_id
:
236 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
238 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
240 if (reg
->file
== BAD_FILE
) {
241 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
242 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
243 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
244 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
249 case nir_intrinsic_load_sample_pos
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
252 if (reg
->file
== BAD_FILE
)
253 *reg
= *v
->emit_samplepos_setup();
256 case nir_intrinsic_load_sample_id
:
257 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
258 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
259 if (reg
->file
== BAD_FILE
)
260 *reg
= *v
->emit_sampleid_setup();
263 case nir_intrinsic_load_sample_mask_in
:
264 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
265 assert(v
->devinfo
->gen
>= 7);
266 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
267 if (reg
->file
== BAD_FILE
)
268 *reg
= *v
->emit_samplemaskin_setup();
271 case nir_intrinsic_load_local_invocation_id
:
272 assert(v
->stage
== MESA_SHADER_COMPUTE
);
273 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
274 if (reg
->file
== BAD_FILE
)
275 *reg
= *v
->emit_cs_local_invocation_id_setup();
278 case nir_intrinsic_load_work_group_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_work_group_id_setup();
285 case nir_intrinsic_load_helper_invocation
:
286 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
288 if (reg
->file
== BAD_FILE
) {
289 const fs_builder abld
=
290 v
->bld
.annotate("gl_HelperInvocation", NULL
);
292 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
293 * pixel mask is in g1.7 of the thread payload.
295 * We move the per-channel pixel enable bit to the low bit of each
296 * channel by shifting the byte containing the pixel mask by the
297 * vector immediate 0x76543210UV.
299 * The region of <1,8,0> reads only 1 byte (the pixel masks for
300 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
301 * masks for 2 and 3) in SIMD16.
303 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
305 stride(byte_offset(retype(brw_vec1_grf(1, 0),
306 BRW_REGISTER_TYPE_UB
), 28),
308 brw_imm_uv(0x76543210));
310 /* A set bit in the pixel mask means the channel is enabled, but
311 * that is the opposite of gl_HelperInvocation so we need to invert
314 * The negate source-modifier bit of logical instructions on Gen8+
315 * performs 1's complement negation, so we can use that instead of
318 fs_reg inverted
= negate(shifted
);
319 if (v
->devinfo
->gen
< 8) {
320 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
321 abld
.NOT(inverted
, shifted
);
324 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
325 * with 1 and negating.
327 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
328 abld
.AND(anded
, inverted
, brw_imm_uw(1));
330 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
331 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
345 fs_visitor::nir_emit_system_values()
347 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
348 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
349 nir_system_values
[i
] = fs_reg();
352 nir_foreach_function(function
, nir
) {
353 assert(strcmp(function
->name
, "main") == 0);
354 assert(function
->impl
);
355 nir_foreach_block(block
, function
->impl
) {
356 emit_system_values_block(block
, this);
362 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
364 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
365 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
366 nir_locals
[i
] = fs_reg();
369 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
370 unsigned array_elems
=
371 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
372 unsigned size
= array_elems
* reg
->num_components
;
373 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
376 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
379 nir_emit_cf_list(&impl
->body
);
383 fs_visitor::nir_emit_cf_list(exec_list
*list
)
385 exec_list_validate(list
);
386 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
387 switch (node
->type
) {
389 nir_emit_if(nir_cf_node_as_if(node
));
392 case nir_cf_node_loop
:
393 nir_emit_loop(nir_cf_node_as_loop(node
));
396 case nir_cf_node_block
:
397 nir_emit_block(nir_cf_node_as_block(node
));
401 unreachable("Invalid CFG node block");
407 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
409 /* first, put the condition into f0 */
410 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
411 retype(get_nir_src(if_stmt
->condition
),
412 BRW_REGISTER_TYPE_D
));
413 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
415 bld
.IF(BRW_PREDICATE_NORMAL
);
417 nir_emit_cf_list(&if_stmt
->then_list
);
419 /* note: if the else is empty, dead CF elimination will remove it */
420 bld
.emit(BRW_OPCODE_ELSE
);
422 nir_emit_cf_list(&if_stmt
->else_list
);
424 bld
.emit(BRW_OPCODE_ENDIF
);
428 fs_visitor::nir_emit_loop(nir_loop
*loop
)
430 bld
.emit(BRW_OPCODE_DO
);
432 nir_emit_cf_list(&loop
->body
);
434 bld
.emit(BRW_OPCODE_WHILE
);
438 fs_visitor::nir_emit_block(nir_block
*block
)
440 nir_foreach_instr(instr
, block
) {
441 nir_emit_instr(instr
);
446 fs_visitor::nir_emit_instr(nir_instr
*instr
)
448 const fs_builder abld
= bld
.annotate(NULL
, instr
);
450 switch (instr
->type
) {
451 case nir_instr_type_alu
:
452 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
455 case nir_instr_type_intrinsic
:
457 case MESA_SHADER_VERTEX
:
458 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
460 case MESA_SHADER_TESS_CTRL
:
461 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
463 case MESA_SHADER_TESS_EVAL
:
464 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
466 case MESA_SHADER_GEOMETRY
:
467 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
469 case MESA_SHADER_FRAGMENT
:
470 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
472 case MESA_SHADER_COMPUTE
:
473 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
476 unreachable("unsupported shader stage");
480 case nir_instr_type_tex
:
481 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
484 case nir_instr_type_load_const
:
485 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
488 case nir_instr_type_ssa_undef
:
489 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
492 case nir_instr_type_jump
:
493 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
497 unreachable("unknown instruction type");
502 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
506 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
507 const fs_reg
&result
)
509 if (!instr
->src
[0].src
.is_ssa
||
510 !instr
->src
[0].src
.ssa
->parent_instr
)
513 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
516 nir_alu_instr
*src0
=
517 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
519 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
520 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
523 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
524 assert(element
!= NULL
);
526 enum opcode extract_op
;
527 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
528 assert(element
->u32
[0] <= 1);
529 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
531 assert(element
->u32
[0] <= 3);
532 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
535 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
536 op0
.type
= brw_type_for_nir_type(nir_op_infos
[src0
->op
].input_types
[0]);
537 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
539 set_saturate(instr
->dest
.saturate
,
540 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
545 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
546 const fs_reg
&result
)
548 if (!instr
->src
[0].src
.is_ssa
||
549 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
552 nir_intrinsic_instr
*src0
=
553 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
555 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
558 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
559 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
562 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
563 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
566 fs_reg tmp
= vgrf(glsl_type::int_type
);
568 if (devinfo
->gen
>= 6) {
569 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
570 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
572 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
574 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
575 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
577 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
579 * This negation looks like it's safe in practice, because bits 0:4 will
580 * surely be TRIANGLES
583 if (value1
->f32
[0] == -1.0f
) {
587 tmp
.type
= BRW_REGISTER_TYPE_W
;
588 tmp
.subreg_offset
= 2;
591 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
593 tmp
.type
= BRW_REGISTER_TYPE_D
;
594 tmp
.subreg_offset
= 0;
597 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
598 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
600 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
602 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
603 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
605 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
607 * This negation looks like it's safe in practice, because bits 0:4 will
608 * surely be TRIANGLES
611 if (value1
->f32
[0] == -1.0f
) {
615 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
617 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
623 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
625 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
628 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
629 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
632 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
633 op
[i
] = get_nir_src(instr
->src
[i
].src
);
634 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
635 op
[i
].abs
= instr
->src
[i
].abs
;
636 op
[i
].negate
= instr
->src
[i
].negate
;
639 /* We get a bunch of mov's out of the from_ssa pass and they may still
640 * be vectorized. We'll handle them as a special-case. We'll also
641 * handle vecN here because it's basically the same thing.
649 fs_reg temp
= result
;
650 bool need_extra_copy
= false;
651 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
652 if (!instr
->src
[i
].src
.is_ssa
&&
653 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
654 need_extra_copy
= true;
655 temp
= bld
.vgrf(result
.type
, 4);
660 for (unsigned i
= 0; i
< 4; i
++) {
661 if (!(instr
->dest
.write_mask
& (1 << i
)))
664 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
665 inst
= bld
.MOV(offset(temp
, bld
, i
),
666 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
668 inst
= bld
.MOV(offset(temp
, bld
, i
),
669 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
671 inst
->saturate
= instr
->dest
.saturate
;
674 /* In this case the source and destination registers were the same,
675 * so we need to insert an extra set of moves in order to deal with
678 if (need_extra_copy
) {
679 for (unsigned i
= 0; i
< 4; i
++) {
680 if (!(instr
->dest
.write_mask
& (1 << i
)))
683 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
692 /* At this point, we have dealt with any instruction that operates on
693 * more than a single channel. Therefore, we can just adjust the source
694 * and destination registers for that channel and emit the instruction.
696 unsigned channel
= 0;
697 if (nir_op_infos
[instr
->op
].output_size
== 0) {
698 /* Since NIR is doing the scalarizing for us, we should only ever see
699 * vectorized operations with a single channel.
701 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
702 channel
= ffs(instr
->dest
.write_mask
) - 1;
704 result
= offset(result
, bld
, channel
);
707 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
708 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
709 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
715 if (optimize_extract_to_float(instr
, result
))
718 inst
= bld
.MOV(result
, op
[0]);
719 inst
->saturate
= instr
->dest
.saturate
;
724 bld
.MOV(result
, op
[0]);
728 /* AND(val, 0x80000000) gives the sign bit.
730 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
733 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
735 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
736 op
[0].type
= BRW_REGISTER_TYPE_UD
;
737 result
.type
= BRW_REGISTER_TYPE_UD
;
738 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
740 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
741 inst
->predicate
= BRW_PREDICATE_NORMAL
;
742 if (instr
->dest
.saturate
) {
743 inst
= bld
.MOV(result
, result
);
744 inst
->saturate
= true;
750 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
751 * -> non-negative val generates 0x00000000.
752 * Predicated OR sets 1 if val is positive.
754 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
755 bld
.ASR(result
, op
[0], brw_imm_d(31));
756 inst
= bld
.OR(result
, result
, brw_imm_d(1));
757 inst
->predicate
= BRW_PREDICATE_NORMAL
;
761 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
762 inst
->saturate
= instr
->dest
.saturate
;
766 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
767 inst
->saturate
= instr
->dest
.saturate
;
771 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
772 inst
->saturate
= instr
->dest
.saturate
;
776 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
777 inst
->saturate
= instr
->dest
.saturate
;
781 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
782 inst
->saturate
= instr
->dest
.saturate
;
786 if (fs_key
->high_quality_derivatives
) {
787 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
789 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
791 inst
->saturate
= instr
->dest
.saturate
;
793 case nir_op_fddx_fine
:
794 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
795 inst
->saturate
= instr
->dest
.saturate
;
797 case nir_op_fddx_coarse
:
798 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
799 inst
->saturate
= instr
->dest
.saturate
;
802 if (fs_key
->high_quality_derivatives
) {
803 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
804 brw_imm_d(fs_key
->render_to_fbo
));
806 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
807 brw_imm_d(fs_key
->render_to_fbo
));
809 inst
->saturate
= instr
->dest
.saturate
;
811 case nir_op_fddy_fine
:
812 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
813 brw_imm_d(fs_key
->render_to_fbo
));
814 inst
->saturate
= instr
->dest
.saturate
;
816 case nir_op_fddy_coarse
:
817 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
818 brw_imm_d(fs_key
->render_to_fbo
));
819 inst
->saturate
= instr
->dest
.saturate
;
824 inst
= bld
.ADD(result
, op
[0], op
[1]);
825 inst
->saturate
= instr
->dest
.saturate
;
829 inst
= bld
.MUL(result
, op
[0], op
[1]);
830 inst
->saturate
= instr
->dest
.saturate
;
834 bld
.MUL(result
, op
[0], op
[1]);
837 case nir_op_imul_high
:
838 case nir_op_umul_high
:
839 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
844 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
847 case nir_op_uadd_carry
:
848 unreachable("Should have been lowered by carry_to_arith().");
850 case nir_op_usub_borrow
:
851 unreachable("Should have been lowered by borrow_to_arith().");
855 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
856 * appears that our hardware just does the right thing for signed
859 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
863 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
864 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
866 /* Math instructions don't support conditional mod */
867 inst
= bld
.MOV(bld
.null_reg_d(), result
);
868 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
870 /* Now, we need to determine if signs of the sources are different.
871 * When we XOR the sources, the top bit is 0 if they are the same and 1
872 * if they are different. We can then use a conditional modifier to
873 * turn that into a predicate. This leads us to an XOR.l instruction.
875 * Technically, according to the PRM, you're not allowed to use .l on a
876 * XOR instruction. However, emperical experiments and Curro's reading
877 * of the simulator source both indicate that it's safe.
879 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
880 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
881 inst
->predicate
= BRW_PREDICATE_NORMAL
;
882 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
884 /* If the result of the initial remainder operation is non-zero and the
885 * two sources have different signs, add in a copy of op[1] to get the
886 * final integer modulus value.
888 inst
= bld
.ADD(result
, result
, op
[1]);
889 inst
->predicate
= BRW_PREDICATE_NORMAL
;
896 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
902 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
907 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
912 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
916 if (devinfo
->gen
>= 8) {
917 op
[0] = resolve_source_modifiers(op
[0]);
919 bld
.NOT(result
, op
[0]);
922 if (devinfo
->gen
>= 8) {
923 op
[0] = resolve_source_modifiers(op
[0]);
924 op
[1] = resolve_source_modifiers(op
[1]);
926 bld
.XOR(result
, op
[0], op
[1]);
929 if (devinfo
->gen
>= 8) {
930 op
[0] = resolve_source_modifiers(op
[0]);
931 op
[1] = resolve_source_modifiers(op
[1]);
933 bld
.OR(result
, op
[0], op
[1]);
936 if (devinfo
->gen
>= 8) {
937 op
[0] = resolve_source_modifiers(op
[0]);
938 op
[1] = resolve_source_modifiers(op
[1]);
940 bld
.AND(result
, op
[0], op
[1]);
946 case nir_op_ball_fequal2
:
947 case nir_op_ball_iequal2
:
948 case nir_op_ball_fequal3
:
949 case nir_op_ball_iequal3
:
950 case nir_op_ball_fequal4
:
951 case nir_op_ball_iequal4
:
952 case nir_op_bany_fnequal2
:
953 case nir_op_bany_inequal2
:
954 case nir_op_bany_fnequal3
:
955 case nir_op_bany_inequal3
:
956 case nir_op_bany_fnequal4
:
957 case nir_op_bany_inequal4
:
958 unreachable("Lowered by nir_lower_alu_reductions");
960 case nir_op_fnoise1_1
:
961 case nir_op_fnoise1_2
:
962 case nir_op_fnoise1_3
:
963 case nir_op_fnoise1_4
:
964 case nir_op_fnoise2_1
:
965 case nir_op_fnoise2_2
:
966 case nir_op_fnoise2_3
:
967 case nir_op_fnoise2_4
:
968 case nir_op_fnoise3_1
:
969 case nir_op_fnoise3_2
:
970 case nir_op_fnoise3_3
:
971 case nir_op_fnoise3_4
:
972 case nir_op_fnoise4_1
:
973 case nir_op_fnoise4_2
:
974 case nir_op_fnoise4_3
:
975 case nir_op_fnoise4_4
:
976 unreachable("not reached: should be handled by lower_noise");
979 unreachable("not reached: should be handled by ldexp_to_arith()");
982 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
983 inst
->saturate
= instr
->dest
.saturate
;
987 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
988 inst
->saturate
= instr
->dest
.saturate
;
993 bld
.MOV(result
, negate(op
[0]));
997 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1000 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1004 inst
= bld
.RNDZ(result
, op
[0]);
1005 inst
->saturate
= instr
->dest
.saturate
;
1008 case nir_op_fceil
: {
1009 op
[0].negate
= !op
[0].negate
;
1010 fs_reg temp
= vgrf(glsl_type::float_type
);
1011 bld
.RNDD(temp
, op
[0]);
1013 inst
= bld
.MOV(result
, temp
);
1014 inst
->saturate
= instr
->dest
.saturate
;
1018 inst
= bld
.RNDD(result
, op
[0]);
1019 inst
->saturate
= instr
->dest
.saturate
;
1022 inst
= bld
.FRC(result
, op
[0]);
1023 inst
->saturate
= instr
->dest
.saturate
;
1025 case nir_op_fround_even
:
1026 inst
= bld
.RNDE(result
, op
[0]);
1027 inst
->saturate
= instr
->dest
.saturate
;
1030 case nir_op_fquantize2f16
: {
1031 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1032 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1033 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1035 /* The destination stride must be at least as big as the source stride. */
1036 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1039 /* Check for denormal */
1040 fs_reg abs_src0
= op
[0];
1041 abs_src0
.abs
= true;
1042 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1044 /* Get the appropriately signed zero */
1045 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1046 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1047 brw_imm_ud(0x80000000));
1048 /* Do the actual F32 -> F16 -> F32 conversion */
1049 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1050 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1051 /* Select that or zero based on normal status */
1052 inst
= bld
.SEL(result
, zero
, tmp32
);
1053 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1054 inst
->saturate
= instr
->dest
.saturate
;
1061 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1062 inst
->saturate
= instr
->dest
.saturate
;
1068 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1069 inst
->saturate
= instr
->dest
.saturate
;
1072 case nir_op_pack_snorm_2x16
:
1073 case nir_op_pack_snorm_4x8
:
1074 case nir_op_pack_unorm_2x16
:
1075 case nir_op_pack_unorm_4x8
:
1076 case nir_op_unpack_snorm_2x16
:
1077 case nir_op_unpack_snorm_4x8
:
1078 case nir_op_unpack_unorm_2x16
:
1079 case nir_op_unpack_unorm_4x8
:
1080 case nir_op_unpack_half_2x16
:
1081 case nir_op_pack_half_2x16
:
1082 unreachable("not reached: should be handled by lower_packing_builtins");
1084 case nir_op_unpack_half_2x16_split_x
:
1085 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1086 inst
->saturate
= instr
->dest
.saturate
;
1088 case nir_op_unpack_half_2x16_split_y
:
1089 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1090 inst
->saturate
= instr
->dest
.saturate
;
1094 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1095 inst
->saturate
= instr
->dest
.saturate
;
1098 case nir_op_bitfield_reverse
:
1099 bld
.BFREV(result
, op
[0]);
1102 case nir_op_bit_count
:
1103 bld
.CBIT(result
, op
[0]);
1106 case nir_op_ufind_msb
:
1107 case nir_op_ifind_msb
: {
1108 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1110 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1111 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1112 * subtract the result from 31 to convert the MSB count into an LSB count.
1114 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1116 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1117 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1118 inst
->src
[0].negate
= true;
1122 case nir_op_find_lsb
:
1123 bld
.FBL(result
, op
[0]);
1126 case nir_op_ubitfield_extract
:
1127 case nir_op_ibitfield_extract
:
1128 unreachable("should have been lowered");
1131 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1134 bld
.BFI1(result
, op
[0], op
[1]);
1137 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1140 case nir_op_bitfield_insert
:
1141 unreachable("not reached: should have been lowered");
1144 bld
.SHL(result
, op
[0], op
[1]);
1147 bld
.ASR(result
, op
[0], op
[1]);
1150 bld
.SHR(result
, op
[0], op
[1]);
1153 case nir_op_pack_half_2x16_split
:
1154 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1158 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1159 inst
->saturate
= instr
->dest
.saturate
;
1163 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1164 inst
->saturate
= instr
->dest
.saturate
;
1168 if (optimize_frontfacing_ternary(instr
, result
))
1171 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1172 inst
= bld
.SEL(result
, op
[1], op
[2]);
1173 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1176 case nir_op_extract_u8
:
1177 case nir_op_extract_i8
: {
1178 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1179 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1180 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1184 case nir_op_extract_u16
:
1185 case nir_op_extract_i16
: {
1186 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1187 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1188 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1193 unreachable("unhandled instruction");
1196 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1197 * to sign extend the low bit to 0/~0
1199 if (devinfo
->gen
<= 5 &&
1200 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1201 fs_reg masked
= vgrf(glsl_type::int_type
);
1202 bld
.AND(masked
, result
, brw_imm_d(1));
1203 masked
.negate
= true;
1204 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1209 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1210 nir_load_const_instr
*instr
)
1212 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1214 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1215 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1217 nir_ssa_values
[instr
->def
.index
] = reg
;
1221 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1223 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1224 instr
->def
.num_components
);
1228 fs_visitor::get_nir_src(nir_src src
)
1232 reg
= nir_ssa_values
[src
.ssa
->index
];
1234 /* We don't handle indirects on locals */
1235 assert(src
.reg
.indirect
== NULL
);
1236 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1237 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1240 /* to avoid floating-point denorm flushing problems, set the type by
1241 * default to D - instructions that need floating point semantics will set
1242 * this to F if they need to
1244 return retype(reg
, BRW_REGISTER_TYPE_D
);
1248 fs_visitor::get_nir_dest(nir_dest dest
)
1251 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1252 dest
.ssa
.num_components
);
1253 return nir_ssa_values
[dest
.ssa
.index
];
1255 /* We don't handle indirects on locals */
1256 assert(dest
.reg
.indirect
== NULL
);
1257 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1258 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1263 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1265 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1266 BRW_REGISTER_TYPE_UD
);
1268 unsigned indirect_max
= 0;
1270 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1271 tail
= tail
->child
) {
1272 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1273 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1274 const unsigned size
= glsl_get_length(tail
->type
);
1275 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1276 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1277 image
= offset(image
, bld
, base
* element_size
);
1279 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1280 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1282 /* Accessing an invalid surface index with the dataport can result
1283 * in a hang. According to the spec "if the index used to
1284 * select an individual element is negative or greater than or
1285 * equal to the size of the array, the results of the operation
1286 * are undefined but may not lead to termination" -- which is one
1287 * of the possible outcomes of the hang. Clamp the index to
1288 * prevent access outside of the array bounds.
1290 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1291 BRW_REGISTER_TYPE_UD
),
1292 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1294 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1296 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1297 if (indirect
.file
== BAD_FILE
) {
1300 bld
.ADD(indirect
, indirect
, tmp
);
1305 if (indirect
.file
== BAD_FILE
) {
1308 /* Emit a pile of MOVs to load the uniform into a temporary. The
1309 * dead-code elimination pass will get rid of what we don't use.
1311 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1312 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1313 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1314 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1315 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1322 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1325 for (unsigned i
= 0; i
< 4; i
++) {
1326 if (!((wr_mask
>> i
) & 1))
1329 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1330 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1331 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1332 if (new_inst
->src
[j
].file
== VGRF
)
1333 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1340 * Get the matching channel register datatype for an image intrinsic of the
1341 * specified GLSL image type.
1344 get_image_base_type(const glsl_type
*type
)
1346 switch ((glsl_base_type
)type
->sampled_type
) {
1347 case GLSL_TYPE_UINT
:
1348 return BRW_REGISTER_TYPE_UD
;
1350 return BRW_REGISTER_TYPE_D
;
1351 case GLSL_TYPE_FLOAT
:
1352 return BRW_REGISTER_TYPE_F
;
1354 unreachable("Not reached.");
1359 * Get the appropriate atomic op for an image atomic intrinsic.
1362 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1365 case nir_intrinsic_image_atomic_add
:
1367 case nir_intrinsic_image_atomic_min
:
1368 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1369 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1370 case nir_intrinsic_image_atomic_max
:
1371 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1372 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1373 case nir_intrinsic_image_atomic_and
:
1375 case nir_intrinsic_image_atomic_or
:
1377 case nir_intrinsic_image_atomic_xor
:
1379 case nir_intrinsic_image_atomic_exchange
:
1381 case nir_intrinsic_image_atomic_comp_swap
:
1382 return BRW_AOP_CMPWR
;
1384 unreachable("Not reachable.");
1389 emit_pixel_interpolater_send(const fs_builder
&bld
,
1394 glsl_interp_qualifier interpolation
)
1400 if (src
.file
== BAD_FILE
) {
1402 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1406 mlen
= 2 * bld
.dispatch_width() / 8;
1409 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1411 /* 2 floats per slot returned */
1412 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1413 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1419 * Computes 1 << x, given a D/UD register containing some value x.
1422 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1424 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1426 fs_reg result
= bld
.vgrf(x
.type
, 1);
1427 fs_reg one
= bld
.vgrf(x
.type
, 1);
1429 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1430 bld
.SHL(result
, one
, x
);
1435 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1437 assert(stage
== MESA_SHADER_GEOMETRY
);
1439 struct brw_gs_prog_data
*gs_prog_data
=
1440 (struct brw_gs_prog_data
*) prog_data
;
1442 /* We can only do EndPrimitive() functionality when the control data
1443 * consists of cut bits. Fortunately, the only time it isn't is when the
1444 * output type is points, in which case EndPrimitive() is a no-op.
1446 if (gs_prog_data
->control_data_format
!=
1447 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1451 /* Cut bits use one bit per vertex. */
1452 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1454 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1455 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1457 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1458 * vertex n, 0 otherwise. So all we need to do here is mark bit
1459 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1460 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1461 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1463 * Note that if EndPrimitive() is called before emitting any vertices, this
1464 * will cause us to set bit 31 of the control_data_bits register to 1.
1465 * That's fine because:
1467 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1468 * output, so the hardware will ignore cut bit 31.
1470 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1471 * last vertex, so setting cut bit 31 has no effect (since the primitive
1472 * is automatically ended when the GS terminates).
1474 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1475 * control_data_bits register to 0 when the first vertex is emitted.
1478 const fs_builder abld
= bld
.annotate("end primitive");
1480 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1481 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1482 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1483 fs_reg mask
= intexp2(abld
, prev_count
);
1484 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1485 * attention to the lower 5 bits of its second source argument, so on this
1486 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1487 * ((vertex_count - 1) % 32).
1489 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1493 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1495 assert(stage
== MESA_SHADER_GEOMETRY
);
1496 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1498 struct brw_gs_prog_data
*gs_prog_data
=
1499 (struct brw_gs_prog_data
*) prog_data
;
1501 const fs_builder abld
= bld
.annotate("emit control data bits");
1502 const fs_builder fwa_bld
= bld
.exec_all();
1504 /* We use a single UD register to accumulate control data bits (32 bits
1505 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1508 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1509 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1510 * use the Channel Mask phase to enable/disable which DWord within that
1511 * group to write. (Remember, different SIMD8 channels may have emitted
1512 * different numbers of vertices, so we may need per-slot offsets.)
1514 * Channel masking presents an annoying problem: we may have to replicate
1515 * the data up to 4 times:
1517 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1519 * To avoid penalizing shaders that emit a small number of vertices, we
1520 * can avoid these sometimes: if the size of the control data header is
1521 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1522 * land in the same 128-bit group, so we can skip per-slot offsets.
1524 * Similarly, if the control data header is <= 32 bits, there is only one
1525 * DWord, so we can skip channel masks.
1527 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1529 fs_reg channel_mask
, per_slot_offset
;
1531 if (gs_compile
->control_data_header_size_bits
> 32) {
1532 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1533 channel_mask
= vgrf(glsl_type::uint_type
);
1536 if (gs_compile
->control_data_header_size_bits
> 128) {
1537 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1538 per_slot_offset
= vgrf(glsl_type::uint_type
);
1541 /* Figure out which DWord we're trying to write to using the formula:
1543 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1545 * Since bits_per_vertex is a power of two, and is known at compile
1546 * time, this can be optimized to:
1548 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1550 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1551 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1552 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1553 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1554 unsigned log2_bits_per_vertex
=
1555 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1556 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1558 if (per_slot_offset
.file
!= BAD_FILE
) {
1559 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1560 * the appropriate OWord within the control data header.
1562 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1565 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1566 * write to the appropriate DWORD within the OWORD.
1568 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1569 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1570 channel_mask
= intexp2(fwa_bld
, channel
);
1571 /* Then the channel masks need to be in bits 23:16. */
1572 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1575 /* Store the control data bits in the message payload and send it. */
1577 if (channel_mask
.file
!= BAD_FILE
)
1578 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1579 if (per_slot_offset
.file
!= BAD_FILE
)
1582 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1583 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1585 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1586 if (per_slot_offset
.file
!= BAD_FILE
)
1587 sources
[i
++] = per_slot_offset
;
1588 if (channel_mask
.file
!= BAD_FILE
)
1589 sources
[i
++] = channel_mask
;
1591 sources
[i
++] = this->control_data_bits
;
1594 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1595 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1597 /* We need to increment Global Offset by 256-bits to make room for
1598 * Broadwell's extra "Vertex Count" payload at the beginning of the
1599 * URB entry. Since this is an OWord message, Global Offset is counted
1600 * in 128-bit units, so we must set it to 2.
1602 if (gs_prog_data
->static_vertex_count
== -1)
1607 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1610 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1612 /* Note: we are calling this *before* increasing vertex_count, so
1613 * this->vertex_count == vertex_count - 1 in the formula above.
1616 /* Stream mode uses 2 bits per vertex */
1617 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1619 /* Must be a valid stream */
1620 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1622 /* Control data bits are initialized to 0 so we don't have to set any
1623 * bits when sending vertices to stream 0.
1628 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1630 /* reg::sid = stream_id */
1631 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1632 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1634 /* reg:shift_count = 2 * (vertex_count - 1) */
1635 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1636 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1638 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1639 * attention to the lower 5 bits of its second source argument, so on this
1640 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1641 * stream_id << ((2 * (vertex_count - 1)) % 32).
1643 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1644 abld
.SHL(mask
, sid
, shift_count
);
1645 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1649 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1652 assert(stage
== MESA_SHADER_GEOMETRY
);
1654 struct brw_gs_prog_data
*gs_prog_data
=
1655 (struct brw_gs_prog_data
*) prog_data
;
1657 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1658 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1660 /* Haswell and later hardware ignores the "Render Stream Select" bits
1661 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1662 * and instead sends all primitives down the pipeline for rasterization.
1663 * If the SOL stage is enabled, "Render Stream Select" is honored and
1664 * primitives bound to non-zero streams are discarded after stream output.
1666 * Since the only purpose of primives sent to non-zero streams is to
1667 * be recorded by transform feedback, we can simply discard all geometry
1668 * bound to these streams when transform feedback is disabled.
1670 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1673 /* If we're outputting 32 control data bits or less, then we can wait
1674 * until the shader is over to output them all. Otherwise we need to
1675 * output them as we go. Now is the time to do it, since we're about to
1676 * output the vertex_count'th vertex, so it's guaranteed that the
1677 * control data bits associated with the (vertex_count - 1)th vertex are
1680 if (gs_compile
->control_data_header_size_bits
> 32) {
1681 const fs_builder abld
=
1682 bld
.annotate("emit vertex: emit control data bits");
1684 /* Only emit control data bits if we've finished accumulating a batch
1685 * of 32 bits. This is the case when:
1687 * (vertex_count * bits_per_vertex) % 32 == 0
1689 * (in other words, when the last 5 bits of vertex_count *
1690 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1691 * integer n (which is always the case, since bits_per_vertex is
1692 * always 1 or 2), this is equivalent to requiring that the last 5-n
1693 * bits of vertex_count are 0:
1695 * vertex_count & (2^(5-n) - 1) == 0
1697 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1700 * vertex_count & (32 / bits_per_vertex - 1) == 0
1702 * TODO: If vertex_count is an immediate, we could do some of this math
1703 * at compile time...
1706 abld
.AND(bld
.null_reg_d(), vertex_count
,
1707 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1708 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1710 abld
.IF(BRW_PREDICATE_NORMAL
);
1711 /* If vertex_count is 0, then no control data bits have been
1712 * accumulated yet, so we can skip emitting them.
1714 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1715 BRW_CONDITIONAL_NEQ
);
1716 abld
.IF(BRW_PREDICATE_NORMAL
);
1717 emit_gs_control_data_bits(vertex_count
);
1718 abld
.emit(BRW_OPCODE_ENDIF
);
1720 /* Reset control_data_bits to 0 so we can start accumulating a new
1723 * Note: in the case where vertex_count == 0, this neutralizes the
1724 * effect of any call to EndPrimitive() that the shader may have
1725 * made before outputting its first vertex.
1727 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1728 inst
->force_writemask_all
= true;
1729 abld
.emit(BRW_OPCODE_ENDIF
);
1732 emit_urb_writes(vertex_count
);
1734 /* In stream mode we have to set control data bits for all vertices
1735 * unless we have disabled control data bits completely (which we do
1736 * do for GL_POINTS outputs that don't use streams).
1738 if (gs_compile
->control_data_header_size_bits
> 0 &&
1739 gs_prog_data
->control_data_format
==
1740 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1741 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1746 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1747 const nir_src
&vertex_src
,
1748 unsigned base_offset
,
1749 const nir_src
&offset_src
,
1750 unsigned num_components
)
1752 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1754 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1755 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1756 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1758 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1759 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1760 * gl_PointSize is available as a GS input, however, so it must be that.
1762 const bool is_point_size
= (base_offset
== 0);
1764 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1765 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1766 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1767 vertex_const
->u32
[0] * push_reg_count
;
1768 /* This input was pushed into registers. */
1769 if (is_point_size
) {
1770 /* gl_PointSize comes in .w */
1771 assert(imm_offset
== 0);
1772 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1774 for (unsigned i
= 0; i
< num_components
; i
++) {
1775 bld
.MOV(offset(dst
, bld
, i
),
1776 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1780 /* Resort to the pull model. Ensure the VUE handles are provided. */
1781 gs_prog_data
->base
.include_vue_handles
= true;
1783 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1787 /* The vertex index is constant; just select the proper URB handle. */
1789 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1790 BRW_REGISTER_TYPE_UD
);
1792 /* The vertex index is non-constant. We need to use indirect
1793 * addressing to fetch the proper URB handle.
1795 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1796 * indicating that channel <n> should read the handle from
1797 * DWord <n>. We convert that to bytes by multiplying by 4.
1799 * Next, we convert the vertex index to bytes by multiplying
1800 * by 32 (shifting by 5), and add the two together. This is
1801 * the final indirect byte offset.
1803 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1804 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1805 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1806 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1807 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1809 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1810 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1811 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1812 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1813 /* Convert vertex_index to bytes (multiply by 32) */
1814 bld
.SHL(vertex_offset_bytes
,
1815 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1817 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1819 /* Use first_icp_handle as the base offset. There is one register
1820 * of URB handles per vertex, so inform the register allocator that
1821 * we might read up to nir->info.gs.vertices_in registers.
1823 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1824 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1825 fs_reg(icp_offset_bytes
),
1826 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1831 /* Constant indexing - use global offset. */
1832 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1833 inst
->offset
= base_offset
+ offset_const
->u32
[0];
1834 inst
->base_mrf
= -1;
1836 inst
->regs_written
= num_components
;
1838 /* Indirect indexing - use per-slot offsets as well. */
1839 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1840 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1841 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1843 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1844 inst
->offset
= base_offset
;
1845 inst
->base_mrf
= -1;
1847 inst
->regs_written
= num_components
;
1850 if (is_point_size
) {
1851 /* Read the whole VUE header (because of alignment) and read .w. */
1852 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1854 inst
->regs_written
= 4;
1855 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1861 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1863 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1864 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1867 /* The only constant offset we should find is 0. brw_nir.c's
1868 * add_const_offset_to_base() will fold other constant offsets
1869 * into instr->const_index[0].
1871 assert(const_value
->u32
[0] == 0);
1875 return get_nir_src(*offset_src
);
1879 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1880 nir_intrinsic_instr
*instr
)
1882 assert(stage
== MESA_SHADER_VERTEX
);
1885 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1886 dest
= get_nir_dest(instr
->dest
);
1888 switch (instr
->intrinsic
) {
1889 case nir_intrinsic_load_vertex_id
:
1890 unreachable("should be lowered by lower_vertex_id()");
1892 case nir_intrinsic_load_vertex_id_zero_base
:
1893 case nir_intrinsic_load_base_vertex
:
1894 case nir_intrinsic_load_instance_id
:
1895 case nir_intrinsic_load_base_instance
:
1896 case nir_intrinsic_load_draw_id
: {
1897 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1898 fs_reg val
= nir_system_values
[sv
];
1899 assert(val
.file
!= BAD_FILE
);
1900 dest
.type
= val
.type
;
1906 nir_emit_intrinsic(bld
, instr
);
1912 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
1913 nir_intrinsic_instr
*instr
)
1915 assert(stage
== MESA_SHADER_TESS_CTRL
);
1916 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
1917 struct brw_tcs_prog_data
*tcs_prog_data
=
1918 (struct brw_tcs_prog_data
*) prog_data
;
1921 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1922 dst
= get_nir_dest(instr
->dest
);
1924 switch (instr
->intrinsic
) {
1925 case nir_intrinsic_load_primitive_id
:
1926 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
1928 case nir_intrinsic_load_invocation_id
:
1929 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
1931 case nir_intrinsic_load_patch_vertices_in
:
1932 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
1933 brw_imm_d(tcs_key
->input_vertices
));
1936 case nir_intrinsic_barrier
: {
1937 if (tcs_prog_data
->instances
== 1)
1940 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1941 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
1943 const fs_builder fwa_bld
= bld
.exec_all();
1945 /* Zero the message header */
1946 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
1948 /* Copy "Barrier ID" from r0.2, bits 16:13 */
1949 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
1950 brw_imm_ud(INTEL_MASK(16, 13)));
1952 /* Shift it up to bits 27:24. */
1953 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
1955 /* Set the Barrier Count and the enable bit */
1956 fwa_bld
.OR(m0_2
, m0_2
,
1957 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
1959 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
1963 case nir_intrinsic_load_input
:
1964 unreachable("nir_lower_io should never give us these.");
1967 case nir_intrinsic_load_per_vertex_input
: {
1968 fs_reg indirect_offset
= get_indirect_offset(instr
);
1969 unsigned imm_offset
= instr
->const_index
[0];
1971 const nir_src
&vertex_src
= instr
->src
[0];
1972 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1979 /* Emit a MOV to resolve <0,1,0> regioning. */
1980 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1982 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
1983 vertex_const
->i32
[0] & 7),
1984 BRW_REGISTER_TYPE_UD
));
1985 } else if (tcs_prog_data
->instances
== 1 &&
1986 vertex_src
.is_ssa
&&
1987 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
1988 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
1989 /* For the common case of only 1 instance, an array index of
1990 * gl_InvocationID means reading g1. Skip all the indirect work.
1992 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
1994 /* The vertex index is non-constant. We need to use indirect
1995 * addressing to fetch the proper URB handle.
1997 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1999 /* Each ICP handle is a single DWord (4 bytes) */
2000 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2001 bld
.SHL(vertex_offset_bytes
,
2002 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2005 /* Start at g1. We might read up to 4 registers. */
2006 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2007 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2008 brw_imm_ud(4 * REG_SIZE
));
2011 if (indirect_offset
.file
== BAD_FILE
) {
2012 /* Constant indexing - use global offset. */
2013 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2014 inst
->offset
= imm_offset
;
2016 inst
->base_mrf
= -1;
2017 inst
->regs_written
= instr
->num_components
;
2019 /* Indirect indexing - use per-slot offsets as well. */
2020 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2021 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2022 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2024 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2025 inst
->offset
= imm_offset
;
2026 inst
->base_mrf
= -1;
2028 inst
->regs_written
= instr
->num_components
;
2031 /* Copy the temporary to the destination to deal with writemasking.
2033 * Also attempt to deal with gl_PointSize being in the .w component.
2035 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2036 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2037 inst
->regs_written
= 4;
2038 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2043 case nir_intrinsic_load_output
:
2044 case nir_intrinsic_load_per_vertex_output
: {
2045 fs_reg indirect_offset
= get_indirect_offset(instr
);
2046 unsigned imm_offset
= instr
->const_index
[0];
2049 if (indirect_offset
.file
== BAD_FILE
) {
2050 /* Replicate the patch handle to all enabled channels */
2051 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2052 bld
.MOV(patch_handle
,
2053 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2055 if (imm_offset
== 0) {
2056 /* This is a read of gl_TessLevelInner[], which lives in the
2057 * Patch URB header. The layout depends on the domain.
2059 dst
.type
= BRW_REGISTER_TYPE_F
;
2060 switch (tcs_key
->tes_primitive_mode
) {
2062 /* DWords 3-2 (reversed) */
2063 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2065 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2068 inst
->base_mrf
= -1;
2069 inst
->regs_written
= 4;
2071 /* dst.xy = tmp.wz */
2072 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2073 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2077 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2078 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2081 inst
->base_mrf
= -1;
2082 inst
->regs_written
= 1;
2085 /* All channels are undefined. */
2088 unreachable("Bogus tessellation domain");
2090 } else if (imm_offset
== 1) {
2091 /* This is a read of gl_TessLevelOuter[], which lives in the
2092 * Patch URB header. The layout depends on the domain.
2094 dst
.type
= BRW_REGISTER_TYPE_F
;
2096 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2097 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2100 inst
->base_mrf
= -1;
2101 inst
->regs_written
= 4;
2103 /* Reswizzle: WZYX */
2105 offset(tmp
, bld
, 3),
2106 offset(tmp
, bld
, 2),
2107 offset(tmp
, bld
, 1),
2108 offset(tmp
, bld
, 0),
2111 unsigned num_components
;
2112 switch (tcs_key
->tes_primitive_mode
) {
2120 /* Isolines are not reversed; swizzle .zw -> .xy */
2121 srcs
[0] = offset(tmp
, bld
, 2);
2122 srcs
[1] = offset(tmp
, bld
, 3);
2126 unreachable("Bogus tessellation domain");
2128 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2130 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2131 inst
->offset
= imm_offset
;
2133 inst
->base_mrf
= -1;
2134 inst
->regs_written
= instr
->num_components
;
2137 /* Indirect indexing - use per-slot offsets as well. */
2138 const fs_reg srcs
[] = {
2139 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2142 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2143 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2145 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2146 inst
->offset
= imm_offset
;
2148 inst
->base_mrf
= -1;
2149 inst
->regs_written
= instr
->num_components
;
2154 case nir_intrinsic_store_output
:
2155 case nir_intrinsic_store_per_vertex_output
: {
2156 fs_reg value
= get_nir_src(instr
->src
[0]);
2157 fs_reg indirect_offset
= get_indirect_offset(instr
);
2158 unsigned imm_offset
= instr
->const_index
[0];
2159 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2160 unsigned mask
= instr
->const_index
[1];
2161 unsigned header_regs
= 0;
2163 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2165 if (indirect_offset
.file
!= BAD_FILE
) {
2166 srcs
[header_regs
++] = indirect_offset
;
2167 } else if (!is_passthrough_shader
) {
2168 if (imm_offset
== 0) {
2169 value
.type
= BRW_REGISTER_TYPE_F
;
2171 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2173 /* This is a write to gl_TessLevelInner[], which lives in the
2174 * Patch URB header. The layout depends on the domain.
2176 switch (tcs_key
->tes_primitive_mode
) {
2178 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2179 * We use an XXYX swizzle to reverse put .xy in the .wz
2180 * channels, and use a .zw writemask.
2182 mask
= writemask_for_backwards_vector(mask
);
2183 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2186 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2187 * writemask to X and bump the URB offset by 1.
2192 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2195 unreachable("Bogus tessellation domain");
2197 } else if (imm_offset
== 1) {
2198 /* This is a write to gl_TessLevelOuter[] which lives in the
2199 * Patch URB Header at DWords 4-7. However, it's reversed, so
2200 * instead of .xyzw we have .wzyx.
2202 value
.type
= BRW_REGISTER_TYPE_F
;
2204 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2206 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2207 /* Isolines .xy should be stored in .zw, in order. */
2208 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2211 /* Other domains are reversed; store .wzyx instead of .xyzw */
2212 swiz
= BRW_SWIZZLE_WZYX
;
2213 mask
= writemask_for_backwards_vector(mask
);
2221 unsigned num_components
= _mesa_fls(mask
);
2224 if (mask
!= WRITEMASK_XYZW
) {
2225 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2226 opcode
= indirect_offset
.file
!= BAD_FILE
?
2227 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2228 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2230 opcode
= indirect_offset
.file
!= BAD_FILE
?
2231 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2232 SHADER_OPCODE_URB_WRITE_SIMD8
;
2235 for (unsigned i
= 0; i
< num_components
; i
++) {
2236 if (mask
& (1 << i
))
2237 srcs
[header_regs
+ i
] = offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2240 unsigned mlen
= header_regs
+ num_components
;
2243 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2244 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2246 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2247 inst
->offset
= imm_offset
;
2249 inst
->base_mrf
= -1;
2254 nir_emit_intrinsic(bld
, instr
);
2260 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2261 nir_intrinsic_instr
*instr
)
2263 assert(stage
== MESA_SHADER_TESS_EVAL
);
2264 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2267 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2268 dest
= get_nir_dest(instr
->dest
);
2270 switch (instr
->intrinsic
) {
2271 case nir_intrinsic_load_primitive_id
:
2272 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2274 case nir_intrinsic_load_tess_coord
:
2275 /* gl_TessCoord is part of the payload in g1-3 */
2276 for (unsigned i
= 0; i
< 3; i
++) {
2277 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2281 case nir_intrinsic_load_tess_level_outer
:
2282 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2283 * appears as a push-model input. So, we can simply use the ATTR file
2284 * rather than issuing URB read messages. The data is stored in the
2285 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2288 switch (tes_prog_data
->domain
) {
2289 case BRW_TESS_DOMAIN_QUAD
:
2290 for (unsigned i
= 0; i
< 4; i
++)
2291 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2293 case BRW_TESS_DOMAIN_TRI
:
2294 for (unsigned i
= 0; i
< 3; i
++)
2295 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2297 case BRW_TESS_DOMAIN_ISOLINE
:
2298 for (unsigned i
= 0; i
< 2; i
++)
2299 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2304 case nir_intrinsic_load_tess_level_inner
:
2305 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2306 * appears as a push-model input. So, we can simply use the ATTR file
2307 * rather than issuing URB read messages.
2309 switch (tes_prog_data
->domain
) {
2310 case BRW_TESS_DOMAIN_QUAD
:
2311 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2312 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2314 case BRW_TESS_DOMAIN_TRI
:
2315 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2317 case BRW_TESS_DOMAIN_ISOLINE
:
2318 /* ignore - value is undefined */
2323 case nir_intrinsic_load_input
:
2324 case nir_intrinsic_load_per_vertex_input
: {
2325 fs_reg indirect_offset
= get_indirect_offset(instr
);
2326 unsigned imm_offset
= instr
->const_index
[0];
2329 if (indirect_offset
.file
== BAD_FILE
) {
2330 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2331 * which is 16 registers (since each holds 2 vec4 slots).
2333 const unsigned max_push_slots
= 32;
2334 if (imm_offset
< max_push_slots
) {
2335 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2336 for (int i
= 0; i
< instr
->num_components
; i
++) {
2337 bld
.MOV(offset(dest
, bld
, i
),
2338 component(src
, 4 * (imm_offset
% 2) + i
));
2340 tes_prog_data
->base
.urb_read_length
=
2341 MAX2(tes_prog_data
->base
.urb_read_length
,
2342 DIV_ROUND_UP(imm_offset
+ 1, 2));
2344 /* Replicate the patch handle to all enabled channels */
2345 const fs_reg srcs
[] = {
2346 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2348 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2349 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2351 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2353 inst
->offset
= imm_offset
;
2354 inst
->base_mrf
= -1;
2355 inst
->regs_written
= instr
->num_components
;
2358 /* Indirect indexing - use per-slot offsets as well. */
2359 const fs_reg srcs
[] = {
2360 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2363 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2364 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2366 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2368 inst
->offset
= imm_offset
;
2369 inst
->base_mrf
= -1;
2370 inst
->regs_written
= instr
->num_components
;
2375 nir_emit_intrinsic(bld
, instr
);
2381 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2382 nir_intrinsic_instr
*instr
)
2384 assert(stage
== MESA_SHADER_GEOMETRY
);
2385 fs_reg indirect_offset
;
2388 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2389 dest
= get_nir_dest(instr
->dest
);
2391 switch (instr
->intrinsic
) {
2392 case nir_intrinsic_load_primitive_id
:
2393 assert(stage
== MESA_SHADER_GEOMETRY
);
2394 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2395 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2396 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2399 case nir_intrinsic_load_input
:
2400 unreachable("load_input intrinsics are invalid for the GS stage");
2402 case nir_intrinsic_load_per_vertex_input
:
2403 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2404 instr
->src
[1], instr
->num_components
);
2407 case nir_intrinsic_emit_vertex_with_counter
:
2408 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2411 case nir_intrinsic_end_primitive_with_counter
:
2412 emit_gs_end_primitive(instr
->src
[0]);
2415 case nir_intrinsic_set_vertex_count
:
2416 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2419 case nir_intrinsic_load_invocation_id
: {
2420 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2421 assert(val
.file
!= BAD_FILE
);
2422 dest
.type
= val
.type
;
2428 nir_emit_intrinsic(bld
, instr
);
2434 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2435 nir_intrinsic_instr
*instr
)
2437 assert(stage
== MESA_SHADER_FRAGMENT
);
2438 struct brw_wm_prog_data
*wm_prog_data
=
2439 (struct brw_wm_prog_data
*) prog_data
;
2440 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
2443 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2444 dest
= get_nir_dest(instr
->dest
);
2446 switch (instr
->intrinsic
) {
2447 case nir_intrinsic_load_front_face
:
2448 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2449 *emit_frontfacing_interpolation());
2452 case nir_intrinsic_load_sample_pos
: {
2453 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2454 assert(sample_pos
.file
!= BAD_FILE
);
2455 dest
.type
= sample_pos
.type
;
2456 bld
.MOV(dest
, sample_pos
);
2457 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2461 case nir_intrinsic_load_helper_invocation
:
2462 case nir_intrinsic_load_sample_mask_in
:
2463 case nir_intrinsic_load_sample_id
: {
2464 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2465 fs_reg val
= nir_system_values
[sv
];
2466 assert(val
.file
!= BAD_FILE
);
2467 dest
.type
= val
.type
;
2472 case nir_intrinsic_discard
:
2473 case nir_intrinsic_discard_if
: {
2474 /* We track our discarded pixels in f0.1. By predicating on it, we can
2475 * update just the flag bits that aren't yet discarded. If there's no
2476 * condition, we emit a CMP of g0 != g0, so all currently executing
2477 * channels will get turned off.
2480 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2481 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2482 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2484 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2485 BRW_REGISTER_TYPE_UW
));
2486 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2488 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2489 cmp
->flag_subreg
= 1;
2491 if (devinfo
->gen
>= 6) {
2492 emit_discard_jump();
2497 case nir_intrinsic_interp_var_at_centroid
:
2498 case nir_intrinsic_interp_var_at_sample
:
2499 case nir_intrinsic_interp_var_at_offset
: {
2500 /* Handle ARB_gpu_shader5 interpolation intrinsics
2502 * It's worth a quick word of explanation as to why we handle the full
2503 * variable-based interpolation intrinsic rather than a lowered version
2504 * with like we do for other inputs. We have to do that because the way
2505 * we set up inputs doesn't allow us to use the already setup inputs for
2506 * interpolation. At the beginning of the shader, we go through all of
2507 * the input variables and do the initial interpolation and put it in
2508 * the nir_inputs array based on its location as determined in
2509 * nir_lower_io. If the input isn't used, dead code cleans up and
2510 * everything works fine. However, when we get to the ARB_gpu_shader5
2511 * interpolation intrinsics, we need to reinterpolate the input
2512 * differently. If we used an intrinsic that just had an index it would
2513 * only give us the offset into the nir_inputs array. However, this is
2514 * useless because that value is post-interpolation and we need
2515 * pre-interpolation. In order to get the actual location of the bits
2516 * we get from the vertex fetching hardware, we need the variable.
2518 wm_prog_data
->pulls_bary
= true;
2520 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2521 const glsl_interp_qualifier interpolation
=
2522 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2524 switch (instr
->intrinsic
) {
2525 case nir_intrinsic_interp_var_at_centroid
:
2526 emit_pixel_interpolater_send(bld
,
2527 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2534 case nir_intrinsic_interp_var_at_sample
: {
2535 if (!wm_key
->multisample_fbo
) {
2536 /* From the ARB_gpu_shader5 specification:
2537 * "If multisample buffers are not available, the input varying
2538 * will be evaluated at the center of the pixel."
2540 emit_pixel_interpolater_send(bld
,
2541 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2549 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2552 unsigned msg_data
= const_sample
->i32
[0] << 4;
2554 emit_pixel_interpolater_send(bld
,
2555 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2558 brw_imm_ud(msg_data
),
2561 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2562 BRW_REGISTER_TYPE_UD
);
2564 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2565 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2566 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2567 bld
.exec_all().group(1, 0)
2568 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2569 emit_pixel_interpolater_send(bld
,
2570 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2576 /* Make a loop that sends a message to the pixel interpolater
2577 * for the sample number in each live channel. If there are
2578 * multiple channels with the same sample number then these
2579 * will be handled simultaneously with a single interation of
2582 bld
.emit(BRW_OPCODE_DO
);
2584 /* Get the next live sample number into sample_id_reg */
2585 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2587 /* Set the flag register so that we can perform the send
2588 * message on all channels that have the same sample number
2590 bld
.CMP(bld
.null_reg_ud(),
2591 sample_src
, sample_id
,
2592 BRW_CONDITIONAL_EQ
);
2593 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2594 bld
.exec_all().group(1, 0)
2595 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2597 emit_pixel_interpolater_send(bld
,
2598 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2603 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2605 /* Continue the loop if there are any live channels left */
2606 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2608 bld
.emit(BRW_OPCODE_WHILE
));
2615 case nir_intrinsic_interp_var_at_offset
: {
2616 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2619 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2620 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2622 emit_pixel_interpolater_send(bld
,
2623 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2626 brw_imm_ud(off_x
| (off_y
<< 4)),
2629 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2630 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2631 BRW_REGISTER_TYPE_F
);
2632 for (int i
= 0; i
< 2; i
++) {
2633 fs_reg temp
= vgrf(glsl_type::float_type
);
2634 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2635 fs_reg itemp
= vgrf(glsl_type::int_type
);
2636 bld
.MOV(itemp
, temp
); /* float to int */
2638 /* Clamp the upper end of the range to +7/16.
2639 * ARB_gpu_shader5 requires that we support a maximum offset
2640 * of +0.5, which isn't representable in a S0.4 value -- if
2641 * we didn't clamp it, we'd end up with -8/16, which is the
2642 * opposite of what the shader author wanted.
2644 * This is legal due to ARB_gpu_shader5's quantization
2647 * "Not all values of <offset> may be supported; x and y
2648 * offsets may be rounded to fixed-point values with the
2649 * number of fraction bits given by the
2650 * implementation-dependent constant
2651 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2653 set_condmod(BRW_CONDITIONAL_L
,
2654 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2657 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2658 emit_pixel_interpolater_send(bld
,
2669 unreachable("Invalid intrinsic");
2672 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2673 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2674 src
.type
= dest
.type
;
2676 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2677 dest
= offset(dest
, bld
, 1);
2682 nir_emit_intrinsic(bld
, instr
);
2688 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2689 nir_intrinsic_instr
*instr
)
2691 assert(stage
== MESA_SHADER_COMPUTE
);
2692 struct brw_cs_prog_data
*cs_prog_data
=
2693 (struct brw_cs_prog_data
*) prog_data
;
2696 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2697 dest
= get_nir_dest(instr
->dest
);
2699 switch (instr
->intrinsic
) {
2700 case nir_intrinsic_barrier
:
2702 cs_prog_data
->uses_barrier
= true;
2705 case nir_intrinsic_load_local_invocation_id
:
2706 case nir_intrinsic_load_work_group_id
: {
2707 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2708 fs_reg val
= nir_system_values
[sv
];
2709 assert(val
.file
!= BAD_FILE
);
2710 dest
.type
= val
.type
;
2711 for (unsigned i
= 0; i
< 3; i
++)
2712 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2716 case nir_intrinsic_load_num_work_groups
: {
2717 const unsigned surface
=
2718 cs_prog_data
->binding_table
.work_groups_start
;
2720 cs_prog_data
->uses_num_work_groups
= true;
2722 fs_reg surf_index
= brw_imm_ud(surface
);
2723 brw_mark_surface_used(prog_data
, surface
);
2725 /* Read the 3 GLuint components of gl_NumWorkGroups */
2726 for (unsigned i
= 0; i
< 3; i
++) {
2727 fs_reg read_result
=
2728 emit_untyped_read(bld
, surf_index
,
2730 1 /* dims */, 1 /* size */,
2731 BRW_PREDICATE_NONE
);
2732 read_result
.type
= dest
.type
;
2733 bld
.MOV(dest
, read_result
);
2734 dest
= offset(dest
, bld
, 1);
2739 case nir_intrinsic_shared_atomic_add
:
2740 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2742 case nir_intrinsic_shared_atomic_imin
:
2743 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2745 case nir_intrinsic_shared_atomic_umin
:
2746 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2748 case nir_intrinsic_shared_atomic_imax
:
2749 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2751 case nir_intrinsic_shared_atomic_umax
:
2752 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2754 case nir_intrinsic_shared_atomic_and
:
2755 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2757 case nir_intrinsic_shared_atomic_or
:
2758 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2760 case nir_intrinsic_shared_atomic_xor
:
2761 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2763 case nir_intrinsic_shared_atomic_exchange
:
2764 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2766 case nir_intrinsic_shared_atomic_comp_swap
:
2767 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2770 case nir_intrinsic_load_shared
: {
2771 assert(devinfo
->gen
>= 7);
2773 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2775 /* Get the offset to read from */
2777 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2779 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
2781 offset_reg
= vgrf(glsl_type::uint_type
);
2783 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2784 brw_imm_ud(instr
->const_index
[0]));
2787 /* Read the vector */
2788 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2790 instr
->num_components
,
2791 BRW_PREDICATE_NONE
);
2792 read_result
.type
= dest
.type
;
2793 for (int i
= 0; i
< instr
->num_components
; i
++)
2794 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2799 case nir_intrinsic_store_shared
: {
2800 assert(devinfo
->gen
>= 7);
2803 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2806 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2809 unsigned writemask
= instr
->const_index
[1];
2811 /* Combine groups of consecutive enabled channels in one write
2812 * message. We use ffs to find the first enabled channel and then ffs on
2813 * the bit-inverse, down-shifted writemask to determine the length of
2814 * the block of enabled bits.
2817 unsigned first_component
= ffs(writemask
) - 1;
2818 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2821 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2823 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
2824 4 * first_component
);
2826 offset_reg
= vgrf(glsl_type::uint_type
);
2828 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2829 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2832 emit_untyped_write(bld
, surf_index
, offset_reg
,
2833 offset(val_reg
, bld
, first_component
),
2834 1 /* dims */, length
,
2835 BRW_PREDICATE_NONE
);
2837 /* Clear the bits in the writemask that we just wrote, then try
2838 * again to see if more channels are left.
2840 writemask
&= (15 << (first_component
+ length
));
2847 nir_emit_intrinsic(bld
, instr
);
2853 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2856 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2857 dest
= get_nir_dest(instr
->dest
);
2859 switch (instr
->intrinsic
) {
2860 case nir_intrinsic_atomic_counter_inc
:
2861 case nir_intrinsic_atomic_counter_dec
:
2862 case nir_intrinsic_atomic_counter_read
: {
2863 /* Get the arguments of the atomic intrinsic. */
2864 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2865 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2866 instr
->const_index
[0]);
2869 /* Emit a surface read or atomic op. */
2870 switch (instr
->intrinsic
) {
2871 case nir_intrinsic_atomic_counter_read
:
2872 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2875 case nir_intrinsic_atomic_counter_inc
:
2876 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2877 fs_reg(), 1, 1, BRW_AOP_INC
);
2880 case nir_intrinsic_atomic_counter_dec
:
2881 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2882 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2886 unreachable("Unreachable");
2889 /* Assign the result. */
2890 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2892 /* Mark the surface as used. */
2893 brw_mark_surface_used(stage_prog_data
, surface
);
2897 case nir_intrinsic_image_load
:
2898 case nir_intrinsic_image_store
:
2899 case nir_intrinsic_image_atomic_add
:
2900 case nir_intrinsic_image_atomic_min
:
2901 case nir_intrinsic_image_atomic_max
:
2902 case nir_intrinsic_image_atomic_and
:
2903 case nir_intrinsic_image_atomic_or
:
2904 case nir_intrinsic_image_atomic_xor
:
2905 case nir_intrinsic_image_atomic_exchange
:
2906 case nir_intrinsic_image_atomic_comp_swap
: {
2907 using namespace image_access
;
2909 /* Get the referenced image variable and type. */
2910 const nir_variable
*var
= instr
->variables
[0]->var
;
2911 const glsl_type
*type
= var
->type
->without_array();
2912 const brw_reg_type base_type
= get_image_base_type(type
);
2914 /* Get some metadata from the image intrinsic. */
2915 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2916 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2917 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2918 const unsigned format
= var
->data
.image
.format
;
2920 /* Get the arguments of the image intrinsic. */
2921 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2922 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2923 BRW_REGISTER_TYPE_UD
);
2924 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2925 retype(get_nir_src(instr
->src
[2]), base_type
) :
2927 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2928 retype(get_nir_src(instr
->src
[3]), base_type
) :
2932 /* Emit an image load, store or atomic op. */
2933 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2934 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2936 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2937 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
2938 var
->data
.image
.write_only
? GL_NONE
: format
);
2941 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2942 surf_dims
, arr_dims
, info
->dest_components
,
2943 get_image_atomic_op(instr
->intrinsic
, type
));
2945 /* Assign the result. */
2946 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2947 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2948 offset(tmp
, bld
, c
));
2952 case nir_intrinsic_memory_barrier_atomic_counter
:
2953 case nir_intrinsic_memory_barrier_buffer
:
2954 case nir_intrinsic_memory_barrier_image
:
2955 case nir_intrinsic_memory_barrier
: {
2956 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2957 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2962 case nir_intrinsic_group_memory_barrier
:
2963 case nir_intrinsic_memory_barrier_shared
:
2964 /* We treat these workgroup-level barriers as no-ops. This should be
2965 * safe at present and as long as:
2967 * - Memory access instructions are not subsequently reordered by the
2968 * compiler back-end.
2970 * - All threads from a given compute shader workgroup fit within a
2971 * single subslice and therefore talk to the same HDC shared unit
2972 * what supposedly guarantees ordering and coherency between threads
2973 * from the same workgroup. This may change in the future when we
2974 * start splitting workgroups across multiple subslices.
2976 * - The context is not in fault-and-stream mode, which could cause
2977 * memory transactions (including to SLM) prior to the barrier to be
2978 * replayed after the barrier if a pagefault occurs. This shouldn't
2979 * be a problem up to and including SKL because fault-and-stream is
2980 * not usable due to hardware issues, but that's likely to change in
2985 case nir_intrinsic_shader_clock
: {
2986 /* We cannot do anything if there is an event, so ignore it for now */
2987 fs_reg shader_clock
= get_timestamp(bld
);
2988 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2990 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2994 case nir_intrinsic_image_size
: {
2995 /* Get the referenced image variable and type. */
2996 const nir_variable
*var
= instr
->variables
[0]->var
;
2997 const glsl_type
*type
= var
->type
->without_array();
2999 /* Get the size of the image. */
3000 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3001 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3003 /* For 1DArray image types, the array index is stored in the Z component.
3004 * Fix this by swizzling the Z component to the Y component.
3006 const bool is_1d_array_image
=
3007 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3008 type
->sampler_array
;
3010 /* For CubeArray images, we should count the number of cubes instead
3011 * of the number of faces. Fix it by dividing the (Z component) by 6.
3013 const bool is_cube_array_image
=
3014 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3015 type
->sampler_array
;
3017 /* Copy all the components. */
3018 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3019 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3020 if ((int)c
>= type
->coordinate_components()) {
3021 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3023 } else if (c
== 1 && is_1d_array_image
) {
3024 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3025 offset(size
, bld
, 2));
3026 } else if (c
== 2 && is_cube_array_image
) {
3027 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3028 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3029 offset(size
, bld
, c
), brw_imm_d(6));
3031 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3032 offset(size
, bld
, c
));
3039 case nir_intrinsic_image_samples
:
3040 /* The driver does not support multi-sampled images. */
3041 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3044 case nir_intrinsic_load_uniform
: {
3045 /* Offsets are in bytes but they should always be multiples of 4 */
3046 assert(instr
->const_index
[0] % 4 == 0);
3048 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3050 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3052 /* Offsets are in bytes but they should always be multiples of 4 */
3053 assert(const_offset
->u32
[0] % 4 == 0);
3054 src
.reg_offset
= const_offset
->u32
[0] / 4;
3056 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3057 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3060 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3061 BRW_REGISTER_TYPE_UD
);
3063 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3064 * go past the end of the uniform. In order to keep the n'th
3065 * component from running past, we subtract off the size of all but
3066 * one component of the vector.
3068 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
3069 unsigned read_size
= instr
->const_index
[1] -
3070 (instr
->num_components
- 1) * 4;
3072 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3073 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3074 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3075 indirect
, brw_imm_ud(read_size
));
3081 case nir_intrinsic_load_ubo
: {
3082 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3086 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3087 const_index
->u32
[0];
3088 surf_index
= brw_imm_ud(index
);
3089 brw_mark_surface_used(prog_data
, index
);
3091 /* The block index is not a constant. Evaluate the index expression
3092 * per-channel and add the base UBO index; we have to select a value
3093 * from any live channel.
3095 surf_index
= vgrf(glsl_type::uint_type
);
3096 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3097 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3098 surf_index
= bld
.emit_uniformize(surf_index
);
3100 /* Assume this may touch any UBO. It would be nice to provide
3101 * a tighter bound, but the array information is already lowered away.
3103 brw_mark_surface_used(prog_data
,
3104 stage_prog_data
->binding_table
.ubo_start
+
3105 nir
->info
.num_ubos
- 1);
3108 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3109 if (const_offset
== NULL
) {
3110 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3111 BRW_REGISTER_TYPE_UD
);
3113 for (int i
= 0; i
< instr
->num_components
; i
++)
3114 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3115 base_offset
, i
* 4);
3117 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
3118 packed_consts
.type
= dest
.type
;
3120 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
3121 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
3122 surf_index
, const_offset_reg
);
3124 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3125 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
3127 /* The std140 packing rules don't allow vectors to cross 16-byte
3128 * boundaries, and a reg is 32 bytes.
3130 assert(packed_consts
.subreg_offset
< 32);
3132 bld
.MOV(dest
, packed_consts
);
3133 dest
= offset(dest
, bld
, 1);
3139 case nir_intrinsic_load_ssbo
: {
3140 assert(devinfo
->gen
>= 7);
3142 nir_const_value
*const_uniform_block
=
3143 nir_src_as_const_value(instr
->src
[0]);
3146 if (const_uniform_block
) {
3147 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3148 const_uniform_block
->u32
[0];
3149 surf_index
= brw_imm_ud(index
);
3150 brw_mark_surface_used(prog_data
, index
);
3152 surf_index
= vgrf(glsl_type::uint_type
);
3153 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3154 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3156 /* Assume this may touch any UBO. It would be nice to provide
3157 * a tighter bound, but the array information is already lowered away.
3159 brw_mark_surface_used(prog_data
,
3160 stage_prog_data
->binding_table
.ssbo_start
+
3161 nir
->info
.num_ssbos
- 1);
3165 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3167 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3169 offset_reg
= get_nir_src(instr
->src
[1]);
3172 /* Read the vector */
3173 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
3175 instr
->num_components
,
3176 BRW_PREDICATE_NONE
);
3177 read_result
.type
= dest
.type
;
3178 for (int i
= 0; i
< instr
->num_components
; i
++)
3179 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3184 case nir_intrinsic_load_input
: {
3186 if (stage
== MESA_SHADER_VERTEX
) {
3187 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3189 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3190 instr
->const_index
[0]);
3193 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3194 assert(const_offset
&& "Indirect input loads not allowed");
3195 src
= offset(src
, bld
, const_offset
->u32
[0]);
3197 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3198 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3203 case nir_intrinsic_store_ssbo
: {
3204 assert(devinfo
->gen
>= 7);
3208 nir_const_value
*const_uniform_block
=
3209 nir_src_as_const_value(instr
->src
[1]);
3210 if (const_uniform_block
) {
3211 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3212 const_uniform_block
->u32
[0];
3213 surf_index
= brw_imm_ud(index
);
3214 brw_mark_surface_used(prog_data
, index
);
3216 surf_index
= vgrf(glsl_type::uint_type
);
3217 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3218 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3220 brw_mark_surface_used(prog_data
,
3221 stage_prog_data
->binding_table
.ssbo_start
+
3222 nir
->info
.num_ssbos
- 1);
3226 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3229 unsigned writemask
= instr
->const_index
[0];
3231 /* Combine groups of consecutive enabled channels in one write
3232 * message. We use ffs to find the first enabled channel and then ffs on
3233 * the bit-inverse, down-shifted writemask to determine the length of
3234 * the block of enabled bits.
3237 unsigned first_component
= ffs(writemask
) - 1;
3238 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3241 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3243 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
3245 offset_reg
= vgrf(glsl_type::uint_type
);
3247 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3248 brw_imm_ud(4 * first_component
));
3251 emit_untyped_write(bld
, surf_index
, offset_reg
,
3252 offset(val_reg
, bld
, first_component
),
3253 1 /* dims */, length
,
3254 BRW_PREDICATE_NONE
);
3256 /* Clear the bits in the writemask that we just wrote, then try
3257 * again to see if more channels are left.
3259 writemask
&= (15 << (first_component
+ length
));
3264 case nir_intrinsic_store_output
: {
3265 fs_reg src
= get_nir_src(instr
->src
[0]);
3266 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3267 instr
->const_index
[0]);
3269 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3270 assert(const_offset
&& "Indirect output stores not allowed");
3271 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3273 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3274 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
3279 case nir_intrinsic_ssbo_atomic_add
:
3280 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
3282 case nir_intrinsic_ssbo_atomic_imin
:
3283 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
3285 case nir_intrinsic_ssbo_atomic_umin
:
3286 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
3288 case nir_intrinsic_ssbo_atomic_imax
:
3289 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
3291 case nir_intrinsic_ssbo_atomic_umax
:
3292 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
3294 case nir_intrinsic_ssbo_atomic_and
:
3295 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
3297 case nir_intrinsic_ssbo_atomic_or
:
3298 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
3300 case nir_intrinsic_ssbo_atomic_xor
:
3301 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
3303 case nir_intrinsic_ssbo_atomic_exchange
:
3304 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
3306 case nir_intrinsic_ssbo_atomic_comp_swap
:
3307 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3310 case nir_intrinsic_get_buffer_size
: {
3311 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
3312 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
3313 int reg_width
= dispatch_width
/ 8;
3316 fs_reg source
= brw_imm_d(0);
3318 int mlen
= 1 * reg_width
;
3320 /* A resinfo's sampler message is used to get the buffer size.
3321 * The SIMD8's writeback message consists of four registers and
3322 * SIMD16's writeback message consists of 8 destination registers
3323 * (two per each component), although we are only interested on the
3324 * first component, where resinfo returns the buffer size for
3327 int regs_written
= 4 * mlen
;
3328 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
3329 BRW_REGISTER_TYPE_UD
);
3330 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
3331 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
3332 BRW_REGISTER_TYPE_UD
);
3333 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
3334 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
3335 src_payload
, brw_imm_ud(index
));
3336 inst
->header_size
= 0;
3338 inst
->regs_written
= regs_written
;
3340 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
3342 brw_mark_surface_used(prog_data
, index
);
3347 unreachable("unknown intrinsic");
3352 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
3353 int op
, nir_intrinsic_instr
*instr
)
3356 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3357 dest
= get_nir_dest(instr
->dest
);
3360 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3361 if (const_surface
) {
3362 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3363 const_surface
->u32
[0];
3364 surface
= brw_imm_ud(surf_index
);
3365 brw_mark_surface_used(prog_data
, surf_index
);
3367 surface
= vgrf(glsl_type::uint_type
);
3368 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3369 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3371 /* Assume this may touch any SSBO. This is the same we do for other
3372 * UBO/SSBO accesses with non-constant surface.
3374 brw_mark_surface_used(prog_data
,
3375 stage_prog_data
->binding_table
.ssbo_start
+
3376 nir
->info
.num_ssbos
- 1);
3379 fs_reg offset
= get_nir_src(instr
->src
[1]);
3380 fs_reg data1
= get_nir_src(instr
->src
[2]);
3382 if (op
== BRW_AOP_CMPWR
)
3383 data2
= get_nir_src(instr
->src
[3]);
3385 /* Emit the actual atomic operation operation */
3387 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3389 1 /* dims */, 1 /* rsize */,
3391 BRW_PREDICATE_NONE
);
3392 dest
.type
= atomic_result
.type
;
3393 bld
.MOV(dest
, atomic_result
);
3397 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3398 int op
, nir_intrinsic_instr
*instr
)
3401 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3402 dest
= get_nir_dest(instr
->dest
);
3404 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3405 fs_reg offset
= get_nir_src(instr
->src
[0]);
3406 fs_reg data1
= get_nir_src(instr
->src
[1]);
3408 if (op
== BRW_AOP_CMPWR
)
3409 data2
= get_nir_src(instr
->src
[2]);
3411 /* Emit the actual atomic operation operation */
3413 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3415 1 /* dims */, 1 /* rsize */,
3417 BRW_PREDICATE_NONE
);
3418 dest
.type
= atomic_result
.type
;
3419 bld
.MOV(dest
, atomic_result
);
3423 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3425 unsigned texture
= instr
->texture_index
;
3426 unsigned sampler
= instr
->sampler_index
;
3428 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3430 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
3431 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
3433 int lod_components
= 0;
3435 /* The hardware requires a LOD for buffer textures */
3436 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3437 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
3439 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3440 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3441 switch (instr
->src
[i
].src_type
) {
3442 case nir_tex_src_bias
:
3443 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3445 case nir_tex_src_comparitor
:
3446 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
3448 case nir_tex_src_coord
:
3449 switch (instr
->op
) {
3451 case nir_texop_txf_ms
:
3452 case nir_texop_samples_identical
:
3453 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
3456 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
3460 case nir_tex_src_ddx
:
3461 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3462 lod_components
= nir_tex_instr_src_size(instr
, i
);
3464 case nir_tex_src_ddy
:
3465 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
3467 case nir_tex_src_lod
:
3468 switch (instr
->op
) {
3470 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3473 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_D
);
3476 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3480 case nir_tex_src_ms_index
:
3481 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3484 case nir_tex_src_offset
: {
3485 nir_const_value
*const_offset
=
3486 nir_src_as_const_value(instr
->src
[i
].src
);
3488 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
3489 if (header_bits
!= 0)
3490 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
3492 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
3493 retype(src
, BRW_REGISTER_TYPE_D
);
3498 case nir_tex_src_projector
:
3499 unreachable("should be lowered");
3501 case nir_tex_src_texture_offset
: {
3502 /* Figure out the highest possible texture index and mark it as used */
3503 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3504 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3505 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3507 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3509 brw_mark_surface_used(prog_data
, max_used
);
3511 /* Emit code to evaluate the actual indexing expression */
3512 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3513 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
3514 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
3518 case nir_tex_src_sampler_offset
: {
3519 /* Emit code to evaluate the actual indexing expression */
3520 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3521 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
3522 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
3527 unreachable("unknown texture source");
3531 if (instr
->op
== nir_texop_txf_ms
||
3532 instr
->op
== nir_texop_samples_identical
) {
3533 if (devinfo
->gen
>= 7 &&
3534 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3535 srcs
[TEX_LOGICAL_SRC_MCS
] =
3536 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
3537 instr
->coord_components
,
3538 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3540 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
3544 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
3545 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
3547 if (instr
->op
== nir_texop_query_levels
) {
3548 /* textureQueryLevels() is implemented in terms of TXS so we need to
3549 * pass a valid LOD argument.
3551 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
3552 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
3556 switch (instr
->op
) {
3558 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
3561 opcode
= FS_OPCODE_TXB_LOGICAL
;
3564 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
3567 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
3570 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
3572 case nir_texop_txf_ms
:
3573 if ((key_tex
->msaa_16
& (1 << sampler
)))
3574 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
3576 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
3578 case nir_texop_query_levels
:
3580 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
3583 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
3586 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
3587 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
3588 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
3590 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
3592 case nir_texop_texture_samples
: {
3593 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3595 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 4);
3596 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, tmp
,
3597 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3598 srcs
[TEX_LOGICAL_SRC_SURFACE
],
3599 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3601 inst
->header_size
= 1;
3602 inst
->base_mrf
= -1;
3603 inst
->regs_written
= 4 * (dispatch_width
/ 8);
3605 /* Pick off the one component we care about */
3609 case nir_texop_samples_identical
: {
3610 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3612 /* If mcs is an immediate value, it means there is no MCS. In that case
3613 * just return false.
3615 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
3616 bld
.MOV(dst
, brw_imm_ud(0u));
3617 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
3618 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3619 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
3620 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
3621 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
3623 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
3624 BRW_CONDITIONAL_EQ
);
3629 unreachable("unknown texture opcode");
3632 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
3633 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
3635 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
3636 if (devinfo
->gen
>= 9 &&
3637 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
3638 unsigned write_mask
= instr
->dest
.is_ssa
?
3639 nir_ssa_def_components_read(&instr
->dest
.ssa
):
3640 (1 << dest_size
) - 1;
3641 assert(write_mask
!= 0); /* dead code should have been eliminated */
3642 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
3644 inst
->regs_written
= 4 * dispatch_width
/ 8;
3647 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
3648 inst
->shadow_compare
= true;
3650 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
3651 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
3653 if (instr
->op
== nir_texop_tg4
) {
3654 if (instr
->component
== 1 &&
3655 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
3656 /* gather4 sampler is broken for green channel on RG32F --
3657 * we must ask for blue instead.
3659 inst
->offset
|= 2 << 16;
3661 inst
->offset
|= instr
->component
<< 16;
3664 if (devinfo
->gen
== 6)
3665 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
3669 for (unsigned i
= 0; i
< dest_size
; i
++)
3670 nir_dest
[i
] = offset(dst
, bld
, i
);
3672 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3675 if (instr
->op
== nir_texop_query_levels
) {
3676 /* # levels is in .w */
3677 nir_dest
[0] = offset(dst
, bld
, 3);
3678 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
3679 (devinfo
->gen
< 7 || is_cube_array
)) {
3680 fs_reg depth
= offset(dst
, bld
, 2);
3681 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
3683 if (is_cube_array
) {
3684 /* fixup #layers for cube map arrays */
3685 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
3686 } else if (devinfo
->gen
< 7) {
3687 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
3688 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
3691 nir_dest
[2] = fixed_depth
;
3694 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
3698 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3700 switch (instr
->type
) {
3701 case nir_jump_break
:
3702 bld
.emit(BRW_OPCODE_BREAK
);
3704 case nir_jump_continue
:
3705 bld
.emit(BRW_OPCODE_CONTINUE
);
3707 case nir_jump_return
:
3709 unreachable("unknown jump");