2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
30 nir_optimize(nir_shader
*nir
)
35 nir_lower_vars_to_ssa(nir
);
36 nir_validate_shader(nir
);
37 nir_lower_alu_to_scalar(nir
);
38 nir_validate_shader(nir
);
39 progress
|= nir_copy_prop(nir
);
40 nir_validate_shader(nir
);
41 nir_lower_phis_to_scalar(nir
);
42 nir_validate_shader(nir
);
43 progress
|= nir_copy_prop(nir
);
44 nir_validate_shader(nir
);
45 progress
|= nir_opt_dce(nir
);
46 nir_validate_shader(nir
);
47 progress
|= nir_opt_cse(nir
);
48 nir_validate_shader(nir
);
49 progress
|= nir_opt_peephole_select(nir
);
50 nir_validate_shader(nir
);
51 progress
|= nir_opt_algebraic(nir
);
52 nir_validate_shader(nir
);
53 progress
|= nir_opt_constant_folding(nir
);
54 nir_validate_shader(nir
);
55 progress
|= nir_opt_remove_phis(nir
);
56 nir_validate_shader(nir
);
61 count_nir_instrs_in_block(nir_block
*block
, void *state
)
63 int *count
= (int *) state
;
64 nir_foreach_instr(block
, instr
) {
71 count_nir_instrs(nir_shader
*nir
)
74 nir_foreach_overload(nir
, overload
) {
77 nir_foreach_block(overload
->impl
, count_nir_instrs_in_block
, &count
);
83 fs_visitor::emit_nir_code()
85 const nir_shader_compiler_options
*options
=
86 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
88 /* first, lower the GLSL IR shader to NIR */
89 lower_output_reads(shader
->base
.ir
);
90 nir_shader
*nir
= glsl_to_nir(&shader
->base
, options
);
91 nir_validate_shader(nir
);
93 nir_lower_global_vars_to_local(nir
);
94 nir_validate_shader(nir
);
96 nir_split_var_copies(nir
);
97 nir_validate_shader(nir
);
101 /* Lower a bunch of stuff */
102 nir_lower_var_copies(nir
);
103 nir_validate_shader(nir
);
105 /* Get rid of split copies */
109 nir_validate_shader(nir
);
111 nir_remove_dead_variables(nir
);
112 nir_validate_shader(nir
);
114 nir_lower_samplers(nir
, shader_prog
, shader
->base
.Program
);
115 nir_validate_shader(nir
);
117 nir_lower_system_values(nir
);
118 nir_validate_shader(nir
);
120 nir_lower_atomics(nir
);
121 nir_validate_shader(nir
);
125 nir_lower_locals_to_regs(nir
);
126 nir_validate_shader(nir
);
128 nir_lower_to_source_mods(nir
);
129 nir_validate_shader(nir
);
131 nir_validate_shader(nir
);
133 if (unlikely(debug_enabled
)) {
134 fprintf(stderr
, "NIR (SSA form) for %s shader:\n", stage_name
);
135 nir_print_shader(nir
, stderr
);
138 if (dispatch_width
== 8) {
139 static GLuint msg_id
= 0;
140 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
141 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
142 MESA_DEBUG_TYPE_OTHER
,
143 MESA_DEBUG_SEVERITY_NOTIFICATION
,
144 "%s NIR shader: %d inst\n",
146 count_nir_instrs(nir
));
149 nir_convert_from_ssa(nir
);
150 nir_validate_shader(nir
);
152 /* emit the arrays used for inputs and outputs - load/store intrinsics will
153 * be converted to reads/writes of these arrays
156 if (nir
->num_inputs
> 0) {
157 nir_inputs
= vgrf(nir
->num_inputs
);
158 nir_setup_inputs(nir
);
161 if (nir
->num_outputs
> 0) {
162 nir_outputs
= vgrf(nir
->num_outputs
);
163 nir_setup_outputs(nir
);
166 if (nir
->num_uniforms
> 0) {
167 nir_uniforms
= fs_reg(UNIFORM
, 0);
168 nir_setup_uniforms(nir
);
171 nir_emit_system_values(nir
);
173 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
174 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
175 unsigned array_elems
=
176 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
177 unsigned size
= array_elems
* reg
->num_components
;
178 nir_globals
[reg
->index
] = vgrf(size
);
181 /* get the main function and emit it */
182 nir_foreach_overload(nir
, overload
) {
183 assert(strcmp(overload
->function
->name
, "main") == 0);
184 assert(overload
->impl
);
185 nir_emit_impl(overload
->impl
);
188 if (unlikely(debug_enabled
)) {
189 fprintf(stderr
, "NIR (final form) for %s shader:\n", stage_name
);
190 nir_print_shader(nir
, stderr
);
197 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
199 struct hash_entry
*entry
;
200 hash_table_foreach(shader
->inputs
, entry
) {
201 nir_variable
*var
= (nir_variable
*) entry
->data
;
202 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
203 fs_reg input
= offset(nir_inputs
, var
->data
.driver_location
);
207 case MESA_SHADER_VERTEX
: {
208 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
209 * stored in nir_variable::location.
211 * However, NIR's load_input intrinsics use a different index - an
212 * offset into a single contiguous array containing all inputs.
213 * This index corresponds to the nir_variable::driver_location field.
215 * So, we need to copy from fs_reg(ATTR, var->location) to
216 * offset(nir_inputs, var->data.driver_location).
218 unsigned components
= var
->type
->without_array()->components();
219 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
220 for (unsigned i
= 0; i
< array_length
; i
++) {
221 for (unsigned j
= 0; j
< components
; j
++) {
222 emit(MOV(retype(offset(input
, components
* i
+ j
), type
),
223 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
), j
)));
228 case MESA_SHADER_GEOMETRY
:
229 case MESA_SHADER_COMPUTE
:
230 unreachable("fs_visitor not used for these stages yet.");
232 case MESA_SHADER_FRAGMENT
:
233 if (var
->data
.location
== VARYING_SLOT_POS
) {
234 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
235 var
->data
.origin_upper_left
);
236 emit_percomp(MOV(input
, reg
), 0xF);
238 emit_general_interpolation(input
, var
->name
, var
->type
,
239 (glsl_interp_qualifier
) var
->data
.interpolation
,
240 var
->data
.location
, var
->data
.centroid
,
249 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
251 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
253 struct hash_entry
*entry
;
254 hash_table_foreach(shader
->outputs
, entry
) {
255 nir_variable
*var
= (nir_variable
*) entry
->data
;
256 fs_reg reg
= offset(nir_outputs
, var
->data
.driver_location
);
258 int vector_elements
=
259 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
260 : var
->type
->vector_elements
;
262 if (stage
== MESA_SHADER_VERTEX
) {
263 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
264 int output
= var
->data
.location
+ i
;
265 this->outputs
[output
] = offset(reg
, 4 * i
);
266 this->output_components
[output
] = vector_elements
;
268 } else if (var
->data
.index
> 0) {
269 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
270 assert(var
->data
.index
== 1);
271 this->dual_src_output
= reg
;
272 this->do_dual_src
= true;
273 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
274 /* Writing gl_FragColor outputs to all color regions. */
275 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
276 this->outputs
[i
] = reg
;
277 this->output_components
[i
] = 4;
279 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
280 this->frag_depth
= reg
;
281 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
282 this->sample_mask
= reg
;
284 /* gl_FragData or a user-defined FS output */
285 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
286 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
288 /* General color output. */
289 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
290 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
291 this->outputs
[output
] = offset(reg
, vector_elements
* i
);
292 this->output_components
[output
] = vector_elements
;
299 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
301 uniforms
= shader
->num_uniforms
;
302 param_size
[0] = shader
->num_uniforms
;
304 if (dispatch_width
!= 8)
307 struct hash_entry
*entry
;
308 hash_table_foreach(shader
->uniforms
, entry
) {
309 nir_variable
*var
= (nir_variable
*) entry
->data
;
311 /* UBO's and atomics don't take up space in the uniform file */
313 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
316 if (strncmp(var
->name
, "gl_", 3) == 0)
317 nir_setup_builtin_uniform(var
);
319 nir_setup_uniform(var
);
324 fs_visitor::nir_setup_uniform(nir_variable
*var
)
326 int namelen
= strlen(var
->name
);
328 /* The data for our (non-builtin) uniforms is stored in a series of
329 * gl_uniform_driver_storage structs for each subcomponent that
330 * glGetUniformLocation() could name. We know it's been set up in the
331 * same order we'd walk the type, so walk the list of storage and find
332 * anything with our name, or the prefix of a component that starts with
335 unsigned index
= var
->data
.driver_location
;
336 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
337 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
339 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
340 (storage
->name
[namelen
] != 0 &&
341 storage
->name
[namelen
] != '.' &&
342 storage
->name
[namelen
] != '[')) {
346 unsigned slots
= storage
->type
->component_slots();
347 if (storage
->array_elements
)
348 slots
*= storage
->array_elements
;
350 for (unsigned i
= 0; i
< slots
; i
++) {
351 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
355 /* Make sure we actually initialized the right amount of stuff here. */
356 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
360 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
362 const nir_state_slot
*const slots
= var
->state_slots
;
363 assert(var
->state_slots
!= NULL
);
365 unsigned uniform_index
= var
->data
.driver_location
;
366 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
367 /* This state reference has already been setup by ir_to_mesa, but we'll
368 * get the same index back here.
370 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
371 (gl_state_index
*)slots
[i
].tokens
);
373 /* Add each of the unique swizzles of the element as a parameter.
374 * This'll end up matching the expected layout of the
375 * array/matrix/structure we're trying to fill in.
378 for (unsigned int j
= 0; j
< 4; j
++) {
379 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
380 if (swiz
== last_swiz
)
384 stage_prog_data
->param
[uniform_index
++] =
385 &prog
->Parameters
->ParameterValues
[index
][swiz
];
391 emit_system_values_block(nir_block
*block
, void *void_visitor
)
393 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
396 nir_foreach_instr(block
, instr
) {
397 if (instr
->type
!= nir_instr_type_intrinsic
)
400 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
401 switch (intrin
->intrinsic
) {
402 case nir_intrinsic_load_vertex_id
:
403 unreachable("should be lowered by lower_vertex_id().");
405 case nir_intrinsic_load_vertex_id_zero_base
:
406 assert(v
->stage
== MESA_SHADER_VERTEX
);
407 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
408 if (reg
->file
== BAD_FILE
)
409 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
412 case nir_intrinsic_load_base_vertex
:
413 assert(v
->stage
== MESA_SHADER_VERTEX
);
414 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
415 if (reg
->file
== BAD_FILE
)
416 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
419 case nir_intrinsic_load_instance_id
:
420 assert(v
->stage
== MESA_SHADER_VERTEX
);
421 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
422 if (reg
->file
== BAD_FILE
)
423 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
426 case nir_intrinsic_load_sample_pos
:
427 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
428 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
429 if (reg
->file
== BAD_FILE
)
430 *reg
= *v
->emit_samplepos_setup();
433 case nir_intrinsic_load_sample_id
:
434 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
435 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
436 if (reg
->file
== BAD_FILE
)
437 *reg
= *v
->emit_sampleid_setup();
440 case nir_intrinsic_load_sample_mask_in
:
441 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
442 assert(v
->brw
->gen
>= 7);
443 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
444 if (reg
->file
== BAD_FILE
)
445 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
446 BRW_REGISTER_TYPE_D
));
458 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
460 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
461 nir_foreach_overload(shader
, overload
) {
462 assert(strcmp(overload
->function
->name
, "main") == 0);
463 assert(overload
->impl
);
464 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
469 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
471 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
472 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
473 unsigned array_elems
=
474 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
475 unsigned size
= array_elems
* reg
->num_components
;
476 nir_locals
[reg
->index
] = vgrf(size
);
479 nir_emit_cf_list(&impl
->body
);
483 fs_visitor::nir_emit_cf_list(exec_list
*list
)
485 exec_list_validate(list
);
486 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
487 switch (node
->type
) {
489 nir_emit_if(nir_cf_node_as_if(node
));
492 case nir_cf_node_loop
:
493 nir_emit_loop(nir_cf_node_as_loop(node
));
496 case nir_cf_node_block
:
497 nir_emit_block(nir_cf_node_as_block(node
));
501 unreachable("Invalid CFG node block");
507 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
509 /* first, put the condition into f0 */
510 fs_inst
*inst
= emit(MOV(reg_null_d
,
511 retype(get_nir_src(if_stmt
->condition
),
512 BRW_REGISTER_TYPE_UD
)));
513 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
515 emit(IF(BRW_PREDICATE_NORMAL
));
517 nir_emit_cf_list(&if_stmt
->then_list
);
519 /* note: if the else is empty, dead CF elimination will remove it */
520 emit(BRW_OPCODE_ELSE
);
522 nir_emit_cf_list(&if_stmt
->else_list
);
524 emit(BRW_OPCODE_ENDIF
);
526 if (!try_replace_with_sel() && brw
->gen
< 6) {
527 no16("Can't support (non-uniform) control flow on SIMD16\n");
532 fs_visitor::nir_emit_loop(nir_loop
*loop
)
535 no16("Can't support (non-uniform) control flow on SIMD16\n");
540 nir_emit_cf_list(&loop
->body
);
542 emit(BRW_OPCODE_WHILE
);
546 fs_visitor::nir_emit_block(nir_block
*block
)
548 nir_foreach_instr(block
, instr
) {
549 nir_emit_instr(instr
);
554 fs_visitor::nir_emit_instr(nir_instr
*instr
)
556 switch (instr
->type
) {
557 case nir_instr_type_alu
:
558 nir_emit_alu(nir_instr_as_alu(instr
));
561 case nir_instr_type_intrinsic
:
562 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
565 case nir_instr_type_tex
:
566 nir_emit_texture(nir_instr_as_tex(instr
));
569 case nir_instr_type_load_const
:
570 /* We can hit these, but we do nothing now and use them as
575 case nir_instr_type_jump
:
576 nir_emit_jump(nir_instr_as_jump(instr
));
580 unreachable("unknown instruction type");
585 brw_type_for_nir_type(nir_alu_type type
)
589 case nir_type_unsigned
:
590 return BRW_REGISTER_TYPE_UD
;
592 return BRW_REGISTER_TYPE_D
;
594 return BRW_REGISTER_TYPE_F
;
596 unreachable("unknown type");
599 return BRW_REGISTER_TYPE_F
;
603 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
604 const fs_reg
&result
)
606 if (instr
->src
[0].src
.is_ssa
||
607 !instr
->src
[0].src
.reg
.reg
||
608 !instr
->src
[0].src
.reg
.reg
->parent_instr
)
611 if (instr
->src
[0].src
.reg
.reg
->parent_instr
->type
!=
612 nir_instr_type_intrinsic
)
615 nir_intrinsic_instr
*src0
=
616 nir_instr_as_intrinsic(instr
->src
[0].src
.reg
.reg
->parent_instr
);
618 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
621 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
622 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
625 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
626 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
629 fs_reg tmp
= vgrf(glsl_type::int_type
);
632 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
633 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
635 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
637 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
638 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
640 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
642 * This negation looks like it's safe in practice, because bits 0:4 will
643 * surely be TRIANGLES
646 if (value1
->f
[0] == -1.0f
) {
650 tmp
.type
= BRW_REGISTER_TYPE_W
;
651 tmp
.subreg_offset
= 2;
654 fs_inst
*or_inst
= emit(OR(tmp
, g0
, fs_reg(0x3f80)));
655 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
657 tmp
.type
= BRW_REGISTER_TYPE_D
;
658 tmp
.subreg_offset
= 0;
661 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
662 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
664 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
666 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
667 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
669 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
671 * This negation looks like it's safe in practice, because bits 0:4 will
672 * surely be TRIANGLES
675 if (value1
->f
[0] == -1.0f
) {
679 emit(OR(tmp
, g1_6
, fs_reg(0x3f800000)));
681 emit(AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000)));
687 fs_visitor::nir_emit_alu(nir_alu_instr
*instr
)
689 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
692 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
693 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
696 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
697 op
[i
] = get_nir_src(instr
->src
[i
].src
);
698 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
699 op
[i
].abs
= instr
->src
[i
].abs
;
700 op
[i
].negate
= instr
->src
[i
].negate
;
703 /* We get a bunch of mov's out of the from_ssa pass and they may still
704 * be vectorized. We'll handle them as a special-case. We'll also
705 * handle vecN here because it's basically the same thing.
713 fs_reg temp
= result
;
714 bool need_extra_copy
= false;
715 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
716 if (!instr
->src
[i
].src
.is_ssa
&&
717 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
718 need_extra_copy
= true;
719 temp
= retype(vgrf(4), result
.type
);
724 for (unsigned i
= 0; i
< 4; i
++) {
725 if (!(instr
->dest
.write_mask
& (1 << i
)))
728 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
729 inst
= emit(MOV(offset(temp
, i
),
730 offset(op
[0], instr
->src
[0].swizzle
[i
])));
732 inst
= emit(MOV(offset(temp
, i
),
733 offset(op
[i
], instr
->src
[i
].swizzle
[0])));
735 inst
->saturate
= instr
->dest
.saturate
;
738 /* In this case the source and destination registers were the same,
739 * so we need to insert an extra set of moves in order to deal with
742 if (need_extra_copy
) {
743 for (unsigned i
= 0; i
< 4; i
++) {
744 if (!(instr
->dest
.write_mask
& (1 << i
)))
747 emit(MOV(offset(result
, i
), offset(temp
, i
)));
756 /* At this point, we have dealt with any instruction that operates on
757 * more than a single channel. Therefore, we can just adjust the source
758 * and destination registers for that channel and emit the instruction.
760 unsigned channel
= 0;
761 if (nir_op_infos
[instr
->op
].output_size
== 0) {
762 /* Since NIR is doing the scalarizing for us, we should only ever see
763 * vectorized operations with a single channel.
765 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
766 channel
= ffs(instr
->dest
.write_mask
) - 1;
768 result
= offset(result
, channel
);
771 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
772 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
773 op
[i
] = offset(op
[i
], instr
->src
[i
].swizzle
[channel
]);
779 inst
= emit(MOV(result
, op
[0]));
780 inst
->saturate
= instr
->dest
.saturate
;
785 emit(MOV(result
, op
[0]));
789 /* AND(val, 0x80000000) gives the sign bit.
791 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
794 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
796 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
797 op
[0].type
= BRW_REGISTER_TYPE_UD
;
798 result
.type
= BRW_REGISTER_TYPE_UD
;
799 emit(AND(result_int
, op
[0], fs_reg(0x80000000u
)));
801 inst
= emit(OR(result_int
, result_int
, fs_reg(0x3f800000u
)));
802 inst
->predicate
= BRW_PREDICATE_NORMAL
;
803 if (instr
->dest
.saturate
) {
804 inst
= emit(MOV(result
, result
));
805 inst
->saturate
= true;
811 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
812 * -> non-negative val generates 0x00000000.
813 * Predicated OR sets 1 if val is positive.
815 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
816 emit(ASR(result
, op
[0], fs_reg(31)));
817 inst
= emit(OR(result
, result
, fs_reg(1)));
818 inst
->predicate
= BRW_PREDICATE_NORMAL
;
822 inst
= emit_math(SHADER_OPCODE_RCP
, result
, op
[0]);
823 inst
->saturate
= instr
->dest
.saturate
;
827 inst
= emit_math(SHADER_OPCODE_EXP2
, result
, op
[0]);
828 inst
->saturate
= instr
->dest
.saturate
;
832 inst
= emit_math(SHADER_OPCODE_LOG2
, result
, op
[0]);
833 inst
->saturate
= instr
->dest
.saturate
;
838 unreachable("not reached: should be handled by ir_explog_to_explog2");
841 case nir_op_fsin_reduced
:
842 inst
= emit_math(SHADER_OPCODE_SIN
, result
, op
[0]);
843 inst
->saturate
= instr
->dest
.saturate
;
847 case nir_op_fcos_reduced
:
848 inst
= emit_math(SHADER_OPCODE_COS
, result
, op
[0]);
849 inst
->saturate
= instr
->dest
.saturate
;
853 if (fs_key
->high_quality_derivatives
) {
854 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
856 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
858 inst
->saturate
= instr
->dest
.saturate
;
860 case nir_op_fddx_fine
:
861 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
862 inst
->saturate
= instr
->dest
.saturate
;
864 case nir_op_fddx_coarse
:
865 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
869 if (fs_key
->high_quality_derivatives
) {
870 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
871 fs_reg(fs_key
->render_to_fbo
));
873 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
874 fs_reg(fs_key
->render_to_fbo
));
876 inst
->saturate
= instr
->dest
.saturate
;
878 case nir_op_fddy_fine
:
879 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
880 fs_reg(fs_key
->render_to_fbo
));
881 inst
->saturate
= instr
->dest
.saturate
;
883 case nir_op_fddy_coarse
:
884 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
885 fs_reg(fs_key
->render_to_fbo
));
886 inst
->saturate
= instr
->dest
.saturate
;
891 inst
= emit(ADD(result
, op
[0], op
[1]));
892 inst
->saturate
= instr
->dest
.saturate
;
896 inst
= emit(MUL(result
, op
[0], op
[1]));
897 inst
->saturate
= instr
->dest
.saturate
;
902 emit(MUL(result
, op
[0], op
[1]));
905 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
906 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
908 if (value0
&& value0
->u
[0] < (1 << 16)) {
910 emit(MUL(result
, op
[0], op
[1]));
912 emit(MUL(result
, op
[1], op
[0]));
915 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
917 emit(MUL(result
, op
[1], op
[0]));
919 emit(MUL(result
, op
[0], op
[1]));
926 no16("SIMD16 explicit accumulator operands unsupported\n");
928 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
930 emit(MUL(acc
, op
[0], op
[1]));
931 emit(MACH(reg_null_d
, op
[0], op
[1]));
932 emit(MOV(result
, fs_reg(acc
)));
936 case nir_op_imul_high
:
937 case nir_op_umul_high
: {
939 no16("SIMD16 explicit accumulator operands unsupported\n");
941 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
943 emit(MUL(acc
, op
[0], op
[1]));
944 emit(MACH(result
, op
[0], op
[1]));
950 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
953 case nir_op_uadd_carry
: {
955 no16("SIMD16 explicit accumulator operands unsupported\n");
957 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
958 BRW_REGISTER_TYPE_UD
);
960 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
961 emit(MOV(result
, fs_reg(acc
)));
965 case nir_op_usub_borrow
: {
967 no16("SIMD16 explicit accumulator operands unsupported\n");
969 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
970 BRW_REGISTER_TYPE_UD
);
972 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
973 emit(MOV(result
, fs_reg(acc
)));
978 emit_math(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
984 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
));
990 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
995 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1000 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1004 if (brw
->gen
>= 8) {
1005 resolve_source_modifiers(&op
[0]);
1007 emit(NOT(result
, op
[0]));
1010 if (brw
->gen
>= 8) {
1011 resolve_source_modifiers(&op
[0]);
1012 resolve_source_modifiers(&op
[1]);
1014 emit(XOR(result
, op
[0], op
[1]));
1017 if (brw
->gen
>= 8) {
1018 resolve_source_modifiers(&op
[0]);
1019 resolve_source_modifiers(&op
[1]);
1021 emit(OR(result
, op
[0], op
[1]));
1024 if (brw
->gen
>= 8) {
1025 resolve_source_modifiers(&op
[0]);
1026 resolve_source_modifiers(&op
[1]);
1028 emit(AND(result
, op
[0], op
[1]));
1040 case nir_op_ball_fequal2
:
1041 case nir_op_ball_iequal2
:
1042 case nir_op_ball_fequal3
:
1043 case nir_op_ball_iequal3
:
1044 case nir_op_ball_fequal4
:
1045 case nir_op_ball_iequal4
:
1046 case nir_op_bany_fnequal2
:
1047 case nir_op_bany_inequal2
:
1048 case nir_op_bany_fnequal3
:
1049 case nir_op_bany_inequal3
:
1050 case nir_op_bany_fnequal4
:
1051 case nir_op_bany_inequal4
:
1052 unreachable("Lowered by nir_lower_alu_reductions");
1054 case nir_op_fnoise1_1
:
1055 case nir_op_fnoise1_2
:
1056 case nir_op_fnoise1_3
:
1057 case nir_op_fnoise1_4
:
1058 case nir_op_fnoise2_1
:
1059 case nir_op_fnoise2_2
:
1060 case nir_op_fnoise2_3
:
1061 case nir_op_fnoise2_4
:
1062 case nir_op_fnoise3_1
:
1063 case nir_op_fnoise3_2
:
1064 case nir_op_fnoise3_3
:
1065 case nir_op_fnoise3_4
:
1066 case nir_op_fnoise4_1
:
1067 case nir_op_fnoise4_2
:
1068 case nir_op_fnoise4_3
:
1069 case nir_op_fnoise4_4
:
1070 unreachable("not reached: should be handled by lower_noise");
1073 unreachable("not reached: should be handled by ldexp_to_arith()");
1076 inst
= emit_math(SHADER_OPCODE_SQRT
, result
, op
[0]);
1077 inst
->saturate
= instr
->dest
.saturate
;
1081 inst
= emit_math(SHADER_OPCODE_RSQ
, result
, op
[0]);
1082 inst
->saturate
= instr
->dest
.saturate
;
1086 emit(AND(result
, op
[0], fs_reg(1)));
1089 emit(AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
)));
1093 emit(CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1096 emit(CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1100 inst
= emit(RNDZ(result
, op
[0]));
1101 inst
->saturate
= instr
->dest
.saturate
;
1104 case nir_op_fceil
: {
1105 op
[0].negate
= !op
[0].negate
;
1106 fs_reg temp
= vgrf(glsl_type::float_type
);
1107 emit(RNDD(temp
, op
[0]));
1109 inst
= emit(MOV(result
, temp
));
1110 inst
->saturate
= instr
->dest
.saturate
;
1114 inst
= emit(RNDD(result
, op
[0]));
1115 inst
->saturate
= instr
->dest
.saturate
;
1118 inst
= emit(FRC(result
, op
[0]));
1119 inst
->saturate
= instr
->dest
.saturate
;
1121 case nir_op_fround_even
:
1122 inst
= emit(RNDE(result
, op
[0]));
1123 inst
->saturate
= instr
->dest
.saturate
;
1129 if (brw
->gen
>= 6) {
1130 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1131 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1133 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1134 inst
= emit(SEL(result
, op
[0], op
[1]));
1136 inst
->saturate
= instr
->dest
.saturate
;
1142 if (brw
->gen
>= 6) {
1143 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1144 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1146 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
1147 inst
= emit(SEL(result
, op
[0], op
[1]));
1149 inst
->saturate
= instr
->dest
.saturate
;
1152 case nir_op_pack_snorm_2x16
:
1153 case nir_op_pack_snorm_4x8
:
1154 case nir_op_pack_unorm_2x16
:
1155 case nir_op_pack_unorm_4x8
:
1156 case nir_op_unpack_snorm_2x16
:
1157 case nir_op_unpack_snorm_4x8
:
1158 case nir_op_unpack_unorm_2x16
:
1159 case nir_op_unpack_unorm_4x8
:
1160 case nir_op_unpack_half_2x16
:
1161 case nir_op_pack_half_2x16
:
1162 unreachable("not reached: should be handled by lower_packing_builtins");
1164 case nir_op_unpack_half_2x16_split_x
:
1165 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1166 inst
->saturate
= instr
->dest
.saturate
;
1168 case nir_op_unpack_half_2x16_split_y
:
1169 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1170 inst
->saturate
= instr
->dest
.saturate
;
1174 inst
= emit_math(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1175 inst
->saturate
= instr
->dest
.saturate
;
1178 case nir_op_bitfield_reverse
:
1179 emit(BFREV(result
, op
[0]));
1182 case nir_op_bit_count
:
1183 emit(CBIT(result
, op
[0]));
1186 case nir_op_ufind_msb
:
1187 case nir_op_ifind_msb
: {
1188 emit(FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]));
1190 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1191 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1192 * subtract the result from 31 to convert the MSB count into an LSB count.
1195 emit(CMP(reg_null_d
, result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1196 fs_reg
neg_result(result
);
1197 neg_result
.negate
= true;
1198 inst
= emit(ADD(result
, neg_result
, fs_reg(31)));
1199 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1203 case nir_op_find_lsb
:
1204 emit(FBL(result
, op
[0]));
1207 case nir_op_ubitfield_extract
:
1208 case nir_op_ibitfield_extract
:
1209 emit(BFE(result
, op
[2], op
[1], op
[0]));
1212 emit(BFI1(result
, op
[0], op
[1]));
1215 emit(BFI2(result
, op
[0], op
[1], op
[2]));
1218 case nir_op_bitfield_insert
:
1219 unreachable("not reached: should be handled by "
1220 "lower_instructions::bitfield_insert_to_bfm_bfi");
1223 emit(SHL(result
, op
[0], op
[1]));
1226 emit(ASR(result
, op
[0], op
[1]));
1229 emit(SHR(result
, op
[0], op
[1]));
1232 case nir_op_pack_half_2x16_split
:
1233 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1237 inst
= emit(MAD(result
, op
[2], op
[1], op
[0]));
1238 inst
->saturate
= instr
->dest
.saturate
;
1242 /* TODO emulate for gen < 6 */
1243 inst
= emit(LRP(result
, op
[2], op
[1], op
[0]));
1244 inst
->saturate
= instr
->dest
.saturate
;
1248 if (optimize_frontfacing_ternary(instr
, result
))
1251 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1252 inst
= emit(SEL(result
, op
[1], op
[2]));
1253 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1257 unreachable("unhandled instruction");
1262 fs_visitor::get_nir_src(nir_src src
)
1265 assert(src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
);
1266 nir_load_const_instr
*load
= nir_instr_as_load_const(src
.ssa
->parent_instr
);
1267 fs_reg reg
= vgrf(src
.ssa
->num_components
);
1268 reg
.type
= BRW_REGISTER_TYPE_D
;
1270 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
1271 emit(MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
])));
1276 if (src
.reg
.reg
->is_global
)
1277 reg
= nir_globals
[src
.reg
.reg
->index
];
1279 reg
= nir_locals
[src
.reg
.reg
->index
];
1281 /* to avoid floating-point denorm flushing problems, set the type by
1282 * default to D - instructions that need floating point semantics will set
1283 * this to F if they need to
1285 reg
= retype(offset(reg
, src
.reg
.base_offset
), BRW_REGISTER_TYPE_D
);
1286 if (src
.reg
.indirect
) {
1287 reg
.reladdr
= new(mem_ctx
) fs_reg();
1288 *reg
.reladdr
= retype(get_nir_src(*src
.reg
.indirect
),
1289 BRW_REGISTER_TYPE_D
);
1297 fs_visitor::get_nir_dest(nir_dest dest
)
1300 if (dest
.reg
.reg
->is_global
)
1301 reg
= nir_globals
[dest
.reg
.reg
->index
];
1303 reg
= nir_locals
[dest
.reg
.reg
->index
];
1305 reg
= offset(reg
, dest
.reg
.base_offset
);
1306 if (dest
.reg
.indirect
) {
1307 reg
.reladdr
= new(mem_ctx
) fs_reg();
1308 *reg
.reladdr
= retype(get_nir_src(*dest
.reg
.indirect
),
1309 BRW_REGISTER_TYPE_D
);
1316 fs_visitor::emit_percomp(fs_inst
*inst
, unsigned wr_mask
)
1318 for (unsigned i
= 0; i
< 4; i
++) {
1319 if (!((wr_mask
>> i
) & 1))
1322 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(*inst
);
1323 new_inst
->dst
= offset(new_inst
->dst
, i
);
1324 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1325 if (inst
->src
[j
].file
== GRF
)
1326 new_inst
->src
[j
] = offset(new_inst
->src
[j
], i
);
1333 fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
1336 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1337 dest
= get_nir_dest(instr
->dest
);
1339 bool has_indirect
= false;
1341 switch (instr
->intrinsic
) {
1342 case nir_intrinsic_discard
:
1343 case nir_intrinsic_discard_if
: {
1344 /* We track our discarded pixels in f0.1. By predicating on it, we can
1345 * update just the flag bits that aren't yet discarded. If there's no
1346 * condition, we emit a CMP of g0 != g0, so all currently executing
1347 * channels will get turned off.
1350 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1351 cmp
= emit(CMP(reg_null_f
, get_nir_src(instr
->src
[0]),
1352 fs_reg(0), BRW_CONDITIONAL_Z
));
1354 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1355 BRW_REGISTER_TYPE_UW
));
1356 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
, BRW_CONDITIONAL_NZ
));
1358 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1359 cmp
->flag_subreg
= 1;
1361 if (brw
->gen
>= 6) {
1362 /* For performance, after a discard, jump to the end of the shader.
1363 * Only jump if all relevant channels have been discarded.
1365 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1366 discard_jump
->flag_subreg
= 1;
1368 discard_jump
->predicate
= (dispatch_width
== 8)
1369 ? BRW_PREDICATE_ALIGN1_ANY8H
1370 : BRW_PREDICATE_ALIGN1_ANY16H
;
1371 discard_jump
->predicate_inverse
= true;
1377 case nir_intrinsic_atomic_counter_inc
:
1378 case nir_intrinsic_atomic_counter_dec
:
1379 case nir_intrinsic_atomic_counter_read
: {
1380 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1381 (unsigned) instr
->const_index
[0];
1382 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1384 switch (instr
->intrinsic
) {
1385 case nir_intrinsic_atomic_counter_inc
:
1386 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1387 fs_reg(), fs_reg());
1389 case nir_intrinsic_atomic_counter_dec
:
1390 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1391 fs_reg(), fs_reg());
1393 case nir_intrinsic_atomic_counter_read
:
1394 emit_untyped_surface_read(surf_index
, dest
, offset
);
1397 unreachable("Unreachable");
1402 case nir_intrinsic_load_front_face
:
1403 emit(MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1404 *emit_frontfacing_interpolation()));
1407 case nir_intrinsic_load_vertex_id
:
1408 unreachable("should be lowered by lower_vertex_id()");
1410 case nir_intrinsic_load_vertex_id_zero_base
: {
1411 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1412 assert(vertex_id
.file
!= BAD_FILE
);
1413 dest
.type
= vertex_id
.type
;
1414 emit(MOV(dest
, vertex_id
));
1418 case nir_intrinsic_load_base_vertex
: {
1419 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1420 assert(base_vertex
.file
!= BAD_FILE
);
1421 dest
.type
= base_vertex
.type
;
1422 emit(MOV(dest
, base_vertex
));
1426 case nir_intrinsic_load_instance_id
: {
1427 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1428 assert(instance_id
.file
!= BAD_FILE
);
1429 dest
.type
= instance_id
.type
;
1430 emit(MOV(dest
, instance_id
));
1434 case nir_intrinsic_load_sample_mask_in
: {
1435 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1436 assert(sample_mask_in
.file
!= BAD_FILE
);
1437 dest
.type
= sample_mask_in
.type
;
1438 emit(MOV(dest
, sample_mask_in
));
1442 case nir_intrinsic_load_sample_pos
: {
1443 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1444 assert(sample_pos
.file
!= BAD_FILE
);
1445 dest
.type
= sample_pos
.type
;
1446 emit(MOV(dest
, sample_pos
));
1447 emit(MOV(offset(dest
, 1), offset(sample_pos
, 1)));
1451 case nir_intrinsic_load_sample_id
: {
1452 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1453 assert(sample_id
.file
!= BAD_FILE
);
1454 dest
.type
= sample_id
.type
;
1455 emit(MOV(dest
, sample_id
));
1459 case nir_intrinsic_load_uniform_indirect
:
1460 has_indirect
= true;
1461 case nir_intrinsic_load_uniform
: {
1463 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1464 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1465 fs_reg src
= offset(retype(nir_uniforms
, dest
.type
),
1466 instr
->const_index
[0] + index
);
1468 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1471 emit(MOV(dest
, src
));
1472 dest
= offset(dest
, 1);
1478 case nir_intrinsic_load_ubo_indirect
:
1479 has_indirect
= true;
1481 case nir_intrinsic_load_ubo
: {
1482 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1486 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1489 /* The block index is not a constant. Evaluate the index expression
1490 * per-channel and add the base UBO index; the generator will select
1491 * a value from any live channel.
1493 surf_index
= vgrf(glsl_type::uint_type
);
1494 emit(ADD(surf_index
, get_nir_src(instr
->src
[0]),
1495 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1496 ->force_writemask_all
= true;
1498 /* Assume this may touch any UBO. It would be nice to provide
1499 * a tighter bound, but the array information is already lowered away.
1501 brw_mark_surface_used(prog_data
,
1502 stage_prog_data
->binding_table
.ubo_start
+
1503 shader_prog
->NumUniformBlocks
- 1);
1507 /* Turn the byte offset into a dword offset. */
1508 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1509 emit(SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1510 BRW_REGISTER_TYPE_D
),
1513 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1514 for (int i
= 0; i
< instr
->num_components
; i
++)
1515 emit(VARYING_PULL_CONSTANT_LOAD(offset(dest
, i
), surf_index
,
1516 base_offset
, vec4_offset
+ i
));
1518 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1519 packed_consts
.type
= dest
.type
;
1521 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1522 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1523 surf_index
, const_offset_reg
);
1525 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1526 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1528 /* The std140 packing rules don't allow vectors to cross 16-byte
1529 * boundaries, and a reg is 32 bytes.
1531 assert(packed_consts
.subreg_offset
< 32);
1533 emit(MOV(dest
, packed_consts
));
1534 dest
= offset(dest
, 1);
1540 case nir_intrinsic_load_input_indirect
:
1541 has_indirect
= true;
1543 case nir_intrinsic_load_input
: {
1545 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1546 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1547 fs_reg src
= offset(retype(nir_inputs
, dest
.type
),
1548 instr
->const_index
[0] + index
);
1550 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1553 emit(MOV(dest
, src
));
1554 dest
= offset(dest
, 1);
1560 /* Handle ARB_gpu_shader5 interpolation intrinsics
1562 * It's worth a quick word of explanation as to why we handle the full
1563 * variable-based interpolation intrinsic rather than a lowered version
1564 * with like we do for other inputs. We have to do that because the way
1565 * we set up inputs doesn't allow us to use the already setup inputs for
1566 * interpolation. At the beginning of the shader, we go through all of
1567 * the input variables and do the initial interpolation and put it in
1568 * the nir_inputs array based on its location as determined in
1569 * nir_lower_io. If the input isn't used, dead code cleans up and
1570 * everything works fine. However, when we get to the ARB_gpu_shader5
1571 * interpolation intrinsics, we need to reinterpolate the input
1572 * differently. If we used an intrinsic that just had an index it would
1573 * only give us the offset into the nir_inputs array. However, this is
1574 * useless because that value is post-interpolation and we need
1575 * pre-interpolation. In order to get the actual location of the bits
1576 * we get from the vertex fetching hardware, we need the variable.
1578 case nir_intrinsic_interp_var_at_centroid
:
1579 case nir_intrinsic_interp_var_at_sample
:
1580 case nir_intrinsic_interp_var_at_offset
: {
1581 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1582 * 8 channels at a time, same as the barycentric coords presented in
1583 * the FS payload. this requires a bit of extra work to support.
1585 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1587 fs_reg dst_x
= vgrf(2);
1588 fs_reg dst_y
= offset(dst_x
, 1);
1590 /* For most messages, we need one reg of ignored data; the hardware
1591 * requires mlen==1 even when there is no payload. in the per-slot
1592 * offset case, we'll replace this with the proper source data.
1594 fs_reg src
= vgrf(glsl_type::float_type
);
1595 int mlen
= 1; /* one reg unless overriden */
1598 switch (instr
->intrinsic
) {
1599 case nir_intrinsic_interp_var_at_centroid
:
1600 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
1603 case nir_intrinsic_interp_var_at_sample
: {
1604 /* XXX: We should probably handle non-constant sample id's */
1605 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1606 assert(const_sample
);
1607 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1608 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
,
1613 case nir_intrinsic_interp_var_at_offset
: {
1614 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1617 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1618 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1620 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
1621 fs_reg(off_x
| (off_y
<< 4)));
1623 src
= vgrf(glsl_type::ivec2_type
);
1624 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1625 BRW_REGISTER_TYPE_F
);
1626 for (int i
= 0; i
< 2; i
++) {
1627 fs_reg temp
= vgrf(glsl_type::float_type
);
1628 emit(MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
)));
1629 fs_reg itemp
= vgrf(glsl_type::int_type
);
1630 emit(MOV(itemp
, temp
)); /* float to int */
1632 /* Clamp the upper end of the range to +7/16.
1633 * ARB_gpu_shader5 requires that we support a maximum offset
1634 * of +0.5, which isn't representable in a S0.4 value -- if
1635 * we didn't clamp it, we'd end up with -8/16, which is the
1636 * opposite of what the shader author wanted.
1638 * This is legal due to ARB_gpu_shader5's quantization
1641 * "Not all values of <offset> may be supported; x and y
1642 * offsets may be rounded to fixed-point values with the
1643 * number of fraction bits given by the
1644 * implementation-dependent constant
1645 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1648 emit(BRW_OPCODE_SEL
, offset(src
, i
), itemp
, fs_reg(7))
1649 ->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
1653 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
1660 unreachable("Invalid intrinsic");
1664 inst
->regs_written
= 2; /* 2 floats per slot returned */
1665 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1666 INTERP_QUALIFIER_NOPERSPECTIVE
;
1668 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1669 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1670 src
.type
= dest
.type
;
1672 emit(FS_OPCODE_LINTERP
, dest
, dst_x
, dst_y
, src
);
1673 dest
= offset(dest
, 1);
1678 case nir_intrinsic_store_output_indirect
:
1679 has_indirect
= true;
1680 case nir_intrinsic_store_output
: {
1681 fs_reg src
= get_nir_src(instr
->src
[0]);
1683 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1684 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1685 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
),
1686 instr
->const_index
[0] + index
);
1688 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1690 emit(MOV(new_dest
, src
));
1691 src
= offset(src
, 1);
1698 unreachable("unknown intrinsic");
1703 fs_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1705 unsigned sampler
= instr
->sampler_index
;
1706 fs_reg
sampler_reg(sampler
);
1708 /* FINISHME: We're failing to recompile our programs when the sampler is
1709 * updated. This only matters for the texture rectangle scale parameters
1710 * (pre-gen6, or gen6+ with GL_CLAMP).
1712 int texunit
= prog
->SamplerUnits
[sampler
];
1714 int gather_component
= instr
->component
;
1716 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1718 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1721 int lod_components
= 0, offset_components
= 0;
1723 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, offset
;
1725 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1726 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1727 switch (instr
->src
[i
].src_type
) {
1728 case nir_tex_src_bias
:
1729 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1731 case nir_tex_src_comparitor
:
1732 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1734 case nir_tex_src_coord
:
1735 switch (instr
->op
) {
1737 case nir_texop_txf_ms
:
1738 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1741 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1745 case nir_tex_src_ddx
:
1746 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1747 lod_components
= nir_tex_instr_src_size(instr
, i
);
1749 case nir_tex_src_ddy
:
1750 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1752 case nir_tex_src_lod
:
1753 switch (instr
->op
) {
1755 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1758 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1761 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1765 case nir_tex_src_ms_index
:
1766 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1768 case nir_tex_src_offset
:
1769 offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1770 if (instr
->is_array
)
1771 offset_components
= instr
->coord_components
- 1;
1773 offset_components
= instr
->coord_components
;
1775 case nir_tex_src_projector
:
1776 unreachable("should be lowered");
1778 case nir_tex_src_sampler_offset
: {
1779 /* Figure out the highest possible sampler index and mark it as used */
1780 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1781 if (instr
->op
== nir_texop_tg4
&& brw
->gen
< 8) {
1782 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1784 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1786 brw_mark_surface_used(prog_data
, max_used
);
1788 /* Emit code to evaluate the actual indexing expression */
1789 sampler_reg
= vgrf(glsl_type::uint_type
);
1790 emit(ADD(sampler_reg
, src
, fs_reg(sampler
)))
1791 ->force_writemask_all
= true;
1796 unreachable("unknown texture source");
1800 if (instr
->op
== nir_texop_txf_ms
) {
1801 if (brw
->gen
>= 7 &&
1802 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1803 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1809 for (unsigned i
= 0; i
< 3; i
++) {
1810 if (instr
->const_offset
[i
] != 0) {
1811 assert(offset_components
== 0);
1812 offset
= fs_reg(brw_texture_offset(ctx
, instr
->const_offset
, 3));
1817 enum glsl_base_type dest_base_type
;
1818 switch (instr
->dest_type
) {
1819 case nir_type_float
:
1820 dest_base_type
= GLSL_TYPE_FLOAT
;
1823 dest_base_type
= GLSL_TYPE_INT
;
1825 case nir_type_unsigned
:
1826 dest_base_type
= GLSL_TYPE_UINT
;
1829 unreachable("bad type");
1832 const glsl_type
*dest_type
=
1833 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1836 ir_texture_opcode op
;
1837 switch (instr
->op
) {
1838 case nir_texop_lod
: op
= ir_lod
; break;
1839 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1840 case nir_texop_tex
: op
= ir_tex
; break;
1841 case nir_texop_tg4
: op
= ir_tg4
; break;
1842 case nir_texop_txb
: op
= ir_txb
; break;
1843 case nir_texop_txd
: op
= ir_txd
; break;
1844 case nir_texop_txf
: op
= ir_txf
; break;
1845 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1846 case nir_texop_txl
: op
= ir_txl
; break;
1847 case nir_texop_txs
: op
= ir_txs
; break;
1849 unreachable("unknown texture opcode");
1852 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1853 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1854 offset
, mcs
, gather_component
,
1855 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1857 fs_reg dest
= get_nir_dest(instr
->dest
);
1858 dest
.type
= this->result
.type
;
1859 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1860 emit_percomp(MOV(dest
, this->result
), (1 << num_components
) - 1);
1864 fs_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1866 switch (instr
->type
) {
1867 case nir_jump_break
:
1868 emit(BRW_OPCODE_BREAK
);
1870 case nir_jump_continue
:
1871 emit(BRW_OPCODE_CONTINUE
);
1873 case nir_jump_return
:
1875 unreachable("unknown jump");