2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
30 fs_visitor::emit_nir_code()
32 /* first, lower the GLSL IR shader to NIR */
33 lower_output_reads(shader
->base
.ir
);
34 nir_shader
*nir
= glsl_to_nir(shader
->base
.ir
, NULL
, true);
35 nir_validate_shader(nir
);
37 nir_lower_global_vars_to_local(nir
);
38 nir_validate_shader(nir
);
40 nir_split_var_copies(nir
);
41 nir_validate_shader(nir
);
46 nir_lower_variables(nir
);
47 nir_validate_shader(nir
);
48 progress
|= nir_copy_prop(nir
);
49 nir_validate_shader(nir
);
50 progress
|= nir_opt_dce(nir
);
51 nir_validate_shader(nir
);
52 progress
|= nir_opt_cse(nir
);
53 nir_validate_shader(nir
);
54 progress
|= nir_opt_peephole_select(nir
);
55 nir_validate_shader(nir
);
56 progress
|= nir_opt_algebraic(nir
);
57 nir_validate_shader(nir
);
58 progress
|= nir_opt_constant_folding(nir
);
59 nir_validate_shader(nir
);
62 /* Lower a bunch of stuff */
64 nir_validate_shader(nir
);
66 nir_lower_locals_to_regs(nir
);
67 nir_validate_shader(nir
);
69 nir_remove_dead_variables(nir
);
70 nir_validate_shader(nir
);
72 nir_lower_atomics(nir
);
73 nir_validate_shader(nir
);
75 nir_lower_to_source_mods(nir
);
76 nir_validate_shader(nir
);
78 nir_validate_shader(nir
);
79 nir_convert_from_ssa(nir
);
80 nir_validate_shader(nir
);
81 nir_lower_vec_to_movs(nir
);
82 nir_validate_shader(nir
);
84 nir_lower_samplers(nir
, shader_prog
, shader
->base
.Program
);
85 nir_validate_shader(nir
);
87 nir_lower_system_values(nir
);
88 nir_validate_shader(nir
);
90 /* emit the arrays used for inputs and outputs - load/store intrinsics will
91 * be converted to reads/writes of these arrays
94 if (nir
->num_inputs
> 0) {
95 nir_inputs
= fs_reg(GRF
, virtual_grf_alloc(nir
->num_inputs
));
96 nir_setup_inputs(nir
);
99 if (nir
->num_outputs
> 0) {
100 nir_outputs
= fs_reg(GRF
, virtual_grf_alloc(nir
->num_outputs
));
101 nir_setup_outputs(nir
);
104 if (nir
->num_uniforms
> 0) {
105 nir_uniforms
= fs_reg(UNIFORM
, 0);
106 nir_setup_uniforms(nir
);
109 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
110 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
111 unsigned array_elems
=
112 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
113 unsigned size
= array_elems
* reg
->num_components
;
114 nir_globals
[reg
->index
] = fs_reg(GRF
, virtual_grf_alloc(size
));
117 /* get the main function and emit it */
118 nir_foreach_overload(nir
, overload
) {
119 assert(strcmp(overload
->function
->name
, "main") == 0);
120 assert(overload
->impl
);
121 nir_emit_impl(overload
->impl
);
128 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
130 fs_reg varying
= nir_inputs
;
132 struct hash_entry
*entry
;
133 hash_table_foreach(shader
->inputs
, entry
) {
134 nir_variable
*var
= (nir_variable
*) entry
->data
;
135 varying
.reg_offset
= var
->data
.driver_location
;
138 if (!strcmp(var
->name
, "gl_FragCoord")) {
139 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
140 var
->data
.origin_upper_left
);
141 emit_percomp(MOV(varying
, reg
), 0xF);
142 } else if (!strcmp(var
->name
, "gl_FrontFacing")) {
143 reg
= *emit_frontfacing_interpolation();
144 emit(MOV(retype(varying
, BRW_REGISTER_TYPE_UD
), reg
));
146 emit_general_interpolation(varying
, var
->name
, var
->type
,
147 (glsl_interp_qualifier
) var
->data
.interpolation
,
148 var
->data
.location
, var
->data
.centroid
,
155 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
157 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
158 fs_reg reg
= nir_outputs
;
160 struct hash_entry
*entry
;
161 hash_table_foreach(shader
->outputs
, entry
) {
162 nir_variable
*var
= (nir_variable
*) entry
->data
;
163 reg
.reg_offset
= var
->data
.driver_location
;
165 if (var
->data
.index
> 0) {
166 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
167 assert(var
->data
.index
== 1);
168 this->dual_src_output
= reg
;
169 this->do_dual_src
= true;
170 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
171 /* Writing gl_FragColor outputs to all color regions. */
172 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
173 this->outputs
[i
] = reg
;
174 this->output_components
[i
] = 4;
176 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
177 this->frag_depth
= reg
;
178 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
179 this->sample_mask
= reg
;
181 /* gl_FragData or a user-defined FS output */
182 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
183 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
185 int vector_elements
=
186 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
187 : var
->type
->vector_elements
;
189 /* General color output. */
190 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
191 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
192 this->outputs
[output
] = reg
;
193 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
194 this->output_components
[output
] = vector_elements
;
201 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
203 uniforms
= shader
->num_uniforms
;
204 param_size
[0] = shader
->num_uniforms
;
206 if (dispatch_width
!= 8)
209 struct hash_entry
*entry
;
210 hash_table_foreach(shader
->uniforms
, entry
) {
211 nir_variable
*var
= (nir_variable
*) entry
->data
;
213 /* UBO's and atomics don't take up space in the uniform file */
215 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
218 if (strncmp(var
->name
, "gl_", 3) == 0)
219 nir_setup_builtin_uniform(var
);
221 nir_setup_uniform(var
);
226 fs_visitor::nir_setup_uniform(nir_variable
*var
)
228 int namelen
= strlen(var
->name
);
230 /* The data for our (non-builtin) uniforms is stored in a series of
231 * gl_uniform_driver_storage structs for each subcomponent that
232 * glGetUniformLocation() could name. We know it's been set up in the
233 * same order we'd walk the type, so walk the list of storage and find
234 * anything with our name, or the prefix of a component that starts with
237 unsigned index
= var
->data
.driver_location
;
238 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
239 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
241 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
242 (storage
->name
[namelen
] != 0 &&
243 storage
->name
[namelen
] != '.' &&
244 storage
->name
[namelen
] != '[')) {
248 unsigned slots
= storage
->type
->component_slots();
249 if (storage
->array_elements
)
250 slots
*= storage
->array_elements
;
252 for (unsigned i
= 0; i
< slots
; i
++) {
253 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
257 /* Make sure we actually initialized the right amount of stuff here. */
258 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
262 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
264 const nir_state_slot
*const slots
= var
->state_slots
;
265 assert(var
->state_slots
!= NULL
);
267 unsigned uniform_index
= var
->data
.driver_location
;
268 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
269 /* This state reference has already been setup by ir_to_mesa, but we'll
270 * get the same index back here.
272 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
273 (gl_state_index
*)slots
[i
].tokens
);
275 /* Add each of the unique swizzles of the element as a parameter.
276 * This'll end up matching the expected layout of the
277 * array/matrix/structure we're trying to fill in.
280 for (unsigned int j
= 0; j
< 4; j
++) {
281 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
282 if (swiz
== last_swiz
)
286 stage_prog_data
->param
[uniform_index
++] =
287 &prog
->Parameters
->ParameterValues
[index
][swiz
];
293 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
295 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
296 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
297 unsigned array_elems
=
298 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
299 unsigned size
= array_elems
* reg
->num_components
;
300 nir_locals
[reg
->index
] = fs_reg(GRF
, virtual_grf_alloc(size
));
303 nir_emit_cf_list(&impl
->body
);
307 fs_visitor::nir_emit_cf_list(exec_list
*list
)
309 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
310 switch (node
->type
) {
312 nir_emit_if(nir_cf_node_as_if(node
));
315 case nir_cf_node_loop
:
316 nir_emit_loop(nir_cf_node_as_loop(node
));
319 case nir_cf_node_block
:
320 nir_emit_block(nir_cf_node_as_block(node
));
324 unreachable("Invalid CFG node block");
330 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
333 no16("Can't support (non-uniform) control flow on SIMD16\n");
336 /* first, put the condition into f0 */
337 fs_inst
*inst
= emit(MOV(reg_null_d
,
338 retype(get_nir_src(if_stmt
->condition
),
339 BRW_REGISTER_TYPE_UD
)));
340 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
342 emit(IF(BRW_PREDICATE_NORMAL
));
344 nir_emit_cf_list(&if_stmt
->then_list
);
346 /* note: if the else is empty, dead CF elimination will remove it */
347 emit(BRW_OPCODE_ELSE
);
349 nir_emit_cf_list(&if_stmt
->else_list
);
351 emit(BRW_OPCODE_ENDIF
);
353 try_replace_with_sel();
357 fs_visitor::nir_emit_loop(nir_loop
*loop
)
360 no16("Can't support (non-uniform) control flow on SIMD16\n");
365 nir_emit_cf_list(&loop
->body
);
367 emit(BRW_OPCODE_WHILE
);
371 fs_visitor::nir_emit_block(nir_block
*block
)
373 nir_foreach_instr(block
, instr
) {
374 nir_emit_instr(instr
);
379 fs_visitor::nir_emit_instr(nir_instr
*instr
)
381 switch (instr
->type
) {
382 case nir_instr_type_alu
:
383 nir_emit_alu(nir_instr_as_alu(instr
));
386 case nir_instr_type_intrinsic
:
387 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
390 case nir_instr_type_tex
:
391 nir_emit_texture(nir_instr_as_tex(instr
));
394 case nir_instr_type_load_const
:
395 nir_emit_load_const(nir_instr_as_load_const(instr
));
398 case nir_instr_type_jump
:
399 nir_emit_jump(nir_instr_as_jump(instr
));
403 unreachable("unknown instruction type");
408 brw_type_for_nir_type(nir_alu_type type
)
412 case nir_type_unsigned
:
413 return BRW_REGISTER_TYPE_UD
;
415 return BRW_REGISTER_TYPE_D
;
417 return BRW_REGISTER_TYPE_F
;
419 unreachable("unknown type");
422 return BRW_REGISTER_TYPE_F
;
426 fs_visitor::nir_emit_alu(nir_alu_instr
*instr
)
428 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
431 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
432 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
434 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
435 op
[i
] = get_nir_alu_src(instr
, i
);
441 fs_inst
*inst
= MOV(result
, op
[0]);
442 inst
->saturate
= instr
->dest
.saturate
;
443 emit_percomp(inst
, instr
->dest
.write_mask
);
450 emit_percomp(MOV(result
, op
[0]), instr
->dest
.write_mask
);
454 /* AND(val, 0x80000000) gives the sign bit.
456 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
459 emit_percomp(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
),
460 instr
->dest
.write_mask
);
462 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
463 op
[0].type
= BRW_REGISTER_TYPE_UD
;
464 result
.type
= BRW_REGISTER_TYPE_UD
;
465 emit_percomp(AND(result_int
, op
[0], fs_reg(0x80000000u
)),
466 instr
->dest
.write_mask
);
468 fs_inst
*inst
= OR(result_int
, result_int
, fs_reg(0x3f800000u
));
469 inst
->predicate
= BRW_PREDICATE_NORMAL
;
470 emit_percomp(inst
, instr
->dest
.write_mask
);
471 if (instr
->dest
.saturate
) {
472 fs_inst
*inst
= MOV(result
, result
);
473 inst
->saturate
= true;
474 emit_percomp(inst
, instr
->dest
.write_mask
);
480 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
481 * -> non-negative val generates 0x00000000.
482 * Predicated OR sets 1 if val is positive.
484 emit_percomp(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
),
485 instr
->dest
.write_mask
);
487 emit_percomp(ASR(result
, op
[0], fs_reg(31)), instr
->dest
.write_mask
);
489 fs_inst
*inst
= OR(result
, result
, fs_reg(1));
490 inst
->predicate
= BRW_PREDICATE_NORMAL
;
491 emit_percomp(inst
, instr
->dest
.write_mask
);
496 emit_math_percomp(SHADER_OPCODE_RCP
, result
, op
[0],
497 instr
->dest
.write_mask
, instr
->dest
.saturate
);
501 emit_math_percomp(SHADER_OPCODE_EXP2
, result
, op
[0],
502 instr
->dest
.write_mask
, instr
->dest
.saturate
);
506 emit_math_percomp(SHADER_OPCODE_LOG2
, result
, op
[0],
507 instr
->dest
.write_mask
, instr
->dest
.saturate
);
512 unreachable("not reached: should be handled by ir_explog_to_explog2");
515 case nir_op_fsin_reduced
:
516 emit_math_percomp(SHADER_OPCODE_SIN
, result
, op
[0],
517 instr
->dest
.write_mask
, instr
->dest
.saturate
);
521 case nir_op_fcos_reduced
:
522 emit_math_percomp(SHADER_OPCODE_COS
, result
, op
[0],
523 instr
->dest
.write_mask
, instr
->dest
.saturate
);
527 if (fs_key
->high_quality_derivatives
)
528 emit_percomp(FS_OPCODE_DDX_FINE
, result
, op
[0],
529 instr
->dest
.write_mask
, instr
->dest
.saturate
);
531 emit_percomp(FS_OPCODE_DDX_COARSE
, result
, op
[0],
532 instr
->dest
.write_mask
, instr
->dest
.saturate
);
534 case nir_op_fddx_fine
:
535 emit_percomp(FS_OPCODE_DDX_FINE
, result
, op
[0],
536 instr
->dest
.write_mask
, instr
->dest
.saturate
);
538 case nir_op_fddx_coarse
:
539 emit_percomp(FS_OPCODE_DDX_COARSE
, result
, op
[0],
540 instr
->dest
.write_mask
, instr
->dest
.saturate
);
543 if (fs_key
->high_quality_derivatives
)
544 emit_percomp(FS_OPCODE_DDY_FINE
, result
, op
[0],
545 fs_reg(fs_key
->render_to_fbo
),
546 instr
->dest
.write_mask
, instr
->dest
.saturate
);
548 emit_percomp(FS_OPCODE_DDY_COARSE
, result
, op
[0],
549 fs_reg(fs_key
->render_to_fbo
),
550 instr
->dest
.write_mask
, instr
->dest
.saturate
);
552 case nir_op_fddy_fine
:
553 emit_percomp(FS_OPCODE_DDY_FINE
, result
, op
[0],
554 fs_reg(fs_key
->render_to_fbo
),
555 instr
->dest
.write_mask
, instr
->dest
.saturate
);
557 case nir_op_fddy_coarse
:
558 emit_percomp(FS_OPCODE_DDY_COARSE
, result
, op
[0],
559 fs_reg(fs_key
->render_to_fbo
),
560 instr
->dest
.write_mask
, instr
->dest
.saturate
);
565 fs_inst
*inst
= ADD(result
, op
[0], op
[1]);
566 inst
->saturate
= instr
->dest
.saturate
;
567 emit_percomp(inst
, instr
->dest
.write_mask
);
572 fs_inst
*inst
= MUL(result
, op
[0], op
[1]);
573 inst
->saturate
= instr
->dest
.saturate
;
574 emit_percomp(inst
, instr
->dest
.write_mask
);
579 /* TODO put in the 16-bit constant optimization once we have SSA */
582 no16("SIMD16 explicit accumulator operands unsupported\n");
584 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
586 emit_percomp(MUL(acc
, op
[0], op
[1]), instr
->dest
.write_mask
);
587 emit_percomp(MACH(reg_null_d
, op
[0], op
[1]), instr
->dest
.write_mask
);
588 emit_percomp(MOV(result
, fs_reg(acc
)), instr
->dest
.write_mask
);
592 case nir_op_imul_high
:
593 case nir_op_umul_high
: {
595 no16("SIMD16 explicit accumulator operands unsupported\n");
597 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
599 emit_percomp(MUL(acc
, op
[0], op
[1]), instr
->dest
.write_mask
);
600 emit_percomp(MACH(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
606 emit_math_percomp(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1],
607 instr
->dest
.write_mask
);
610 case nir_op_uadd_carry
: {
612 no16("SIMD16 explicit accumulator operands unsupported\n");
614 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
615 BRW_REGISTER_TYPE_UD
);
617 emit_percomp(ADDC(reg_null_ud
, op
[0], op
[1]), instr
->dest
.write_mask
);
618 emit_percomp(MOV(result
, fs_reg(acc
)), instr
->dest
.write_mask
);
622 case nir_op_usub_borrow
: {
624 no16("SIMD16 explicit accumulator operands unsupported\n");
626 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
627 BRW_REGISTER_TYPE_UD
);
629 emit_percomp(SUBB(reg_null_ud
, op
[0], op
[1]), instr
->dest
.write_mask
);
630 emit_percomp(MOV(result
, fs_reg(acc
)), instr
->dest
.write_mask
);
635 emit_math_percomp(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0],
636 op
[1], instr
->dest
.write_mask
);
642 emit_percomp(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
),
643 instr
->dest
.write_mask
);
649 emit_percomp(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
),
650 instr
->dest
.write_mask
);
655 emit_percomp(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
),
656 instr
->dest
.write_mask
);
661 emit_percomp(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
),
662 instr
->dest
.write_mask
);
665 case nir_op_ball_fequal2
:
666 case nir_op_ball_iequal2
:
667 case nir_op_ball_fequal3
:
668 case nir_op_ball_iequal3
:
669 case nir_op_ball_fequal4
:
670 case nir_op_ball_iequal4
: {
671 unsigned num_components
= nir_op_infos
[instr
->op
].input_sizes
[0];
672 fs_reg temp
= fs_reg(GRF
, virtual_grf_alloc(num_components
));
673 emit_percomp(CMP(temp
, op
[0], op
[1], BRW_CONDITIONAL_Z
),
674 (1 << num_components
) - 1);
675 emit_reduction(BRW_OPCODE_AND
, result
, temp
, num_components
);
679 case nir_op_bany_fnequal2
:
680 case nir_op_bany_inequal2
:
681 case nir_op_bany_fnequal3
:
682 case nir_op_bany_inequal3
:
683 case nir_op_bany_fnequal4
:
684 case nir_op_bany_inequal4
: {
685 unsigned num_components
= nir_op_infos
[instr
->op
].input_sizes
[0];
686 fs_reg temp
= fs_reg(GRF
, virtual_grf_alloc(num_components
));
687 temp
.type
= BRW_REGISTER_TYPE_UD
;
688 emit_percomp(CMP(temp
, op
[0], op
[1], BRW_CONDITIONAL_NZ
),
689 (1 << num_components
) - 1);
690 emit_reduction(BRW_OPCODE_OR
, result
, temp
, num_components
);
695 emit_percomp(NOT(result
, op
[0]), instr
->dest
.write_mask
);
698 emit_percomp(XOR(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
701 emit_percomp(OR(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
704 emit_percomp(AND(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
710 unsigned num_components
= nir_op_infos
[instr
->op
].input_sizes
[0];
711 fs_reg temp
= fs_reg(GRF
, virtual_grf_alloc(num_components
));
712 emit_percomp(MUL(temp
, op
[0], op
[1]), (1 << num_components
) - 1);
713 emit_reduction(BRW_OPCODE_ADD
, result
, temp
, num_components
);
714 if (instr
->dest
.saturate
) {
715 fs_inst
*inst
= emit(MOV(result
, result
));
716 inst
->saturate
= true;
724 unsigned num_components
= nir_op_infos
[instr
->op
].input_sizes
[0];
725 emit_reduction(BRW_OPCODE_OR
, result
, op
[0], num_components
);
732 unsigned num_components
= nir_op_infos
[instr
->op
].input_sizes
[0];
733 emit_reduction(BRW_OPCODE_AND
, result
, op
[0], num_components
);
737 case nir_op_fnoise1_1
:
738 case nir_op_fnoise1_2
:
739 case nir_op_fnoise1_3
:
740 case nir_op_fnoise1_4
:
741 case nir_op_fnoise2_1
:
742 case nir_op_fnoise2_2
:
743 case nir_op_fnoise2_3
:
744 case nir_op_fnoise2_4
:
745 case nir_op_fnoise3_1
:
746 case nir_op_fnoise3_2
:
747 case nir_op_fnoise3_3
:
748 case nir_op_fnoise3_4
:
749 case nir_op_fnoise4_1
:
750 case nir_op_fnoise4_2
:
751 case nir_op_fnoise4_3
:
752 case nir_op_fnoise4_4
:
753 unreachable("not reached: should be handled by lower_noise");
758 unreachable("not reached: should be handled by lower_quadop_vector");
761 unreachable("not reached: should be handled by ldexp_to_arith()");
764 emit_math_percomp(SHADER_OPCODE_SQRT
, result
, op
[0],
765 instr
->dest
.write_mask
, instr
->dest
.saturate
);
769 emit_math_percomp(SHADER_OPCODE_RSQ
, result
, op
[0],
770 instr
->dest
.write_mask
, instr
->dest
.saturate
);
774 emit_percomp(AND(result
, op
[0], fs_reg(1)), instr
->dest
.write_mask
);
777 emit_percomp(AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0],
778 fs_reg(0x3f800000u
)),
779 instr
->dest
.write_mask
);
784 emit_percomp(CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
),
785 instr
->dest
.write_mask
);
788 emit_percomp(CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
),
789 instr
->dest
.write_mask
);
792 case nir_op_ftrunc
: {
793 fs_inst
*inst
= RNDZ(result
, op
[0]);
794 inst
->saturate
= instr
->dest
.saturate
;
795 emit_percomp(inst
, instr
->dest
.write_mask
);
799 op
[0].negate
= !op
[0].negate
;
800 fs_reg temp
= fs_reg(this, glsl_type::vec4_type
);
801 emit_percomp(RNDD(temp
, op
[0]), instr
->dest
.write_mask
);
803 fs_inst
*inst
= MOV(result
, temp
);
804 inst
->saturate
= instr
->dest
.saturate
;
805 emit_percomp(inst
, instr
->dest
.write_mask
);
808 case nir_op_ffloor
: {
809 fs_inst
*inst
= RNDD(result
, op
[0]);
810 inst
->saturate
= instr
->dest
.saturate
;
811 emit_percomp(inst
, instr
->dest
.write_mask
);
814 case nir_op_ffract
: {
815 fs_inst
*inst
= FRC(result
, op
[0]);
816 inst
->saturate
= instr
->dest
.saturate
;
817 emit_percomp(inst
, instr
->dest
.write_mask
);
820 case nir_op_fround_even
: {
821 fs_inst
*inst
= RNDE(result
, op
[0]);
822 inst
->saturate
= instr
->dest
.saturate
;
823 emit_percomp(inst
, instr
->dest
.write_mask
);
831 emit_percomp(BRW_OPCODE_SEL
, result
, op
[0], op
[1],
832 instr
->dest
.write_mask
, instr
->dest
.saturate
,
833 BRW_PREDICATE_NONE
, BRW_CONDITIONAL_L
);
835 emit_percomp(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_L
),
836 instr
->dest
.write_mask
);
838 emit_percomp(BRW_OPCODE_SEL
, result
, op
[0], op
[1],
839 instr
->dest
.write_mask
, instr
->dest
.saturate
,
840 BRW_PREDICATE_NORMAL
);
848 emit_percomp(BRW_OPCODE_SEL
, result
, op
[0], op
[1],
849 instr
->dest
.write_mask
, instr
->dest
.saturate
,
850 BRW_PREDICATE_NONE
, BRW_CONDITIONAL_GE
);
852 emit_percomp(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_GE
),
853 instr
->dest
.write_mask
);
855 emit_percomp(BRW_OPCODE_SEL
, result
, op
[0], op
[1],
856 instr
->dest
.write_mask
, instr
->dest
.saturate
,
857 BRW_PREDICATE_NORMAL
);
861 case nir_op_pack_snorm_2x16
:
862 case nir_op_pack_snorm_4x8
:
863 case nir_op_pack_unorm_2x16
:
864 case nir_op_pack_unorm_4x8
:
865 case nir_op_unpack_snorm_2x16
:
866 case nir_op_unpack_snorm_4x8
:
867 case nir_op_unpack_unorm_2x16
:
868 case nir_op_unpack_unorm_4x8
:
869 case nir_op_unpack_half_2x16
:
870 case nir_op_pack_half_2x16
:
871 unreachable("not reached: should be handled by lower_packing_builtins");
873 case nir_op_unpack_half_2x16_split_x
:
874 emit_percomp(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0],
875 instr
->dest
.write_mask
, instr
->dest
.saturate
);
877 case nir_op_unpack_half_2x16_split_y
:
878 emit_percomp(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0],
879 instr
->dest
.write_mask
, instr
->dest
.saturate
);
883 emit_percomp(SHADER_OPCODE_POW
, result
, op
[0], op
[1],
884 instr
->dest
.write_mask
, instr
->dest
.saturate
);
887 case nir_op_bitfield_reverse
:
888 emit_percomp(BFREV(result
, op
[0]), instr
->dest
.write_mask
);
891 case nir_op_bit_count
:
892 emit_percomp(CBIT(result
, op
[0]), instr
->dest
.write_mask
);
895 case nir_op_ufind_msb
:
896 case nir_op_ifind_msb
: {
897 emit_percomp(FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]),
898 instr
->dest
.write_mask
);
900 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
901 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
902 * subtract the result from 31 to convert the MSB count into an LSB count.
905 emit_percomp(CMP(reg_null_d
, result
, fs_reg(-1), BRW_CONDITIONAL_NZ
),
906 instr
->dest
.write_mask
);
907 fs_reg
neg_result(result
);
908 neg_result
.negate
= true;
909 fs_inst
*inst
= ADD(result
, neg_result
, fs_reg(31));
910 inst
->predicate
= BRW_PREDICATE_NORMAL
;
911 emit_percomp(inst
, instr
->dest
.write_mask
);
915 case nir_op_find_lsb
:
916 emit_percomp(FBL(result
, op
[0]), instr
->dest
.write_mask
);
919 case nir_op_ubitfield_extract
:
920 case nir_op_ibitfield_extract
:
921 emit_percomp(BFE(result
, op
[2], op
[1], op
[0]), instr
->dest
.write_mask
);
924 emit_percomp(BFI1(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
927 emit_percomp(BFI2(result
, op
[0], op
[1], op
[2]), instr
->dest
.write_mask
);
930 case nir_op_bitfield_insert
:
931 unreachable("not reached: should be handled by "
932 "lower_instructions::bitfield_insert_to_bfm_bfi");
935 emit_percomp(SHL(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
938 emit_percomp(ASR(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
941 emit_percomp(SHR(result
, op
[0], op
[1]), instr
->dest
.write_mask
);
944 case nir_op_pack_half_2x16_split
:
945 emit_percomp(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1],
946 instr
->dest
.write_mask
);
950 emit_percomp(MAD(result
, op
[2], op
[1], op
[0]), instr
->dest
.write_mask
);
954 /* TODO emulate for gen < 6 */
955 emit_percomp(LRP(result
, op
[2], op
[1], op
[0]), instr
->dest
.write_mask
);
959 for (unsigned i
= 0; i
< 4; i
++) {
960 if (!((instr
->dest
.write_mask
>> i
) & 1))
963 emit(CMP(reg_null_d
, offset(op
[0], i
), fs_reg(0), BRW_CONDITIONAL_NZ
));
964 emit(SEL(offset(result
, i
), offset(op
[1], i
), offset(op
[2], i
)))
965 ->predicate
= BRW_PREDICATE_NORMAL
;
970 unreachable("unhandled instruction");
975 fs_visitor::get_nir_src(nir_src src
)
978 assert(src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
);
979 nir_load_const_instr
*load
= nir_instr_as_load_const(src
.ssa
->parent_instr
);
980 fs_reg
reg(GRF
, virtual_grf_alloc(src
.ssa
->num_components
),
981 BRW_REGISTER_TYPE_D
);
983 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
984 emit(MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
])));
989 if (src
.reg
.reg
->is_global
)
990 reg
= nir_globals
[src
.reg
.reg
->index
];
992 reg
= nir_locals
[src
.reg
.reg
->index
];
994 /* to avoid floating-point denorm flushing problems, set the type by
995 * default to D - instructions that need floating point semantics will set
996 * this to F if they need to
998 reg
.type
= BRW_REGISTER_TYPE_D
;
999 reg
.reg_offset
= src
.reg
.base_offset
;
1000 if (src
.reg
.indirect
) {
1001 reg
.reladdr
= new(mem_ctx
) fs_reg();
1002 *reg
.reladdr
= retype(get_nir_src(*src
.reg
.indirect
),
1003 BRW_REGISTER_TYPE_D
);
1011 fs_visitor::get_nir_alu_src(nir_alu_instr
*instr
, unsigned src
)
1013 fs_reg reg
= get_nir_src(instr
->src
[src
].src
);
1015 reg
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[src
]);
1016 reg
.abs
= instr
->src
[src
].abs
;
1017 reg
.negate
= instr
->src
[src
].negate
;
1019 bool needs_swizzle
= false;
1020 unsigned num_components
= 0;
1021 for (unsigned i
= 0; i
< 4; i
++) {
1022 if (!nir_alu_instr_channel_used(instr
, src
, i
))
1025 if (instr
->src
[src
].swizzle
[i
] != i
)
1026 needs_swizzle
= true;
1028 num_components
= i
+ 1;
1031 if (needs_swizzle
) {
1032 /* resolve the swizzle through MOV's */
1033 fs_reg new_reg
= fs_reg(GRF
, virtual_grf_alloc(num_components
), reg
.type
);
1035 for (unsigned i
= 0; i
< 4; i
++) {
1036 if (!nir_alu_instr_channel_used(instr
, src
, i
))
1039 emit(MOV(offset(new_reg
, i
),
1040 offset(reg
, instr
->src
[src
].swizzle
[i
])));
1050 fs_visitor::get_nir_dest(nir_dest dest
)
1053 if (dest
.reg
.reg
->is_global
)
1054 reg
= nir_globals
[dest
.reg
.reg
->index
];
1056 reg
= nir_locals
[dest
.reg
.reg
->index
];
1058 reg
.reg_offset
= dest
.reg
.base_offset
;
1059 if (dest
.reg
.indirect
) {
1060 reg
.reladdr
= new(mem_ctx
) fs_reg();
1061 *reg
.reladdr
= retype(get_nir_src(*dest
.reg
.indirect
),
1062 BRW_REGISTER_TYPE_D
);
1069 fs_visitor::emit_percomp(fs_inst
*inst
, unsigned wr_mask
)
1071 for (unsigned i
= 0; i
< 4; i
++) {
1072 if (!((wr_mask
>> i
) & 1))
1075 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(*inst
);
1076 new_inst
->dst
.reg_offset
+= i
;
1077 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1078 if (inst
->src
[j
].file
== GRF
)
1079 new_inst
->src
[j
].reg_offset
+= i
;
1086 fs_visitor::emit_percomp(enum opcode op
, fs_reg dest
, fs_reg src0
,
1087 unsigned wr_mask
, bool saturate
,
1088 enum brw_predicate predicate
,
1089 enum brw_conditional_mod mod
)
1091 for (unsigned i
= 0; i
< 4; i
++) {
1092 if (!((wr_mask
>> i
) & 1))
1095 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(op
, dest
, src0
);
1096 new_inst
->dst
.reg_offset
+= i
;
1097 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1098 if (new_inst
->src
[j
].file
== GRF
)
1099 new_inst
->src
[j
].reg_offset
+= i
;
1101 new_inst
->predicate
= predicate
;
1102 new_inst
->conditional_mod
= mod
;
1103 new_inst
->saturate
= saturate
;
1109 fs_visitor::emit_percomp(enum opcode op
, fs_reg dest
, fs_reg src0
, fs_reg src1
,
1110 unsigned wr_mask
, bool saturate
,
1111 enum brw_predicate predicate
,
1112 enum brw_conditional_mod mod
)
1114 for (unsigned i
= 0; i
< 4; i
++) {
1115 if (!((wr_mask
>> i
) & 1))
1118 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(op
, dest
, src0
, src1
);
1119 new_inst
->dst
.reg_offset
+= i
;
1120 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1121 if (new_inst
->src
[j
].file
== GRF
)
1122 new_inst
->src
[j
].reg_offset
+= i
;
1124 new_inst
->predicate
= predicate
;
1125 new_inst
->conditional_mod
= mod
;
1126 new_inst
->saturate
= saturate
;
1132 fs_visitor::emit_math_percomp(enum opcode op
, fs_reg dest
, fs_reg src0
,
1133 unsigned wr_mask
, bool saturate
)
1135 for (unsigned i
= 0; i
< 4; i
++) {
1136 if (!((wr_mask
>> i
) & 1))
1139 fs_reg new_dest
= dest
;
1140 new_dest
.reg_offset
+= i
;
1141 fs_reg new_src0
= src0
;
1142 if (src0
.file
== GRF
)
1143 new_src0
.reg_offset
+= i
;
1145 fs_inst
*new_inst
= emit_math(op
, new_dest
, new_src0
);
1146 new_inst
->saturate
= saturate
;
1151 fs_visitor::emit_math_percomp(enum opcode op
, fs_reg dest
, fs_reg src0
,
1152 fs_reg src1
, unsigned wr_mask
,
1155 for (unsigned i
= 0; i
< 4; i
++) {
1156 if (!((wr_mask
>> i
) & 1))
1159 fs_reg new_dest
= dest
;
1160 new_dest
.reg_offset
+= i
;
1161 fs_reg new_src0
= src0
;
1162 if (src0
.file
== GRF
)
1163 new_src0
.reg_offset
+= i
;
1164 fs_reg new_src1
= src1
;
1165 if (src1
.file
== GRF
)
1166 new_src1
.reg_offset
+= i
;
1168 fs_inst
*new_inst
= emit_math(op
, new_dest
, new_src0
, new_src1
);
1169 new_inst
->saturate
= saturate
;
1174 fs_visitor::emit_reduction(enum opcode op
, fs_reg dest
, fs_reg src
,
1175 unsigned num_components
)
1181 if (num_components
== 2) {
1182 emit(op
, dest
, src0
, src1
);
1186 fs_reg temp1
= fs_reg(GRF
, virtual_grf_alloc(1));
1187 temp1
.type
= src
.type
;
1188 emit(op
, temp1
, src0
, src1
);
1191 src2
.reg_offset
+= 2;
1193 if (num_components
== 3) {
1194 emit(op
, dest
, temp1
, src2
);
1198 assert(num_components
== 4);
1201 src3
.reg_offset
+= 3;
1202 fs_reg temp2
= fs_reg(GRF
, virtual_grf_alloc(1));
1203 temp2
.type
= src
.type
;
1205 emit(op
, temp2
, src2
, src3
);
1206 emit(op
, dest
, temp1
, temp2
);
1210 fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
1213 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1214 dest
= get_nir_dest(instr
->dest
);
1216 bool has_indirect
= false;
1218 switch (instr
->intrinsic
) {
1219 case nir_intrinsic_discard
: {
1220 /* We track our discarded pixels in f0.1. By predicating on it, we can
1221 * update just the flag bits that aren't yet discarded. By emitting a
1222 * CMP of g0 != g0, all our currently executing channels will get turned
1225 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1226 BRW_REGISTER_TYPE_UW
));
1227 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
1228 BRW_CONDITIONAL_NZ
));
1229 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1230 cmp
->flag_subreg
= 1;
1232 if (brw
->gen
>= 6) {
1233 /* For performance, after a discard, jump to the end of the shader.
1234 * Only jump if all relevant channels have been discarded.
1236 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1237 discard_jump
->flag_subreg
= 1;
1239 discard_jump
->predicate
= (dispatch_width
== 8)
1240 ? BRW_PREDICATE_ALIGN1_ANY8H
1241 : BRW_PREDICATE_ALIGN1_ANY16H
;
1242 discard_jump
->predicate_inverse
= true;
1248 case nir_intrinsic_atomic_counter_inc
:
1249 case nir_intrinsic_atomic_counter_dec
:
1250 case nir_intrinsic_atomic_counter_read
: {
1251 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1252 (unsigned) instr
->const_index
[0];
1253 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1255 switch (instr
->intrinsic
) {
1256 case nir_intrinsic_atomic_counter_inc
:
1257 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1258 fs_reg(), fs_reg());
1260 case nir_intrinsic_atomic_counter_dec
:
1261 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1262 fs_reg(), fs_reg());
1264 case nir_intrinsic_atomic_counter_read
:
1265 emit_untyped_surface_read(surf_index
, dest
, offset
);
1268 unreachable("Unreachable");
1273 case nir_intrinsic_load_front_face
:
1276 case nir_intrinsic_load_sample_mask_in
: {
1277 assert(brw
->gen
>= 7);
1278 fs_reg reg
= fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1279 BRW_REGISTER_TYPE_D
));
1280 dest
.type
= reg
.type
;
1281 emit(MOV(dest
, reg
));
1285 case nir_intrinsic_load_sample_pos
: {
1286 fs_reg
*reg
= emit_samplepos_setup();
1287 dest
.type
= reg
->type
;
1288 emit(MOV(dest
, *reg
));
1289 emit(MOV(offset(dest
, 1), offset(*reg
, 1)));
1293 case nir_intrinsic_load_sample_id
: {
1294 fs_reg
*reg
= emit_sampleid_setup();
1295 dest
.type
= reg
->type
;
1296 emit(MOV(dest
, *reg
));
1300 case nir_intrinsic_load_uniform_indirect
:
1301 has_indirect
= true;
1302 case nir_intrinsic_load_uniform
: {
1304 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1305 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1306 fs_reg src
= nir_uniforms
;
1307 src
.reg_offset
= instr
->const_index
[0] + index
;
1309 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1310 src
.type
= dest
.type
;
1313 emit(MOV(dest
, src
));
1320 case nir_intrinsic_load_ubo_indirect
:
1321 has_indirect
= true;
1322 case nir_intrinsic_load_ubo
: {
1323 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1327 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1330 /* The block index is not a constant. Evaluate the index expression
1331 * per-channel and add the base UBO index; the generator will select
1332 * a value from any live channel.
1334 surf_index
= fs_reg(this, glsl_type::uint_type
);
1335 emit(ADD(surf_index
, get_nir_src(instr
->src
[0]),
1336 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1337 ->force_writemask_all
= true;
1339 /* Assume this may touch any UBO. It would be nice to provide
1340 * a tighter bound, but the array information is already lowered away.
1342 brw_mark_surface_used(prog_data
,
1343 stage_prog_data
->binding_table
.ubo_start
+
1344 shader_prog
->NumUniformBlocks
- 1);
1348 /* Turn the byte offset into a dword offset. */
1349 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
1350 emit(SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1351 BRW_REGISTER_TYPE_D
),
1354 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1355 for (int i
= 0; i
< instr
->num_components
; i
++)
1356 emit(VARYING_PULL_CONSTANT_LOAD(offset(dest
, i
), surf_index
,
1357 base_offset
, vec4_offset
+ i
));
1359 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
1360 packed_consts
.type
= dest
.type
;
1362 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1363 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1364 surf_index
, const_offset_reg
);
1366 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1367 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1369 /* The std140 packing rules don't allow vectors to cross 16-byte
1370 * boundaries, and a reg is 32 bytes.
1372 assert(packed_consts
.subreg_offset
< 32);
1374 emit(MOV(dest
, packed_consts
));
1381 case nir_intrinsic_load_input_indirect
:
1382 has_indirect
= true;
1383 case nir_intrinsic_load_input
: {
1385 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1386 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1387 fs_reg src
= nir_inputs
;
1388 src
.reg_offset
= instr
->const_index
[0] + index
;
1390 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1391 src
.type
= dest
.type
;
1394 emit(MOV(dest
, src
));
1401 /* Handle ARB_gpu_shader5 interpolation intrinsics
1403 * It's worth a quick word of explanation as to why we handle the full
1404 * variable-based interpolation intrinsic rather than a lowered version
1405 * with like we do for other inputs. We have to do that because the way
1406 * we set up inputs doesn't allow us to use the already setup inputs for
1407 * interpolation. At the beginning of the shader, we go through all of
1408 * the input variables and do the initial interpolation and put it in
1409 * the nir_inputs array based on its location as determined in
1410 * nir_lower_io. If the input isn't used, dead code cleans up and
1411 * everything works fine. However, when we get to the ARB_gpu_shader5
1412 * interpolation intrinsics, we need to reinterpolate the input
1413 * differently. If we used an intrinsic that just had an index it would
1414 * only give us the offset into the nir_inputs array. However, this is
1415 * useless because that value is post-interpolation and we need
1416 * pre-interpolation. In order to get the actual location of the bits
1417 * we get from the vertex fetching hardware, we need the variable.
1419 case nir_intrinsic_interp_var_at_centroid
:
1420 case nir_intrinsic_interp_var_at_sample
:
1421 case nir_intrinsic_interp_var_at_offset
: {
1422 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1423 * 8 channels at a time, same as the barycentric coords presented in
1424 * the FS payload. this requires a bit of extra work to support.
1426 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1428 fs_reg
dst_x(GRF
, virtual_grf_alloc(2), BRW_REGISTER_TYPE_F
);
1429 fs_reg dst_y
= offset(dst_x
, 1);
1431 /* For most messages, we need one reg of ignored data; the hardware
1432 * requires mlen==1 even when there is no payload. in the per-slot
1433 * offset case, we'll replace this with the proper source data.
1435 fs_reg
src(this, glsl_type::float_type
);
1436 int mlen
= 1; /* one reg unless overriden */
1439 switch (instr
->intrinsic
) {
1440 case nir_intrinsic_interp_var_at_centroid
:
1441 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
1444 case nir_intrinsic_interp_var_at_sample
: {
1445 /* XXX: We should probably handle non-constant sample id's */
1446 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1447 assert(const_sample
);
1448 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1449 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
,
1454 case nir_intrinsic_interp_var_at_offset
: {
1455 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1458 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1459 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1461 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
1462 fs_reg(off_x
| (off_y
<< 4)));
1464 src
= fs_reg(this, glsl_type::ivec2_type
);
1465 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1466 BRW_REGISTER_TYPE_F
);
1467 for (int i
= 0; i
< 2; i
++) {
1468 fs_reg
temp(this, glsl_type::float_type
);
1469 emit(MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
)));
1470 fs_reg
itemp(this, glsl_type::int_type
);
1471 emit(MOV(itemp
, temp
)); /* float to int */
1473 /* Clamp the upper end of the range to +7/16.
1474 * ARB_gpu_shader5 requires that we support a maximum offset
1475 * of +0.5, which isn't representable in a S0.4 value -- if
1476 * we didn't clamp it, we'd end up with -8/16, which is the
1477 * opposite of what the shader author wanted.
1479 * This is legal due to ARB_gpu_shader5's quantization
1482 * "Not all values of <offset> may be supported; x and y
1483 * offsets may be rounded to fixed-point values with the
1484 * number of fraction bits given by the
1485 * implementation-dependent constant
1486 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1489 emit(BRW_OPCODE_SEL
, offset(src
, i
), itemp
, fs_reg(7))
1490 ->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
1494 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
1501 unreachable("Invalid intrinsic");
1505 inst
->regs_written
= 2; /* 2 floats per slot returned */
1506 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1507 INTERP_QUALIFIER_NOPERSPECTIVE
;
1509 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1510 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1511 src
.type
= dest
.type
;
1513 emit(FS_OPCODE_LINTERP
, dest
, dst_x
, dst_y
, src
);
1519 case nir_intrinsic_store_output_indirect
:
1520 has_indirect
= true;
1521 case nir_intrinsic_store_output
: {
1522 fs_reg src
= get_nir_src(instr
->src
[0]);
1524 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1525 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1526 fs_reg new_dest
= nir_outputs
;
1527 new_dest
.reg_offset
= instr
->const_index
[0] + index
;
1529 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1530 new_dest
.type
= src
.type
;
1532 emit(MOV(new_dest
, src
));
1540 unreachable("unknown intrinsic");
1545 fs_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1547 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1548 unsigned sampler
= instr
->sampler_index
;
1549 fs_reg
sampler_reg(sampler
);
1551 /* FINISHME: We're failing to recompile our programs when the sampler is
1552 * updated. This only matters for the texture rectangle scale parameters
1553 * (pre-gen6, or gen6+ with GL_CLAMP).
1555 int texunit
= prog
->SamplerUnits
[sampler
];
1557 int gather_component
= instr
->component
;
1559 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1561 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1564 int lod_components
, offset_components
= 0;
1566 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, offset
;
1568 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1569 fs_reg src
= get_nir_src(instr
->src
[i
]);
1570 switch (instr
->src_type
[i
]) {
1571 case nir_tex_src_bias
:
1572 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1574 case nir_tex_src_comparitor
:
1575 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1577 case nir_tex_src_coord
:
1578 switch (instr
->op
) {
1580 case nir_texop_txf_ms
:
1581 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1584 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1588 case nir_tex_src_ddx
:
1589 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1590 lod_components
= nir_tex_instr_src_size(instr
, i
);
1592 case nir_tex_src_ddy
:
1593 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1595 case nir_tex_src_lod
:
1596 switch (instr
->op
) {
1598 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1601 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1604 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1608 case nir_tex_src_ms_index
:
1609 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1611 case nir_tex_src_offset
:
1612 offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1613 if (instr
->is_array
)
1614 offset_components
= instr
->coord_components
- 1;
1616 offset_components
= instr
->coord_components
;
1618 case nir_tex_src_projector
:
1619 unreachable("should be lowered");
1621 case nir_tex_src_sampler_offset
: {
1622 /* Figure out the highest possible sampler index and mark it as used */
1623 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1624 if (instr
->op
== nir_texop_tg4
&& brw
->gen
< 8) {
1625 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1627 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1629 brw_mark_surface_used(prog_data
, max_used
);
1631 /* Emit code to evaluate the actual indexing expression */
1632 sampler_reg
= fs_reg(this, glsl_type::uint_type
);
1633 emit(ADD(sampler_reg
, src
, fs_reg(sampler
)))
1634 ->force_writemask_all
= true;
1639 unreachable("unknown texture source");
1643 if (instr
->op
== nir_texop_txf_ms
) {
1644 if (brw
->gen
>= 7 && key
->tex
.compressed_multisample_layout_mask
& (1<<sampler
))
1645 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1650 for (unsigned i
= 0; i
< 3; i
++) {
1651 if (instr
->const_offset
[i
] != 0) {
1652 assert(offset_components
== 0);
1653 offset
= fs_reg(brw_texture_offset(ctx
, instr
->const_offset
, 3));
1658 enum glsl_base_type dest_base_type
;
1659 switch (instr
->dest_type
) {
1660 case nir_type_float
:
1661 dest_base_type
= GLSL_TYPE_FLOAT
;
1664 dest_base_type
= GLSL_TYPE_INT
;
1666 case nir_type_unsigned
:
1667 dest_base_type
= GLSL_TYPE_UINT
;
1670 unreachable("bad type");
1673 const glsl_type
*dest_type
=
1674 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1677 ir_texture_opcode op
;
1678 switch (instr
->op
) {
1679 case nir_texop_lod
: op
= ir_lod
; break;
1680 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1681 case nir_texop_tex
: op
= ir_tex
; break;
1682 case nir_texop_tg4
: op
= ir_tg4
; break;
1683 case nir_texop_txb
: op
= ir_txb
; break;
1684 case nir_texop_txd
: op
= ir_txd
; break;
1685 case nir_texop_txf
: op
= ir_txf
; break;
1686 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1687 case nir_texop_txl
: op
= ir_txl
; break;
1688 case nir_texop_txs
: op
= ir_txs
; break;
1690 unreachable("unknown texture opcode");
1693 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1694 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1695 offset
, offset_components
, mcs
, gather_component
,
1696 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1698 fs_reg dest
= get_nir_dest(instr
->dest
);
1699 dest
.type
= this->result
.type
;
1700 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1701 emit_percomp(MOV(dest
, this->result
), (1 << num_components
) - 1);
1705 fs_visitor::nir_emit_load_const(nir_load_const_instr
*instr
)
1707 /* Bail on SSA constant loads. These are used for immediates. */
1708 if (instr
->dest
.is_ssa
)
1711 fs_reg dest
= get_nir_dest(instr
->dest
);
1712 dest
.type
= BRW_REGISTER_TYPE_UD
;
1713 if (instr
->array_elems
== 0) {
1714 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1715 emit(MOV(dest
, fs_reg(instr
->value
.u
[i
])));
1719 for (unsigned i
= 0; i
< instr
->array_elems
; i
++) {
1720 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1721 emit(MOV(dest
, fs_reg(instr
->array
[i
].u
[j
])));
1729 fs_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1731 switch (instr
->type
) {
1732 case nir_jump_break
:
1733 emit(BRW_OPCODE_BREAK
);
1735 case nir_jump_continue
:
1736 emit(BRW_OPCODE_CONTINUE
);
1738 case nir_jump_return
:
1740 unreachable("unknown jump");