2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
32 #include "brw_fs_surface_builder.h"
33 #include "brw_vec4_gs_visitor.h"
36 using namespace brw::surface_access
;
39 fs_visitor::emit_nir_code()
41 /* emit the arrays used for inputs and outputs - load/store intrinsics will
42 * be converted to reads/writes of these arrays
47 nir_emit_system_values();
49 /* get the main function and emit it */
50 nir_foreach_overload(nir
, overload
) {
51 assert(strcmp(overload
->function
->name
, "main") == 0);
52 assert(overload
->impl
);
53 nir_emit_impl(overload
->impl
);
58 fs_visitor::nir_setup_inputs()
60 if (stage
!= MESA_SHADER_FRAGMENT
)
63 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
65 nir_foreach_variable(var
, &nir
->inputs
) {
66 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
69 if (var
->data
.location
== VARYING_SLOT_POS
) {
70 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
71 var
->data
.origin_upper_left
);
72 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
74 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
78 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
79 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
80 reg
.type
= BRW_REGISTER_TYPE_D
;
81 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
83 emit_general_interpolation(input
, var
->name
, var
->type
,
84 (glsl_interp_qualifier
) var
->data
.interpolation
,
85 var
->data
.location
, var
->data
.centroid
,
92 fs_visitor::nir_setup_outputs()
94 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
96 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
98 nir_foreach_variable(var
, &nir
->outputs
) {
99 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
101 int vector_elements
= var
->type
->without_array()->vector_elements
;
104 case MESA_SHADER_VERTEX
:
105 for (unsigned int i
= 0; i
< ALIGN(type_size_scalar(var
->type
), 4) / 4; i
++) {
106 int output
= var
->data
.location
+ i
;
107 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
108 this->output_components
[output
] = vector_elements
;
111 case MESA_SHADER_FRAGMENT
:
112 if (var
->data
.index
> 0) {
113 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
114 assert(var
->data
.index
== 1);
115 this->dual_src_output
= reg
;
116 this->do_dual_src
= true;
117 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
118 /* Writing gl_FragColor outputs to all color regions. */
119 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
120 this->outputs
[i
] = reg
;
121 this->output_components
[i
] = 4;
123 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
124 this->frag_depth
= reg
;
125 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
126 this->frag_stencil
= reg
;
127 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
128 this->sample_mask
= reg
;
130 /* gl_FragData or a user-defined FS output */
131 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
132 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
134 /* General color output. */
135 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
136 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
137 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
138 this->output_components
[output
] = vector_elements
;
143 unreachable("unhandled shader stage");
149 fs_visitor::nir_setup_uniforms()
151 if (dispatch_width
!= 8)
154 uniforms
= nir
->num_uniforms
;
156 nir_foreach_variable(var
, &nir
->uniforms
) {
157 /* UBO's and atomics don't take up space in the uniform file */
158 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
161 if (type_size_scalar(var
->type
) > 0)
162 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
167 emit_system_values_block(nir_block
*block
, void *void_visitor
)
169 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
172 nir_foreach_instr(block
, instr
) {
173 if (instr
->type
!= nir_instr_type_intrinsic
)
176 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
177 switch (intrin
->intrinsic
) {
178 case nir_intrinsic_load_vertex_id
:
179 unreachable("should be lowered by lower_vertex_id().");
181 case nir_intrinsic_load_vertex_id_zero_base
:
182 assert(v
->stage
== MESA_SHADER_VERTEX
);
183 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
184 if (reg
->file
== BAD_FILE
)
185 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
188 case nir_intrinsic_load_base_vertex
:
189 assert(v
->stage
== MESA_SHADER_VERTEX
);
190 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
191 if (reg
->file
== BAD_FILE
)
192 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
195 case nir_intrinsic_load_instance_id
:
196 assert(v
->stage
== MESA_SHADER_VERTEX
);
197 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
198 if (reg
->file
== BAD_FILE
)
199 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
202 case nir_intrinsic_load_invocation_id
:
203 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
204 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
205 if (reg
->file
== BAD_FILE
) {
206 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
207 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
208 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
209 abld
.SHR(iid
, g1
, fs_reg(27u));
214 case nir_intrinsic_load_sample_pos
:
215 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
216 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
217 if (reg
->file
== BAD_FILE
)
218 *reg
= *v
->emit_samplepos_setup();
221 case nir_intrinsic_load_sample_id
:
222 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= *v
->emit_sampleid_setup();
228 case nir_intrinsic_load_sample_mask_in
:
229 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
230 assert(v
->devinfo
->gen
>= 7);
231 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
232 if (reg
->file
== BAD_FILE
)
233 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
234 BRW_REGISTER_TYPE_D
));
237 case nir_intrinsic_load_local_invocation_id
:
238 assert(v
->stage
== MESA_SHADER_COMPUTE
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
240 if (reg
->file
== BAD_FILE
)
241 *reg
= *v
->emit_cs_local_invocation_id_setup();
244 case nir_intrinsic_load_work_group_id
:
245 assert(v
->stage
== MESA_SHADER_COMPUTE
);
246 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
247 if (reg
->file
== BAD_FILE
)
248 *reg
= *v
->emit_cs_work_group_id_setup();
260 fs_visitor::nir_emit_system_values()
262 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
263 nir_foreach_overload(nir
, overload
) {
264 assert(strcmp(overload
->function
->name
, "main") == 0);
265 assert(overload
->impl
);
266 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
271 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
273 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
274 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
275 unsigned array_elems
=
276 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
277 unsigned size
= array_elems
* reg
->num_components
;
278 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
281 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
284 nir_emit_cf_list(&impl
->body
);
288 fs_visitor::nir_emit_cf_list(exec_list
*list
)
290 exec_list_validate(list
);
291 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
292 switch (node
->type
) {
294 nir_emit_if(nir_cf_node_as_if(node
));
297 case nir_cf_node_loop
:
298 nir_emit_loop(nir_cf_node_as_loop(node
));
301 case nir_cf_node_block
:
302 nir_emit_block(nir_cf_node_as_block(node
));
306 unreachable("Invalid CFG node block");
312 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
314 /* first, put the condition into f0 */
315 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
316 retype(get_nir_src(if_stmt
->condition
),
317 BRW_REGISTER_TYPE_D
));
318 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
320 bld
.IF(BRW_PREDICATE_NORMAL
);
322 nir_emit_cf_list(&if_stmt
->then_list
);
324 /* note: if the else is empty, dead CF elimination will remove it */
325 bld
.emit(BRW_OPCODE_ELSE
);
327 nir_emit_cf_list(&if_stmt
->else_list
);
329 bld
.emit(BRW_OPCODE_ENDIF
);
333 fs_visitor::nir_emit_loop(nir_loop
*loop
)
335 bld
.emit(BRW_OPCODE_DO
);
337 nir_emit_cf_list(&loop
->body
);
339 bld
.emit(BRW_OPCODE_WHILE
);
343 fs_visitor::nir_emit_block(nir_block
*block
)
345 nir_foreach_instr(block
, instr
) {
346 nir_emit_instr(instr
);
351 fs_visitor::nir_emit_instr(nir_instr
*instr
)
353 const fs_builder abld
= bld
.annotate(NULL
, instr
);
355 switch (instr
->type
) {
356 case nir_instr_type_alu
:
357 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
360 case nir_instr_type_intrinsic
:
361 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
364 case nir_instr_type_tex
:
365 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
368 case nir_instr_type_load_const
:
369 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
372 case nir_instr_type_ssa_undef
:
373 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
376 case nir_instr_type_jump
:
377 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
381 unreachable("unknown instruction type");
386 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
387 const fs_reg
&result
)
389 if (!instr
->src
[0].src
.is_ssa
||
390 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
393 nir_intrinsic_instr
*src0
=
394 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
396 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
399 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
400 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
403 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
404 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
407 fs_reg tmp
= vgrf(glsl_type::int_type
);
409 if (devinfo
->gen
>= 6) {
410 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
411 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
413 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
415 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
416 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
418 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
420 * This negation looks like it's safe in practice, because bits 0:4 will
421 * surely be TRIANGLES
424 if (value1
->f
[0] == -1.0f
) {
428 tmp
.type
= BRW_REGISTER_TYPE_W
;
429 tmp
.subreg_offset
= 2;
432 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
433 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
435 tmp
.type
= BRW_REGISTER_TYPE_D
;
436 tmp
.subreg_offset
= 0;
439 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
440 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
442 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
444 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
445 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
447 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
449 * This negation looks like it's safe in practice, because bits 0:4 will
450 * surely be TRIANGLES
453 if (value1
->f
[0] == -1.0f
) {
457 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
459 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
465 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
467 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
470 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
471 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
474 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
475 op
[i
] = get_nir_src(instr
->src
[i
].src
);
476 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
477 op
[i
].abs
= instr
->src
[i
].abs
;
478 op
[i
].negate
= instr
->src
[i
].negate
;
481 /* We get a bunch of mov's out of the from_ssa pass and they may still
482 * be vectorized. We'll handle them as a special-case. We'll also
483 * handle vecN here because it's basically the same thing.
491 fs_reg temp
= result
;
492 bool need_extra_copy
= false;
493 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
494 if (!instr
->src
[i
].src
.is_ssa
&&
495 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
496 need_extra_copy
= true;
497 temp
= bld
.vgrf(result
.type
, 4);
502 for (unsigned i
= 0; i
< 4; i
++) {
503 if (!(instr
->dest
.write_mask
& (1 << i
)))
506 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
507 inst
= bld
.MOV(offset(temp
, bld
, i
),
508 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
510 inst
= bld
.MOV(offset(temp
, bld
, i
),
511 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
513 inst
->saturate
= instr
->dest
.saturate
;
516 /* In this case the source and destination registers were the same,
517 * so we need to insert an extra set of moves in order to deal with
520 if (need_extra_copy
) {
521 for (unsigned i
= 0; i
< 4; i
++) {
522 if (!(instr
->dest
.write_mask
& (1 << i
)))
525 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
534 /* At this point, we have dealt with any instruction that operates on
535 * more than a single channel. Therefore, we can just adjust the source
536 * and destination registers for that channel and emit the instruction.
538 unsigned channel
= 0;
539 if (nir_op_infos
[instr
->op
].output_size
== 0) {
540 /* Since NIR is doing the scalarizing for us, we should only ever see
541 * vectorized operations with a single channel.
543 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
544 channel
= ffs(instr
->dest
.write_mask
) - 1;
546 result
= offset(result
, bld
, channel
);
549 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
550 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
551 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
557 inst
= bld
.MOV(result
, op
[0]);
558 inst
->saturate
= instr
->dest
.saturate
;
563 bld
.MOV(result
, op
[0]);
567 /* AND(val, 0x80000000) gives the sign bit.
569 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
572 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
574 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
575 op
[0].type
= BRW_REGISTER_TYPE_UD
;
576 result
.type
= BRW_REGISTER_TYPE_UD
;
577 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
579 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
580 inst
->predicate
= BRW_PREDICATE_NORMAL
;
581 if (instr
->dest
.saturate
) {
582 inst
= bld
.MOV(result
, result
);
583 inst
->saturate
= true;
589 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
590 * -> non-negative val generates 0x00000000.
591 * Predicated OR sets 1 if val is positive.
593 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
594 bld
.ASR(result
, op
[0], fs_reg(31));
595 inst
= bld
.OR(result
, result
, fs_reg(1));
596 inst
->predicate
= BRW_PREDICATE_NORMAL
;
600 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
601 inst
->saturate
= instr
->dest
.saturate
;
605 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
606 inst
->saturate
= instr
->dest
.saturate
;
610 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
611 inst
->saturate
= instr
->dest
.saturate
;
615 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
616 inst
->saturate
= instr
->dest
.saturate
;
620 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
621 inst
->saturate
= instr
->dest
.saturate
;
625 if (fs_key
->high_quality_derivatives
) {
626 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
628 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
630 inst
->saturate
= instr
->dest
.saturate
;
632 case nir_op_fddx_fine
:
633 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
634 inst
->saturate
= instr
->dest
.saturate
;
636 case nir_op_fddx_coarse
:
637 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
638 inst
->saturate
= instr
->dest
.saturate
;
641 if (fs_key
->high_quality_derivatives
) {
642 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
643 fs_reg(fs_key
->render_to_fbo
));
645 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
646 fs_reg(fs_key
->render_to_fbo
));
648 inst
->saturate
= instr
->dest
.saturate
;
650 case nir_op_fddy_fine
:
651 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
652 fs_reg(fs_key
->render_to_fbo
));
653 inst
->saturate
= instr
->dest
.saturate
;
655 case nir_op_fddy_coarse
:
656 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
657 fs_reg(fs_key
->render_to_fbo
));
658 inst
->saturate
= instr
->dest
.saturate
;
663 inst
= bld
.ADD(result
, op
[0], op
[1]);
664 inst
->saturate
= instr
->dest
.saturate
;
668 inst
= bld
.MUL(result
, op
[0], op
[1]);
669 inst
->saturate
= instr
->dest
.saturate
;
673 bld
.MUL(result
, op
[0], op
[1]);
676 case nir_op_imul_high
:
677 case nir_op_umul_high
:
678 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
683 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
686 case nir_op_uadd_carry
:
687 unreachable("Should have been lowered by carry_to_arith().");
689 case nir_op_usub_borrow
:
690 unreachable("Should have been lowered by borrow_to_arith().");
693 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
699 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
705 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
710 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
715 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
719 if (devinfo
->gen
>= 8) {
720 op
[0] = resolve_source_modifiers(op
[0]);
722 bld
.NOT(result
, op
[0]);
725 if (devinfo
->gen
>= 8) {
726 op
[0] = resolve_source_modifiers(op
[0]);
727 op
[1] = resolve_source_modifiers(op
[1]);
729 bld
.XOR(result
, op
[0], op
[1]);
732 if (devinfo
->gen
>= 8) {
733 op
[0] = resolve_source_modifiers(op
[0]);
734 op
[1] = resolve_source_modifiers(op
[1]);
736 bld
.OR(result
, op
[0], op
[1]);
739 if (devinfo
->gen
>= 8) {
740 op
[0] = resolve_source_modifiers(op
[0]);
741 op
[1] = resolve_source_modifiers(op
[1]);
743 bld
.AND(result
, op
[0], op
[1]);
755 case nir_op_ball_fequal2
:
756 case nir_op_ball_iequal2
:
757 case nir_op_ball_fequal3
:
758 case nir_op_ball_iequal3
:
759 case nir_op_ball_fequal4
:
760 case nir_op_ball_iequal4
:
761 case nir_op_bany_fnequal2
:
762 case nir_op_bany_inequal2
:
763 case nir_op_bany_fnequal3
:
764 case nir_op_bany_inequal3
:
765 case nir_op_bany_fnequal4
:
766 case nir_op_bany_inequal4
:
767 unreachable("Lowered by nir_lower_alu_reductions");
769 case nir_op_fnoise1_1
:
770 case nir_op_fnoise1_2
:
771 case nir_op_fnoise1_3
:
772 case nir_op_fnoise1_4
:
773 case nir_op_fnoise2_1
:
774 case nir_op_fnoise2_2
:
775 case nir_op_fnoise2_3
:
776 case nir_op_fnoise2_4
:
777 case nir_op_fnoise3_1
:
778 case nir_op_fnoise3_2
:
779 case nir_op_fnoise3_3
:
780 case nir_op_fnoise3_4
:
781 case nir_op_fnoise4_1
:
782 case nir_op_fnoise4_2
:
783 case nir_op_fnoise4_3
:
784 case nir_op_fnoise4_4
:
785 unreachable("not reached: should be handled by lower_noise");
788 unreachable("not reached: should be handled by ldexp_to_arith()");
791 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
792 inst
->saturate
= instr
->dest
.saturate
;
796 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
797 inst
->saturate
= instr
->dest
.saturate
;
802 bld
.MOV(result
, negate(op
[0]));
806 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
809 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
813 inst
= bld
.RNDZ(result
, op
[0]);
814 inst
->saturate
= instr
->dest
.saturate
;
818 op
[0].negate
= !op
[0].negate
;
819 fs_reg temp
= vgrf(glsl_type::float_type
);
820 bld
.RNDD(temp
, op
[0]);
822 inst
= bld
.MOV(result
, temp
);
823 inst
->saturate
= instr
->dest
.saturate
;
827 inst
= bld
.RNDD(result
, op
[0]);
828 inst
->saturate
= instr
->dest
.saturate
;
831 inst
= bld
.FRC(result
, op
[0]);
832 inst
->saturate
= instr
->dest
.saturate
;
834 case nir_op_fround_even
:
835 inst
= bld
.RNDE(result
, op
[0]);
836 inst
->saturate
= instr
->dest
.saturate
;
842 if (devinfo
->gen
>= 6) {
843 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
844 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
846 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
847 inst
= bld
.SEL(result
, op
[0], op
[1]);
848 inst
->predicate
= BRW_PREDICATE_NORMAL
;
850 inst
->saturate
= instr
->dest
.saturate
;
856 if (devinfo
->gen
>= 6) {
857 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
858 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
860 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
861 inst
= bld
.SEL(result
, op
[0], op
[1]);
862 inst
->predicate
= BRW_PREDICATE_NORMAL
;
864 inst
->saturate
= instr
->dest
.saturate
;
867 case nir_op_pack_snorm_2x16
:
868 case nir_op_pack_snorm_4x8
:
869 case nir_op_pack_unorm_2x16
:
870 case nir_op_pack_unorm_4x8
:
871 case nir_op_unpack_snorm_2x16
:
872 case nir_op_unpack_snorm_4x8
:
873 case nir_op_unpack_unorm_2x16
:
874 case nir_op_unpack_unorm_4x8
:
875 case nir_op_unpack_half_2x16
:
876 case nir_op_pack_half_2x16
:
877 unreachable("not reached: should be handled by lower_packing_builtins");
879 case nir_op_unpack_half_2x16_split_x
:
880 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
881 inst
->saturate
= instr
->dest
.saturate
;
883 case nir_op_unpack_half_2x16_split_y
:
884 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
885 inst
->saturate
= instr
->dest
.saturate
;
889 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
890 inst
->saturate
= instr
->dest
.saturate
;
893 case nir_op_bitfield_reverse
:
894 bld
.BFREV(result
, op
[0]);
897 case nir_op_bit_count
:
898 bld
.CBIT(result
, op
[0]);
901 case nir_op_ufind_msb
:
902 case nir_op_ifind_msb
: {
903 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
905 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
906 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
907 * subtract the result from 31 to convert the MSB count into an LSB count.
910 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
911 fs_reg
neg_result(result
);
912 neg_result
.negate
= true;
913 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
914 inst
->predicate
= BRW_PREDICATE_NORMAL
;
918 case nir_op_find_lsb
:
919 bld
.FBL(result
, op
[0]);
922 case nir_op_ubitfield_extract
:
923 case nir_op_ibitfield_extract
:
924 bld
.BFE(result
, op
[2], op
[1], op
[0]);
927 bld
.BFI1(result
, op
[0], op
[1]);
930 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
933 case nir_op_bitfield_insert
:
934 unreachable("not reached: should be handled by "
935 "lower_instructions::bitfield_insert_to_bfm_bfi");
938 bld
.SHL(result
, op
[0], op
[1]);
941 bld
.ASR(result
, op
[0], op
[1]);
944 bld
.SHR(result
, op
[0], op
[1]);
947 case nir_op_pack_half_2x16_split
:
948 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
952 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
953 inst
->saturate
= instr
->dest
.saturate
;
957 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
958 inst
->saturate
= instr
->dest
.saturate
;
962 if (optimize_frontfacing_ternary(instr
, result
))
965 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
966 inst
= bld
.SEL(result
, op
[1], op
[2]);
967 inst
->predicate
= BRW_PREDICATE_NORMAL
;
971 unreachable("unhandled instruction");
974 /* If we need to do a boolean resolve, replace the result with -(x & 1)
975 * to sign extend the low bit to 0/~0
977 if (devinfo
->gen
<= 5 &&
978 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
979 fs_reg masked
= vgrf(glsl_type::int_type
);
980 bld
.AND(masked
, result
, fs_reg(1));
981 masked
.negate
= true;
982 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
987 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
988 nir_load_const_instr
*instr
)
990 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
992 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
993 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
995 nir_ssa_values
[instr
->def
.index
] = reg
;
999 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1001 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1002 instr
->def
.num_components
);
1006 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1007 unsigned base_offset
, nir_src
*indirect
)
1011 assert(!nir_reg
->is_global
);
1013 reg
= v
->nir_locals
[nir_reg
->index
];
1015 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1017 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1019 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1020 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1021 fs_reg(multiplier
));
1028 fs_visitor::get_nir_src(nir_src src
)
1032 reg
= nir_ssa_values
[src
.ssa
->index
];
1034 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1038 /* to avoid floating-point denorm flushing problems, set the type by
1039 * default to D - instructions that need floating point semantics will set
1040 * this to F if they need to
1042 return retype(reg
, BRW_REGISTER_TYPE_D
);
1046 fs_visitor::get_nir_dest(nir_dest dest
)
1049 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1050 dest
.ssa
.num_components
);
1051 return nir_ssa_values
[dest
.ssa
.index
];
1054 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1059 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1061 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1062 BRW_REGISTER_TYPE_UD
);
1064 if (deref
->deref
.child
) {
1065 const nir_deref_array
*deref_array
=
1066 nir_deref_as_array(deref
->deref
.child
);
1067 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1068 deref_array
->deref
.child
== NULL
);
1069 const unsigned size
= glsl_get_length(deref
->var
->type
);
1070 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1072 image
= offset(image
, bld
, base
* BRW_IMAGE_PARAM_SIZE
);
1074 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1075 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1077 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1078 /* IVB hangs when trying to access an invalid surface index with
1079 * the dataport. According to the spec "if the index used to
1080 * select an individual element is negative or greater than or
1081 * equal to the size of the array, the results of the operation
1082 * are undefined but may not lead to termination" -- which is one
1083 * of the possible outcomes of the hang. Clamp the index to
1084 * prevent access outside of the array bounds.
1086 bld
.emit_minmax(*tmp
, retype(get_nir_src(deref_array
->indirect
),
1087 BRW_REGISTER_TYPE_UD
),
1088 fs_reg(size
- base
- 1), BRW_CONDITIONAL_L
);
1090 bld
.MOV(*tmp
, get_nir_src(deref_array
->indirect
));
1093 bld
.MUL(*tmp
, *tmp
, fs_reg(BRW_IMAGE_PARAM_SIZE
));
1094 image
.reladdr
= tmp
;
1102 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1105 for (unsigned i
= 0; i
< 4; i
++) {
1106 if (!((wr_mask
>> i
) & 1))
1109 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1110 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1111 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1112 if (new_inst
->src
[j
].file
== GRF
)
1113 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1120 * Get the matching channel register datatype for an image intrinsic of the
1121 * specified GLSL image type.
1124 get_image_base_type(const glsl_type
*type
)
1126 switch ((glsl_base_type
)type
->sampler_type
) {
1127 case GLSL_TYPE_UINT
:
1128 return BRW_REGISTER_TYPE_UD
;
1130 return BRW_REGISTER_TYPE_D
;
1131 case GLSL_TYPE_FLOAT
:
1132 return BRW_REGISTER_TYPE_F
;
1134 unreachable("Not reached.");
1139 * Get the appropriate atomic op for an image atomic intrinsic.
1142 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1145 case nir_intrinsic_image_atomic_add
:
1147 case nir_intrinsic_image_atomic_min
:
1148 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1149 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1150 case nir_intrinsic_image_atomic_max
:
1151 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1152 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1153 case nir_intrinsic_image_atomic_and
:
1155 case nir_intrinsic_image_atomic_or
:
1157 case nir_intrinsic_image_atomic_xor
:
1159 case nir_intrinsic_image_atomic_exchange
:
1161 case nir_intrinsic_image_atomic_comp_swap
:
1162 return BRW_AOP_CMPWR
;
1164 unreachable("Not reachable.");
1169 emit_pixel_interpolater_send(const fs_builder
&bld
,
1174 glsl_interp_qualifier interpolation
)
1180 if (src
.file
== BAD_FILE
) {
1182 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1186 mlen
= 2 * bld
.dispatch_width() / 8;
1189 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1191 /* 2 floats per slot returned */
1192 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1193 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1199 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1202 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1203 dest
= get_nir_dest(instr
->dest
);
1205 bool has_indirect
= false;
1207 switch (instr
->intrinsic
) {
1208 case nir_intrinsic_discard
:
1209 case nir_intrinsic_discard_if
: {
1210 /* We track our discarded pixels in f0.1. By predicating on it, we can
1211 * update just the flag bits that aren't yet discarded. If there's no
1212 * condition, we emit a CMP of g0 != g0, so all currently executing
1213 * channels will get turned off.
1216 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1217 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1218 fs_reg(0), BRW_CONDITIONAL_Z
);
1220 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1221 BRW_REGISTER_TYPE_UW
));
1222 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1224 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1225 cmp
->flag_subreg
= 1;
1227 if (devinfo
->gen
>= 6) {
1228 emit_discard_jump();
1233 case nir_intrinsic_atomic_counter_inc
:
1234 case nir_intrinsic_atomic_counter_dec
:
1235 case nir_intrinsic_atomic_counter_read
: {
1236 using namespace surface_access
;
1238 /* Get the arguments of the atomic intrinsic. */
1239 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1240 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1241 instr
->const_index
[0]);
1244 /* Emit a surface read or atomic op. */
1245 switch (instr
->intrinsic
) {
1246 case nir_intrinsic_atomic_counter_read
:
1247 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1250 case nir_intrinsic_atomic_counter_inc
:
1251 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1252 fs_reg(), 1, 1, BRW_AOP_INC
);
1255 case nir_intrinsic_atomic_counter_dec
:
1256 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1257 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1261 unreachable("Unreachable");
1264 /* Assign the result. */
1265 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1267 /* Mark the surface as used. */
1268 brw_mark_surface_used(stage_prog_data
, surface
);
1272 case nir_intrinsic_image_load
:
1273 case nir_intrinsic_image_store
:
1274 case nir_intrinsic_image_atomic_add
:
1275 case nir_intrinsic_image_atomic_min
:
1276 case nir_intrinsic_image_atomic_max
:
1277 case nir_intrinsic_image_atomic_and
:
1278 case nir_intrinsic_image_atomic_or
:
1279 case nir_intrinsic_image_atomic_xor
:
1280 case nir_intrinsic_image_atomic_exchange
:
1281 case nir_intrinsic_image_atomic_comp_swap
: {
1282 using namespace image_access
;
1284 /* Get the referenced image variable and type. */
1285 const nir_variable
*var
= instr
->variables
[0]->var
;
1286 const glsl_type
*type
= var
->type
->without_array();
1287 const brw_reg_type base_type
= get_image_base_type(type
);
1289 /* Get some metadata from the image intrinsic. */
1290 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1291 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
1292 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
1293 const mesa_format format
=
1294 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
1295 _mesa_get_shader_image_format(var
->data
.image
.format
));
1297 /* Get the arguments of the image intrinsic. */
1298 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1299 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
1300 BRW_REGISTER_TYPE_UD
);
1301 const fs_reg src0
= (info
->num_srcs
>= 3 ?
1302 retype(get_nir_src(instr
->src
[2]), base_type
) :
1304 const fs_reg src1
= (info
->num_srcs
>= 4 ?
1305 retype(get_nir_src(instr
->src
[3]), base_type
) :
1309 /* Emit an image load, store or atomic op. */
1310 if (instr
->intrinsic
== nir_intrinsic_image_load
)
1311 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
1313 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
1314 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
1317 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
1318 surf_dims
, arr_dims
, info
->dest_components
,
1319 get_image_atomic_op(instr
->intrinsic
, type
));
1321 /* Assign the result. */
1322 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
1323 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
1324 offset(tmp
, bld
, c
));
1328 case nir_intrinsic_memory_barrier
: {
1329 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1330 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1335 case nir_intrinsic_image_size
: {
1336 /* Get the referenced image variable and type. */
1337 const nir_variable
*var
= instr
->variables
[0]->var
;
1338 const glsl_type
*type
= var
->type
->without_array();
1340 /* Get the size of the image. */
1341 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
1342 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
1344 /* For 1DArray image types, the array index is stored in the Z component.
1345 * Fix this by swizzling the Z component to the Y component.
1347 const bool is_1d_array_image
=
1348 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
1349 type
->sampler_array
;
1351 /* For CubeArray images, we should count the number of cubes instead
1352 * of the number of faces. Fix it by dividing the (Z component) by 6.
1354 const bool is_cube_array_image
=
1355 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
1356 type
->sampler_array
;
1358 /* Copy all the components. */
1359 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
1360 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
1361 if ((int)c
>= type
->coordinate_components()) {
1362 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1364 } else if (c
== 1 && is_1d_array_image
) {
1365 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1366 offset(size
, bld
, 2));
1367 } else if (c
== 2 && is_cube_array_image
) {
1368 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
1369 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1370 offset(size
, bld
, c
), fs_reg(6));
1372 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
1373 offset(size
, bld
, c
));
1380 case nir_intrinsic_image_samples
:
1381 /* The driver does not support multi-sampled images. */
1382 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), fs_reg(1));
1385 case nir_intrinsic_load_front_face
:
1386 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1387 *emit_frontfacing_interpolation());
1390 case nir_intrinsic_load_vertex_id
:
1391 unreachable("should be lowered by lower_vertex_id()");
1393 case nir_intrinsic_load_primitive_id
:
1394 assert(stage
== MESA_SHADER_GEOMETRY
);
1395 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1396 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1397 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1400 case nir_intrinsic_load_vertex_id_zero_base
:
1401 case nir_intrinsic_load_base_vertex
:
1402 case nir_intrinsic_load_instance_id
:
1403 case nir_intrinsic_load_invocation_id
:
1404 case nir_intrinsic_load_sample_mask_in
:
1405 case nir_intrinsic_load_sample_id
: {
1406 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1407 fs_reg val
= nir_system_values
[sv
];
1408 assert(val
.file
!= BAD_FILE
);
1409 dest
.type
= val
.type
;
1414 case nir_intrinsic_load_sample_pos
: {
1415 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1416 assert(sample_pos
.file
!= BAD_FILE
);
1417 dest
.type
= sample_pos
.type
;
1418 bld
.MOV(dest
, sample_pos
);
1419 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1423 case nir_intrinsic_load_uniform_indirect
:
1424 has_indirect
= true;
1426 case nir_intrinsic_load_uniform
: {
1427 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
1428 uniform_reg
.reg_offset
= instr
->const_index
[1];
1430 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1431 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
1433 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1436 dest
= offset(dest
, bld
, 1);
1441 case nir_intrinsic_load_ubo_indirect
:
1442 has_indirect
= true;
1444 case nir_intrinsic_load_ubo
: {
1445 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1449 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1452 /* The block index is not a constant. Evaluate the index expression
1453 * per-channel and add the base UBO index; we have to select a value
1454 * from any live channel.
1456 surf_index
= vgrf(glsl_type::uint_type
);
1457 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1458 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1459 surf_index
= bld
.emit_uniformize(surf_index
);
1461 /* Assume this may touch any UBO. It would be nice to provide
1462 * a tighter bound, but the array information is already lowered away.
1464 brw_mark_surface_used(prog_data
,
1465 stage_prog_data
->binding_table
.ubo_start
+
1466 nir
->info
.num_ubos
- 1);
1470 /* Turn the byte offset into a dword offset. */
1471 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1472 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1473 BRW_REGISTER_TYPE_D
),
1476 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1477 for (int i
= 0; i
< instr
->num_components
; i
++)
1478 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1479 base_offset
, vec4_offset
+ i
);
1481 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1482 packed_consts
.type
= dest
.type
;
1484 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1485 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1486 surf_index
, const_offset_reg
);
1488 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1489 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1491 /* The std140 packing rules don't allow vectors to cross 16-byte
1492 * boundaries, and a reg is 32 bytes.
1494 assert(packed_consts
.subreg_offset
< 32);
1496 bld
.MOV(dest
, packed_consts
);
1497 dest
= offset(dest
, bld
, 1);
1503 case nir_intrinsic_load_ssbo_indirect
:
1504 has_indirect
= true;
1506 case nir_intrinsic_load_ssbo
: {
1507 assert(devinfo
->gen
>= 7);
1509 nir_const_value
*const_uniform_block
=
1510 nir_src_as_const_value(instr
->src
[0]);
1513 if (const_uniform_block
) {
1514 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
1515 const_uniform_block
->u
[0];
1516 surf_index
= fs_reg(index
);
1517 brw_mark_surface_used(prog_data
, index
);
1519 surf_index
= vgrf(glsl_type::uint_type
);
1520 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1521 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1523 /* Assume this may touch any UBO. It would be nice to provide
1524 * a tighter bound, but the array information is already lowered away.
1526 brw_mark_surface_used(prog_data
,
1527 stage_prog_data
->binding_table
.ssbo_start
+
1528 nir
->info
.num_ssbos
- 1);
1531 /* Get the offset to read from */
1534 offset_reg
= get_nir_src(instr
->src
[1]);
1536 offset_reg
= fs_reg(instr
->const_index
[0]);
1539 /* Read the vector */
1540 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
1542 instr
->num_components
,
1543 BRW_PREDICATE_NONE
);
1544 read_result
.type
= dest
.type
;
1545 for (int i
= 0; i
< instr
->num_components
; i
++)
1546 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
1551 case nir_intrinsic_load_input_indirect
:
1552 has_indirect
= true;
1554 case nir_intrinsic_load_input
: {
1556 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1558 if (stage
== MESA_SHADER_VERTEX
) {
1559 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
1561 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1562 instr
->const_index
[0] + index
);
1565 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1569 dest
= offset(dest
, bld
, 1);
1574 /* Handle ARB_gpu_shader5 interpolation intrinsics
1576 * It's worth a quick word of explanation as to why we handle the full
1577 * variable-based interpolation intrinsic rather than a lowered version
1578 * with like we do for other inputs. We have to do that because the way
1579 * we set up inputs doesn't allow us to use the already setup inputs for
1580 * interpolation. At the beginning of the shader, we go through all of
1581 * the input variables and do the initial interpolation and put it in
1582 * the nir_inputs array based on its location as determined in
1583 * nir_lower_io. If the input isn't used, dead code cleans up and
1584 * everything works fine. However, when we get to the ARB_gpu_shader5
1585 * interpolation intrinsics, we need to reinterpolate the input
1586 * differently. If we used an intrinsic that just had an index it would
1587 * only give us the offset into the nir_inputs array. However, this is
1588 * useless because that value is post-interpolation and we need
1589 * pre-interpolation. In order to get the actual location of the bits
1590 * we get from the vertex fetching hardware, we need the variable.
1592 case nir_intrinsic_interp_var_at_centroid
:
1593 case nir_intrinsic_interp_var_at_sample
:
1594 case nir_intrinsic_interp_var_at_offset
: {
1595 assert(stage
== MESA_SHADER_FRAGMENT
);
1597 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1599 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1600 const glsl_interp_qualifier interpolation
=
1601 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1603 switch (instr
->intrinsic
) {
1604 case nir_intrinsic_interp_var_at_centroid
:
1605 emit_pixel_interpolater_send(bld
,
1606 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1613 case nir_intrinsic_interp_var_at_sample
: {
1614 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1617 unsigned msg_data
= const_sample
->i
[0] << 4;
1619 emit_pixel_interpolater_send(bld
,
1620 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1626 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1627 BRW_REGISTER_TYPE_UD
);
1629 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1630 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1631 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1632 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1633 emit_pixel_interpolater_send(bld
,
1634 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1640 /* Make a loop that sends a message to the pixel interpolater
1641 * for the sample number in each live channel. If there are
1642 * multiple channels with the same sample number then these
1643 * will be handled simultaneously with a single interation of
1646 bld
.emit(BRW_OPCODE_DO
);
1648 /* Get the next live sample number into sample_id_reg */
1649 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1651 /* Set the flag register so that we can perform the send
1652 * message on all channels that have the same sample number
1654 bld
.CMP(bld
.null_reg_ud(),
1655 sample_src
, sample_id
,
1656 BRW_CONDITIONAL_EQ
);
1657 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1658 bld
.exec_all().group(1, 0).SHL(msg_data
, sample_id
, fs_reg(4u));
1660 emit_pixel_interpolater_send(bld
,
1661 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1666 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1668 /* Continue the loop if there are any live channels left */
1669 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1671 bld
.emit(BRW_OPCODE_WHILE
));
1678 case nir_intrinsic_interp_var_at_offset
: {
1679 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1682 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1683 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1685 emit_pixel_interpolater_send(bld
,
1686 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1689 fs_reg(off_x
| (off_y
<< 4)),
1692 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1693 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1694 BRW_REGISTER_TYPE_F
);
1695 for (int i
= 0; i
< 2; i
++) {
1696 fs_reg temp
= vgrf(glsl_type::float_type
);
1697 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1698 fs_reg itemp
= vgrf(glsl_type::int_type
);
1699 bld
.MOV(itemp
, temp
); /* float to int */
1701 /* Clamp the upper end of the range to +7/16.
1702 * ARB_gpu_shader5 requires that we support a maximum offset
1703 * of +0.5, which isn't representable in a S0.4 value -- if
1704 * we didn't clamp it, we'd end up with -8/16, which is the
1705 * opposite of what the shader author wanted.
1707 * This is legal due to ARB_gpu_shader5's quantization
1710 * "Not all values of <offset> may be supported; x and y
1711 * offsets may be rounded to fixed-point values with the
1712 * number of fraction bits given by the
1713 * implementation-dependent constant
1714 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1716 set_condmod(BRW_CONDITIONAL_L
,
1717 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1720 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
1721 emit_pixel_interpolater_send(bld
,
1732 unreachable("Invalid intrinsic");
1735 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1736 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1737 src
.type
= dest
.type
;
1739 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1740 dest
= offset(dest
, bld
, 1);
1745 case nir_intrinsic_store_ssbo_indirect
:
1746 has_indirect
= true;
1748 case nir_intrinsic_store_ssbo
: {
1749 assert(devinfo
->gen
>= 7);
1753 nir_const_value
*const_uniform_block
=
1754 nir_src_as_const_value(instr
->src
[1]);
1755 if (const_uniform_block
) {
1756 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
1757 const_uniform_block
->u
[0];
1758 surf_index
= fs_reg(index
);
1759 brw_mark_surface_used(prog_data
, index
);
1761 surf_index
= vgrf(glsl_type::uint_type
);
1762 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
1763 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1765 brw_mark_surface_used(prog_data
,
1766 stage_prog_data
->binding_table
.ssbo_start
+
1767 nir
->info
.num_ssbos
- 1);
1771 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
1774 unsigned writemask
= instr
->const_index
[1];
1776 /* Combine groups of consecutive enabled channels in one write
1777 * message. We use ffs to find the first enabled channel and then ffs on
1778 * the bit-inverse, down-shifted writemask to determine the length of
1779 * the block of enabled bits.
1782 unsigned first_component
= ffs(writemask
) - 1;
1783 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
1786 if (!has_indirect
) {
1787 offset_reg
= fs_reg(instr
->const_index
[0] + 4 * first_component
);
1789 offset_reg
= vgrf(glsl_type::uint_type
);
1791 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
1792 fs_reg(4 * first_component
));
1795 emit_untyped_write(bld
, surf_index
, offset_reg
,
1796 offset(val_reg
, bld
, first_component
),
1797 1 /* dims */, length
,
1798 BRW_PREDICATE_NONE
);
1800 /* Clear the bits in the writemask that we just wrote, then try
1801 * again to see if more channels are left.
1803 writemask
&= (15 << (first_component
+ length
));
1808 case nir_intrinsic_store_output_indirect
:
1809 has_indirect
= true;
1811 case nir_intrinsic_store_output
: {
1812 fs_reg src
= get_nir_src(instr
->src
[0]);
1814 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1815 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1816 instr
->const_index
[0] + index
);
1818 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1820 bld
.MOV(new_dest
, src
);
1821 src
= offset(src
, bld
, 1);
1826 case nir_intrinsic_barrier
:
1828 if (stage
== MESA_SHADER_COMPUTE
)
1829 ((struct brw_cs_prog_data
*) prog_data
)->uses_barrier
= true;
1832 case nir_intrinsic_load_local_invocation_id
:
1833 case nir_intrinsic_load_work_group_id
: {
1834 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1835 fs_reg val
= nir_system_values
[sv
];
1836 assert(val
.file
!= BAD_FILE
);
1837 dest
.type
= val
.type
;
1838 for (unsigned i
= 0; i
< 3; i
++)
1839 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
1843 case nir_intrinsic_ssbo_atomic_add
:
1844 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
1846 case nir_intrinsic_ssbo_atomic_imin
:
1847 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
1849 case nir_intrinsic_ssbo_atomic_umin
:
1850 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
1852 case nir_intrinsic_ssbo_atomic_imax
:
1853 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
1855 case nir_intrinsic_ssbo_atomic_umax
:
1856 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
1858 case nir_intrinsic_ssbo_atomic_and
:
1859 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
1861 case nir_intrinsic_ssbo_atomic_or
:
1862 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
1864 case nir_intrinsic_ssbo_atomic_xor
:
1865 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
1867 case nir_intrinsic_ssbo_atomic_exchange
:
1868 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
1870 case nir_intrinsic_ssbo_atomic_comp_swap
:
1871 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
1874 case nir_intrinsic_get_buffer_size
: {
1875 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
1876 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
1877 int reg_width
= dispatch_width
/ 8;
1880 fs_reg source
= fs_reg(0);
1882 int mlen
= 1 * reg_width
;
1883 fs_reg src_payload
= fs_reg(GRF
, alloc
.allocate(mlen
),
1884 BRW_REGISTER_TYPE_UD
);
1885 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
1887 fs_reg surf_index
= fs_reg(prog_data
->binding_table
.ssbo_start
+ ssbo_index
);
1888 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, dest
,
1889 src_payload
, surf_index
);
1890 inst
->header_size
= 0;
1896 case nir_intrinsic_load_num_work_groups
: {
1897 assert(devinfo
->gen
>= 7);
1898 assert(stage
== MESA_SHADER_COMPUTE
);
1900 struct brw_cs_prog_data
*cs_prog_data
=
1901 (struct brw_cs_prog_data
*) prog_data
;
1902 const unsigned surface
=
1903 cs_prog_data
->binding_table
.work_groups_start
;
1905 cs_prog_data
->uses_num_work_groups
= true;
1907 fs_reg surf_index
= fs_reg(surface
);
1908 brw_mark_surface_used(prog_data
, surface
);
1910 /* Read the 3 GLuint components of gl_NumWorkGroups */
1911 for (unsigned i
= 0; i
< 3; i
++) {
1912 fs_reg read_result
=
1913 emit_untyped_read(bld
, surf_index
,
1915 1 /* dims */, 1 /* size */,
1916 BRW_PREDICATE_NONE
);
1917 read_result
.type
= dest
.type
;
1918 bld
.MOV(dest
, read_result
);
1919 dest
= offset(dest
, bld
, 1);
1925 unreachable("unknown intrinsic");
1930 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
1931 int op
, nir_intrinsic_instr
*instr
)
1934 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1935 dest
= get_nir_dest(instr
->dest
);
1938 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
1939 if (const_surface
) {
1940 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
1941 const_surface
->u
[0];
1942 surface
= fs_reg(surf_index
);
1943 brw_mark_surface_used(prog_data
, surf_index
);
1945 surface
= vgrf(glsl_type::uint_type
);
1946 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
1947 fs_reg(stage_prog_data
->binding_table
.ssbo_start
));
1949 /* Assume this may touch any SSBO. This is the same we do for other
1950 * UBO/SSBO accesses with non-constant surface.
1952 brw_mark_surface_used(prog_data
,
1953 stage_prog_data
->binding_table
.ssbo_start
+
1954 nir
->info
.num_ssbos
- 1);
1957 fs_reg offset
= get_nir_src(instr
->src
[1]);
1958 fs_reg data1
= get_nir_src(instr
->src
[2]);
1960 if (op
== BRW_AOP_CMPWR
)
1961 data2
= get_nir_src(instr
->src
[3]);
1963 /* Emit the actual atomic operation operation */
1965 fs_reg atomic_result
=
1966 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
1968 1 /* dims */, 1 /* rsize */,
1970 BRW_PREDICATE_NONE
);
1971 dest
.type
= atomic_result
.type
;
1972 bld
.MOV(dest
, atomic_result
);
1976 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1978 unsigned sampler
= instr
->sampler_index
;
1979 fs_reg
sampler_reg(sampler
);
1981 int gather_component
= instr
->component
;
1983 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1985 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1988 int lod_components
= 0;
1989 int UNUSED offset_components
= 0;
1991 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1993 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1994 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1995 switch (instr
->src
[i
].src_type
) {
1996 case nir_tex_src_bias
:
1997 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1999 case nir_tex_src_comparitor
:
2000 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2002 case nir_tex_src_coord
:
2003 switch (instr
->op
) {
2005 case nir_texop_txf_ms
:
2006 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2009 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2013 case nir_tex_src_ddx
:
2014 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2015 lod_components
= nir_tex_instr_src_size(instr
, i
);
2017 case nir_tex_src_ddy
:
2018 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2020 case nir_tex_src_lod
:
2021 switch (instr
->op
) {
2023 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2026 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2029 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2033 case nir_tex_src_ms_index
:
2034 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2036 case nir_tex_src_offset
:
2037 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2038 if (instr
->is_array
)
2039 offset_components
= instr
->coord_components
- 1;
2041 offset_components
= instr
->coord_components
;
2043 case nir_tex_src_projector
:
2044 unreachable("should be lowered");
2046 case nir_tex_src_sampler_offset
: {
2047 /* Figure out the highest possible sampler index and mark it as used */
2048 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2049 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2050 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2052 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2054 brw_mark_surface_used(prog_data
, max_used
);
2056 /* Emit code to evaluate the actual indexing expression */
2057 sampler_reg
= vgrf(glsl_type::uint_type
);
2058 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
2059 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2064 unreachable("unknown texture source");
2068 if (instr
->op
== nir_texop_txf_ms
) {
2069 if (devinfo
->gen
>= 7 &&
2070 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2071 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2077 for (unsigned i
= 0; i
< 3; i
++) {
2078 if (instr
->const_offset
[i
] != 0) {
2079 assert(offset_components
== 0);
2080 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
2085 enum glsl_base_type dest_base_type
=
2086 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2088 const glsl_type
*dest_type
=
2089 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2092 ir_texture_opcode op
;
2093 switch (instr
->op
) {
2094 case nir_texop_lod
: op
= ir_lod
; break;
2095 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2096 case nir_texop_tex
: op
= ir_tex
; break;
2097 case nir_texop_tg4
: op
= ir_tg4
; break;
2098 case nir_texop_txb
: op
= ir_txb
; break;
2099 case nir_texop_txd
: op
= ir_txd
; break;
2100 case nir_texop_txf
: op
= ir_txf
; break;
2101 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2102 case nir_texop_txl
: op
= ir_txl
; break;
2103 case nir_texop_txs
: op
= ir_txs
; break;
2104 case nir_texop_texture_samples
: {
2105 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2106 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2107 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2110 inst
->header_size
= 1;
2111 inst
->base_mrf
= -1;
2115 unreachable("unknown texture opcode");
2118 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2119 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2120 tex_offset
, mcs
, gather_component
,
2121 is_cube_array
, is_rect
, sampler
, sampler_reg
);
2123 fs_reg dest
= get_nir_dest(instr
->dest
);
2124 dest
.type
= this->result
.type
;
2125 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2126 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2127 dest
, this->result
),
2128 (1 << num_components
) - 1);
2132 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2134 switch (instr
->type
) {
2135 case nir_jump_break
:
2136 bld
.emit(BRW_OPCODE_BREAK
);
2138 case nir_jump_continue
:
2139 bld
.emit(BRW_OPCODE_CONTINUE
);
2141 case nir_jump_return
:
2143 unreachable("unknown jump");