2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
29 #include "brw_fs_surface_builder.h"
35 fs_visitor::emit_nir_code()
37 nir_shader
*nir
= prog
->nir
;
39 /* emit the arrays used for inputs and outputs - load/store intrinsics will
40 * be converted to reads/writes of these arrays
42 nir_setup_inputs(nir
);
43 nir_setup_outputs(nir
);
44 nir_setup_uniforms(nir
);
45 nir_emit_system_values(nir
);
47 /* get the main function and emit it */
48 nir_foreach_overload(nir
, overload
) {
49 assert(strcmp(overload
->function
->name
, "main") == 0);
50 assert(overload
->impl
);
51 nir_emit_impl(overload
->impl
);
56 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_inputs
);
60 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
61 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
66 case MESA_SHADER_VERTEX
: {
67 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
68 * stored in nir_variable::location.
70 * However, NIR's load_input intrinsics use a different index - an
71 * offset into a single contiguous array containing all inputs.
72 * This index corresponds to the nir_variable::driver_location field.
74 * So, we need to copy from fs_reg(ATTR, var->location) to
75 * offset(nir_inputs, var->data.driver_location).
77 const glsl_type
*const t
= var
->type
->without_array();
78 const unsigned components
= t
->components();
79 const unsigned cols
= t
->matrix_columns
;
80 const unsigned elts
= t
->vector_elements
;
81 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
82 for (unsigned i
= 0; i
< array_length
; i
++) {
83 for (unsigned j
= 0; j
< cols
; j
++) {
84 for (unsigned k
= 0; k
< elts
; k
++) {
85 bld
.MOV(offset(retype(input
, type
), bld
,
86 components
* i
+ elts
* j
+ k
),
87 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
94 case MESA_SHADER_GEOMETRY
:
95 case MESA_SHADER_COMPUTE
:
96 case MESA_SHADER_TESS_CTRL
:
97 case MESA_SHADER_TESS_EVAL
:
98 unreachable("fs_visitor not used for these stages yet.");
100 case MESA_SHADER_FRAGMENT
:
101 if (var
->data
.location
== VARYING_SLOT_POS
) {
102 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
103 var
->data
.origin_upper_left
);
104 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
107 emit_general_interpolation(input
, var
->name
, var
->type
,
108 (glsl_interp_qualifier
) var
->data
.interpolation
,
109 var
->data
.location
, var
->data
.centroid
,
118 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
120 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
122 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, shader
->num_outputs
);
124 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
125 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 int vector_elements
=
128 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
129 : var
->type
->vector_elements
;
132 case MESA_SHADER_VERTEX
:
133 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
134 int output
= var
->data
.location
+ i
;
135 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
136 this->output_components
[output
] = vector_elements
;
139 case MESA_SHADER_FRAGMENT
:
140 if (var
->data
.index
> 0) {
141 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
142 assert(var
->data
.index
== 1);
143 this->dual_src_output
= reg
;
144 this->do_dual_src
= true;
145 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
146 /* Writing gl_FragColor outputs to all color regions. */
147 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
148 this->outputs
[i
] = reg
;
149 this->output_components
[i
] = 4;
151 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
152 this->frag_depth
= reg
;
153 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
154 this->sample_mask
= reg
;
156 /* gl_FragData or a user-defined FS output */
157 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
158 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
160 /* General color output. */
161 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
162 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
163 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
164 this->output_components
[output
] = vector_elements
;
169 unreachable("unhandled shader stage");
175 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
177 num_direct_uniforms
= shader
->num_direct_uniforms
;
179 if (dispatch_width
!= 8)
182 /* We split the uniform register file in half. The first half is
183 * entirely direct uniforms. The second half is indirect.
185 if (num_direct_uniforms
> 0)
186 param_size
[0] = num_direct_uniforms
;
187 if (shader
->num_uniforms
> num_direct_uniforms
)
188 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
190 uniforms
= shader
->num_uniforms
;
193 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
194 /* UBO's and atomics don't take up space in the uniform file */
195 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
198 if (strncmp(var
->name
, "gl_", 3) == 0)
199 nir_setup_builtin_uniform(var
);
201 nir_setup_uniform(var
);
204 /* prog_to_nir doesn't create uniform variables; set param up directly. */
205 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
206 for (unsigned int i
= 0; i
< 4; i
++) {
207 stage_prog_data
->param
[4 * p
+ i
] =
208 &prog
->Parameters
->ParameterValues
[p
][i
];
215 fs_visitor::nir_setup_uniform(nir_variable
*var
)
217 int namelen
= strlen(var
->name
);
219 /* The data for our (non-builtin) uniforms is stored in a series of
220 * gl_uniform_driver_storage structs for each subcomponent that
221 * glGetUniformLocation() could name. We know it's been set up in the
222 * same order we'd walk the type, so walk the list of storage and find
223 * anything with our name, or the prefix of a component that starts with
226 unsigned index
= var
->data
.driver_location
;
227 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
228 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
230 if (storage
->builtin
)
233 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
234 (storage
->name
[namelen
] != 0 &&
235 storage
->name
[namelen
] != '.' &&
236 storage
->name
[namelen
] != '[')) {
240 if (storage
->type
->is_image()) {
241 /* Images don't get a valid location assigned by nir_lower_io()
242 * because their size is driver-specific, so we need to allocate
243 * space for them here at the end of the parameter array.
245 var
->data
.driver_location
= uniforms
;
246 param_size
[uniforms
] =
247 BRW_IMAGE_PARAM_SIZE
* MAX2(storage
->array_elements
, 1);
249 setup_image_uniform_values(storage
);
251 unsigned slots
= storage
->type
->component_slots();
252 if (storage
->array_elements
)
253 slots
*= storage
->array_elements
;
255 for (unsigned i
= 0; i
< slots
; i
++) {
256 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
263 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
265 const nir_state_slot
*const slots
= var
->state_slots
;
266 assert(var
->state_slots
!= NULL
);
268 unsigned uniform_index
= var
->data
.driver_location
;
269 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
270 /* This state reference has already been setup by ir_to_mesa, but we'll
271 * get the same index back here.
273 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
274 (gl_state_index
*)slots
[i
].tokens
);
276 /* Add each of the unique swizzles of the element as a parameter.
277 * This'll end up matching the expected layout of the
278 * array/matrix/structure we're trying to fill in.
281 for (unsigned int j
= 0; j
< 4; j
++) {
282 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
283 if (swiz
== last_swiz
)
287 stage_prog_data
->param
[uniform_index
++] =
288 &prog
->Parameters
->ParameterValues
[index
][swiz
];
294 emit_system_values_block(nir_block
*block
, void *void_visitor
)
296 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
299 nir_foreach_instr(block
, instr
) {
300 if (instr
->type
!= nir_instr_type_intrinsic
)
303 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
304 switch (intrin
->intrinsic
) {
305 case nir_intrinsic_load_vertex_id
:
306 unreachable("should be lowered by lower_vertex_id().");
308 case nir_intrinsic_load_vertex_id_zero_base
:
309 assert(v
->stage
== MESA_SHADER_VERTEX
);
310 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
311 if (reg
->file
== BAD_FILE
)
312 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
315 case nir_intrinsic_load_base_vertex
:
316 assert(v
->stage
== MESA_SHADER_VERTEX
);
317 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
318 if (reg
->file
== BAD_FILE
)
319 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
322 case nir_intrinsic_load_instance_id
:
323 assert(v
->stage
== MESA_SHADER_VERTEX
);
324 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
325 if (reg
->file
== BAD_FILE
)
326 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
329 case nir_intrinsic_load_sample_pos
:
330 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
331 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
332 if (reg
->file
== BAD_FILE
)
333 *reg
= *v
->emit_samplepos_setup();
336 case nir_intrinsic_load_sample_id
:
337 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
338 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
339 if (reg
->file
== BAD_FILE
)
340 *reg
= *v
->emit_sampleid_setup();
343 case nir_intrinsic_load_sample_mask_in
:
344 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
345 assert(v
->devinfo
->gen
>= 7);
346 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
347 if (reg
->file
== BAD_FILE
)
348 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
349 BRW_REGISTER_TYPE_D
));
361 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
363 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
364 nir_foreach_overload(shader
, overload
) {
365 assert(strcmp(overload
->function
->name
, "main") == 0);
366 assert(overload
->impl
);
367 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
372 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
374 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
375 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
376 unsigned array_elems
=
377 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
378 unsigned size
= array_elems
* reg
->num_components
;
379 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
382 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
385 nir_emit_cf_list(&impl
->body
);
389 fs_visitor::nir_emit_cf_list(exec_list
*list
)
391 exec_list_validate(list
);
392 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
393 switch (node
->type
) {
395 nir_emit_if(nir_cf_node_as_if(node
));
398 case nir_cf_node_loop
:
399 nir_emit_loop(nir_cf_node_as_loop(node
));
402 case nir_cf_node_block
:
403 nir_emit_block(nir_cf_node_as_block(node
));
407 unreachable("Invalid CFG node block");
413 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
415 /* first, put the condition into f0 */
416 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
417 retype(get_nir_src(if_stmt
->condition
),
418 BRW_REGISTER_TYPE_D
));
419 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
421 bld
.IF(BRW_PREDICATE_NORMAL
);
423 nir_emit_cf_list(&if_stmt
->then_list
);
425 /* note: if the else is empty, dead CF elimination will remove it */
426 bld
.emit(BRW_OPCODE_ELSE
);
428 nir_emit_cf_list(&if_stmt
->else_list
);
430 bld
.emit(BRW_OPCODE_ENDIF
);
432 try_replace_with_sel();
436 fs_visitor::nir_emit_loop(nir_loop
*loop
)
438 bld
.emit(BRW_OPCODE_DO
);
440 nir_emit_cf_list(&loop
->body
);
442 bld
.emit(BRW_OPCODE_WHILE
);
446 fs_visitor::nir_emit_block(nir_block
*block
)
448 nir_foreach_instr(block
, instr
) {
449 nir_emit_instr(instr
);
454 fs_visitor::nir_emit_instr(nir_instr
*instr
)
456 const fs_builder abld
= bld
.annotate(NULL
, instr
);
458 switch (instr
->type
) {
459 case nir_instr_type_alu
:
460 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
463 case nir_instr_type_intrinsic
:
464 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case nir_instr_type_tex
:
468 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
471 case nir_instr_type_load_const
:
472 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
475 case nir_instr_type_ssa_undef
:
476 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
479 case nir_instr_type_jump
:
480 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
484 unreachable("unknown instruction type");
489 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
490 const fs_reg
&result
)
492 if (!instr
->src
[0].src
.is_ssa
||
493 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
496 nir_intrinsic_instr
*src0
=
497 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
499 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
502 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
503 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
506 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
507 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
510 fs_reg tmp
= vgrf(glsl_type::int_type
);
512 if (devinfo
->gen
>= 6) {
513 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
514 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
516 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
518 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
519 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
521 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
523 * This negation looks like it's safe in practice, because bits 0:4 will
524 * surely be TRIANGLES
527 if (value1
->f
[0] == -1.0f
) {
531 tmp
.type
= BRW_REGISTER_TYPE_W
;
532 tmp
.subreg_offset
= 2;
535 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
536 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
538 tmp
.type
= BRW_REGISTER_TYPE_D
;
539 tmp
.subreg_offset
= 0;
542 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
543 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
545 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
547 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
548 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
550 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
552 * This negation looks like it's safe in practice, because bits 0:4 will
553 * surely be TRIANGLES
556 if (value1
->f
[0] == -1.0f
) {
560 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
562 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
568 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
570 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
573 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
574 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
577 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
578 op
[i
] = get_nir_src(instr
->src
[i
].src
);
579 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
580 op
[i
].abs
= instr
->src
[i
].abs
;
581 op
[i
].negate
= instr
->src
[i
].negate
;
584 /* We get a bunch of mov's out of the from_ssa pass and they may still
585 * be vectorized. We'll handle them as a special-case. We'll also
586 * handle vecN here because it's basically the same thing.
594 fs_reg temp
= result
;
595 bool need_extra_copy
= false;
596 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
597 if (!instr
->src
[i
].src
.is_ssa
&&
598 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
599 need_extra_copy
= true;
600 temp
= bld
.vgrf(result
.type
, 4);
605 for (unsigned i
= 0; i
< 4; i
++) {
606 if (!(instr
->dest
.write_mask
& (1 << i
)))
609 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
610 inst
= bld
.MOV(offset(temp
, bld
, i
),
611 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
613 inst
= bld
.MOV(offset(temp
, bld
, i
),
614 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
616 inst
->saturate
= instr
->dest
.saturate
;
619 /* In this case the source and destination registers were the same,
620 * so we need to insert an extra set of moves in order to deal with
623 if (need_extra_copy
) {
624 for (unsigned i
= 0; i
< 4; i
++) {
625 if (!(instr
->dest
.write_mask
& (1 << i
)))
628 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
637 /* At this point, we have dealt with any instruction that operates on
638 * more than a single channel. Therefore, we can just adjust the source
639 * and destination registers for that channel and emit the instruction.
641 unsigned channel
= 0;
642 if (nir_op_infos
[instr
->op
].output_size
== 0) {
643 /* Since NIR is doing the scalarizing for us, we should only ever see
644 * vectorized operations with a single channel.
646 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
647 channel
= ffs(instr
->dest
.write_mask
) - 1;
649 result
= offset(result
, bld
, channel
);
652 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
653 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
654 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
660 inst
= bld
.MOV(result
, op
[0]);
661 inst
->saturate
= instr
->dest
.saturate
;
666 bld
.MOV(result
, op
[0]);
670 /* AND(val, 0x80000000) gives the sign bit.
672 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
675 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
677 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
678 op
[0].type
= BRW_REGISTER_TYPE_UD
;
679 result
.type
= BRW_REGISTER_TYPE_UD
;
680 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
682 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
683 inst
->predicate
= BRW_PREDICATE_NORMAL
;
684 if (instr
->dest
.saturate
) {
685 inst
= bld
.MOV(result
, result
);
686 inst
->saturate
= true;
692 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
693 * -> non-negative val generates 0x00000000.
694 * Predicated OR sets 1 if val is positive.
696 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
697 bld
.ASR(result
, op
[0], fs_reg(31));
698 inst
= bld
.OR(result
, result
, fs_reg(1));
699 inst
->predicate
= BRW_PREDICATE_NORMAL
;
703 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
704 inst
->saturate
= instr
->dest
.saturate
;
708 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
709 inst
->saturate
= instr
->dest
.saturate
;
713 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
714 inst
->saturate
= instr
->dest
.saturate
;
718 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
719 inst
->saturate
= instr
->dest
.saturate
;
723 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
728 if (fs_key
->high_quality_derivatives
) {
729 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
731 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
735 case nir_op_fddx_fine
:
736 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
737 inst
->saturate
= instr
->dest
.saturate
;
739 case nir_op_fddx_coarse
:
740 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
741 inst
->saturate
= instr
->dest
.saturate
;
744 if (fs_key
->high_quality_derivatives
) {
745 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
746 fs_reg(fs_key
->render_to_fbo
));
748 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
749 fs_reg(fs_key
->render_to_fbo
));
751 inst
->saturate
= instr
->dest
.saturate
;
753 case nir_op_fddy_fine
:
754 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
755 fs_reg(fs_key
->render_to_fbo
));
756 inst
->saturate
= instr
->dest
.saturate
;
758 case nir_op_fddy_coarse
:
759 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
760 fs_reg(fs_key
->render_to_fbo
));
761 inst
->saturate
= instr
->dest
.saturate
;
766 inst
= bld
.ADD(result
, op
[0], op
[1]);
767 inst
->saturate
= instr
->dest
.saturate
;
771 inst
= bld
.MUL(result
, op
[0], op
[1]);
772 inst
->saturate
= instr
->dest
.saturate
;
776 bld
.MUL(result
, op
[0], op
[1]);
779 case nir_op_imul_high
:
780 case nir_op_umul_high
:
781 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
786 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
789 case nir_op_uadd_carry
:
790 unreachable("Should have been lowered by carry_to_arith().");
792 case nir_op_usub_borrow
:
793 unreachable("Should have been lowered by borrow_to_arith().");
796 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
802 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
808 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
813 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
818 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
822 if (devinfo
->gen
>= 8) {
823 op
[0] = resolve_source_modifiers(op
[0]);
825 bld
.NOT(result
, op
[0]);
828 if (devinfo
->gen
>= 8) {
829 op
[0] = resolve_source_modifiers(op
[0]);
830 op
[1] = resolve_source_modifiers(op
[1]);
832 bld
.XOR(result
, op
[0], op
[1]);
835 if (devinfo
->gen
>= 8) {
836 op
[0] = resolve_source_modifiers(op
[0]);
837 op
[1] = resolve_source_modifiers(op
[1]);
839 bld
.OR(result
, op
[0], op
[1]);
842 if (devinfo
->gen
>= 8) {
843 op
[0] = resolve_source_modifiers(op
[0]);
844 op
[1] = resolve_source_modifiers(op
[1]);
846 bld
.AND(result
, op
[0], op
[1]);
858 case nir_op_ball_fequal2
:
859 case nir_op_ball_iequal2
:
860 case nir_op_ball_fequal3
:
861 case nir_op_ball_iequal3
:
862 case nir_op_ball_fequal4
:
863 case nir_op_ball_iequal4
:
864 case nir_op_bany_fnequal2
:
865 case nir_op_bany_inequal2
:
866 case nir_op_bany_fnequal3
:
867 case nir_op_bany_inequal3
:
868 case nir_op_bany_fnequal4
:
869 case nir_op_bany_inequal4
:
870 unreachable("Lowered by nir_lower_alu_reductions");
872 case nir_op_fnoise1_1
:
873 case nir_op_fnoise1_2
:
874 case nir_op_fnoise1_3
:
875 case nir_op_fnoise1_4
:
876 case nir_op_fnoise2_1
:
877 case nir_op_fnoise2_2
:
878 case nir_op_fnoise2_3
:
879 case nir_op_fnoise2_4
:
880 case nir_op_fnoise3_1
:
881 case nir_op_fnoise3_2
:
882 case nir_op_fnoise3_3
:
883 case nir_op_fnoise3_4
:
884 case nir_op_fnoise4_1
:
885 case nir_op_fnoise4_2
:
886 case nir_op_fnoise4_3
:
887 case nir_op_fnoise4_4
:
888 unreachable("not reached: should be handled by lower_noise");
891 unreachable("not reached: should be handled by ldexp_to_arith()");
894 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
895 inst
->saturate
= instr
->dest
.saturate
;
899 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
900 inst
->saturate
= instr
->dest
.saturate
;
905 bld
.MOV(result
, negate(op
[0]));
909 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
912 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
916 inst
= bld
.RNDZ(result
, op
[0]);
917 inst
->saturate
= instr
->dest
.saturate
;
921 op
[0].negate
= !op
[0].negate
;
922 fs_reg temp
= vgrf(glsl_type::float_type
);
923 bld
.RNDD(temp
, op
[0]);
925 inst
= bld
.MOV(result
, temp
);
926 inst
->saturate
= instr
->dest
.saturate
;
930 inst
= bld
.RNDD(result
, op
[0]);
931 inst
->saturate
= instr
->dest
.saturate
;
934 inst
= bld
.FRC(result
, op
[0]);
935 inst
->saturate
= instr
->dest
.saturate
;
937 case nir_op_fround_even
:
938 inst
= bld
.RNDE(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
945 if (devinfo
->gen
>= 6) {
946 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
947 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
949 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
950 inst
= bld
.SEL(result
, op
[0], op
[1]);
951 inst
->predicate
= BRW_PREDICATE_NORMAL
;
953 inst
->saturate
= instr
->dest
.saturate
;
959 if (devinfo
->gen
>= 6) {
960 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
961 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
963 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
964 inst
= bld
.SEL(result
, op
[0], op
[1]);
965 inst
->predicate
= BRW_PREDICATE_NORMAL
;
967 inst
->saturate
= instr
->dest
.saturate
;
970 case nir_op_pack_snorm_2x16
:
971 case nir_op_pack_snorm_4x8
:
972 case nir_op_pack_unorm_2x16
:
973 case nir_op_pack_unorm_4x8
:
974 case nir_op_unpack_snorm_2x16
:
975 case nir_op_unpack_snorm_4x8
:
976 case nir_op_unpack_unorm_2x16
:
977 case nir_op_unpack_unorm_4x8
:
978 case nir_op_unpack_half_2x16
:
979 case nir_op_pack_half_2x16
:
980 unreachable("not reached: should be handled by lower_packing_builtins");
982 case nir_op_unpack_half_2x16_split_x
:
983 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
984 inst
->saturate
= instr
->dest
.saturate
;
986 case nir_op_unpack_half_2x16_split_y
:
987 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
988 inst
->saturate
= instr
->dest
.saturate
;
992 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
993 inst
->saturate
= instr
->dest
.saturate
;
996 case nir_op_bitfield_reverse
:
997 bld
.BFREV(result
, op
[0]);
1000 case nir_op_bit_count
:
1001 bld
.CBIT(result
, op
[0]);
1004 case nir_op_ufind_msb
:
1005 case nir_op_ifind_msb
: {
1006 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1008 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1009 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1010 * subtract the result from 31 to convert the MSB count into an LSB count.
1013 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1014 fs_reg
neg_result(result
);
1015 neg_result
.negate
= true;
1016 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1017 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1021 case nir_op_find_lsb
:
1022 bld
.FBL(result
, op
[0]);
1025 case nir_op_ubitfield_extract
:
1026 case nir_op_ibitfield_extract
:
1027 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1030 bld
.BFI1(result
, op
[0], op
[1]);
1033 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1036 case nir_op_bitfield_insert
:
1037 unreachable("not reached: should be handled by "
1038 "lower_instructions::bitfield_insert_to_bfm_bfi");
1041 bld
.SHL(result
, op
[0], op
[1]);
1044 bld
.ASR(result
, op
[0], op
[1]);
1047 bld
.SHR(result
, op
[0], op
[1]);
1050 case nir_op_pack_half_2x16_split
:
1051 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1055 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1056 inst
->saturate
= instr
->dest
.saturate
;
1060 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1061 inst
->saturate
= instr
->dest
.saturate
;
1065 if (optimize_frontfacing_ternary(instr
, result
))
1068 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1069 inst
= bld
.SEL(result
, op
[1], op
[2]);
1070 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1074 unreachable("unhandled instruction");
1077 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1078 * to sign extend the low bit to 0/~0
1080 if (devinfo
->gen
<= 5 &&
1081 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1082 fs_reg masked
= vgrf(glsl_type::int_type
);
1083 bld
.AND(masked
, result
, fs_reg(1));
1084 masked
.negate
= true;
1085 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1090 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1091 nir_load_const_instr
*instr
)
1093 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1095 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1096 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1098 nir_ssa_values
[instr
->def
.index
] = reg
;
1102 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1104 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1105 instr
->def
.num_components
);
1109 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1110 unsigned base_offset
, nir_src
*indirect
)
1114 assert(!nir_reg
->is_global
);
1116 reg
= v
->nir_locals
[nir_reg
->index
];
1118 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1120 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1122 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1123 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1124 fs_reg(multiplier
));
1131 fs_visitor::get_nir_src(nir_src src
)
1135 reg
= nir_ssa_values
[src
.ssa
->index
];
1137 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1141 /* to avoid floating-point denorm flushing problems, set the type by
1142 * default to D - instructions that need floating point semantics will set
1143 * this to F if they need to
1145 return retype(reg
, BRW_REGISTER_TYPE_D
);
1149 fs_visitor::get_nir_dest(nir_dest dest
)
1152 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1153 dest
.ssa
.num_components
);
1154 return nir_ssa_values
[dest
.ssa
.index
];
1157 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1162 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1164 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1165 BRW_REGISTER_TYPE_UD
);
1167 if (deref
->deref
.child
) {
1168 const nir_deref_array
*deref_array
=
1169 nir_deref_as_array(deref
->deref
.child
);
1170 assert(deref
->deref
.child
->deref_type
== nir_deref_type_array
&&
1171 deref_array
->deref
.child
== NULL
);
1173 image
= offset(image
, bld
,
1174 deref_array
->base_offset
* BRW_IMAGE_PARAM_SIZE
);
1176 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1177 fs_reg
*tmp
= new(mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1178 bld
.MUL(*tmp
, get_nir_src(deref_array
->indirect
),
1179 fs_reg(BRW_IMAGE_PARAM_SIZE
));
1180 image
.reladdr
= tmp
;
1188 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1191 for (unsigned i
= 0; i
< 4; i
++) {
1192 if (!((wr_mask
>> i
) & 1))
1195 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1196 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1197 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1198 if (new_inst
->src
[j
].file
== GRF
)
1199 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1206 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1209 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1210 dest
= get_nir_dest(instr
->dest
);
1212 bool has_indirect
= false;
1214 switch (instr
->intrinsic
) {
1215 case nir_intrinsic_discard
:
1216 case nir_intrinsic_discard_if
: {
1217 /* We track our discarded pixels in f0.1. By predicating on it, we can
1218 * update just the flag bits that aren't yet discarded. If there's no
1219 * condition, we emit a CMP of g0 != g0, so all currently executing
1220 * channels will get turned off.
1223 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1224 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1225 fs_reg(0), BRW_CONDITIONAL_Z
);
1227 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1228 BRW_REGISTER_TYPE_UW
));
1229 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1231 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1232 cmp
->flag_subreg
= 1;
1234 if (devinfo
->gen
>= 6) {
1235 emit_discard_jump();
1240 case nir_intrinsic_atomic_counter_inc
:
1241 case nir_intrinsic_atomic_counter_dec
:
1242 case nir_intrinsic_atomic_counter_read
: {
1243 using namespace surface_access
;
1245 /* Get the arguments of the atomic intrinsic. */
1246 const fs_reg offset
= get_nir_src(instr
->src
[0]);
1247 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
1248 instr
->const_index
[0]);
1251 /* Emit a surface read or atomic op. */
1252 switch (instr
->intrinsic
) {
1253 case nir_intrinsic_atomic_counter_read
:
1254 tmp
= emit_untyped_read(bld
, fs_reg(surface
), offset
, 1, 1);
1257 case nir_intrinsic_atomic_counter_inc
:
1258 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1259 fs_reg(), 1, 1, BRW_AOP_INC
);
1262 case nir_intrinsic_atomic_counter_dec
:
1263 tmp
= emit_untyped_atomic(bld
, fs_reg(surface
), offset
, fs_reg(),
1264 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
1268 unreachable("Unreachable");
1271 /* Assign the result. */
1272 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
1274 /* Mark the surface as used. */
1275 brw_mark_surface_used(stage_prog_data
, surface
);
1279 case nir_intrinsic_memory_barrier
: {
1280 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
1281 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
1286 case nir_intrinsic_load_front_face
:
1287 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1288 *emit_frontfacing_interpolation());
1291 case nir_intrinsic_load_vertex_id
:
1292 unreachable("should be lowered by lower_vertex_id()");
1294 case nir_intrinsic_load_vertex_id_zero_base
: {
1295 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1296 assert(vertex_id
.file
!= BAD_FILE
);
1297 dest
.type
= vertex_id
.type
;
1298 bld
.MOV(dest
, vertex_id
);
1302 case nir_intrinsic_load_base_vertex
: {
1303 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1304 assert(base_vertex
.file
!= BAD_FILE
);
1305 dest
.type
= base_vertex
.type
;
1306 bld
.MOV(dest
, base_vertex
);
1310 case nir_intrinsic_load_instance_id
: {
1311 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1312 assert(instance_id
.file
!= BAD_FILE
);
1313 dest
.type
= instance_id
.type
;
1314 bld
.MOV(dest
, instance_id
);
1318 case nir_intrinsic_load_sample_mask_in
: {
1319 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1320 assert(sample_mask_in
.file
!= BAD_FILE
);
1321 dest
.type
= sample_mask_in
.type
;
1322 bld
.MOV(dest
, sample_mask_in
);
1326 case nir_intrinsic_load_sample_pos
: {
1327 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1328 assert(sample_pos
.file
!= BAD_FILE
);
1329 dest
.type
= sample_pos
.type
;
1330 bld
.MOV(dest
, sample_pos
);
1331 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1335 case nir_intrinsic_load_sample_id
: {
1336 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1337 assert(sample_id
.file
!= BAD_FILE
);
1338 dest
.type
= sample_id
.type
;
1339 bld
.MOV(dest
, sample_id
);
1343 case nir_intrinsic_load_uniform_indirect
:
1344 has_indirect
= true;
1346 case nir_intrinsic_load_uniform
: {
1347 unsigned index
= instr
->const_index
[0];
1350 if (index
< num_direct_uniforms
) {
1351 uniform_reg
= fs_reg(UNIFORM
, 0);
1353 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1354 index
-= num_direct_uniforms
;
1357 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1358 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1360 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1364 dest
= offset(dest
, bld
, 1);
1369 case nir_intrinsic_load_ubo_indirect
:
1370 has_indirect
= true;
1372 case nir_intrinsic_load_ubo
: {
1373 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1377 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1380 /* The block index is not a constant. Evaluate the index expression
1381 * per-channel and add the base UBO index; we have to select a value
1382 * from any live channel.
1384 surf_index
= vgrf(glsl_type::uint_type
);
1385 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1386 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1387 surf_index
= bld
.emit_uniformize(surf_index
);
1389 /* Assume this may touch any UBO. It would be nice to provide
1390 * a tighter bound, but the array information is already lowered away.
1392 brw_mark_surface_used(prog_data
,
1393 stage_prog_data
->binding_table
.ubo_start
+
1394 shader_prog
->NumUniformBlocks
- 1);
1398 /* Turn the byte offset into a dword offset. */
1399 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1400 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1401 BRW_REGISTER_TYPE_D
),
1404 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1405 for (int i
= 0; i
< instr
->num_components
; i
++)
1406 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1407 base_offset
, vec4_offset
+ i
);
1409 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1410 packed_consts
.type
= dest
.type
;
1412 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1413 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1414 surf_index
, const_offset_reg
);
1416 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1417 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1419 /* The std140 packing rules don't allow vectors to cross 16-byte
1420 * boundaries, and a reg is 32 bytes.
1422 assert(packed_consts
.subreg_offset
< 32);
1424 bld
.MOV(dest
, packed_consts
);
1425 dest
= offset(dest
, bld
, 1);
1431 case nir_intrinsic_load_input_indirect
:
1432 has_indirect
= true;
1434 case nir_intrinsic_load_input
: {
1436 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1437 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1438 instr
->const_index
[0] + index
);
1440 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1444 dest
= offset(dest
, bld
, 1);
1449 /* Handle ARB_gpu_shader5 interpolation intrinsics
1451 * It's worth a quick word of explanation as to why we handle the full
1452 * variable-based interpolation intrinsic rather than a lowered version
1453 * with like we do for other inputs. We have to do that because the way
1454 * we set up inputs doesn't allow us to use the already setup inputs for
1455 * interpolation. At the beginning of the shader, we go through all of
1456 * the input variables and do the initial interpolation and put it in
1457 * the nir_inputs array based on its location as determined in
1458 * nir_lower_io. If the input isn't used, dead code cleans up and
1459 * everything works fine. However, when we get to the ARB_gpu_shader5
1460 * interpolation intrinsics, we need to reinterpolate the input
1461 * differently. If we used an intrinsic that just had an index it would
1462 * only give us the offset into the nir_inputs array. However, this is
1463 * useless because that value is post-interpolation and we need
1464 * pre-interpolation. In order to get the actual location of the bits
1465 * we get from the vertex fetching hardware, we need the variable.
1467 case nir_intrinsic_interp_var_at_centroid
:
1468 case nir_intrinsic_interp_var_at_sample
:
1469 case nir_intrinsic_interp_var_at_offset
: {
1470 assert(stage
== MESA_SHADER_FRAGMENT
);
1472 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1474 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1476 /* For most messages, we need one reg of ignored data; the hardware
1477 * requires mlen==1 even when there is no payload. in the per-slot
1478 * offset case, we'll replace this with the proper source data.
1480 fs_reg src
= vgrf(glsl_type::float_type
);
1481 int mlen
= 1; /* one reg unless overriden */
1484 switch (instr
->intrinsic
) {
1485 case nir_intrinsic_interp_var_at_centroid
:
1486 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1487 dst_xy
, src
, fs_reg(0u));
1490 case nir_intrinsic_interp_var_at_sample
: {
1491 /* XXX: We should probably handle non-constant sample id's */
1492 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1493 assert(const_sample
);
1494 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1495 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1500 case nir_intrinsic_interp_var_at_offset
: {
1501 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1504 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1505 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1507 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1508 fs_reg(off_x
| (off_y
<< 4)));
1510 src
= vgrf(glsl_type::ivec2_type
);
1511 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1512 BRW_REGISTER_TYPE_F
);
1513 for (int i
= 0; i
< 2; i
++) {
1514 fs_reg temp
= vgrf(glsl_type::float_type
);
1515 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1516 fs_reg itemp
= vgrf(glsl_type::int_type
);
1517 bld
.MOV(itemp
, temp
); /* float to int */
1519 /* Clamp the upper end of the range to +7/16.
1520 * ARB_gpu_shader5 requires that we support a maximum offset
1521 * of +0.5, which isn't representable in a S0.4 value -- if
1522 * we didn't clamp it, we'd end up with -8/16, which is the
1523 * opposite of what the shader author wanted.
1525 * This is legal due to ARB_gpu_shader5's quantization
1528 * "Not all values of <offset> may be supported; x and y
1529 * offsets may be rounded to fixed-point values with the
1530 * number of fraction bits given by the
1531 * implementation-dependent constant
1532 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1534 set_condmod(BRW_CONDITIONAL_L
,
1535 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1538 mlen
= 2 * dispatch_width
/ 8;
1539 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1546 unreachable("Invalid intrinsic");
1550 /* 2 floats per slot returned */
1551 inst
->regs_written
= 2 * dispatch_width
/ 8;
1552 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1553 INTERP_QUALIFIER_NOPERSPECTIVE
;
1555 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1556 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1557 src
.type
= dest
.type
;
1559 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1560 dest
= offset(dest
, bld
, 1);
1565 case nir_intrinsic_store_output_indirect
:
1566 has_indirect
= true;
1568 case nir_intrinsic_store_output
: {
1569 fs_reg src
= get_nir_src(instr
->src
[0]);
1571 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1572 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1573 instr
->const_index
[0] + index
);
1575 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1577 bld
.MOV(new_dest
, src
);
1578 src
= offset(src
, bld
, 1);
1583 case nir_intrinsic_barrier
:
1588 unreachable("unknown intrinsic");
1593 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1595 unsigned sampler
= instr
->sampler_index
;
1596 fs_reg
sampler_reg(sampler
);
1598 /* FINISHME: We're failing to recompile our programs when the sampler is
1599 * updated. This only matters for the texture rectangle scale parameters
1600 * (pre-gen6, or gen6+ with GL_CLAMP).
1602 int texunit
= prog
->SamplerUnits
[sampler
];
1604 int gather_component
= instr
->component
;
1606 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1608 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1611 int lod_components
= 0;
1612 int UNUSED offset_components
= 0;
1614 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1616 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1617 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1618 switch (instr
->src
[i
].src_type
) {
1619 case nir_tex_src_bias
:
1620 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1622 case nir_tex_src_comparitor
:
1623 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1625 case nir_tex_src_coord
:
1626 switch (instr
->op
) {
1628 case nir_texop_txf_ms
:
1629 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1632 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1636 case nir_tex_src_ddx
:
1637 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1638 lod_components
= nir_tex_instr_src_size(instr
, i
);
1640 case nir_tex_src_ddy
:
1641 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1643 case nir_tex_src_lod
:
1644 switch (instr
->op
) {
1646 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1649 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1652 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1656 case nir_tex_src_ms_index
:
1657 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1659 case nir_tex_src_offset
:
1660 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1661 if (instr
->is_array
)
1662 offset_components
= instr
->coord_components
- 1;
1664 offset_components
= instr
->coord_components
;
1666 case nir_tex_src_projector
:
1667 unreachable("should be lowered");
1669 case nir_tex_src_sampler_offset
: {
1670 /* Figure out the highest possible sampler index and mark it as used */
1671 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1672 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1673 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1675 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1677 brw_mark_surface_used(prog_data
, max_used
);
1679 /* Emit code to evaluate the actual indexing expression */
1680 sampler_reg
= vgrf(glsl_type::uint_type
);
1681 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1682 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1687 unreachable("unknown texture source");
1691 if (instr
->op
== nir_texop_txf_ms
) {
1692 if (devinfo
->gen
>= 7 &&
1693 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1694 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1700 for (unsigned i
= 0; i
< 3; i
++) {
1701 if (instr
->const_offset
[i
] != 0) {
1702 assert(offset_components
== 0);
1703 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1708 enum glsl_base_type dest_base_type
=
1709 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
1711 const glsl_type
*dest_type
=
1712 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1715 ir_texture_opcode op
;
1716 switch (instr
->op
) {
1717 case nir_texop_lod
: op
= ir_lod
; break;
1718 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1719 case nir_texop_tex
: op
= ir_tex
; break;
1720 case nir_texop_tg4
: op
= ir_tg4
; break;
1721 case nir_texop_txb
: op
= ir_txb
; break;
1722 case nir_texop_txd
: op
= ir_txd
; break;
1723 case nir_texop_txf
: op
= ir_txf
; break;
1724 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1725 case nir_texop_txl
: op
= ir_txl
; break;
1726 case nir_texop_txs
: op
= ir_txs
; break;
1728 unreachable("unknown texture opcode");
1731 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1732 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1733 tex_offset
, mcs
, gather_component
,
1734 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1736 fs_reg dest
= get_nir_dest(instr
->dest
);
1737 dest
.type
= this->result
.type
;
1738 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1739 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1740 dest
, this->result
),
1741 (1 << num_components
) - 1);
1745 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1747 switch (instr
->type
) {
1748 case nir_jump_break
:
1749 bld
.emit(BRW_OPCODE_BREAK
);
1751 case nir_jump_continue
:
1752 bld
.emit(BRW_OPCODE_CONTINUE
);
1754 case nir_jump_return
:
1756 unreachable("unknown jump");