2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
53 const glsl_type
*type
,
56 if (type
->is_array() || type
->is_matrix()) {
57 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
58 const unsigned length
= glsl_get_length(type
);
60 for (unsigned i
= 0; i
< length
; i
++) {
61 nir_setup_single_output_varying(reg
, elem_type
, location
);
63 } else if (type
->is_record()) {
64 for (unsigned i
= 0; i
< type
->length
; i
++) {
65 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
66 nir_setup_single_output_varying(reg
, field_type
, location
);
69 assert(type
->is_scalar() || type
->is_vector());
70 unsigned num_iter
= 1;
71 if (type
->is_dual_slot())
73 for (unsigned count
= 0; count
< num_iter
; count
++) {
74 this->outputs
[*location
] = *reg
;
75 *reg
= offset(*reg
, bld
, 4);
82 fs_visitor::nir_setup_outputs()
84 if (stage
== MESA_SHADER_TESS_CTRL
)
87 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
89 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
91 nir_foreach_variable(var
, &nir
->outputs
) {
92 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
95 case MESA_SHADER_VERTEX
:
96 case MESA_SHADER_TESS_EVAL
:
97 case MESA_SHADER_GEOMETRY
: {
98 unsigned location
= var
->data
.location
;
99 nir_setup_single_output_varying(®
, var
->type
, &location
);
102 case MESA_SHADER_FRAGMENT
:
103 if (key
->force_dual_color_blend
&&
104 var
->data
.location
== FRAG_RESULT_DATA1
) {
105 this->dual_src_output
= reg
;
106 this->do_dual_src
= true;
107 } else if (var
->data
.index
> 0) {
108 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
109 assert(var
->data
.index
== 1);
110 this->dual_src_output
= reg
;
111 this->do_dual_src
= true;
112 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
113 /* Writing gl_FragColor outputs to all color regions. */
114 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
115 this->outputs
[i
] = reg
;
117 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
118 this->frag_depth
= reg
;
119 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
120 this->frag_stencil
= reg
;
121 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
122 this->sample_mask
= reg
;
124 /* gl_FragData or a user-defined FS output */
125 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
126 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
128 /* General color output. */
129 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
130 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
131 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
136 unreachable("unhandled shader stage");
142 fs_visitor::nir_setup_uniforms()
144 if (dispatch_width
!= min_dispatch_width
)
147 uniforms
= nir
->num_uniforms
/ 4;
151 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
155 nir_foreach_instr(instr
, block
) {
156 if (instr
->type
!= nir_instr_type_intrinsic
)
159 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
160 switch (intrin
->intrinsic
) {
161 case nir_intrinsic_load_vertex_id
:
162 unreachable("should be lowered by lower_vertex_id().");
164 case nir_intrinsic_load_vertex_id_zero_base
:
165 assert(v
->stage
== MESA_SHADER_VERTEX
);
166 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
167 if (reg
->file
== BAD_FILE
)
168 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
171 case nir_intrinsic_load_base_vertex
:
172 assert(v
->stage
== MESA_SHADER_VERTEX
);
173 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
174 if (reg
->file
== BAD_FILE
)
175 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
178 case nir_intrinsic_load_instance_id
:
179 assert(v
->stage
== MESA_SHADER_VERTEX
);
180 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
181 if (reg
->file
== BAD_FILE
)
182 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
185 case nir_intrinsic_load_base_instance
:
186 assert(v
->stage
== MESA_SHADER_VERTEX
);
187 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
188 if (reg
->file
== BAD_FILE
)
189 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
192 case nir_intrinsic_load_draw_id
:
193 assert(v
->stage
== MESA_SHADER_VERTEX
);
194 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
195 if (reg
->file
== BAD_FILE
)
196 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
199 case nir_intrinsic_load_invocation_id
:
200 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
202 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
203 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
204 if (reg
->file
== BAD_FILE
) {
205 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
206 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
207 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
208 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
213 case nir_intrinsic_load_sample_pos
:
214 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
215 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
216 if (reg
->file
== BAD_FILE
)
217 *reg
= *v
->emit_samplepos_setup();
220 case nir_intrinsic_load_sample_id
:
221 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
222 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
223 if (reg
->file
== BAD_FILE
)
224 *reg
= *v
->emit_sampleid_setup();
227 case nir_intrinsic_load_sample_mask_in
:
228 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
229 assert(v
->devinfo
->gen
>= 7);
230 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
231 if (reg
->file
== BAD_FILE
)
232 *reg
= *v
->emit_samplemaskin_setup();
235 case nir_intrinsic_load_work_group_id
:
236 assert(v
->stage
== MESA_SHADER_COMPUTE
);
237 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
238 if (reg
->file
== BAD_FILE
)
239 *reg
= *v
->emit_cs_work_group_id_setup();
242 case nir_intrinsic_load_helper_invocation
:
243 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
244 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
245 if (reg
->file
== BAD_FILE
) {
246 const fs_builder abld
=
247 v
->bld
.annotate("gl_HelperInvocation", NULL
);
249 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
250 * pixel mask is in g1.7 of the thread payload.
252 * We move the per-channel pixel enable bit to the low bit of each
253 * channel by shifting the byte containing the pixel mask by the
254 * vector immediate 0x76543210UV.
256 * The region of <1,8,0> reads only 1 byte (the pixel masks for
257 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
258 * masks for 2 and 3) in SIMD16.
260 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
262 stride(byte_offset(retype(brw_vec1_grf(1, 0),
263 BRW_REGISTER_TYPE_UB
), 28),
265 brw_imm_v(0x76543210));
267 /* A set bit in the pixel mask means the channel is enabled, but
268 * that is the opposite of gl_HelperInvocation so we need to invert
271 * The negate source-modifier bit of logical instructions on Gen8+
272 * performs 1's complement negation, so we can use that instead of
275 fs_reg inverted
= negate(shifted
);
276 if (v
->devinfo
->gen
< 8) {
277 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
278 abld
.NOT(inverted
, shifted
);
281 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
282 * with 1 and negating.
284 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
285 abld
.AND(anded
, inverted
, brw_imm_uw(1));
287 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
288 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
302 fs_visitor::nir_emit_system_values()
304 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
305 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
306 nir_system_values
[i
] = fs_reg();
309 nir_foreach_function(function
, nir
) {
310 assert(strcmp(function
->name
, "main") == 0);
311 assert(function
->impl
);
312 nir_foreach_block(block
, function
->impl
) {
313 emit_system_values_block(block
, this);
319 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
321 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
322 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
323 nir_locals
[i
] = fs_reg();
326 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
327 unsigned array_elems
=
328 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
329 unsigned size
= array_elems
* reg
->num_components
;
330 const brw_reg_type reg_type
=
331 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
332 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
335 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
338 nir_emit_cf_list(&impl
->body
);
342 fs_visitor::nir_emit_cf_list(exec_list
*list
)
344 exec_list_validate(list
);
345 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
346 switch (node
->type
) {
348 nir_emit_if(nir_cf_node_as_if(node
));
351 case nir_cf_node_loop
:
352 nir_emit_loop(nir_cf_node_as_loop(node
));
355 case nir_cf_node_block
:
356 nir_emit_block(nir_cf_node_as_block(node
));
360 unreachable("Invalid CFG node block");
366 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
368 /* first, put the condition into f0 */
369 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
370 retype(get_nir_src(if_stmt
->condition
),
371 BRW_REGISTER_TYPE_D
));
372 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
374 bld
.IF(BRW_PREDICATE_NORMAL
);
376 nir_emit_cf_list(&if_stmt
->then_list
);
378 /* note: if the else is empty, dead CF elimination will remove it */
379 bld
.emit(BRW_OPCODE_ELSE
);
381 nir_emit_cf_list(&if_stmt
->else_list
);
383 bld
.emit(BRW_OPCODE_ENDIF
);
387 fs_visitor::nir_emit_loop(nir_loop
*loop
)
389 bld
.emit(BRW_OPCODE_DO
);
391 nir_emit_cf_list(&loop
->body
);
393 bld
.emit(BRW_OPCODE_WHILE
);
397 fs_visitor::nir_emit_block(nir_block
*block
)
399 nir_foreach_instr(instr
, block
) {
400 nir_emit_instr(instr
);
405 fs_visitor::nir_emit_instr(nir_instr
*instr
)
407 const fs_builder abld
= bld
.annotate(NULL
, instr
);
409 switch (instr
->type
) {
410 case nir_instr_type_alu
:
411 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
414 case nir_instr_type_intrinsic
:
416 case MESA_SHADER_VERTEX
:
417 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
419 case MESA_SHADER_TESS_CTRL
:
420 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
422 case MESA_SHADER_TESS_EVAL
:
423 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
425 case MESA_SHADER_GEOMETRY
:
426 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
428 case MESA_SHADER_FRAGMENT
:
429 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
431 case MESA_SHADER_COMPUTE
:
432 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
435 unreachable("unsupported shader stage");
439 case nir_instr_type_tex
:
440 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
443 case nir_instr_type_load_const
:
444 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
447 case nir_instr_type_ssa_undef
:
448 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
451 case nir_instr_type_jump
:
452 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
456 unreachable("unknown instruction type");
461 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
465 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
466 const fs_reg
&result
)
468 if (!instr
->src
[0].src
.is_ssa
||
469 !instr
->src
[0].src
.ssa
->parent_instr
)
472 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
475 nir_alu_instr
*src0
=
476 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
478 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
479 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
482 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
483 assert(element
!= NULL
);
485 /* Element type to extract.*/
486 const brw_reg_type type
= brw_int_type(
487 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
488 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
490 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
491 op0
.type
= brw_type_for_nir_type(
492 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
493 nir_src_bit_size(src0
->src
[0].src
)));
494 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
496 set_saturate(instr
->dest
.saturate
,
497 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
502 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
503 const fs_reg
&result
)
505 if (!instr
->src
[0].src
.is_ssa
||
506 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
509 nir_intrinsic_instr
*src0
=
510 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
512 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
515 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
516 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
519 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
520 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
523 fs_reg tmp
= vgrf(glsl_type::int_type
);
525 if (devinfo
->gen
>= 6) {
526 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
527 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
529 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
531 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
532 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
534 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
536 * This negation looks like it's safe in practice, because bits 0:4 will
537 * surely be TRIANGLES
540 if (value1
->f32
[0] == -1.0f
) {
544 tmp
.type
= BRW_REGISTER_TYPE_W
;
545 tmp
.subreg_offset
= 2;
548 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
550 tmp
.type
= BRW_REGISTER_TYPE_D
;
551 tmp
.subreg_offset
= 0;
554 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
555 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
557 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
559 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
560 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
562 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
564 * This negation looks like it's safe in practice, because bits 0:4 will
565 * surely be TRIANGLES
568 if (value1
->f32
[0] == -1.0f
) {
572 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
574 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
580 emit_find_msb_using_lzd(const fs_builder
&bld
,
581 const fs_reg
&result
,
589 /* LZD of an absolute value source almost always does the right
590 * thing. There are two problem values:
592 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
593 * 0. However, findMSB(int(0x80000000)) == 30.
595 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
596 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
598 * For a value of zero or negative one, -1 will be returned.
600 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
601 * findMSB(-(1<<x)) should return x-1.
603 * For all negative number cases, including 0x80000000 and
604 * 0xffffffff, the correct value is obtained from LZD if instead of
605 * negating the (already negative) value the logical-not is used. A
606 * conditonal logical-not can be achieved in two instructions.
608 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
610 bld
.ASR(temp
, src
, brw_imm_d(31));
611 bld
.XOR(temp
, temp
, src
);
614 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
615 retype(temp
, BRW_REGISTER_TYPE_UD
));
617 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
618 * from the LSB side. Subtract the result from 31 to convert the MSB
619 * count into an LSB count. If no bits are set, LZD will return 32.
620 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
622 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
623 inst
->src
[0].negate
= true;
627 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
629 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
632 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
633 result
.type
= brw_type_for_nir_type(
634 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
635 nir_dest_bit_size(instr
->dest
.dest
)));
638 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 op
[i
] = get_nir_src(instr
->src
[i
].src
);
640 op
[i
].type
= brw_type_for_nir_type(
641 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
642 nir_src_bit_size(instr
->src
[i
].src
)));
643 op
[i
].abs
= instr
->src
[i
].abs
;
644 op
[i
].negate
= instr
->src
[i
].negate
;
647 /* We get a bunch of mov's out of the from_ssa pass and they may still
648 * be vectorized. We'll handle them as a special-case. We'll also
649 * handle vecN here because it's basically the same thing.
657 fs_reg temp
= result
;
658 bool need_extra_copy
= false;
659 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
660 if (!instr
->src
[i
].src
.is_ssa
&&
661 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
662 need_extra_copy
= true;
663 temp
= bld
.vgrf(result
.type
, 4);
668 for (unsigned i
= 0; i
< 4; i
++) {
669 if (!(instr
->dest
.write_mask
& (1 << i
)))
672 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
673 inst
= bld
.MOV(offset(temp
, bld
, i
),
674 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
676 inst
= bld
.MOV(offset(temp
, bld
, i
),
677 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
679 inst
->saturate
= instr
->dest
.saturate
;
682 /* In this case the source and destination registers were the same,
683 * so we need to insert an extra set of moves in order to deal with
686 if (need_extra_copy
) {
687 for (unsigned i
= 0; i
< 4; i
++) {
688 if (!(instr
->dest
.write_mask
& (1 << i
)))
691 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
700 /* At this point, we have dealt with any instruction that operates on
701 * more than a single channel. Therefore, we can just adjust the source
702 * and destination registers for that channel and emit the instruction.
704 unsigned channel
= 0;
705 if (nir_op_infos
[instr
->op
].output_size
== 0) {
706 /* Since NIR is doing the scalarizing for us, we should only ever see
707 * vectorized operations with a single channel.
709 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
710 channel
= ffs(instr
->dest
.write_mask
) - 1;
712 result
= offset(result
, bld
, channel
);
715 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
716 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
717 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
723 if (optimize_extract_to_float(instr
, result
))
725 inst
= bld
.MOV(result
, op
[0]);
726 inst
->saturate
= instr
->dest
.saturate
;
732 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
734 * "When source or destination is 64b (...), regioning in Align1
735 * must follow these rules:
737 * 1. Source and destination horizontal stride must be aligned to
741 * This means that 32-bit to 64-bit conversions need to have the 32-bit
742 * data elements aligned to 64-bit. This restriction does not apply to
745 if (devinfo
->is_cherryview
|| devinfo
->is_broxton
) {
746 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
747 tmp
= subscript(tmp
, op
[0].type
, 0);
748 inst
= bld
.MOV(tmp
, op
[0]);
749 inst
= bld
.MOV(result
, tmp
);
750 inst
->saturate
= instr
->dest
.saturate
;
757 inst
= bld
.MOV(result
, op
[0]);
758 inst
->saturate
= instr
->dest
.saturate
;
763 bld
.MOV(result
, op
[0]);
767 if (type_sz(op
[0].type
) < 8) {
768 /* AND(val, 0x80000000) gives the sign bit.
770 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
773 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
775 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
776 op
[0].type
= BRW_REGISTER_TYPE_UD
;
777 result
.type
= BRW_REGISTER_TYPE_UD
;
778 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
780 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
781 inst
->predicate
= BRW_PREDICATE_NORMAL
;
782 if (instr
->dest
.saturate
) {
783 inst
= bld
.MOV(result
, result
);
784 inst
->saturate
= true;
787 /* For doubles we do the same but we need to consider:
789 * - 2-src instructions can't operate with 64-bit immediates
790 * - The sign is encoded in the high 32-bit of each DF
791 * - CMP with DF requires special handling in SIMD16
792 * - We need to produce a DF result.
795 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
796 * a register and compare with that.
798 fs_reg tmp
= vgrf(glsl_type::double_type
);
799 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
801 /* A direct DF CMP using the flag register (null dst) won't work in
802 * SIMD16 because the CMP will be split in two by lower_simd_width,
803 * resulting in two CMP instructions with the same dst (NULL),
804 * leading to dead code elimination of the first one. In SIMD8,
805 * however, there is no need to split the CMP and we can save some
808 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
809 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
811 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
812 * so we store the result of the comparison in a vgrf instead and
813 * then we generate a UD comparison from that that won't have to
814 * be split by lower_simd_width. This is what NIR does to handle
815 * double comparisons in the general case.
817 if (bld
.dispatch_width() == 16 ) {
818 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
819 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
820 bld
.CMP(bld
.null_reg_ud(),
821 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
824 /* Get the high 32-bit of each double component where the sign is */
825 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
826 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
828 /* Get the sign bit */
829 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
831 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
832 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
833 inst
->predicate
= BRW_PREDICATE_NORMAL
;
835 /* Convert from 32-bit float to 64-bit double */
836 result
.type
= BRW_REGISTER_TYPE_DF
;
837 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
839 if (instr
->dest
.saturate
) {
840 inst
= bld
.MOV(result
, result
);
841 inst
->saturate
= true;
848 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
849 * -> non-negative val generates 0x00000000.
850 * Predicated OR sets 1 if val is positive.
852 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
853 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
854 bld
.ASR(result
, op
[0], brw_imm_d(31));
855 inst
= bld
.OR(result
, result
, brw_imm_d(1));
856 inst
->predicate
= BRW_PREDICATE_NORMAL
;
860 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
861 inst
->saturate
= instr
->dest
.saturate
;
865 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
870 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
875 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
876 inst
->saturate
= instr
->dest
.saturate
;
880 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
881 inst
->saturate
= instr
->dest
.saturate
;
885 if (fs_key
->high_quality_derivatives
) {
886 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
888 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
892 case nir_op_fddx_fine
:
893 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
894 inst
->saturate
= instr
->dest
.saturate
;
896 case nir_op_fddx_coarse
:
897 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
898 inst
->saturate
= instr
->dest
.saturate
;
901 if (fs_key
->high_quality_derivatives
) {
902 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
904 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
906 inst
->saturate
= instr
->dest
.saturate
;
908 case nir_op_fddy_fine
:
909 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
910 inst
->saturate
= instr
->dest
.saturate
;
912 case nir_op_fddy_coarse
:
913 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
914 inst
->saturate
= instr
->dest
.saturate
;
918 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
920 inst
= bld
.ADD(result
, op
[0], op
[1]);
921 inst
->saturate
= instr
->dest
.saturate
;
925 inst
= bld
.MUL(result
, op
[0], op
[1]);
926 inst
->saturate
= instr
->dest
.saturate
;
930 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
931 bld
.MUL(result
, op
[0], op
[1]);
934 case nir_op_imul_high
:
935 case nir_op_umul_high
:
936 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
937 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
942 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
943 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
946 case nir_op_uadd_carry
:
947 unreachable("Should have been lowered by carry_to_arith().");
949 case nir_op_usub_borrow
:
950 unreachable("Should have been lowered by borrow_to_arith().");
954 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
955 * appears that our hardware just does the right thing for signed
958 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
959 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
963 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
964 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
966 /* Math instructions don't support conditional mod */
967 inst
= bld
.MOV(bld
.null_reg_d(), result
);
968 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
970 /* Now, we need to determine if signs of the sources are different.
971 * When we XOR the sources, the top bit is 0 if they are the same and 1
972 * if they are different. We can then use a conditional modifier to
973 * turn that into a predicate. This leads us to an XOR.l instruction.
975 * Technically, according to the PRM, you're not allowed to use .l on a
976 * XOR instruction. However, emperical experiments and Curro's reading
977 * of the simulator source both indicate that it's safe.
979 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
980 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
981 inst
->predicate
= BRW_PREDICATE_NORMAL
;
982 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
984 /* If the result of the initial remainder operation is non-zero and the
985 * two sources have different signs, add in a copy of op[1] to get the
986 * final integer modulus value.
988 inst
= bld
.ADD(result
, result
, op
[1]);
989 inst
->predicate
= BRW_PREDICATE_NORMAL
;
997 fs_reg dest
= result
;
998 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
999 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
1001 brw_conditional_mod cond
;
1002 switch (instr
->op
) {
1004 cond
= BRW_CONDITIONAL_L
;
1007 cond
= BRW_CONDITIONAL_GE
;
1010 cond
= BRW_CONDITIONAL_Z
;
1013 cond
= BRW_CONDITIONAL_NZ
;
1016 unreachable("bad opcode");
1018 bld
.CMP(dest
, op
[0], op
[1], cond
);
1019 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1020 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1027 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1028 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1033 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1034 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1038 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1039 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1043 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1044 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1048 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1049 if (devinfo
->gen
>= 8) {
1050 op
[0] = resolve_source_modifiers(op
[0]);
1052 bld
.NOT(result
, op
[0]);
1055 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1056 if (devinfo
->gen
>= 8) {
1057 op
[0] = resolve_source_modifiers(op
[0]);
1058 op
[1] = resolve_source_modifiers(op
[1]);
1060 bld
.XOR(result
, op
[0], op
[1]);
1063 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1064 if (devinfo
->gen
>= 8) {
1065 op
[0] = resolve_source_modifiers(op
[0]);
1066 op
[1] = resolve_source_modifiers(op
[1]);
1068 bld
.OR(result
, op
[0], op
[1]);
1071 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1072 if (devinfo
->gen
>= 8) {
1073 op
[0] = resolve_source_modifiers(op
[0]);
1074 op
[1] = resolve_source_modifiers(op
[1]);
1076 bld
.AND(result
, op
[0], op
[1]);
1082 case nir_op_ball_fequal2
:
1083 case nir_op_ball_iequal2
:
1084 case nir_op_ball_fequal3
:
1085 case nir_op_ball_iequal3
:
1086 case nir_op_ball_fequal4
:
1087 case nir_op_ball_iequal4
:
1088 case nir_op_bany_fnequal2
:
1089 case nir_op_bany_inequal2
:
1090 case nir_op_bany_fnequal3
:
1091 case nir_op_bany_inequal3
:
1092 case nir_op_bany_fnequal4
:
1093 case nir_op_bany_inequal4
:
1094 unreachable("Lowered by nir_lower_alu_reductions");
1096 case nir_op_fnoise1_1
:
1097 case nir_op_fnoise1_2
:
1098 case nir_op_fnoise1_3
:
1099 case nir_op_fnoise1_4
:
1100 case nir_op_fnoise2_1
:
1101 case nir_op_fnoise2_2
:
1102 case nir_op_fnoise2_3
:
1103 case nir_op_fnoise2_4
:
1104 case nir_op_fnoise3_1
:
1105 case nir_op_fnoise3_2
:
1106 case nir_op_fnoise3_3
:
1107 case nir_op_fnoise3_4
:
1108 case nir_op_fnoise4_1
:
1109 case nir_op_fnoise4_2
:
1110 case nir_op_fnoise4_3
:
1111 case nir_op_fnoise4_4
:
1112 unreachable("not reached: should be handled by lower_noise");
1115 unreachable("not reached: should be handled by ldexp_to_arith()");
1118 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1119 inst
->saturate
= instr
->dest
.saturate
;
1123 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1124 inst
->saturate
= instr
->dest
.saturate
;
1129 bld
.MOV(result
, negate(op
[0]));
1133 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1136 /* two-argument instructions can't take 64-bit immediates */
1137 fs_reg zero
= vgrf(glsl_type::double_type
);
1138 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1139 /* A SIMD16 execution needs to be split in two instructions, so use
1140 * a vgrf instead of the flag register as dst so instruction splitting
1143 fs_reg tmp
= vgrf(glsl_type::double_type
);
1144 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1145 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1149 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1153 inst
= bld
.RNDZ(result
, op
[0]);
1154 inst
->saturate
= instr
->dest
.saturate
;
1157 case nir_op_fceil
: {
1158 op
[0].negate
= !op
[0].negate
;
1159 fs_reg temp
= vgrf(glsl_type::float_type
);
1160 bld
.RNDD(temp
, op
[0]);
1162 inst
= bld
.MOV(result
, temp
);
1163 inst
->saturate
= instr
->dest
.saturate
;
1167 inst
= bld
.RNDD(result
, op
[0]);
1168 inst
->saturate
= instr
->dest
.saturate
;
1171 inst
= bld
.FRC(result
, op
[0]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1174 case nir_op_fround_even
:
1175 inst
= bld
.RNDE(result
, op
[0]);
1176 inst
->saturate
= instr
->dest
.saturate
;
1179 case nir_op_fquantize2f16
: {
1180 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1181 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1182 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1184 /* The destination stride must be at least as big as the source stride. */
1185 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1188 /* Check for denormal */
1189 fs_reg abs_src0
= op
[0];
1190 abs_src0
.abs
= true;
1191 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1193 /* Get the appropriately signed zero */
1194 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1195 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1196 brw_imm_ud(0x80000000));
1197 /* Do the actual F32 -> F16 -> F32 conversion */
1198 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1199 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1200 /* Select that or zero based on normal status */
1201 inst
= bld
.SEL(result
, zero
, tmp32
);
1202 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1203 inst
->saturate
= instr
->dest
.saturate
;
1209 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1211 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1212 inst
->saturate
= instr
->dest
.saturate
;
1217 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1219 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1220 inst
->saturate
= instr
->dest
.saturate
;
1223 case nir_op_pack_snorm_2x16
:
1224 case nir_op_pack_snorm_4x8
:
1225 case nir_op_pack_unorm_2x16
:
1226 case nir_op_pack_unorm_4x8
:
1227 case nir_op_unpack_snorm_2x16
:
1228 case nir_op_unpack_snorm_4x8
:
1229 case nir_op_unpack_unorm_2x16
:
1230 case nir_op_unpack_unorm_4x8
:
1231 case nir_op_unpack_half_2x16
:
1232 case nir_op_pack_half_2x16
:
1233 unreachable("not reached: should be handled by lower_packing_builtins");
1235 case nir_op_unpack_half_2x16_split_x
:
1236 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1237 inst
->saturate
= instr
->dest
.saturate
;
1239 case nir_op_unpack_half_2x16_split_y
:
1240 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1241 inst
->saturate
= instr
->dest
.saturate
;
1244 case nir_op_pack_double_2x32_split
:
1245 /* Optimize the common case where we are re-packing a double with
1246 * the result of a previous double unpack. In this case we can take the
1247 * 32-bit value to use in the re-pack from the original double and bypass
1248 * the unpack operation.
1250 for (int i
= 0; i
< 2; i
++) {
1251 if (instr
->src
[i
].src
.is_ssa
)
1254 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1255 if (parent_instr
->type
== nir_instr_type_alu
)
1258 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1259 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1260 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1263 if (!alu_parent
->src
[0].src
.is_ssa
)
1266 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1267 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1268 alu_parent
->src
[0].swizzle
[channel
]);
1269 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1270 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1272 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1274 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1277 case nir_op_unpack_double_2x32_split_x
:
1278 case nir_op_unpack_double_2x32_split_y
: {
1279 /* Optimize the common case where we are unpacking from a double we have
1280 * previously packed. In this case we can just bypass the pack operation
1281 * and source directly from its arguments.
1283 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1284 if (instr
->src
[0].src
.is_ssa
) {
1285 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1286 if (parent_instr
->type
== nir_instr_type_alu
) {
1287 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1288 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1289 alu_parent
->src
[index
].src
.is_ssa
) {
1290 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1291 BRW_REGISTER_TYPE_UD
);
1293 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1294 bld
.MOV(result
, op
[0]);
1300 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1301 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1303 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1308 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1309 inst
->saturate
= instr
->dest
.saturate
;
1312 case nir_op_bitfield_reverse
:
1313 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1314 bld
.BFREV(result
, op
[0]);
1317 case nir_op_bit_count
:
1318 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1319 bld
.CBIT(result
, op
[0]);
1322 case nir_op_ufind_msb
: {
1323 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1324 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1328 case nir_op_ifind_msb
: {
1329 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 if (devinfo
->gen
< 7) {
1332 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1334 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1336 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1337 * count from the LSB side. If FBH didn't return an error
1338 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1339 * count into an LSB count.
1341 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1343 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1344 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1345 inst
->src
[0].negate
= true;
1350 case nir_op_find_lsb
:
1351 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1353 if (devinfo
->gen
< 7) {
1354 fs_reg temp
= vgrf(glsl_type::int_type
);
1356 /* (x & -x) generates a value that consists of only the LSB of x.
1357 * For all powers of 2, findMSB(y) == findLSB(y).
1359 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1360 fs_reg negated_src
= src
;
1362 /* One must be negated, and the other must be non-negated. It
1363 * doesn't matter which is which.
1365 negated_src
.negate
= true;
1368 bld
.AND(temp
, src
, negated_src
);
1369 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1371 bld
.FBL(result
, op
[0]);
1375 case nir_op_ubitfield_extract
:
1376 case nir_op_ibitfield_extract
:
1377 unreachable("should have been lowered");
1380 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1381 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1384 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1385 bld
.BFI1(result
, op
[0], op
[1]);
1388 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1389 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1392 case nir_op_bitfield_insert
:
1393 unreachable("not reached: should have been lowered");
1396 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1397 bld
.SHL(result
, op
[0], op
[1]);
1400 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1401 bld
.ASR(result
, op
[0], op
[1]);
1404 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1405 bld
.SHR(result
, op
[0], op
[1]);
1408 case nir_op_pack_half_2x16_split
:
1409 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1413 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1414 inst
->saturate
= instr
->dest
.saturate
;
1418 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1419 inst
->saturate
= instr
->dest
.saturate
;
1423 if (optimize_frontfacing_ternary(instr
, result
))
1426 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1427 inst
= bld
.SEL(result
, op
[1], op
[2]);
1428 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1431 case nir_op_extract_u8
:
1432 case nir_op_extract_i8
: {
1433 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1434 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1435 assert(byte
!= NULL
);
1436 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1440 case nir_op_extract_u16
:
1441 case nir_op_extract_i16
: {
1442 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1443 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1444 assert(word
!= NULL
);
1445 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1450 unreachable("unhandled instruction");
1453 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1454 * to sign extend the low bit to 0/~0
1456 if (devinfo
->gen
<= 5 &&
1457 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1458 fs_reg masked
= vgrf(glsl_type::int_type
);
1459 bld
.AND(masked
, result
, brw_imm_d(1));
1460 masked
.negate
= true;
1461 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1466 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1467 nir_load_const_instr
*instr
)
1469 const brw_reg_type reg_type
=
1470 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1471 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1473 switch (instr
->def
.bit_size
) {
1475 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1476 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1480 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1481 bld
.MOV(offset(reg
, bld
, i
),
1482 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1486 unreachable("Invalid bit size");
1489 nir_ssa_values
[instr
->def
.index
] = reg
;
1493 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1495 const brw_reg_type reg_type
=
1496 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1497 nir_ssa_values
[instr
->def
.index
] =
1498 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1502 fs_visitor::get_nir_src(const nir_src
&src
)
1506 reg
= nir_ssa_values
[src
.ssa
->index
];
1508 /* We don't handle indirects on locals */
1509 assert(src
.reg
.indirect
== NULL
);
1510 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1511 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1514 /* to avoid floating-point denorm flushing problems, set the type by
1515 * default to D - instructions that need floating point semantics will set
1516 * this to F if they need to
1518 return retype(reg
, BRW_REGISTER_TYPE_D
);
1522 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1525 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1527 nir_const_value
*val
= nir_src_as_const_value(src
);
1528 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1532 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1535 const brw_reg_type reg_type
=
1536 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1537 nir_ssa_values
[dest
.ssa
.index
] =
1538 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1539 return nir_ssa_values
[dest
.ssa
.index
];
1541 /* We don't handle indirects on locals */
1542 assert(dest
.reg
.indirect
== NULL
);
1543 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1544 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1549 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1551 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1552 BRW_REGISTER_TYPE_UD
);
1554 unsigned indirect_max
= 0;
1556 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1557 tail
= tail
->child
) {
1558 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1559 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1560 const unsigned size
= glsl_get_length(tail
->type
);
1561 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1562 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1563 image
= offset(image
, bld
, base
* element_size
);
1565 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1566 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1568 /* Accessing an invalid surface index with the dataport can result
1569 * in a hang. According to the spec "if the index used to
1570 * select an individual element is negative or greater than or
1571 * equal to the size of the array, the results of the operation
1572 * are undefined but may not lead to termination" -- which is one
1573 * of the possible outcomes of the hang. Clamp the index to
1574 * prevent access outside of the array bounds.
1576 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1577 BRW_REGISTER_TYPE_UD
),
1578 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1580 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1582 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1583 if (indirect
.file
== BAD_FILE
) {
1586 bld
.ADD(indirect
, indirect
, tmp
);
1591 if (indirect
.file
== BAD_FILE
) {
1594 /* Emit a pile of MOVs to load the uniform into a temporary. The
1595 * dead-code elimination pass will get rid of what we don't use.
1597 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1598 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1599 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1600 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1601 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1608 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1611 for (unsigned i
= 0; i
< 4; i
++) {
1612 if (!((wr_mask
>> i
) & 1))
1615 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1616 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1617 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1618 if (new_inst
->src
[j
].file
== VGRF
)
1619 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1626 * Get the matching channel register datatype for an image intrinsic of the
1627 * specified GLSL image type.
1630 get_image_base_type(const glsl_type
*type
)
1632 switch ((glsl_base_type
)type
->sampled_type
) {
1633 case GLSL_TYPE_UINT
:
1634 return BRW_REGISTER_TYPE_UD
;
1636 return BRW_REGISTER_TYPE_D
;
1637 case GLSL_TYPE_FLOAT
:
1638 return BRW_REGISTER_TYPE_F
;
1640 unreachable("Not reached.");
1645 * Get the appropriate atomic op for an image atomic intrinsic.
1648 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1651 case nir_intrinsic_image_atomic_add
:
1653 case nir_intrinsic_image_atomic_min
:
1654 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1655 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1656 case nir_intrinsic_image_atomic_max
:
1657 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1658 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1659 case nir_intrinsic_image_atomic_and
:
1661 case nir_intrinsic_image_atomic_or
:
1663 case nir_intrinsic_image_atomic_xor
:
1665 case nir_intrinsic_image_atomic_exchange
:
1667 case nir_intrinsic_image_atomic_comp_swap
:
1668 return BRW_AOP_CMPWR
;
1670 unreachable("Not reachable.");
1675 emit_pixel_interpolater_send(const fs_builder
&bld
,
1680 glsl_interp_mode interpolation
)
1682 struct brw_wm_prog_data
*wm_prog_data
=
1683 (struct brw_wm_prog_data
*) bld
.shader
->stage_prog_data
;
1688 if (src
.file
== BAD_FILE
) {
1690 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1694 mlen
= 2 * bld
.dispatch_width() / 8;
1697 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1699 /* 2 floats per slot returned */
1700 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1701 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1703 wm_prog_data
->pulls_bary
= true;
1709 * Computes 1 << x, given a D/UD register containing some value x.
1712 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1714 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1716 fs_reg result
= bld
.vgrf(x
.type
, 1);
1717 fs_reg one
= bld
.vgrf(x
.type
, 1);
1719 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1720 bld
.SHL(result
, one
, x
);
1725 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1727 assert(stage
== MESA_SHADER_GEOMETRY
);
1729 struct brw_gs_prog_data
*gs_prog_data
=
1730 (struct brw_gs_prog_data
*) prog_data
;
1732 if (gs_compile
->control_data_header_size_bits
== 0)
1735 /* We can only do EndPrimitive() functionality when the control data
1736 * consists of cut bits. Fortunately, the only time it isn't is when the
1737 * output type is points, in which case EndPrimitive() is a no-op.
1739 if (gs_prog_data
->control_data_format
!=
1740 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1744 /* Cut bits use one bit per vertex. */
1745 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1747 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1748 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1750 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1751 * vertex n, 0 otherwise. So all we need to do here is mark bit
1752 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1753 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1754 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1756 * Note that if EndPrimitive() is called before emitting any vertices, this
1757 * will cause us to set bit 31 of the control_data_bits register to 1.
1758 * That's fine because:
1760 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1761 * output, so the hardware will ignore cut bit 31.
1763 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1764 * last vertex, so setting cut bit 31 has no effect (since the primitive
1765 * is automatically ended when the GS terminates).
1767 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1768 * control_data_bits register to 0 when the first vertex is emitted.
1771 const fs_builder abld
= bld
.annotate("end primitive");
1773 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1774 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1775 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1776 fs_reg mask
= intexp2(abld
, prev_count
);
1777 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1778 * attention to the lower 5 bits of its second source argument, so on this
1779 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1780 * ((vertex_count - 1) % 32).
1782 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1786 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1788 assert(stage
== MESA_SHADER_GEOMETRY
);
1789 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1791 struct brw_gs_prog_data
*gs_prog_data
=
1792 (struct brw_gs_prog_data
*) prog_data
;
1794 const fs_builder abld
= bld
.annotate("emit control data bits");
1795 const fs_builder fwa_bld
= bld
.exec_all();
1797 /* We use a single UD register to accumulate control data bits (32 bits
1798 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1801 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1802 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1803 * use the Channel Mask phase to enable/disable which DWord within that
1804 * group to write. (Remember, different SIMD8 channels may have emitted
1805 * different numbers of vertices, so we may need per-slot offsets.)
1807 * Channel masking presents an annoying problem: we may have to replicate
1808 * the data up to 4 times:
1810 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1812 * To avoid penalizing shaders that emit a small number of vertices, we
1813 * can avoid these sometimes: if the size of the control data header is
1814 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1815 * land in the same 128-bit group, so we can skip per-slot offsets.
1817 * Similarly, if the control data header is <= 32 bits, there is only one
1818 * DWord, so we can skip channel masks.
1820 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1822 fs_reg channel_mask
, per_slot_offset
;
1824 if (gs_compile
->control_data_header_size_bits
> 32) {
1825 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1826 channel_mask
= vgrf(glsl_type::uint_type
);
1829 if (gs_compile
->control_data_header_size_bits
> 128) {
1830 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1831 per_slot_offset
= vgrf(glsl_type::uint_type
);
1834 /* Figure out which DWord we're trying to write to using the formula:
1836 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1838 * Since bits_per_vertex is a power of two, and is known at compile
1839 * time, this can be optimized to:
1841 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1843 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1844 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1845 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1846 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1847 unsigned log2_bits_per_vertex
=
1848 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1849 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1851 if (per_slot_offset
.file
!= BAD_FILE
) {
1852 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1853 * the appropriate OWord within the control data header.
1855 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1858 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1859 * write to the appropriate DWORD within the OWORD.
1861 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1862 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1863 channel_mask
= intexp2(fwa_bld
, channel
);
1864 /* Then the channel masks need to be in bits 23:16. */
1865 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1868 /* Store the control data bits in the message payload and send it. */
1870 if (channel_mask
.file
!= BAD_FILE
)
1871 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1872 if (per_slot_offset
.file
!= BAD_FILE
)
1875 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1876 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1878 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1879 if (per_slot_offset
.file
!= BAD_FILE
)
1880 sources
[i
++] = per_slot_offset
;
1881 if (channel_mask
.file
!= BAD_FILE
)
1882 sources
[i
++] = channel_mask
;
1884 sources
[i
++] = this->control_data_bits
;
1887 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1888 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1890 /* We need to increment Global Offset by 256-bits to make room for
1891 * Broadwell's extra "Vertex Count" payload at the beginning of the
1892 * URB entry. Since this is an OWord message, Global Offset is counted
1893 * in 128-bit units, so we must set it to 2.
1895 if (gs_prog_data
->static_vertex_count
== -1)
1900 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1903 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1905 /* Note: we are calling this *before* increasing vertex_count, so
1906 * this->vertex_count == vertex_count - 1 in the formula above.
1909 /* Stream mode uses 2 bits per vertex */
1910 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1912 /* Must be a valid stream */
1913 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1915 /* Control data bits are initialized to 0 so we don't have to set any
1916 * bits when sending vertices to stream 0.
1921 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1923 /* reg::sid = stream_id */
1924 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1925 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1927 /* reg:shift_count = 2 * (vertex_count - 1) */
1928 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1929 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1931 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1932 * attention to the lower 5 bits of its second source argument, so on this
1933 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1934 * stream_id << ((2 * (vertex_count - 1)) % 32).
1936 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1937 abld
.SHL(mask
, sid
, shift_count
);
1938 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1942 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1945 assert(stage
== MESA_SHADER_GEOMETRY
);
1947 struct brw_gs_prog_data
*gs_prog_data
=
1948 (struct brw_gs_prog_data
*) prog_data
;
1950 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1951 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1953 /* Haswell and later hardware ignores the "Render Stream Select" bits
1954 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1955 * and instead sends all primitives down the pipeline for rasterization.
1956 * If the SOL stage is enabled, "Render Stream Select" is honored and
1957 * primitives bound to non-zero streams are discarded after stream output.
1959 * Since the only purpose of primives sent to non-zero streams is to
1960 * be recorded by transform feedback, we can simply discard all geometry
1961 * bound to these streams when transform feedback is disabled.
1963 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1966 /* If we're outputting 32 control data bits or less, then we can wait
1967 * until the shader is over to output them all. Otherwise we need to
1968 * output them as we go. Now is the time to do it, since we're about to
1969 * output the vertex_count'th vertex, so it's guaranteed that the
1970 * control data bits associated with the (vertex_count - 1)th vertex are
1973 if (gs_compile
->control_data_header_size_bits
> 32) {
1974 const fs_builder abld
=
1975 bld
.annotate("emit vertex: emit control data bits");
1977 /* Only emit control data bits if we've finished accumulating a batch
1978 * of 32 bits. This is the case when:
1980 * (vertex_count * bits_per_vertex) % 32 == 0
1982 * (in other words, when the last 5 bits of vertex_count *
1983 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1984 * integer n (which is always the case, since bits_per_vertex is
1985 * always 1 or 2), this is equivalent to requiring that the last 5-n
1986 * bits of vertex_count are 0:
1988 * vertex_count & (2^(5-n) - 1) == 0
1990 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1993 * vertex_count & (32 / bits_per_vertex - 1) == 0
1995 * TODO: If vertex_count is an immediate, we could do some of this math
1996 * at compile time...
1999 abld
.AND(bld
.null_reg_d(), vertex_count
,
2000 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
2001 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2003 abld
.IF(BRW_PREDICATE_NORMAL
);
2004 /* If vertex_count is 0, then no control data bits have been
2005 * accumulated yet, so we can skip emitting them.
2007 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
2008 BRW_CONDITIONAL_NEQ
);
2009 abld
.IF(BRW_PREDICATE_NORMAL
);
2010 emit_gs_control_data_bits(vertex_count
);
2011 abld
.emit(BRW_OPCODE_ENDIF
);
2013 /* Reset control_data_bits to 0 so we can start accumulating a new
2016 * Note: in the case where vertex_count == 0, this neutralizes the
2017 * effect of any call to EndPrimitive() that the shader may have
2018 * made before outputting its first vertex.
2020 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
2021 inst
->force_writemask_all
= true;
2022 abld
.emit(BRW_OPCODE_ENDIF
);
2025 emit_urb_writes(vertex_count
);
2027 /* In stream mode we have to set control data bits for all vertices
2028 * unless we have disabled control data bits completely (which we do
2029 * do for GL_POINTS outputs that don't use streams).
2031 if (gs_compile
->control_data_header_size_bits
> 0 &&
2032 gs_prog_data
->control_data_format
==
2033 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
2034 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
2039 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
2040 const nir_src
&vertex_src
,
2041 unsigned base_offset
,
2042 const nir_src
&offset_src
,
2043 unsigned num_components
,
2044 unsigned first_component
)
2046 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
2048 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2049 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2050 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2052 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
2053 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
2054 * gl_PointSize is available as a GS input, however, so it must be that.
2056 const bool is_point_size
= (base_offset
== 0);
2058 /* TODO: figure out push input layout for invocations == 1 */
2059 if (gs_prog_data
->invocations
== 1 &&
2060 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2061 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2062 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2063 vertex_const
->u32
[0] * push_reg_count
;
2064 /* This input was pushed into registers. */
2065 if (is_point_size
) {
2066 /* gl_PointSize comes in .w */
2067 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2069 for (unsigned i
= 0; i
< num_components
; i
++) {
2070 bld
.MOV(offset(dst
, bld
, i
),
2071 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2077 /* Resort to the pull model. Ensure the VUE handles are provided. */
2078 gs_prog_data
->base
.include_vue_handles
= true;
2080 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2081 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2083 if (gs_prog_data
->invocations
== 1) {
2085 /* The vertex index is constant; just select the proper URB handle. */
2087 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2088 BRW_REGISTER_TYPE_UD
);
2090 /* The vertex index is non-constant. We need to use indirect
2091 * addressing to fetch the proper URB handle.
2093 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2094 * indicating that channel <n> should read the handle from
2095 * DWord <n>. We convert that to bytes by multiplying by 4.
2097 * Next, we convert the vertex index to bytes by multiplying
2098 * by 32 (shifting by 5), and add the two together. This is
2099 * the final indirect byte offset.
2101 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2102 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2103 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2104 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2106 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2107 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2108 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2109 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2110 /* Convert vertex_index to bytes (multiply by 32) */
2111 bld
.SHL(vertex_offset_bytes
,
2112 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2114 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2116 /* Use first_icp_handle as the base offset. There is one register
2117 * of URB handles per vertex, so inform the register allocator that
2118 * we might read up to nir->info.gs.vertices_in registers.
2120 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2121 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2122 fs_reg(icp_offset_bytes
),
2123 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2126 assert(gs_prog_data
->invocations
> 1);
2129 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2131 retype(brw_vec1_grf(first_icp_handle
+
2132 vertex_const
->i32
[0] / 8,
2133 vertex_const
->i32
[0] % 8),
2134 BRW_REGISTER_TYPE_UD
));
2136 /* The vertex index is non-constant. We need to use indirect
2137 * addressing to fetch the proper URB handle.
2140 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2142 /* Convert vertex_index to bytes (multiply by 4) */
2143 bld
.SHL(icp_offset_bytes
,
2144 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2147 /* Use first_icp_handle as the base offset. There is one DWord
2148 * of URB handles per vertex, so inform the register allocator that
2149 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2151 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2152 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2153 fs_reg(icp_offset_bytes
),
2154 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2161 fs_reg tmp_dst
= dst
;
2162 fs_reg indirect_offset
= get_nir_src(offset_src
);
2163 unsigned num_iterations
= 1;
2164 unsigned orig_num_components
= num_components
;
2166 if (type_sz(dst
.type
) == 8) {
2167 if (num_components
> 2) {
2171 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2173 first_component
= first_component
/ 2;
2176 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2178 /* Constant indexing - use global offset. */
2179 if (first_component
!= 0) {
2180 unsigned read_components
= num_components
+ first_component
;
2181 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2182 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2183 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2184 for (unsigned i
= 0; i
< num_components
; i
++) {
2185 bld
.MOV(offset(tmp_dst
, bld
, i
),
2186 offset(tmp
, bld
, i
+ first_component
));
2189 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2191 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2193 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2196 /* Indirect indexing - use per-slot offsets as well. */
2197 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2198 unsigned read_components
= num_components
+ first_component
;
2199 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2200 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2201 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2202 if (first_component
!= 0) {
2203 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2205 inst
->regs_written
= read_components
* type_sz(tmp_dst
.type
) / 4;
2206 for (unsigned i
= 0; i
< num_components
; i
++) {
2207 bld
.MOV(offset(tmp_dst
, bld
, i
),
2208 offset(tmp
, bld
, i
+ first_component
));
2211 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2213 inst
->regs_written
= num_components
* type_sz(tmp_dst
.type
) / 4;
2215 inst
->offset
= base_offset
;
2219 if (type_sz(dst
.type
) == 8) {
2220 shuffle_32bit_load_result_to_64bit_data(
2221 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2223 for (unsigned c
= 0; c
< num_components
; c
++)
2224 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2227 if (num_iterations
> 1) {
2228 num_components
= orig_num_components
- 2;
2232 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2233 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2234 indirect_offset
= new_indirect
;
2239 if (is_point_size
) {
2240 /* Read the whole VUE header (because of alignment) and read .w. */
2241 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2243 inst
->regs_written
= 4;
2244 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2249 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2251 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2252 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2255 /* The only constant offset we should find is 0. brw_nir.c's
2256 * add_const_offset_to_base() will fold other constant offsets
2257 * into instr->const_index[0].
2259 assert(const_value
->u32
[0] == 0);
2263 return get_nir_src(*offset_src
);
2267 do_untyped_vector_read(const fs_builder
&bld
,
2269 const fs_reg surf_index
,
2270 const fs_reg offset_reg
,
2271 unsigned num_components
)
2273 if (type_sz(dest
.type
) == 4) {
2274 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2277 BRW_PREDICATE_NONE
);
2278 read_result
.type
= dest
.type
;
2279 for (unsigned i
= 0; i
< num_components
; i
++)
2280 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2281 } else if (type_sz(dest
.type
) == 8) {
2282 /* Reading a dvec, so we need to:
2284 * 1. Multiply num_components by 2, to account for the fact that we
2285 * need to read 64-bit components.
2286 * 2. Shuffle the result of the load to form valid 64-bit elements
2287 * 3. Emit a second load (for components z/w) if needed.
2289 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2290 bld
.MOV(read_offset
, offset_reg
);
2292 int iters
= num_components
<= 2 ? 1 : 2;
2294 /* Load the dvec, the first iteration loads components x/y, the second
2295 * iteration, if needed, loads components z/w
2297 for (int it
= 0; it
< iters
; it
++) {
2298 /* Compute number of components to read in this iteration */
2299 int iter_components
= MIN2(2, num_components
);
2300 num_components
-= iter_components
;
2302 /* Read. Since this message reads 32-bit components, we need to
2303 * read twice as many components.
2305 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2307 iter_components
* 2,
2308 BRW_PREDICATE_NONE
);
2310 /* Shuffle the 32-bit load result into valid 64-bit data */
2311 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2312 shuffle_32bit_load_result_to_64bit_data(
2313 bld
, packed_result
, read_result
, iter_components
);
2315 /* Move each component to its destination */
2316 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2317 for (int c
= 0; c
< iter_components
; c
++) {
2318 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2319 offset(packed_result
, bld
, c
));
2322 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2325 unreachable("Unsupported type");
2330 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2331 nir_intrinsic_instr
*instr
)
2333 assert(stage
== MESA_SHADER_VERTEX
);
2336 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2337 dest
= get_nir_dest(instr
->dest
);
2339 switch (instr
->intrinsic
) {
2340 case nir_intrinsic_load_vertex_id
:
2341 unreachable("should be lowered by lower_vertex_id()");
2343 case nir_intrinsic_load_vertex_id_zero_base
:
2344 case nir_intrinsic_load_base_vertex
:
2345 case nir_intrinsic_load_instance_id
:
2346 case nir_intrinsic_load_base_instance
:
2347 case nir_intrinsic_load_draw_id
: {
2348 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2349 fs_reg val
= nir_system_values
[sv
];
2350 assert(val
.file
!= BAD_FILE
);
2351 dest
.type
= val
.type
;
2356 case nir_intrinsic_load_input
: {
2357 fs_reg src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2358 unsigned first_component
= nir_intrinsic_component(instr
);
2359 unsigned num_components
= instr
->num_components
;
2360 enum brw_reg_type type
= dest
.type
;
2362 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2363 assert(const_offset
&& "Indirect input loads not allowed");
2364 src
= offset(src
, bld
, const_offset
->u32
[0]);
2366 for (unsigned j
= 0; j
< num_components
; j
++) {
2367 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2370 if (type
== BRW_REGISTER_TYPE_DF
) {
2371 /* Once the double vector is read, set again its original register
2372 * type to continue with normal execution.
2374 src
= retype(src
, type
);
2375 dest
= retype(dest
, type
);
2378 if (type_sz(src
.type
) == 8) {
2379 shuffle_32bit_load_result_to_64bit_data(bld
,
2381 retype(dest
, BRW_REGISTER_TYPE_F
),
2382 instr
->num_components
);
2388 nir_emit_intrinsic(bld
, instr
);
2394 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2395 nir_intrinsic_instr
*instr
)
2397 assert(stage
== MESA_SHADER_TESS_CTRL
);
2398 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2399 struct brw_tcs_prog_data
*tcs_prog_data
=
2400 (struct brw_tcs_prog_data
*) prog_data
;
2403 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2404 dst
= get_nir_dest(instr
->dest
);
2406 switch (instr
->intrinsic
) {
2407 case nir_intrinsic_load_primitive_id
:
2408 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2410 case nir_intrinsic_load_invocation_id
:
2411 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2413 case nir_intrinsic_load_patch_vertices_in
:
2414 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2415 brw_imm_d(tcs_key
->input_vertices
));
2418 case nir_intrinsic_barrier
: {
2419 if (tcs_prog_data
->instances
== 1)
2422 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2423 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2425 const fs_builder fwa_bld
= bld
.exec_all();
2427 /* Zero the message header */
2428 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2430 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2431 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2432 brw_imm_ud(INTEL_MASK(16, 13)));
2434 /* Shift it up to bits 27:24. */
2435 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2437 /* Set the Barrier Count and the enable bit */
2438 fwa_bld
.OR(m0_2
, m0_2
,
2439 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2441 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2445 case nir_intrinsic_load_input
:
2446 unreachable("nir_lower_io should never give us these.");
2449 case nir_intrinsic_load_per_vertex_input
: {
2450 fs_reg indirect_offset
= get_indirect_offset(instr
);
2451 unsigned imm_offset
= instr
->const_index
[0];
2453 const nir_src
&vertex_src
= instr
->src
[0];
2454 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2461 /* Emit a MOV to resolve <0,1,0> regioning. */
2462 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2464 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2465 vertex_const
->i32
[0] & 7),
2466 BRW_REGISTER_TYPE_UD
));
2467 } else if (tcs_prog_data
->instances
== 1 &&
2468 vertex_src
.is_ssa
&&
2469 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2470 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2471 /* For the common case of only 1 instance, an array index of
2472 * gl_InvocationID means reading g1. Skip all the indirect work.
2474 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2476 /* The vertex index is non-constant. We need to use indirect
2477 * addressing to fetch the proper URB handle.
2479 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2481 /* Each ICP handle is a single DWord (4 bytes) */
2482 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2483 bld
.SHL(vertex_offset_bytes
,
2484 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2487 /* Start at g1. We might read up to 4 registers. */
2488 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2489 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2490 brw_imm_ud(4 * REG_SIZE
));
2493 /* We can only read two double components with each URB read, so
2494 * we send two read messages in that case, each one loading up to
2495 * two double components.
2497 unsigned num_iterations
= 1;
2498 unsigned num_components
= instr
->num_components
;
2499 unsigned first_component
= nir_intrinsic_component(instr
);
2500 fs_reg orig_dst
= dst
;
2501 if (type_sz(dst
.type
) == 8) {
2502 first_component
= first_component
/ 2;
2503 if (instr
->num_components
> 2) {
2508 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2512 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2513 if (indirect_offset
.file
== BAD_FILE
) {
2514 /* Constant indexing - use global offset. */
2515 if (first_component
!= 0) {
2516 unsigned read_components
= num_components
+ first_component
;
2517 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2518 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2519 for (unsigned i
= 0; i
< num_components
; i
++) {
2520 bld
.MOV(offset(dst
, bld
, i
),
2521 offset(tmp
, bld
, i
+ first_component
));
2524 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2526 inst
->offset
= imm_offset
;
2529 /* Indirect indexing - use per-slot offsets as well. */
2530 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2531 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2532 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2533 if (first_component
!= 0) {
2534 unsigned read_components
= num_components
+ first_component
;
2535 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2536 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2538 for (unsigned i
= 0; i
< num_components
; i
++) {
2539 bld
.MOV(offset(dst
, bld
, i
),
2540 offset(tmp
, bld
, i
+ first_component
));
2543 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2546 inst
->offset
= imm_offset
;
2549 inst
->regs_written
=
2550 ((num_components
+ first_component
) * type_sz(dst
.type
) / 4);
2552 /* If we are reading 64-bit data using 32-bit read messages we need
2553 * build proper 64-bit data elements by shuffling the low and high
2554 * 32-bit components around like we do for other things like UBOs
2557 if (type_sz(dst
.type
) == 8) {
2558 shuffle_32bit_load_result_to_64bit_data(
2559 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2561 for (unsigned c
= 0; c
< num_components
; c
++) {
2562 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2563 offset(dst
, bld
, c
));
2567 /* Copy the temporary to the destination to deal with writemasking.
2569 * Also attempt to deal with gl_PointSize being in the .w component.
2571 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2572 assert(type_sz(dst
.type
) < 8);
2573 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2574 inst
->regs_written
= 4;
2575 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2578 /* If we are loading double data and we need a second read message
2579 * adjust the write offset
2581 if (num_iterations
> 1) {
2582 num_components
= instr
->num_components
- 2;
2589 case nir_intrinsic_load_output
:
2590 case nir_intrinsic_load_per_vertex_output
: {
2591 fs_reg indirect_offset
= get_indirect_offset(instr
);
2592 unsigned imm_offset
= instr
->const_index
[0];
2593 unsigned first_component
= nir_intrinsic_component(instr
);
2596 if (indirect_offset
.file
== BAD_FILE
) {
2597 /* Replicate the patch handle to all enabled channels */
2598 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2599 bld
.MOV(patch_handle
,
2600 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2602 if (imm_offset
== 0) {
2603 /* This is a read of gl_TessLevelInner[], which lives in the
2604 * Patch URB header. The layout depends on the domain.
2606 dst
.type
= BRW_REGISTER_TYPE_F
;
2607 switch (tcs_key
->tes_primitive_mode
) {
2609 /* DWords 3-2 (reversed) */
2610 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2612 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2615 inst
->regs_written
= 4;
2617 /* dst.xy = tmp.wz */
2618 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2619 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2623 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2624 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2627 inst
->regs_written
= 1;
2630 /* All channels are undefined. */
2633 unreachable("Bogus tessellation domain");
2635 } else if (imm_offset
== 1) {
2636 /* This is a read of gl_TessLevelOuter[], which lives in the
2637 * Patch URB header. The layout depends on the domain.
2639 dst
.type
= BRW_REGISTER_TYPE_F
;
2641 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2642 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2645 inst
->regs_written
= 4;
2647 /* Reswizzle: WZYX */
2649 offset(tmp
, bld
, 3),
2650 offset(tmp
, bld
, 2),
2651 offset(tmp
, bld
, 1),
2652 offset(tmp
, bld
, 0),
2655 unsigned num_components
;
2656 switch (tcs_key
->tes_primitive_mode
) {
2664 /* Isolines are not reversed; swizzle .zw -> .xy */
2665 srcs
[0] = offset(tmp
, bld
, 2);
2666 srcs
[1] = offset(tmp
, bld
, 3);
2670 unreachable("Bogus tessellation domain");
2672 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2674 if (first_component
!= 0) {
2675 unsigned read_components
=
2676 instr
->num_components
+ first_component
;
2677 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2678 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2680 inst
->regs_written
= read_components
;
2681 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2682 bld
.MOV(offset(dst
, bld
, i
),
2683 offset(tmp
, bld
, i
+ first_component
));
2686 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2688 inst
->regs_written
= instr
->num_components
;
2690 inst
->offset
= imm_offset
;
2694 /* Indirect indexing - use per-slot offsets as well. */
2695 const fs_reg srcs
[] = {
2696 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2699 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2700 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2701 if (first_component
!= 0) {
2702 unsigned read_components
=
2703 instr
->num_components
+ first_component
;
2704 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2705 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2707 inst
->regs_written
= read_components
;
2708 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2709 bld
.MOV(offset(dst
, bld
, i
),
2710 offset(tmp
, bld
, i
+ first_component
));
2713 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2715 inst
->regs_written
= instr
->num_components
;
2717 inst
->offset
= imm_offset
;
2723 case nir_intrinsic_store_output
:
2724 case nir_intrinsic_store_per_vertex_output
: {
2725 fs_reg value
= get_nir_src(instr
->src
[0]);
2726 bool is_64bit
= (instr
->src
[0].is_ssa
?
2727 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2728 fs_reg indirect_offset
= get_indirect_offset(instr
);
2729 unsigned imm_offset
= instr
->const_index
[0];
2730 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2731 unsigned mask
= instr
->const_index
[1];
2732 unsigned header_regs
= 0;
2734 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2736 if (indirect_offset
.file
!= BAD_FILE
) {
2737 srcs
[header_regs
++] = indirect_offset
;
2738 } else if (!is_passthrough_shader
) {
2739 if (imm_offset
== 0) {
2740 value
.type
= BRW_REGISTER_TYPE_F
;
2742 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2744 /* This is a write to gl_TessLevelInner[], which lives in the
2745 * Patch URB header. The layout depends on the domain.
2747 switch (tcs_key
->tes_primitive_mode
) {
2749 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2750 * We use an XXYX swizzle to reverse put .xy in the .wz
2751 * channels, and use a .zw writemask.
2753 mask
= writemask_for_backwards_vector(mask
);
2754 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2757 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2758 * writemask to X and bump the URB offset by 1.
2763 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2766 unreachable("Bogus tessellation domain");
2768 } else if (imm_offset
== 1) {
2769 /* This is a write to gl_TessLevelOuter[] which lives in the
2770 * Patch URB Header at DWords 4-7. However, it's reversed, so
2771 * instead of .xyzw we have .wzyx.
2773 value
.type
= BRW_REGISTER_TYPE_F
;
2775 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2777 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2778 /* Isolines .xy should be stored in .zw, in order. */
2779 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2782 /* Other domains are reversed; store .wzyx instead of .xyzw */
2783 swiz
= BRW_SWIZZLE_WZYX
;
2784 mask
= writemask_for_backwards_vector(mask
);
2792 unsigned num_components
= _mesa_fls(mask
);
2795 /* We can only pack two 64-bit components in a single message, so send
2796 * 2 messages if we have more components
2798 unsigned num_iterations
= 1;
2799 unsigned iter_components
= num_components
;
2800 unsigned first_component
= nir_intrinsic_component(instr
);
2802 first_component
= first_component
/ 2;
2803 if (instr
->num_components
> 2) {
2805 iter_components
= 2;
2809 /* 64-bit data needs to me shuffled before we can write it to the URB.
2810 * We will use this temporary to shuffle the components in each
2814 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2816 mask
= mask
<< first_component
;
2818 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2819 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2820 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2821 opcode
= indirect_offset
.file
!= BAD_FILE
?
2822 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2823 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2824 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2825 /* Expand the 64-bit mask to 32-bit channels. We only handle
2826 * two channels in each iteration, so we only care about X/Y.
2828 unsigned mask32
= 0;
2829 if (mask
& WRITEMASK_X
)
2830 mask32
|= WRITEMASK_XY
;
2831 if (mask
& WRITEMASK_Y
)
2832 mask32
|= WRITEMASK_ZW
;
2834 /* If the mask does not include any of the channels X or Y there
2835 * is nothing to do in this iteration. Move on to the next couple
2836 * of 64-bit channels.
2844 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2845 opcode
= indirect_offset
.file
!= BAD_FILE
?
2846 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2847 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2849 opcode
= indirect_offset
.file
!= BAD_FILE
?
2850 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2851 SHADER_OPCODE_URB_WRITE_SIMD8
;
2854 for (unsigned i
= 0; i
< iter_components
; i
++) {
2855 if (!(mask
& (1 << (i
+ first_component
))))
2859 srcs
[header_regs
+ i
+ first_component
] =
2860 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2862 /* We need to shuffle the 64-bit data to match the layout
2863 * expected by our 32-bit URB write messages. We use a temporary
2866 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2867 shuffle_64bit_data_for_32bit_write(bld
,
2868 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2869 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2872 /* Now copy the data to the destination */
2873 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2874 unsigned idx
= 2 * i
;
2875 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2876 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2877 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2878 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2879 offset(dest
, bld
, 1);
2884 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2885 (is_64bit
? 2 * first_component
: first_component
);
2887 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2888 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2890 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2891 inst
->offset
= imm_offset
;
2894 /* If this is a 64-bit attribute, select the next two 64-bit channels
2895 * to be handled in the next iteration.
2906 nir_emit_intrinsic(bld
, instr
);
2912 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2913 nir_intrinsic_instr
*instr
)
2915 assert(stage
== MESA_SHADER_TESS_EVAL
);
2916 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2919 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2920 dest
= get_nir_dest(instr
->dest
);
2922 switch (instr
->intrinsic
) {
2923 case nir_intrinsic_load_primitive_id
:
2924 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2926 case nir_intrinsic_load_tess_coord
:
2927 /* gl_TessCoord is part of the payload in g1-3 */
2928 for (unsigned i
= 0; i
< 3; i
++) {
2929 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2933 case nir_intrinsic_load_tess_level_outer
:
2934 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2935 * appears as a push-model input. So, we can simply use the ATTR file
2936 * rather than issuing URB read messages. The data is stored in the
2937 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2940 switch (tes_prog_data
->domain
) {
2941 case BRW_TESS_DOMAIN_QUAD
:
2942 for (unsigned i
= 0; i
< 4; i
++)
2943 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2945 case BRW_TESS_DOMAIN_TRI
:
2946 for (unsigned i
= 0; i
< 3; i
++)
2947 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2949 case BRW_TESS_DOMAIN_ISOLINE
:
2950 for (unsigned i
= 0; i
< 2; i
++)
2951 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 6 + i
));
2956 case nir_intrinsic_load_tess_level_inner
:
2957 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2958 * appears as a push-model input. So, we can simply use the ATTR file
2959 * rather than issuing URB read messages.
2961 switch (tes_prog_data
->domain
) {
2962 case BRW_TESS_DOMAIN_QUAD
:
2963 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2964 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2966 case BRW_TESS_DOMAIN_TRI
:
2967 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2969 case BRW_TESS_DOMAIN_ISOLINE
:
2970 /* ignore - value is undefined */
2975 case nir_intrinsic_load_input
:
2976 case nir_intrinsic_load_per_vertex_input
: {
2977 fs_reg indirect_offset
= get_indirect_offset(instr
);
2978 unsigned imm_offset
= instr
->const_index
[0];
2979 unsigned first_component
= nir_intrinsic_component(instr
);
2981 if (type_sz(dest
.type
) == 8) {
2982 first_component
= first_component
/ 2;
2986 if (indirect_offset
.file
== BAD_FILE
) {
2987 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2988 * which is 16 registers (since each holds 2 vec4 slots).
2990 const unsigned max_push_slots
= 32;
2991 if (imm_offset
< max_push_slots
) {
2992 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2993 for (int i
= 0; i
< instr
->num_components
; i
++) {
2994 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2995 i
+ first_component
;
2996 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2998 tes_prog_data
->base
.urb_read_length
=
2999 MAX2(tes_prog_data
->base
.urb_read_length
,
3000 DIV_ROUND_UP(imm_offset
+ 1, 2));
3002 /* Replicate the patch handle to all enabled channels */
3003 const fs_reg srcs
[] = {
3004 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
3006 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
3007 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
3009 if (first_component
!= 0) {
3010 unsigned read_components
=
3011 instr
->num_components
+ first_component
;
3012 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3013 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
3015 inst
->regs_written
= read_components
;
3016 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3017 bld
.MOV(offset(dest
, bld
, i
),
3018 offset(tmp
, bld
, i
+ first_component
));
3021 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
3023 inst
->regs_written
= instr
->num_components
;
3026 inst
->offset
= imm_offset
;
3029 /* Indirect indexing - use per-slot offsets as well. */
3031 /* We can only read two double components with each URB read, so
3032 * we send two read messages in that case, each one loading up to
3033 * two double components.
3035 unsigned num_iterations
= 1;
3036 unsigned num_components
= instr
->num_components
;
3037 fs_reg orig_dest
= dest
;
3038 if (type_sz(dest
.type
) == 8) {
3039 if (instr
->num_components
> 2) {
3043 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3047 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3048 const fs_reg srcs
[] = {
3049 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3052 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3053 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3055 if (first_component
!= 0) {
3056 unsigned read_components
=
3057 num_components
+ first_component
;
3058 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3059 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3061 for (unsigned i
= 0; i
< num_components
; i
++) {
3062 bld
.MOV(offset(dest
, bld
, i
),
3063 offset(tmp
, bld
, i
+ first_component
));
3066 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3070 inst
->offset
= imm_offset
;
3071 inst
->regs_written
=
3072 ((num_components
+ first_component
) * type_sz(dest
.type
) / 4);
3074 /* If we are reading 64-bit data using 32-bit read messages we need
3075 * build proper 64-bit data elements by shuffling the low and high
3076 * 32-bit components around like we do for other things like UBOs
3079 if (type_sz(dest
.type
) == 8) {
3080 shuffle_32bit_load_result_to_64bit_data(
3081 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
3083 for (unsigned c
= 0; c
< num_components
; c
++) {
3084 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
3085 offset(dest
, bld
, c
));
3089 /* If we are loading double data and we need a second read message
3092 if (num_iterations
> 1) {
3093 num_components
= instr
->num_components
- 2;
3101 nir_emit_intrinsic(bld
, instr
);
3107 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3108 nir_intrinsic_instr
*instr
)
3110 assert(stage
== MESA_SHADER_GEOMETRY
);
3111 fs_reg indirect_offset
;
3114 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3115 dest
= get_nir_dest(instr
->dest
);
3117 switch (instr
->intrinsic
) {
3118 case nir_intrinsic_load_primitive_id
:
3119 assert(stage
== MESA_SHADER_GEOMETRY
);
3120 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
3121 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3122 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3125 case nir_intrinsic_load_input
:
3126 unreachable("load_input intrinsics are invalid for the GS stage");
3128 case nir_intrinsic_load_per_vertex_input
:
3129 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3130 instr
->src
[1], instr
->num_components
,
3131 nir_intrinsic_component(instr
));
3134 case nir_intrinsic_emit_vertex_with_counter
:
3135 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3138 case nir_intrinsic_end_primitive_with_counter
:
3139 emit_gs_end_primitive(instr
->src
[0]);
3142 case nir_intrinsic_set_vertex_count
:
3143 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3146 case nir_intrinsic_load_invocation_id
: {
3147 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3148 assert(val
.file
!= BAD_FILE
);
3149 dest
.type
= val
.type
;
3155 nir_emit_intrinsic(bld
, instr
);
3161 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3162 nir_intrinsic_instr
*instr
)
3164 assert(stage
== MESA_SHADER_FRAGMENT
);
3167 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3168 dest
= get_nir_dest(instr
->dest
);
3170 switch (instr
->intrinsic
) {
3171 case nir_intrinsic_load_front_face
:
3172 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3173 *emit_frontfacing_interpolation());
3176 case nir_intrinsic_load_sample_pos
: {
3177 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3178 assert(sample_pos
.file
!= BAD_FILE
);
3179 dest
.type
= sample_pos
.type
;
3180 bld
.MOV(dest
, sample_pos
);
3181 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3185 case nir_intrinsic_load_helper_invocation
:
3186 case nir_intrinsic_load_sample_mask_in
:
3187 case nir_intrinsic_load_sample_id
: {
3188 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3189 fs_reg val
= nir_system_values
[sv
];
3190 assert(val
.file
!= BAD_FILE
);
3191 dest
.type
= val
.type
;
3196 case nir_intrinsic_discard
:
3197 case nir_intrinsic_discard_if
: {
3198 /* We track our discarded pixels in f0.1. By predicating on it, we can
3199 * update just the flag bits that aren't yet discarded. If there's no
3200 * condition, we emit a CMP of g0 != g0, so all currently executing
3201 * channels will get turned off.
3204 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3205 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3206 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3208 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3209 BRW_REGISTER_TYPE_UW
));
3210 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3212 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3213 cmp
->flag_subreg
= 1;
3215 if (devinfo
->gen
>= 6) {
3216 emit_discard_jump();
3221 case nir_intrinsic_load_input
: {
3222 /* load_input is only used for flat inputs */
3223 unsigned base
= nir_intrinsic_base(instr
);
3224 unsigned component
= nir_intrinsic_component(instr
);
3225 unsigned num_components
= instr
->num_components
;
3226 enum brw_reg_type type
= dest
.type
;
3228 /* Special case fields in the VUE header */
3229 if (base
== VARYING_SLOT_LAYER
)
3231 else if (base
== VARYING_SLOT_VIEWPORT
)
3234 if (nir_dest_bit_size(instr
->dest
) == 64) {
3235 /* const_index is in 32-bit type size units that could not be aligned
3236 * with DF. We need to read the double vector as if it was a float
3237 * vector of twice the number of components to fetch the right data.
3239 type
= BRW_REGISTER_TYPE_F
;
3240 num_components
*= 2;
3243 for (unsigned int i
= 0; i
< num_components
; i
++) {
3244 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3245 interp
= suboffset(interp
, 3);
3246 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3247 retype(fs_reg(interp
), type
));
3250 if (nir_dest_bit_size(instr
->dest
) == 64) {
3251 shuffle_32bit_load_result_to_64bit_data(bld
,
3254 instr
->num_components
);
3259 case nir_intrinsic_load_barycentric_pixel
:
3260 case nir_intrinsic_load_barycentric_centroid
:
3261 case nir_intrinsic_load_barycentric_sample
:
3262 /* Do nothing - load_interpolated_input handling will handle it later. */
3265 case nir_intrinsic_load_barycentric_at_sample
: {
3266 const glsl_interp_mode interpolation
=
3267 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3269 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3272 unsigned msg_data
= const_sample
->i32
[0] << 4;
3274 emit_pixel_interpolater_send(bld
,
3275 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3278 brw_imm_ud(msg_data
),
3281 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3282 BRW_REGISTER_TYPE_UD
);
3284 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3285 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3286 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3287 bld
.exec_all().group(1, 0)
3288 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3289 emit_pixel_interpolater_send(bld
,
3290 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3296 /* Make a loop that sends a message to the pixel interpolater
3297 * for the sample number in each live channel. If there are
3298 * multiple channels with the same sample number then these
3299 * will be handled simultaneously with a single interation of
3302 bld
.emit(BRW_OPCODE_DO
);
3304 /* Get the next live sample number into sample_id_reg */
3305 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3307 /* Set the flag register so that we can perform the send
3308 * message on all channels that have the same sample number
3310 bld
.CMP(bld
.null_reg_ud(),
3311 sample_src
, sample_id
,
3312 BRW_CONDITIONAL_EQ
);
3313 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3314 bld
.exec_all().group(1, 0)
3315 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3317 emit_pixel_interpolater_send(bld
,
3318 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3323 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3325 /* Continue the loop if there are any live channels left */
3326 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3328 bld
.emit(BRW_OPCODE_WHILE
));
3334 case nir_intrinsic_load_barycentric_at_offset
: {
3335 const glsl_interp_mode interpolation
=
3336 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3338 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3341 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3342 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3344 emit_pixel_interpolater_send(bld
,
3345 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3348 brw_imm_ud(off_x
| (off_y
<< 4)),
3351 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3352 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3353 BRW_REGISTER_TYPE_F
);
3354 for (int i
= 0; i
< 2; i
++) {
3355 fs_reg temp
= vgrf(glsl_type::float_type
);
3356 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3357 fs_reg itemp
= vgrf(glsl_type::int_type
);
3359 bld
.MOV(itemp
, temp
);
3361 /* Clamp the upper end of the range to +7/16.
3362 * ARB_gpu_shader5 requires that we support a maximum offset
3363 * of +0.5, which isn't representable in a S0.4 value -- if
3364 * we didn't clamp it, we'd end up with -8/16, which is the
3365 * opposite of what the shader author wanted.
3367 * This is legal due to ARB_gpu_shader5's quantization
3370 * "Not all values of <offset> may be supported; x and y
3371 * offsets may be rounded to fixed-point values with the
3372 * number of fraction bits given by the
3373 * implementation-dependent constant
3374 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3376 set_condmod(BRW_CONDITIONAL_L
,
3377 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3380 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3381 emit_pixel_interpolater_send(bld
,
3391 case nir_intrinsic_load_interpolated_input
: {
3392 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3393 emit_fragcoord_interpolation(dest
);
3397 assert(instr
->src
[0].ssa
&&
3398 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3399 nir_intrinsic_instr
*bary_intrinsic
=
3400 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3401 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3402 enum glsl_interp_mode interp_mode
=
3403 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3406 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3407 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3408 /* Use the result of the PI message */
3409 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3411 /* Use the delta_xy values computed from the payload */
3412 enum brw_barycentric_mode bary
=
3413 brw_barycentric_mode(interp_mode
, bary_intrin
);
3415 dst_xy
= this->delta_xy
[bary
];
3418 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3420 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3421 nir_intrinsic_component(instr
) + i
));
3422 interp
.type
= BRW_REGISTER_TYPE_F
;
3423 dest
.type
= BRW_REGISTER_TYPE_F
;
3425 if (devinfo
->needs_unlit_centroid_workaround
&&
3426 bary_intrin
== nir_intrinsic_load_barycentric_centroid
) {
3428 /* Get the pixel/sample mask into f0 so that we know which
3429 * pixels are lit. Then, for each channel that is unlit,
3430 * replace the centroid data with non-centroid data.
3432 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
3434 fs_reg dest_i
= offset(dest
, bld
, i
);
3435 fs_reg dst_xy_pixel
=
3436 delta_xy
[brw_barycentric_mode(interp_mode
,
3437 nir_intrinsic_load_barycentric_pixel
)];
3440 inst
= bld
.emit(FS_OPCODE_LINTERP
, dest_i
, dst_xy_pixel
, interp
);
3441 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3442 inst
->predicate_inverse
= true;
3443 inst
->no_dd_clear
= true;
3445 inst
= bld
.emit(FS_OPCODE_LINTERP
, dest_i
, dst_xy
, interp
);
3446 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3447 inst
->predicate_inverse
= false;
3448 inst
->no_dd_check
= true;
3449 } else if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3450 fs_reg tmp
= vgrf(glsl_type::float_type
);
3451 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3452 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3454 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3461 nir_emit_intrinsic(bld
, instr
);
3467 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3468 nir_intrinsic_instr
*instr
)
3470 assert(stage
== MESA_SHADER_COMPUTE
);
3471 struct brw_cs_prog_data
*cs_prog_data
=
3472 (struct brw_cs_prog_data
*) prog_data
;
3475 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3476 dest
= get_nir_dest(instr
->dest
);
3478 switch (instr
->intrinsic
) {
3479 case nir_intrinsic_barrier
:
3481 cs_prog_data
->uses_barrier
= true;
3484 case nir_intrinsic_load_local_invocation_id
:
3485 case nir_intrinsic_load_work_group_id
: {
3486 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3487 fs_reg val
= nir_system_values
[sv
];
3488 assert(val
.file
!= BAD_FILE
);
3489 dest
.type
= val
.type
;
3490 for (unsigned i
= 0; i
< 3; i
++)
3491 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3495 case nir_intrinsic_load_num_work_groups
: {
3496 const unsigned surface
=
3497 cs_prog_data
->binding_table
.work_groups_start
;
3499 cs_prog_data
->uses_num_work_groups
= true;
3501 fs_reg surf_index
= brw_imm_ud(surface
);
3502 brw_mark_surface_used(prog_data
, surface
);
3504 /* Read the 3 GLuint components of gl_NumWorkGroups */
3505 for (unsigned i
= 0; i
< 3; i
++) {
3506 fs_reg read_result
=
3507 emit_untyped_read(bld
, surf_index
,
3509 1 /* dims */, 1 /* size */,
3510 BRW_PREDICATE_NONE
);
3511 read_result
.type
= dest
.type
;
3512 bld
.MOV(dest
, read_result
);
3513 dest
= offset(dest
, bld
, 1);
3518 case nir_intrinsic_shared_atomic_add
:
3519 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3521 case nir_intrinsic_shared_atomic_imin
:
3522 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3524 case nir_intrinsic_shared_atomic_umin
:
3525 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3527 case nir_intrinsic_shared_atomic_imax
:
3528 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3530 case nir_intrinsic_shared_atomic_umax
:
3531 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3533 case nir_intrinsic_shared_atomic_and
:
3534 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3536 case nir_intrinsic_shared_atomic_or
:
3537 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3539 case nir_intrinsic_shared_atomic_xor
:
3540 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3542 case nir_intrinsic_shared_atomic_exchange
:
3543 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3545 case nir_intrinsic_shared_atomic_comp_swap
:
3546 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3549 case nir_intrinsic_load_shared
: {
3550 assert(devinfo
->gen
>= 7);
3552 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3554 /* Get the offset to read from */
3556 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3558 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3560 offset_reg
= vgrf(glsl_type::uint_type
);
3562 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3563 brw_imm_ud(instr
->const_index
[0]));
3566 /* Read the vector */
3567 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3568 instr
->num_components
);
3572 case nir_intrinsic_store_shared
: {
3573 assert(devinfo
->gen
>= 7);
3576 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3579 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3582 unsigned writemask
= instr
->const_index
[1];
3584 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3585 * since the untyped writes below operate in units of 32-bits, which
3586 * means that we need to write twice as many components each time.
3587 * Also, we have to suffle 64-bit data to be in the appropriate layout
3588 * expected by our 32-bit write messages.
3590 unsigned type_size
= 4;
3591 unsigned bit_size
= instr
->src
[0].is_ssa
?
3592 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3593 if (bit_size
== 64) {
3596 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3597 shuffle_64bit_data_for_32bit_write(
3599 retype(tmp
, BRW_REGISTER_TYPE_F
),
3600 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3601 instr
->num_components
);
3605 unsigned type_slots
= type_size
/ 4;
3607 /* Combine groups of consecutive enabled channels in one write
3608 * message. We use ffs to find the first enabled channel and then ffs on
3609 * the bit-inverse, down-shifted writemask to determine the length of
3610 * the block of enabled bits.
3613 unsigned first_component
= ffs(writemask
) - 1;
3614 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3616 /* We can't write more than 2 64-bit components at once. Limit the
3617 * length of the write to what we can do and let the next iteration
3621 length
= MIN2(2, length
);
3624 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3626 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3627 type_size
* first_component
);
3629 offset_reg
= vgrf(glsl_type::uint_type
);
3631 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3632 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3635 emit_untyped_write(bld
, surf_index
, offset_reg
,
3636 offset(val_reg
, bld
, first_component
* type_slots
),
3637 1 /* dims */, length
* type_slots
,
3638 BRW_PREDICATE_NONE
);
3640 /* Clear the bits in the writemask that we just wrote, then try
3641 * again to see if more channels are left.
3643 writemask
&= (15 << (first_component
+ length
));
3650 nir_emit_intrinsic(bld
, instr
);
3656 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3659 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3660 dest
= get_nir_dest(instr
->dest
);
3662 switch (instr
->intrinsic
) {
3663 case nir_intrinsic_atomic_counter_inc
:
3664 case nir_intrinsic_atomic_counter_dec
:
3665 case nir_intrinsic_atomic_counter_read
: {
3666 if (stage
== MESA_SHADER_FRAGMENT
&&
3667 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3668 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3670 /* Get the arguments of the atomic intrinsic. */
3671 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3672 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3673 instr
->const_index
[0]);
3676 /* Emit a surface read or atomic op. */
3677 switch (instr
->intrinsic
) {
3678 case nir_intrinsic_atomic_counter_read
:
3679 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3682 case nir_intrinsic_atomic_counter_inc
:
3683 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3684 fs_reg(), 1, 1, BRW_AOP_INC
);
3687 case nir_intrinsic_atomic_counter_dec
:
3688 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3689 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3693 unreachable("Unreachable");
3696 /* Assign the result. */
3697 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3699 /* Mark the surface as used. */
3700 brw_mark_surface_used(stage_prog_data
, surface
);
3704 case nir_intrinsic_image_load
:
3705 case nir_intrinsic_image_store
:
3706 case nir_intrinsic_image_atomic_add
:
3707 case nir_intrinsic_image_atomic_min
:
3708 case nir_intrinsic_image_atomic_max
:
3709 case nir_intrinsic_image_atomic_and
:
3710 case nir_intrinsic_image_atomic_or
:
3711 case nir_intrinsic_image_atomic_xor
:
3712 case nir_intrinsic_image_atomic_exchange
:
3713 case nir_intrinsic_image_atomic_comp_swap
: {
3714 using namespace image_access
;
3716 if (stage
== MESA_SHADER_FRAGMENT
&&
3717 instr
->intrinsic
!= nir_intrinsic_image_load
)
3718 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
3720 /* Get the referenced image variable and type. */
3721 const nir_variable
*var
= instr
->variables
[0]->var
;
3722 const glsl_type
*type
= var
->type
->without_array();
3723 const brw_reg_type base_type
= get_image_base_type(type
);
3725 /* Get some metadata from the image intrinsic. */
3726 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3727 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3728 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3729 const unsigned format
= var
->data
.image
.format
;
3731 /* Get the arguments of the image intrinsic. */
3732 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3733 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3734 BRW_REGISTER_TYPE_UD
);
3735 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3736 retype(get_nir_src(instr
->src
[2]), base_type
) :
3738 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3739 retype(get_nir_src(instr
->src
[3]), base_type
) :
3743 /* Emit an image load, store or atomic op. */
3744 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3745 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3747 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3748 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3749 var
->data
.image
.write_only
? GL_NONE
: format
);
3752 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3753 surf_dims
, arr_dims
, info
->dest_components
,
3754 get_image_atomic_op(instr
->intrinsic
, type
));
3756 /* Assign the result. */
3757 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3758 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3759 offset(tmp
, bld
, c
));
3763 case nir_intrinsic_memory_barrier_atomic_counter
:
3764 case nir_intrinsic_memory_barrier_buffer
:
3765 case nir_intrinsic_memory_barrier_image
:
3766 case nir_intrinsic_memory_barrier
: {
3767 const fs_builder ubld
= bld
.group(8, 0);
3768 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3769 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3774 case nir_intrinsic_group_memory_barrier
:
3775 case nir_intrinsic_memory_barrier_shared
:
3776 /* We treat these workgroup-level barriers as no-ops. This should be
3777 * safe at present and as long as:
3779 * - Memory access instructions are not subsequently reordered by the
3780 * compiler back-end.
3782 * - All threads from a given compute shader workgroup fit within a
3783 * single subslice and therefore talk to the same HDC shared unit
3784 * what supposedly guarantees ordering and coherency between threads
3785 * from the same workgroup. This may change in the future when we
3786 * start splitting workgroups across multiple subslices.
3788 * - The context is not in fault-and-stream mode, which could cause
3789 * memory transactions (including to SLM) prior to the barrier to be
3790 * replayed after the barrier if a pagefault occurs. This shouldn't
3791 * be a problem up to and including SKL because fault-and-stream is
3792 * not usable due to hardware issues, but that's likely to change in
3797 case nir_intrinsic_shader_clock
: {
3798 /* We cannot do anything if there is an event, so ignore it for now */
3799 fs_reg shader_clock
= get_timestamp(bld
);
3800 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3802 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3806 case nir_intrinsic_image_size
: {
3807 /* Get the referenced image variable and type. */
3808 const nir_variable
*var
= instr
->variables
[0]->var
;
3809 const glsl_type
*type
= var
->type
->without_array();
3811 /* Get the size of the image. */
3812 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3813 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3815 /* For 1DArray image types, the array index is stored in the Z component.
3816 * Fix this by swizzling the Z component to the Y component.
3818 const bool is_1d_array_image
=
3819 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3820 type
->sampler_array
;
3822 /* For CubeArray images, we should count the number of cubes instead
3823 * of the number of faces. Fix it by dividing the (Z component) by 6.
3825 const bool is_cube_array_image
=
3826 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3827 type
->sampler_array
;
3829 /* Copy all the components. */
3830 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3831 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3832 if ((int)c
>= type
->coordinate_components()) {
3833 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3835 } else if (c
== 1 && is_1d_array_image
) {
3836 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3837 offset(size
, bld
, 2));
3838 } else if (c
== 2 && is_cube_array_image
) {
3839 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3840 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3841 offset(size
, bld
, c
), brw_imm_d(6));
3843 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3844 offset(size
, bld
, c
));
3851 case nir_intrinsic_image_samples
:
3852 /* The driver does not support multi-sampled images. */
3853 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3856 case nir_intrinsic_load_uniform
: {
3857 /* Offsets are in bytes but they should always be multiples of 4 */
3858 assert(instr
->const_index
[0] % 4 == 0);
3860 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3862 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3864 /* Offsets are in bytes but they should always be multiples of 4 */
3865 assert(const_offset
->u32
[0] % 4 == 0);
3866 src
.reg_offset
= const_offset
->u32
[0] / 4;
3868 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3869 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3872 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3873 BRW_REGISTER_TYPE_UD
);
3875 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3876 * go past the end of the uniform. In order to keep the n'th
3877 * component from running past, we subtract off the size of all but
3878 * one component of the vector.
3880 assert(instr
->const_index
[1] >=
3881 instr
->num_components
* (int) type_sz(dest
.type
));
3882 unsigned read_size
= instr
->const_index
[1] -
3883 (instr
->num_components
- 1) * type_sz(dest
.type
);
3885 fs_reg indirect_chv_high_32bit
;
3886 bool is_chv_bxt_64bit
=
3887 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
3888 type_sz(dest
.type
) == 8;
3889 if (is_chv_bxt_64bit
) {
3890 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
3891 /* Calculate indirect address to read high 32 bits */
3892 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
3895 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3896 if (!is_chv_bxt_64bit
) {
3897 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3898 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3899 indirect
, brw_imm_ud(read_size
));
3901 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3902 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
3903 offset(src
, bld
, j
),
3904 indirect
, brw_imm_ud(read_size
));
3906 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3907 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
3908 offset(src
, bld
, j
),
3909 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
3916 case nir_intrinsic_load_ubo
: {
3917 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3921 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3922 const_index
->u32
[0];
3923 surf_index
= brw_imm_ud(index
);
3924 brw_mark_surface_used(prog_data
, index
);
3926 /* The block index is not a constant. Evaluate the index expression
3927 * per-channel and add the base UBO index; we have to select a value
3928 * from any live channel.
3930 surf_index
= vgrf(glsl_type::uint_type
);
3931 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3932 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3933 surf_index
= bld
.emit_uniformize(surf_index
);
3935 /* Assume this may touch any UBO. It would be nice to provide
3936 * a tighter bound, but the array information is already lowered away.
3938 brw_mark_surface_used(prog_data
,
3939 stage_prog_data
->binding_table
.ubo_start
+
3940 nir
->info
.num_ubos
- 1);
3943 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3944 if (const_offset
== NULL
) {
3945 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3946 BRW_REGISTER_TYPE_UD
);
3948 for (int i
= 0; i
< instr
->num_components
; i
++)
3949 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3950 base_offset
, i
* type_sz(dest
.type
));
3952 /* Even if we are loading doubles, a pull constant load will load
3953 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3954 * need to load a full dvec4 we will have to emit 2 loads. This is
3955 * similar to demote_pull_constants(), except that in that case we
3956 * see individual accesses to each component of the vector and then
3957 * we let CSE deal with duplicate loads. Here we see a vector access
3958 * and we have to split it if necessary.
3960 const unsigned type_size
= type_sz(dest
.type
);
3961 const fs_reg packed_consts
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
3962 for (unsigned c
= 0; c
< instr
->num_components
;) {
3963 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3965 /* Number of usable components in the next 16B-aligned load */
3966 const unsigned count
= MIN2(instr
->num_components
- c
,
3967 (16 - base
% 16) / type_size
);
3970 .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3971 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
3973 const fs_reg consts
=
3974 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
3976 for (unsigned d
= 0; d
< count
; d
++)
3977 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3985 case nir_intrinsic_load_ssbo
: {
3986 assert(devinfo
->gen
>= 7);
3988 nir_const_value
*const_uniform_block
=
3989 nir_src_as_const_value(instr
->src
[0]);
3992 if (const_uniform_block
) {
3993 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3994 const_uniform_block
->u32
[0];
3995 surf_index
= brw_imm_ud(index
);
3996 brw_mark_surface_used(prog_data
, index
);
3998 surf_index
= vgrf(glsl_type::uint_type
);
3999 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4000 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4002 /* Assume this may touch any UBO. It would be nice to provide
4003 * a tighter bound, but the array information is already lowered away.
4005 brw_mark_surface_used(prog_data
,
4006 stage_prog_data
->binding_table
.ssbo_start
+
4007 nir
->info
.num_ssbos
- 1);
4011 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4013 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4015 offset_reg
= get_nir_src(instr
->src
[1]);
4018 /* Read the vector */
4019 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4020 instr
->num_components
);
4025 case nir_intrinsic_store_ssbo
: {
4026 assert(devinfo
->gen
>= 7);
4028 if (stage
== MESA_SHADER_FRAGMENT
)
4029 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4033 nir_const_value
*const_uniform_block
=
4034 nir_src_as_const_value(instr
->src
[1]);
4035 if (const_uniform_block
) {
4036 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4037 const_uniform_block
->u32
[0];
4038 surf_index
= brw_imm_ud(index
);
4039 brw_mark_surface_used(prog_data
, index
);
4041 surf_index
= vgrf(glsl_type::uint_type
);
4042 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4043 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4045 brw_mark_surface_used(prog_data
,
4046 stage_prog_data
->binding_table
.ssbo_start
+
4047 nir
->info
.num_ssbos
- 1);
4051 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4054 unsigned writemask
= instr
->const_index
[0];
4056 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4057 * since the untyped writes below operate in units of 32-bits, which
4058 * means that we need to write twice as many components each time.
4059 * Also, we have to suffle 64-bit data to be in the appropriate layout
4060 * expected by our 32-bit write messages.
4062 unsigned type_size
= 4;
4063 unsigned bit_size
= instr
->src
[0].is_ssa
?
4064 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4065 if (bit_size
== 64) {
4068 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4069 shuffle_64bit_data_for_32bit_write(bld
,
4070 retype(tmp
, BRW_REGISTER_TYPE_F
),
4071 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4072 instr
->num_components
);
4076 unsigned type_slots
= type_size
/ 4;
4078 /* Combine groups of consecutive enabled channels in one write
4079 * message. We use ffs to find the first enabled channel and then ffs on
4080 * the bit-inverse, down-shifted writemask to determine the length of
4081 * the block of enabled bits.
4084 unsigned first_component
= ffs(writemask
) - 1;
4085 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4087 /* We can't write more than 2 64-bit components at once. Limit the
4088 * length of the write to what we can do and let the next iteration
4092 length
= MIN2(2, length
);
4095 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4097 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4098 type_size
* first_component
);
4100 offset_reg
= vgrf(glsl_type::uint_type
);
4102 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4103 brw_imm_ud(type_size
* first_component
));
4107 emit_untyped_write(bld
, surf_index
, offset_reg
,
4108 offset(val_reg
, bld
, first_component
* type_slots
),
4109 1 /* dims */, length
* type_slots
,
4110 BRW_PREDICATE_NONE
);
4112 /* Clear the bits in the writemask that we just wrote, then try
4113 * again to see if more channels are left.
4115 writemask
&= (15 << (first_component
+ length
));
4120 case nir_intrinsic_store_output
: {
4121 fs_reg src
= get_nir_src(instr
->src
[0]);
4122 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
4123 instr
->const_index
[0]);
4125 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4126 assert(const_offset
&& "Indirect output stores not allowed");
4127 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
4129 unsigned num_components
= instr
->num_components
;
4130 unsigned first_component
= nir_intrinsic_component(instr
);
4131 unsigned bit_size
= instr
->src
[0].is_ssa
?
4132 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4133 if (bit_size
== 64) {
4135 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4136 BRW_REGISTER_TYPE_F
);
4137 shuffle_64bit_data_for_32bit_write(
4138 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4139 src
= retype(tmp
, src
.type
);
4140 num_components
*= 2;
4143 for (unsigned j
= 0; j
< num_components
; j
++) {
4144 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4145 offset(src
, bld
, j
));
4150 case nir_intrinsic_ssbo_atomic_add
:
4151 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4153 case nir_intrinsic_ssbo_atomic_imin
:
4154 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4156 case nir_intrinsic_ssbo_atomic_umin
:
4157 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4159 case nir_intrinsic_ssbo_atomic_imax
:
4160 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4162 case nir_intrinsic_ssbo_atomic_umax
:
4163 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4165 case nir_intrinsic_ssbo_atomic_and
:
4166 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4168 case nir_intrinsic_ssbo_atomic_or
:
4169 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4171 case nir_intrinsic_ssbo_atomic_xor
:
4172 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4174 case nir_intrinsic_ssbo_atomic_exchange
:
4175 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4177 case nir_intrinsic_ssbo_atomic_comp_swap
:
4178 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4181 case nir_intrinsic_get_buffer_size
: {
4182 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4183 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4185 /* A resinfo's sampler message is used to get the buffer size. The
4186 * SIMD8's writeback message consists of four registers and SIMD16's
4187 * writeback message consists of 8 destination registers (two per each
4188 * component). Because we are only interested on the first channel of
4189 * the first returned component, where resinfo returns the buffer size
4190 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4191 * the dispatch width.
4193 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4194 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4195 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4198 ubld
.MOV(src_payload
, brw_imm_d(0));
4200 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4201 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4202 src_payload
, brw_imm_ud(index
));
4203 inst
->header_size
= 0;
4205 inst
->regs_written
= 4;
4207 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4208 brw_mark_surface_used(prog_data
, index
);
4212 case nir_intrinsic_load_channel_num
: {
4213 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4214 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4215 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4216 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4217 if (dispatch_width
> 8)
4218 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4219 if (dispatch_width
> 16) {
4220 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4221 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4228 unreachable("unknown intrinsic");
4233 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4234 int op
, nir_intrinsic_instr
*instr
)
4236 if (stage
== MESA_SHADER_FRAGMENT
)
4237 ((struct brw_wm_prog_data
*)prog_data
)->has_side_effects
= true;
4240 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4241 dest
= get_nir_dest(instr
->dest
);
4244 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4245 if (const_surface
) {
4246 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4247 const_surface
->u32
[0];
4248 surface
= brw_imm_ud(surf_index
);
4249 brw_mark_surface_used(prog_data
, surf_index
);
4251 surface
= vgrf(glsl_type::uint_type
);
4252 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4253 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4255 /* Assume this may touch any SSBO. This is the same we do for other
4256 * UBO/SSBO accesses with non-constant surface.
4258 brw_mark_surface_used(prog_data
,
4259 stage_prog_data
->binding_table
.ssbo_start
+
4260 nir
->info
.num_ssbos
- 1);
4263 fs_reg offset
= get_nir_src(instr
->src
[1]);
4264 fs_reg data1
= get_nir_src(instr
->src
[2]);
4266 if (op
== BRW_AOP_CMPWR
)
4267 data2
= get_nir_src(instr
->src
[3]);
4269 /* Emit the actual atomic operation */
4271 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4273 1 /* dims */, 1 /* rsize */,
4275 BRW_PREDICATE_NONE
);
4276 dest
.type
= atomic_result
.type
;
4277 bld
.MOV(dest
, atomic_result
);
4281 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4282 int op
, nir_intrinsic_instr
*instr
)
4285 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4286 dest
= get_nir_dest(instr
->dest
);
4288 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4290 fs_reg data1
= get_nir_src(instr
->src
[1]);
4292 if (op
== BRW_AOP_CMPWR
)
4293 data2
= get_nir_src(instr
->src
[2]);
4295 /* Get the offset */
4296 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4298 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4300 offset
= vgrf(glsl_type::uint_type
);
4302 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4303 brw_imm_ud(instr
->const_index
[0]));
4306 /* Emit the actual atomic operation operation */
4308 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4310 1 /* dims */, 1 /* rsize */,
4312 BRW_PREDICATE_NONE
);
4313 dest
.type
= atomic_result
.type
;
4314 bld
.MOV(dest
, atomic_result
);
4318 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4320 unsigned texture
= instr
->texture_index
;
4321 unsigned sampler
= instr
->sampler_index
;
4323 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4325 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4326 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4328 int lod_components
= 0;
4330 /* The hardware requires a LOD for buffer textures */
4331 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4332 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4334 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4335 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4336 switch (instr
->src
[i
].src_type
) {
4337 case nir_tex_src_bias
:
4338 srcs
[TEX_LOGICAL_SRC_LOD
] =
4339 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4341 case nir_tex_src_comparitor
:
4342 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4344 case nir_tex_src_coord
:
4345 switch (instr
->op
) {
4347 case nir_texop_txf_ms
:
4348 case nir_texop_txf_ms_mcs
:
4349 case nir_texop_samples_identical
:
4350 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4353 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4357 case nir_tex_src_ddx
:
4358 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4359 lod_components
= nir_tex_instr_src_size(instr
, i
);
4361 case nir_tex_src_ddy
:
4362 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4364 case nir_tex_src_lod
:
4365 switch (instr
->op
) {
4367 srcs
[TEX_LOGICAL_SRC_LOD
] =
4368 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4371 srcs
[TEX_LOGICAL_SRC_LOD
] =
4372 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4375 srcs
[TEX_LOGICAL_SRC_LOD
] =
4376 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4380 case nir_tex_src_ms_index
:
4381 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4384 case nir_tex_src_offset
: {
4385 nir_const_value
*const_offset
=
4386 nir_src_as_const_value(instr
->src
[i
].src
);
4388 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4389 if (header_bits
!= 0)
4390 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4392 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4393 retype(src
, BRW_REGISTER_TYPE_D
);
4398 case nir_tex_src_projector
:
4399 unreachable("should be lowered");
4401 case nir_tex_src_texture_offset
: {
4402 /* Figure out the highest possible texture index and mark it as used */
4403 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4404 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4405 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4407 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4409 brw_mark_surface_used(prog_data
, max_used
);
4411 /* Emit code to evaluate the actual indexing expression */
4412 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4413 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4414 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4418 case nir_tex_src_sampler_offset
: {
4419 /* Emit code to evaluate the actual indexing expression */
4420 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4421 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4422 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4426 case nir_tex_src_ms_mcs
:
4427 assert(instr
->op
== nir_texop_txf_ms
);
4428 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4431 case nir_tex_src_plane
: {
4432 nir_const_value
*const_plane
=
4433 nir_src_as_const_value(instr
->src
[i
].src
);
4434 const uint32_t plane
= const_plane
->u32
[0];
4435 const uint32_t texture_index
=
4436 instr
->texture_index
+
4437 stage_prog_data
->binding_table
.plane_start
[plane
] -
4438 stage_prog_data
->binding_table
.texture_start
;
4440 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4445 unreachable("unknown texture source");
4449 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4450 (instr
->op
== nir_texop_txf_ms
||
4451 instr
->op
== nir_texop_samples_identical
)) {
4452 if (devinfo
->gen
>= 7 &&
4453 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4454 srcs
[TEX_LOGICAL_SRC_MCS
] =
4455 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4456 instr
->coord_components
,
4457 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4459 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4463 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4464 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4466 if (instr
->op
== nir_texop_query_levels
) {
4467 /* textureQueryLevels() is implemented in terms of TXS so we need to
4468 * pass a valid LOD argument.
4470 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4471 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4475 switch (instr
->op
) {
4477 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
4480 opcode
= FS_OPCODE_TXB_LOGICAL
;
4483 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4486 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4489 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4491 case nir_texop_txf_ms
:
4492 if ((key_tex
->msaa_16
& (1 << sampler
)))
4493 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4495 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4497 case nir_texop_txf_ms_mcs
:
4498 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4500 case nir_texop_query_levels
:
4502 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4505 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4508 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4509 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4510 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4512 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4514 case nir_texop_texture_samples
:
4515 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4517 case nir_texop_samples_identical
: {
4518 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4520 /* If mcs is an immediate value, it means there is no MCS. In that case
4521 * just return false.
4523 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4524 bld
.MOV(dst
, brw_imm_ud(0u));
4525 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4526 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4527 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4528 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4529 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4531 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4532 BRW_CONDITIONAL_EQ
);
4537 unreachable("unknown texture opcode");
4540 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4541 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4543 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4544 if (devinfo
->gen
>= 9 &&
4545 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4546 unsigned write_mask
= instr
->dest
.is_ssa
?
4547 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4548 (1 << dest_size
) - 1;
4549 assert(write_mask
!= 0); /* dead code should have been eliminated */
4550 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
4552 inst
->regs_written
= 4 * dispatch_width
/ 8;
4555 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4556 inst
->shadow_compare
= true;
4558 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4559 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4561 if (instr
->op
== nir_texop_tg4
) {
4562 if (instr
->component
== 1 &&
4563 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4564 /* gather4 sampler is broken for green channel on RG32F --
4565 * we must ask for blue instead.
4567 inst
->offset
|= 2 << 16;
4569 inst
->offset
|= instr
->component
<< 16;
4572 if (devinfo
->gen
== 6)
4573 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4577 for (unsigned i
= 0; i
< dest_size
; i
++)
4578 nir_dest
[i
] = offset(dst
, bld
, i
);
4580 if (instr
->op
== nir_texop_query_levels
) {
4581 /* # levels is in .w */
4582 nir_dest
[0] = offset(dst
, bld
, 3);
4583 } else if (instr
->op
== nir_texop_txs
&&
4584 dest_size
>= 3 && devinfo
->gen
< 7) {
4585 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4586 fs_reg depth
= offset(dst
, bld
, 2);
4587 nir_dest
[2] = vgrf(glsl_type::int_type
);
4588 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4591 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4595 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4597 switch (instr
->type
) {
4598 case nir_jump_break
:
4599 bld
.emit(BRW_OPCODE_BREAK
);
4601 case nir_jump_continue
:
4602 bld
.emit(BRW_OPCODE_CONTINUE
);
4604 case nir_jump_return
:
4606 unreachable("unknown jump");
4611 * This helper takes the result of a load operation that reads 32-bit elements
4619 * and shuffles the data to get this:
4626 * Which is exactly what we want if the load is reading 64-bit components
4627 * like doubles, where x represents the low 32-bit of the x double component
4628 * and y represents the high 32-bit of the x double component (likewise with
4629 * z and w for double component y). The parameter @components represents
4630 * the number of 64-bit components present in @src. This would typically be
4631 * 2 at most, since we can only fit 2 double elements in the result of a
4634 * Notice that @dst and @src can be the same register.
4637 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4640 uint32_t components
)
4642 assert(type_sz(src
.type
) == 4);
4643 assert(type_sz(dst
.type
) == 8);
4645 /* A temporary that we will use to shuffle the 32-bit data of each
4646 * component in the vector into valid 64-bit data. We can't write directly
4647 * to dst because dst can be (and would usually be) the same as src
4648 * and in that case the first MOV in the loop below would overwrite the
4649 * data read in the second MOV.
4651 fs_reg tmp
= bld
.vgrf(dst
.type
);
4653 for (unsigned i
= 0; i
< components
; i
++) {
4654 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4656 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4657 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4659 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4664 * This helper does the inverse operation of
4665 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4667 * We need to do this when we are going to use untyped write messsages that
4668 * operate with 32-bit components in order to arrange our 64-bit data to be
4669 * in the expected layout.
4671 * Notice that callers of this function, unlike in the case of the inverse
4672 * operation, would typically need to call this with dst and src being
4673 * different registers, since they would otherwise corrupt the original
4674 * 64-bit data they are about to write. Because of this the function checks
4675 * that the src and dst regions involved in the operation do not overlap.
4678 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4681 uint32_t components
)
4683 assert(type_sz(src
.type
) == 8);
4684 assert(type_sz(dst
.type
) == 4);
4686 assert(!src
.in_range(dst
, 2 * components
* bld
.dispatch_width() / 8));
4688 for (unsigned i
= 0; i
< components
; i
++) {
4689 const fs_reg component_i
= offset(src
, bld
, i
);
4690 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4691 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4696 setup_imm_df(const fs_builder
&bld
, double v
)
4698 const struct brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4699 assert(devinfo
->gen
>= 7);
4701 if (devinfo
->gen
>= 8)
4702 return brw_imm_df(v
);
4704 /* gen7.5 does not support DF immediates straighforward but the DIM
4705 * instruction allows to set the 64-bit immediate value.
4707 if (devinfo
->is_haswell
) {
4708 const fs_builder ubld
= bld
.exec_all();
4709 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4710 ubld
.DIM(dst
, brw_imm_df(v
));
4711 return component(dst
, 0);
4714 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4715 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4716 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4718 * Alternatively, we could also produce a normal VGRF (without stride 0)
4719 * by writing to all the channels in the VGRF, however, that would hit the
4720 * gen7 bug where we have to split writes that span more than 1 register
4721 * into instructions with a width of 4 (otherwise the write to the second
4722 * register written runs into an execmask hardware bug) which isn't very
4735 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4736 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4737 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4738 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4740 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);