2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_overload(nir
, overload
) {
47 assert(strcmp(overload
->function
->name
, "main") == 0);
48 assert(overload
->impl
);
49 nir_emit_impl(overload
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (var
->data
.index
> 0) {
134 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
135 assert(var
->data
.index
== 1);
136 this->dual_src_output
= reg
;
137 this->do_dual_src
= true;
138 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
139 /* Writing gl_FragColor outputs to all color regions. */
140 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
141 this->outputs
[i
] = reg
;
142 this->output_components
[i
] = 4;
144 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
145 this->frag_depth
= reg
;
146 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
147 this->frag_stencil
= reg
;
148 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
149 this->sample_mask
= reg
;
151 int vector_elements
= var
->type
->without_array()->vector_elements
;
153 /* gl_FragData or a user-defined FS output */
154 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
155 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
157 /* General color output. */
158 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
159 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
160 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
161 this->output_components
[output
] = vector_elements
;
166 unreachable("unhandled shader stage");
172 fs_visitor::nir_setup_uniforms()
174 if (dispatch_width
!= 8)
177 uniforms
= nir
->num_uniforms
/ 4;
179 nir_foreach_variable(var
, &nir
->uniforms
) {
180 /* UBO's and atomics don't take up space in the uniform file */
181 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
184 if (type_size_scalar(var
->type
) > 0)
185 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
190 emit_system_values_block(nir_block
*block
, void *void_visitor
)
192 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
195 nir_foreach_instr(block
, instr
) {
196 if (instr
->type
!= nir_instr_type_intrinsic
)
199 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
200 switch (intrin
->intrinsic
) {
201 case nir_intrinsic_load_vertex_id
:
202 unreachable("should be lowered by lower_vertex_id().");
204 case nir_intrinsic_load_vertex_id_zero_base
:
205 assert(v
->stage
== MESA_SHADER_VERTEX
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
207 if (reg
->file
== BAD_FILE
)
208 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
211 case nir_intrinsic_load_base_vertex
:
212 assert(v
->stage
== MESA_SHADER_VERTEX
);
213 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
214 if (reg
->file
== BAD_FILE
)
215 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
218 case nir_intrinsic_load_instance_id
:
219 assert(v
->stage
== MESA_SHADER_VERTEX
);
220 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
221 if (reg
->file
== BAD_FILE
)
222 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
225 case nir_intrinsic_load_invocation_id
:
226 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
227 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
228 if (reg
->file
== BAD_FILE
) {
229 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
230 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
231 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
232 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
237 case nir_intrinsic_load_sample_pos
:
238 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
240 if (reg
->file
== BAD_FILE
)
241 *reg
= *v
->emit_samplepos_setup();
244 case nir_intrinsic_load_sample_id
:
245 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
246 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
247 if (reg
->file
== BAD_FILE
)
248 *reg
= *v
->emit_sampleid_setup();
251 case nir_intrinsic_load_sample_mask_in
:
252 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
253 assert(v
->devinfo
->gen
>= 7);
254 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
255 if (reg
->file
== BAD_FILE
)
256 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
257 BRW_REGISTER_TYPE_D
));
260 case nir_intrinsic_load_local_invocation_id
:
261 assert(v
->stage
== MESA_SHADER_COMPUTE
);
262 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
263 if (reg
->file
== BAD_FILE
)
264 *reg
= *v
->emit_cs_local_invocation_id_setup();
267 case nir_intrinsic_load_work_group_id
:
268 assert(v
->stage
== MESA_SHADER_COMPUTE
);
269 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
270 if (reg
->file
== BAD_FILE
)
271 *reg
= *v
->emit_cs_work_group_id_setup();
274 case nir_intrinsic_load_helper_invocation
:
275 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
276 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
277 if (reg
->file
== BAD_FILE
) {
278 const fs_builder abld
=
279 v
->bld
.annotate("gl_HelperInvocation", NULL
);
281 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
282 * pixel mask is in g1.7 of the thread payload.
284 * We move the per-channel pixel enable bit to the low bit of each
285 * channel by shifting the byte containing the pixel mask by the
286 * vector immediate 0x76543210UV.
288 * The region of <1,8,0> reads only 1 byte (the pixel masks for
289 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
290 * masks for 2 and 3) in SIMD16.
292 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
294 stride(byte_offset(retype(brw_vec1_grf(1, 0),
295 BRW_REGISTER_TYPE_UB
), 28),
297 brw_imm_uv(0x76543210));
299 /* A set bit in the pixel mask means the channel is enabled, but
300 * that is the opposite of gl_HelperInvocation so we need to invert
303 * The negate source-modifier bit of logical instructions on Gen8+
304 * performs 1's complement negation, so we can use that instead of
307 fs_reg inverted
= negate(shifted
);
308 if (v
->devinfo
->gen
< 8) {
309 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
310 abld
.NOT(inverted
, shifted
);
313 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
314 * with 1 and negating.
316 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
317 abld
.AND(anded
, inverted
, brw_imm_uw(1));
319 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
320 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
334 fs_visitor::nir_emit_system_values()
336 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
337 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
338 nir_system_values
[i
] = fs_reg();
341 nir_foreach_overload(nir
, overload
) {
342 assert(strcmp(overload
->function
->name
, "main") == 0);
343 assert(overload
->impl
);
344 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
349 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
351 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
352 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
353 nir_locals
[i
] = fs_reg();
356 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
357 unsigned array_elems
=
358 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
359 unsigned size
= array_elems
* reg
->num_components
;
360 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
363 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
366 nir_emit_cf_list(&impl
->body
);
370 fs_visitor::nir_emit_cf_list(exec_list
*list
)
372 exec_list_validate(list
);
373 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
374 switch (node
->type
) {
376 nir_emit_if(nir_cf_node_as_if(node
));
379 case nir_cf_node_loop
:
380 nir_emit_loop(nir_cf_node_as_loop(node
));
383 case nir_cf_node_block
:
384 nir_emit_block(nir_cf_node_as_block(node
));
388 unreachable("Invalid CFG node block");
394 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
396 /* first, put the condition into f0 */
397 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
398 retype(get_nir_src(if_stmt
->condition
),
399 BRW_REGISTER_TYPE_D
));
400 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
402 bld
.IF(BRW_PREDICATE_NORMAL
);
404 nir_emit_cf_list(&if_stmt
->then_list
);
406 /* note: if the else is empty, dead CF elimination will remove it */
407 bld
.emit(BRW_OPCODE_ELSE
);
409 nir_emit_cf_list(&if_stmt
->else_list
);
411 bld
.emit(BRW_OPCODE_ENDIF
);
415 fs_visitor::nir_emit_loop(nir_loop
*loop
)
417 bld
.emit(BRW_OPCODE_DO
);
419 nir_emit_cf_list(&loop
->body
);
421 bld
.emit(BRW_OPCODE_WHILE
);
425 fs_visitor::nir_emit_block(nir_block
*block
)
427 nir_foreach_instr(block
, instr
) {
428 nir_emit_instr(instr
);
433 fs_visitor::nir_emit_instr(nir_instr
*instr
)
435 const fs_builder abld
= bld
.annotate(NULL
, instr
);
437 switch (instr
->type
) {
438 case nir_instr_type_alu
:
439 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
442 case nir_instr_type_intrinsic
:
444 case MESA_SHADER_VERTEX
:
445 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
447 case MESA_SHADER_TESS_EVAL
:
448 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
450 case MESA_SHADER_GEOMETRY
:
451 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
453 case MESA_SHADER_FRAGMENT
:
454 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 case MESA_SHADER_COMPUTE
:
457 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
460 unreachable("unsupported shader stage");
464 case nir_instr_type_tex
:
465 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
468 case nir_instr_type_load_const
:
469 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
472 case nir_instr_type_ssa_undef
:
473 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
476 case nir_instr_type_jump
:
477 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
481 unreachable("unknown instruction type");
486 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
487 const fs_reg
&result
)
489 if (!instr
->src
[0].src
.is_ssa
||
490 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
493 nir_intrinsic_instr
*src0
=
494 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
496 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
499 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
500 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
503 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
504 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
507 fs_reg tmp
= vgrf(glsl_type::int_type
);
509 if (devinfo
->gen
>= 6) {
510 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
511 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
513 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
515 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
516 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
518 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
520 * This negation looks like it's safe in practice, because bits 0:4 will
521 * surely be TRIANGLES
524 if (value1
->f
[0] == -1.0f
) {
528 tmp
.type
= BRW_REGISTER_TYPE_W
;
529 tmp
.subreg_offset
= 2;
532 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
534 tmp
.type
= BRW_REGISTER_TYPE_D
;
535 tmp
.subreg_offset
= 0;
538 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
539 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
541 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
543 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
544 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
546 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
548 * This negation looks like it's safe in practice, because bits 0:4 will
549 * surely be TRIANGLES
552 if (value1
->f
[0] == -1.0f
) {
556 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
558 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
564 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
566 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
569 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
570 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
573 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
574 op
[i
] = get_nir_src(instr
->src
[i
].src
);
575 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
576 op
[i
].abs
= instr
->src
[i
].abs
;
577 op
[i
].negate
= instr
->src
[i
].negate
;
580 /* We get a bunch of mov's out of the from_ssa pass and they may still
581 * be vectorized. We'll handle them as a special-case. We'll also
582 * handle vecN here because it's basically the same thing.
590 fs_reg temp
= result
;
591 bool need_extra_copy
= false;
592 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
593 if (!instr
->src
[i
].src
.is_ssa
&&
594 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
595 need_extra_copy
= true;
596 temp
= bld
.vgrf(result
.type
, 4);
601 for (unsigned i
= 0; i
< 4; i
++) {
602 if (!(instr
->dest
.write_mask
& (1 << i
)))
605 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
606 inst
= bld
.MOV(offset(temp
, bld
, i
),
607 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
609 inst
= bld
.MOV(offset(temp
, bld
, i
),
610 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
612 inst
->saturate
= instr
->dest
.saturate
;
615 /* In this case the source and destination registers were the same,
616 * so we need to insert an extra set of moves in order to deal with
619 if (need_extra_copy
) {
620 for (unsigned i
= 0; i
< 4; i
++) {
621 if (!(instr
->dest
.write_mask
& (1 << i
)))
624 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
633 /* At this point, we have dealt with any instruction that operates on
634 * more than a single channel. Therefore, we can just adjust the source
635 * and destination registers for that channel and emit the instruction.
637 unsigned channel
= 0;
638 if (nir_op_infos
[instr
->op
].output_size
== 0) {
639 /* Since NIR is doing the scalarizing for us, we should only ever see
640 * vectorized operations with a single channel.
642 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
643 channel
= ffs(instr
->dest
.write_mask
) - 1;
645 result
= offset(result
, bld
, channel
);
648 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
649 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
650 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
656 inst
= bld
.MOV(result
, op
[0]);
657 inst
->saturate
= instr
->dest
.saturate
;
662 bld
.MOV(result
, op
[0]);
666 /* AND(val, 0x80000000) gives the sign bit.
668 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
671 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
673 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
674 op
[0].type
= BRW_REGISTER_TYPE_UD
;
675 result
.type
= BRW_REGISTER_TYPE_UD
;
676 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
678 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
679 inst
->predicate
= BRW_PREDICATE_NORMAL
;
680 if (instr
->dest
.saturate
) {
681 inst
= bld
.MOV(result
, result
);
682 inst
->saturate
= true;
688 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
689 * -> non-negative val generates 0x00000000.
690 * Predicated OR sets 1 if val is positive.
692 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
693 bld
.ASR(result
, op
[0], brw_imm_d(31));
694 inst
= bld
.OR(result
, result
, brw_imm_d(1));
695 inst
->predicate
= BRW_PREDICATE_NORMAL
;
699 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
700 inst
->saturate
= instr
->dest
.saturate
;
704 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
705 inst
->saturate
= instr
->dest
.saturate
;
709 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
710 inst
->saturate
= instr
->dest
.saturate
;
714 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
715 inst
->saturate
= instr
->dest
.saturate
;
719 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
720 inst
->saturate
= instr
->dest
.saturate
;
724 if (fs_key
->high_quality_derivatives
) {
725 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
727 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
729 inst
->saturate
= instr
->dest
.saturate
;
731 case nir_op_fddx_fine
:
732 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
735 case nir_op_fddx_coarse
:
736 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
737 inst
->saturate
= instr
->dest
.saturate
;
740 if (fs_key
->high_quality_derivatives
) {
741 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
742 brw_imm_d(fs_key
->render_to_fbo
));
744 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
745 brw_imm_d(fs_key
->render_to_fbo
));
747 inst
->saturate
= instr
->dest
.saturate
;
749 case nir_op_fddy_fine
:
750 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
751 brw_imm_d(fs_key
->render_to_fbo
));
752 inst
->saturate
= instr
->dest
.saturate
;
754 case nir_op_fddy_coarse
:
755 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
756 brw_imm_d(fs_key
->render_to_fbo
));
757 inst
->saturate
= instr
->dest
.saturate
;
762 inst
= bld
.ADD(result
, op
[0], op
[1]);
763 inst
->saturate
= instr
->dest
.saturate
;
767 inst
= bld
.MUL(result
, op
[0], op
[1]);
768 inst
->saturate
= instr
->dest
.saturate
;
772 bld
.MUL(result
, op
[0], op
[1]);
775 case nir_op_imul_high
:
776 case nir_op_umul_high
:
777 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
782 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
785 case nir_op_uadd_carry
:
786 unreachable("Should have been lowered by carry_to_arith().");
788 case nir_op_usub_borrow
:
789 unreachable("Should have been lowered by borrow_to_arith().");
792 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
798 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
804 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
809 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
814 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
818 if (devinfo
->gen
>= 8) {
819 op
[0] = resolve_source_modifiers(op
[0]);
821 bld
.NOT(result
, op
[0]);
824 if (devinfo
->gen
>= 8) {
825 op
[0] = resolve_source_modifiers(op
[0]);
826 op
[1] = resolve_source_modifiers(op
[1]);
828 bld
.XOR(result
, op
[0], op
[1]);
831 if (devinfo
->gen
>= 8) {
832 op
[0] = resolve_source_modifiers(op
[0]);
833 op
[1] = resolve_source_modifiers(op
[1]);
835 bld
.OR(result
, op
[0], op
[1]);
838 if (devinfo
->gen
>= 8) {
839 op
[0] = resolve_source_modifiers(op
[0]);
840 op
[1] = resolve_source_modifiers(op
[1]);
842 bld
.AND(result
, op
[0], op
[1]);
848 case nir_op_ball_fequal2
:
849 case nir_op_ball_iequal2
:
850 case nir_op_ball_fequal3
:
851 case nir_op_ball_iequal3
:
852 case nir_op_ball_fequal4
:
853 case nir_op_ball_iequal4
:
854 case nir_op_bany_fnequal2
:
855 case nir_op_bany_inequal2
:
856 case nir_op_bany_fnequal3
:
857 case nir_op_bany_inequal3
:
858 case nir_op_bany_fnequal4
:
859 case nir_op_bany_inequal4
:
860 unreachable("Lowered by nir_lower_alu_reductions");
862 case nir_op_fnoise1_1
:
863 case nir_op_fnoise1_2
:
864 case nir_op_fnoise1_3
:
865 case nir_op_fnoise1_4
:
866 case nir_op_fnoise2_1
:
867 case nir_op_fnoise2_2
:
868 case nir_op_fnoise2_3
:
869 case nir_op_fnoise2_4
:
870 case nir_op_fnoise3_1
:
871 case nir_op_fnoise3_2
:
872 case nir_op_fnoise3_3
:
873 case nir_op_fnoise3_4
:
874 case nir_op_fnoise4_1
:
875 case nir_op_fnoise4_2
:
876 case nir_op_fnoise4_3
:
877 case nir_op_fnoise4_4
:
878 unreachable("not reached: should be handled by lower_noise");
881 unreachable("not reached: should be handled by ldexp_to_arith()");
884 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
885 inst
->saturate
= instr
->dest
.saturate
;
889 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
890 inst
->saturate
= instr
->dest
.saturate
;
895 bld
.MOV(result
, negate(op
[0]));
899 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
902 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
906 inst
= bld
.RNDZ(result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
911 op
[0].negate
= !op
[0].negate
;
912 fs_reg temp
= vgrf(glsl_type::float_type
);
913 bld
.RNDD(temp
, op
[0]);
915 inst
= bld
.MOV(result
, temp
);
916 inst
->saturate
= instr
->dest
.saturate
;
920 inst
= bld
.RNDD(result
, op
[0]);
921 inst
->saturate
= instr
->dest
.saturate
;
924 inst
= bld
.FRC(result
, op
[0]);
925 inst
->saturate
= instr
->dest
.saturate
;
927 case nir_op_fround_even
:
928 inst
= bld
.RNDE(result
, op
[0]);
929 inst
->saturate
= instr
->dest
.saturate
;
935 if (devinfo
->gen
>= 6) {
936 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
937 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
939 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
940 inst
= bld
.SEL(result
, op
[0], op
[1]);
941 inst
->predicate
= BRW_PREDICATE_NORMAL
;
943 inst
->saturate
= instr
->dest
.saturate
;
949 if (devinfo
->gen
>= 6) {
950 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
951 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
953 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
954 inst
= bld
.SEL(result
, op
[0], op
[1]);
955 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 inst
->saturate
= instr
->dest
.saturate
;
960 case nir_op_pack_snorm_2x16
:
961 case nir_op_pack_snorm_4x8
:
962 case nir_op_pack_unorm_2x16
:
963 case nir_op_pack_unorm_4x8
:
964 case nir_op_unpack_snorm_2x16
:
965 case nir_op_unpack_snorm_4x8
:
966 case nir_op_unpack_unorm_2x16
:
967 case nir_op_unpack_unorm_4x8
:
968 case nir_op_unpack_half_2x16
:
969 case nir_op_pack_half_2x16
:
970 unreachable("not reached: should be handled by lower_packing_builtins");
972 case nir_op_unpack_half_2x16_split_x
:
973 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
974 inst
->saturate
= instr
->dest
.saturate
;
976 case nir_op_unpack_half_2x16_split_y
:
977 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
978 inst
->saturate
= instr
->dest
.saturate
;
982 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
983 inst
->saturate
= instr
->dest
.saturate
;
986 case nir_op_bitfield_reverse
:
987 bld
.BFREV(result
, op
[0]);
990 case nir_op_bit_count
:
991 bld
.CBIT(result
, op
[0]);
994 case nir_op_ufind_msb
:
995 case nir_op_ifind_msb
: {
996 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
998 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
999 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1000 * subtract the result from 31 to convert the MSB count into an LSB count.
1002 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1004 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1005 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1006 inst
->src
[0].negate
= true;
1010 case nir_op_find_lsb
:
1011 bld
.FBL(result
, op
[0]);
1014 case nir_op_ubitfield_extract
:
1015 case nir_op_ibitfield_extract
:
1016 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1019 bld
.BFI1(result
, op
[0], op
[1]);
1022 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1025 case nir_op_bitfield_insert
:
1026 unreachable("not reached: should be handled by "
1027 "lower_instructions::bitfield_insert_to_bfm_bfi");
1030 bld
.SHL(result
, op
[0], op
[1]);
1033 bld
.ASR(result
, op
[0], op
[1]);
1036 bld
.SHR(result
, op
[0], op
[1]);
1039 case nir_op_pack_half_2x16_split
:
1040 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1044 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1045 inst
->saturate
= instr
->dest
.saturate
;
1049 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1050 inst
->saturate
= instr
->dest
.saturate
;
1054 if (optimize_frontfacing_ternary(instr
, result
))
1057 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1058 inst
= bld
.SEL(result
, op
[1], op
[2]);
1059 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1063 unreachable("unhandled instruction");
1066 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1067 * to sign extend the low bit to 0/~0
1069 if (devinfo
->gen
<= 5 &&
1070 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1071 fs_reg masked
= vgrf(glsl_type::int_type
);
1072 bld
.AND(masked
, result
, brw_imm_d(1));
1073 masked
.negate
= true;
1074 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1079 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1080 nir_load_const_instr
*instr
)
1082 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1084 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1085 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1087 nir_ssa_values
[instr
->def
.index
] = reg
;
1091 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1093 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1094 instr
->def
.num_components
);
1098 fs_visitor::get_nir_src(nir_src src
)
1102 reg
= nir_ssa_values
[src
.ssa
->index
];
1104 /* We don't handle indirects on locals */
1105 assert(src
.reg
.indirect
== NULL
);
1106 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1107 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1110 /* to avoid floating-point denorm flushing problems, set the type by
1111 * default to D - instructions that need floating point semantics will set
1112 * this to F if they need to
1114 return retype(reg
, BRW_REGISTER_TYPE_D
);
1118 fs_visitor::get_nir_dest(nir_dest dest
)
1121 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1122 dest
.ssa
.num_components
);
1123 return nir_ssa_values
[dest
.ssa
.index
];
1125 /* We don't handle indirects on locals */
1126 assert(dest
.reg
.indirect
== NULL
);
1127 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1128 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1133 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1135 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1136 BRW_REGISTER_TYPE_UD
);
1138 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1139 tail
= tail
->child
) {
1140 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1141 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1142 const unsigned size
= glsl_get_length(tail
->type
);
1143 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1144 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1145 image
= offset(image
, bld
, base
* element_size
);
1147 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1148 fs_reg tmp
= vgrf(glsl_type::int_type
);
1150 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1151 /* IVB hangs when trying to access an invalid surface index with
1152 * the dataport. According to the spec "if the index used to
1153 * select an individual element is negative or greater than or
1154 * equal to the size of the array, the results of the operation
1155 * are undefined but may not lead to termination" -- which is one
1156 * of the possible outcomes of the hang. Clamp the index to
1157 * prevent access outside of the array bounds.
1159 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1160 BRW_REGISTER_TYPE_UD
),
1161 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1163 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1166 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1168 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1170 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1178 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1181 for (unsigned i
= 0; i
< 4; i
++) {
1182 if (!((wr_mask
>> i
) & 1))
1185 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1186 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1187 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1188 if (new_inst
->src
[j
].file
== VGRF
)
1189 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1196 * Get the matching channel register datatype for an image intrinsic of the
1197 * specified GLSL image type.
1200 get_image_base_type(const glsl_type
*type
)
1202 switch ((glsl_base_type
)type
->sampler_type
) {
1203 case GLSL_TYPE_UINT
:
1204 return BRW_REGISTER_TYPE_UD
;
1206 return BRW_REGISTER_TYPE_D
;
1207 case GLSL_TYPE_FLOAT
:
1208 return BRW_REGISTER_TYPE_F
;
1210 unreachable("Not reached.");
1215 * Get the appropriate atomic op for an image atomic intrinsic.
1218 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1221 case nir_intrinsic_image_atomic_add
:
1223 case nir_intrinsic_image_atomic_min
:
1224 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1225 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1226 case nir_intrinsic_image_atomic_max
:
1227 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1228 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1229 case nir_intrinsic_image_atomic_and
:
1231 case nir_intrinsic_image_atomic_or
:
1233 case nir_intrinsic_image_atomic_xor
:
1235 case nir_intrinsic_image_atomic_exchange
:
1237 case nir_intrinsic_image_atomic_comp_swap
:
1238 return BRW_AOP_CMPWR
;
1240 unreachable("Not reachable.");
1245 emit_pixel_interpolater_send(const fs_builder
&bld
,
1250 glsl_interp_qualifier interpolation
)
1256 if (src
.file
== BAD_FILE
) {
1258 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1262 mlen
= 2 * bld
.dispatch_width() / 8;
1265 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1267 /* 2 floats per slot returned */
1268 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1269 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1275 * Computes 1 << x, given a D/UD register containing some value x.
1278 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1280 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1282 fs_reg result
= bld
.vgrf(x
.type
, 1);
1283 fs_reg one
= bld
.vgrf(x
.type
, 1);
1285 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1286 bld
.SHL(result
, one
, x
);
1291 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1293 assert(stage
== MESA_SHADER_GEOMETRY
);
1295 struct brw_gs_prog_data
*gs_prog_data
=
1296 (struct brw_gs_prog_data
*) prog_data
;
1298 /* We can only do EndPrimitive() functionality when the control data
1299 * consists of cut bits. Fortunately, the only time it isn't is when the
1300 * output type is points, in which case EndPrimitive() is a no-op.
1302 if (gs_prog_data
->control_data_format
!=
1303 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1307 /* Cut bits use one bit per vertex. */
1308 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1310 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1311 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1313 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1314 * vertex n, 0 otherwise. So all we need to do here is mark bit
1315 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1316 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1317 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1319 * Note that if EndPrimitive() is called before emitting any vertices, this
1320 * will cause us to set bit 31 of the control_data_bits register to 1.
1321 * That's fine because:
1323 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1324 * output, so the hardware will ignore cut bit 31.
1326 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1327 * last vertex, so setting cut bit 31 has no effect (since the primitive
1328 * is automatically ended when the GS terminates).
1330 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1331 * control_data_bits register to 0 when the first vertex is emitted.
1334 const fs_builder abld
= bld
.annotate("end primitive");
1336 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1337 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1338 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1339 fs_reg mask
= intexp2(abld
, prev_count
);
1340 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1341 * attention to the lower 5 bits of its second source argument, so on this
1342 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1343 * ((vertex_count - 1) % 32).
1345 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1349 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1351 assert(stage
== MESA_SHADER_GEOMETRY
);
1352 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1354 struct brw_gs_prog_data
*gs_prog_data
=
1355 (struct brw_gs_prog_data
*) prog_data
;
1357 const fs_builder abld
= bld
.annotate("emit control data bits");
1358 const fs_builder fwa_bld
= bld
.exec_all();
1360 /* We use a single UD register to accumulate control data bits (32 bits
1361 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1364 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1365 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1366 * use the Channel Mask phase to enable/disable which DWord within that
1367 * group to write. (Remember, different SIMD8 channels may have emitted
1368 * different numbers of vertices, so we may need per-slot offsets.)
1370 * Channel masking presents an annoying problem: we may have to replicate
1371 * the data up to 4 times:
1373 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1375 * To avoid penalizing shaders that emit a small number of vertices, we
1376 * can avoid these sometimes: if the size of the control data header is
1377 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1378 * land in the same 128-bit group, so we can skip per-slot offsets.
1380 * Similarly, if the control data header is <= 32 bits, there is only one
1381 * DWord, so we can skip channel masks.
1383 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1385 fs_reg channel_mask
, per_slot_offset
;
1387 if (gs_compile
->control_data_header_size_bits
> 32) {
1388 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1389 channel_mask
= vgrf(glsl_type::uint_type
);
1392 if (gs_compile
->control_data_header_size_bits
> 128) {
1393 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1394 per_slot_offset
= vgrf(glsl_type::uint_type
);
1397 /* Figure out which DWord we're trying to write to using the formula:
1399 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1401 * Since bits_per_vertex is a power of two, and is known at compile
1402 * time, this can be optimized to:
1404 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1406 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1407 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1408 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1409 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1410 unsigned log2_bits_per_vertex
=
1411 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1412 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1414 if (per_slot_offset
.file
!= BAD_FILE
) {
1415 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1416 * the appropriate OWord within the control data header.
1418 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1421 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1422 * write to the appropriate DWORD within the OWORD.
1424 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1425 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1426 channel_mask
= intexp2(fwa_bld
, channel
);
1427 /* Then the channel masks need to be in bits 23:16. */
1428 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1431 /* Store the control data bits in the message payload and send it. */
1433 if (channel_mask
.file
!= BAD_FILE
)
1434 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1435 if (per_slot_offset
.file
!= BAD_FILE
)
1438 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1439 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1441 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1442 if (per_slot_offset
.file
!= BAD_FILE
)
1443 sources
[i
++] = per_slot_offset
;
1444 if (channel_mask
.file
!= BAD_FILE
)
1445 sources
[i
++] = channel_mask
;
1447 sources
[i
++] = this->control_data_bits
;
1450 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1451 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1453 /* We need to increment Global Offset by 256-bits to make room for
1454 * Broadwell's extra "Vertex Count" payload at the beginning of the
1455 * URB entry. Since this is an OWord message, Global Offset is counted
1456 * in 128-bit units, so we must set it to 2.
1458 if (gs_prog_data
->static_vertex_count
== -1)
1463 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1466 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1468 /* Note: we are calling this *before* increasing vertex_count, so
1469 * this->vertex_count == vertex_count - 1 in the formula above.
1472 /* Stream mode uses 2 bits per vertex */
1473 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1475 /* Must be a valid stream */
1476 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1478 /* Control data bits are initialized to 0 so we don't have to set any
1479 * bits when sending vertices to stream 0.
1484 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1486 /* reg::sid = stream_id */
1487 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1488 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1490 /* reg:shift_count = 2 * (vertex_count - 1) */
1491 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1492 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1494 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1495 * attention to the lower 5 bits of its second source argument, so on this
1496 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1497 * stream_id << ((2 * (vertex_count - 1)) % 32).
1499 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1500 abld
.SHL(mask
, sid
, shift_count
);
1501 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1505 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1508 assert(stage
== MESA_SHADER_GEOMETRY
);
1510 struct brw_gs_prog_data
*gs_prog_data
=
1511 (struct brw_gs_prog_data
*) prog_data
;
1513 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1514 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1516 /* Haswell and later hardware ignores the "Render Stream Select" bits
1517 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1518 * and instead sends all primitives down the pipeline for rasterization.
1519 * If the SOL stage is enabled, "Render Stream Select" is honored and
1520 * primitives bound to non-zero streams are discarded after stream output.
1522 * Since the only purpose of primives sent to non-zero streams is to
1523 * be recorded by transform feedback, we can simply discard all geometry
1524 * bound to these streams when transform feedback is disabled.
1526 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1529 /* If we're outputting 32 control data bits or less, then we can wait
1530 * until the shader is over to output them all. Otherwise we need to
1531 * output them as we go. Now is the time to do it, since we're about to
1532 * output the vertex_count'th vertex, so it's guaranteed that the
1533 * control data bits associated with the (vertex_count - 1)th vertex are
1536 if (gs_compile
->control_data_header_size_bits
> 32) {
1537 const fs_builder abld
=
1538 bld
.annotate("emit vertex: emit control data bits");
1540 /* Only emit control data bits if we've finished accumulating a batch
1541 * of 32 bits. This is the case when:
1543 * (vertex_count * bits_per_vertex) % 32 == 0
1545 * (in other words, when the last 5 bits of vertex_count *
1546 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1547 * integer n (which is always the case, since bits_per_vertex is
1548 * always 1 or 2), this is equivalent to requiring that the last 5-n
1549 * bits of vertex_count are 0:
1551 * vertex_count & (2^(5-n) - 1) == 0
1553 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1556 * vertex_count & (32 / bits_per_vertex - 1) == 0
1558 * TODO: If vertex_count is an immediate, we could do some of this math
1559 * at compile time...
1562 abld
.AND(bld
.null_reg_d(), vertex_count
,
1563 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1564 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1566 abld
.IF(BRW_PREDICATE_NORMAL
);
1567 /* If vertex_count is 0, then no control data bits have been
1568 * accumulated yet, so we can skip emitting them.
1570 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1571 BRW_CONDITIONAL_NEQ
);
1572 abld
.IF(BRW_PREDICATE_NORMAL
);
1573 emit_gs_control_data_bits(vertex_count
);
1574 abld
.emit(BRW_OPCODE_ENDIF
);
1576 /* Reset control_data_bits to 0 so we can start accumulating a new
1579 * Note: in the case where vertex_count == 0, this neutralizes the
1580 * effect of any call to EndPrimitive() that the shader may have
1581 * made before outputting its first vertex.
1583 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1584 inst
->force_writemask_all
= true;
1585 abld
.emit(BRW_OPCODE_ENDIF
);
1588 emit_urb_writes(vertex_count
);
1590 /* In stream mode we have to set control data bits for all vertices
1591 * unless we have disabled control data bits completely (which we do
1592 * do for GL_POINTS outputs that don't use streams).
1594 if (gs_compile
->control_data_header_size_bits
> 0 &&
1595 gs_prog_data
->control_data_format
==
1596 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1597 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1602 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1603 const nir_src
&vertex_src
,
1604 unsigned base_offset
,
1605 const nir_src
&offset_src
,
1606 unsigned num_components
)
1608 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1610 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1611 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1612 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1614 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1615 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1616 * gl_PointSize is available as a GS input, however, so it must be that.
1618 const bool is_point_size
= (base_offset
== 0);
1620 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1621 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1622 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1623 vertex_const
->u
[0] * push_reg_count
;
1624 /* This input was pushed into registers. */
1625 if (is_point_size
) {
1626 /* gl_PointSize comes in .w */
1627 assert(imm_offset
== 0);
1628 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1630 for (unsigned i
= 0; i
< num_components
; i
++) {
1631 bld
.MOV(offset(dst
, bld
, i
),
1632 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1636 /* Resort to the pull model. Ensure the VUE handles are provided. */
1637 gs_prog_data
->base
.include_vue_handles
= true;
1639 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1643 /* The vertex index is constant; just select the proper URB handle. */
1645 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1646 BRW_REGISTER_TYPE_UD
);
1648 /* The vertex index is non-constant. We need to use indirect
1649 * addressing to fetch the proper URB handle.
1651 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1652 * indicating that channel <n> should read the handle from
1653 * DWord <n>. We convert that to bytes by multiplying by 4.
1655 * Next, we convert the vertex index to bytes by multiplying
1656 * by 32 (shifting by 5), and add the two together. This is
1657 * the final indirect byte offset.
1659 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1660 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1661 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1662 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1663 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1665 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1666 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1667 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1668 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1669 /* Convert vertex_index to bytes (multiply by 32) */
1670 bld
.SHL(vertex_offset_bytes
,
1671 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1673 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1675 /* Use first_icp_handle as the base offset. There is one register
1676 * of URB handles per vertex, so inform the register allocator that
1677 * we might read up to nir->info.gs.vertices_in registers.
1679 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1680 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1681 fs_reg(icp_offset_bytes
),
1682 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1687 /* Constant indexing - use global offset. */
1688 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1689 inst
->offset
= base_offset
+ offset_const
->u
[0];
1690 inst
->base_mrf
= -1;
1692 inst
->regs_written
= num_components
;
1694 /* Indirect indexing - use per-slot offsets as well. */
1695 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1696 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1697 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1699 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1700 inst
->offset
= base_offset
;
1701 inst
->base_mrf
= -1;
1703 inst
->regs_written
= num_components
;
1706 if (is_point_size
) {
1707 /* Read the whole VUE header (because of alignment) and read .w. */
1708 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1710 inst
->regs_written
= 4;
1711 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1717 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1719 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1720 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1723 /* The only constant offset we should find is 0. brw_nir.c's
1724 * add_const_offset_to_base() will fold other constant offsets
1725 * into instr->const_index[0].
1727 assert(const_value
->u
[0] == 0);
1731 return get_nir_src(*offset_src
);
1735 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1736 nir_intrinsic_instr
*instr
)
1738 assert(stage
== MESA_SHADER_VERTEX
);
1741 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1742 dest
= get_nir_dest(instr
->dest
);
1744 switch (instr
->intrinsic
) {
1745 case nir_intrinsic_load_vertex_id
:
1746 unreachable("should be lowered by lower_vertex_id()");
1748 case nir_intrinsic_load_vertex_id_zero_base
:
1749 case nir_intrinsic_load_base_vertex
:
1750 case nir_intrinsic_load_instance_id
: {
1751 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1752 fs_reg val
= nir_system_values
[sv
];
1753 assert(val
.file
!= BAD_FILE
);
1754 dest
.type
= val
.type
;
1760 nir_emit_intrinsic(bld
, instr
);
1766 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1767 nir_intrinsic_instr
*instr
)
1769 assert(stage
== MESA_SHADER_TESS_EVAL
);
1770 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1773 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1774 dest
= get_nir_dest(instr
->dest
);
1776 switch (instr
->intrinsic
) {
1777 case nir_intrinsic_load_primitive_id
:
1778 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1780 case nir_intrinsic_load_tess_coord
:
1781 /* gl_TessCoord is part of the payload in g1-3 */
1782 for (unsigned i
= 0; i
< 3; i
++) {
1783 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1787 case nir_intrinsic_load_tess_level_outer
:
1788 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1789 * appears as a push-model input. So, we can simply use the ATTR file
1790 * rather than issuing URB read messages. The data is stored in the
1791 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1794 switch (tes_prog_data
->domain
) {
1795 case BRW_TESS_DOMAIN_QUAD
:
1796 for (unsigned i
= 0; i
< 4; i
++)
1797 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1799 case BRW_TESS_DOMAIN_TRI
:
1800 for (unsigned i
= 0; i
< 3; i
++)
1801 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1803 case BRW_TESS_DOMAIN_ISOLINE
:
1804 for (unsigned i
= 0; i
< 2; i
++)
1805 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1810 case nir_intrinsic_load_tess_level_inner
:
1811 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1812 * appears as a push-model input. So, we can simply use the ATTR file
1813 * rather than issuing URB read messages.
1815 switch (tes_prog_data
->domain
) {
1816 case BRW_TESS_DOMAIN_QUAD
:
1817 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1818 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1820 case BRW_TESS_DOMAIN_TRI
:
1821 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1823 case BRW_TESS_DOMAIN_ISOLINE
:
1824 /* ignore - value is undefined */
1829 case nir_intrinsic_load_input
:
1830 case nir_intrinsic_load_per_vertex_input
: {
1831 fs_reg indirect_offset
= get_indirect_offset(instr
);
1832 unsigned imm_offset
= instr
->const_index
[0];
1835 if (indirect_offset
.file
== BAD_FILE
) {
1836 /* Replicate the patch handle to all enabled channels */
1837 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1838 bld
.MOV(patch_handle
, retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1840 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1843 /* Indirect indexing - use per-slot offsets as well. */
1844 const fs_reg srcs
[] = {
1845 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1848 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1849 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1851 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1854 inst
->offset
= imm_offset
;
1855 inst
->base_mrf
= -1;
1856 inst
->regs_written
= instr
->num_components
;
1860 nir_emit_intrinsic(bld
, instr
);
1866 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1867 nir_intrinsic_instr
*instr
)
1869 assert(stage
== MESA_SHADER_GEOMETRY
);
1870 fs_reg indirect_offset
;
1873 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1874 dest
= get_nir_dest(instr
->dest
);
1876 switch (instr
->intrinsic
) {
1877 case nir_intrinsic_load_primitive_id
:
1878 assert(stage
== MESA_SHADER_GEOMETRY
);
1879 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1880 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1881 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1884 case nir_intrinsic_load_input
:
1885 unreachable("load_input intrinsics are invalid for the GS stage");
1887 case nir_intrinsic_load_per_vertex_input
:
1888 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1889 instr
->src
[1], instr
->num_components
);
1892 case nir_intrinsic_emit_vertex_with_counter
:
1893 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1896 case nir_intrinsic_end_primitive_with_counter
:
1897 emit_gs_end_primitive(instr
->src
[0]);
1900 case nir_intrinsic_set_vertex_count
:
1901 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1904 case nir_intrinsic_load_invocation_id
: {
1905 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1906 assert(val
.file
!= BAD_FILE
);
1907 dest
.type
= val
.type
;
1913 nir_emit_intrinsic(bld
, instr
);
1919 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1920 nir_intrinsic_instr
*instr
)
1922 assert(stage
== MESA_SHADER_FRAGMENT
);
1923 struct brw_wm_prog_data
*wm_prog_data
=
1924 (struct brw_wm_prog_data
*) prog_data
;
1927 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1928 dest
= get_nir_dest(instr
->dest
);
1930 switch (instr
->intrinsic
) {
1931 case nir_intrinsic_load_front_face
:
1932 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1933 *emit_frontfacing_interpolation());
1936 case nir_intrinsic_load_sample_pos
: {
1937 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1938 assert(sample_pos
.file
!= BAD_FILE
);
1939 dest
.type
= sample_pos
.type
;
1940 bld
.MOV(dest
, sample_pos
);
1941 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1945 case nir_intrinsic_load_helper_invocation
:
1946 case nir_intrinsic_load_sample_mask_in
:
1947 case nir_intrinsic_load_sample_id
: {
1948 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1949 fs_reg val
= nir_system_values
[sv
];
1950 assert(val
.file
!= BAD_FILE
);
1951 dest
.type
= val
.type
;
1956 case nir_intrinsic_discard
:
1957 case nir_intrinsic_discard_if
: {
1958 /* We track our discarded pixels in f0.1. By predicating on it, we can
1959 * update just the flag bits that aren't yet discarded. If there's no
1960 * condition, we emit a CMP of g0 != g0, so all currently executing
1961 * channels will get turned off.
1964 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1965 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1966 brw_imm_d(0), BRW_CONDITIONAL_Z
);
1968 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1969 BRW_REGISTER_TYPE_UW
));
1970 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1972 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1973 cmp
->flag_subreg
= 1;
1975 if (devinfo
->gen
>= 6) {
1976 emit_discard_jump();
1981 case nir_intrinsic_interp_var_at_centroid
:
1982 case nir_intrinsic_interp_var_at_sample
:
1983 case nir_intrinsic_interp_var_at_offset
: {
1984 /* Handle ARB_gpu_shader5 interpolation intrinsics
1986 * It's worth a quick word of explanation as to why we handle the full
1987 * variable-based interpolation intrinsic rather than a lowered version
1988 * with like we do for other inputs. We have to do that because the way
1989 * we set up inputs doesn't allow us to use the already setup inputs for
1990 * interpolation. At the beginning of the shader, we go through all of
1991 * the input variables and do the initial interpolation and put it in
1992 * the nir_inputs array based on its location as determined in
1993 * nir_lower_io. If the input isn't used, dead code cleans up and
1994 * everything works fine. However, when we get to the ARB_gpu_shader5
1995 * interpolation intrinsics, we need to reinterpolate the input
1996 * differently. If we used an intrinsic that just had an index it would
1997 * only give us the offset into the nir_inputs array. However, this is
1998 * useless because that value is post-interpolation and we need
1999 * pre-interpolation. In order to get the actual location of the bits
2000 * we get from the vertex fetching hardware, we need the variable.
2002 wm_prog_data
->pulls_bary
= true;
2004 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2005 const glsl_interp_qualifier interpolation
=
2006 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2008 switch (instr
->intrinsic
) {
2009 case nir_intrinsic_interp_var_at_centroid
:
2010 emit_pixel_interpolater_send(bld
,
2011 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2018 case nir_intrinsic_interp_var_at_sample
: {
2019 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2022 unsigned msg_data
= const_sample
->i
[0] << 4;
2024 emit_pixel_interpolater_send(bld
,
2025 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2028 brw_imm_ud(msg_data
),
2031 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2032 BRW_REGISTER_TYPE_UD
);
2034 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2035 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2036 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2037 bld
.exec_all().group(1, 0)
2038 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2039 emit_pixel_interpolater_send(bld
,
2040 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2046 /* Make a loop that sends a message to the pixel interpolater
2047 * for the sample number in each live channel. If there are
2048 * multiple channels with the same sample number then these
2049 * will be handled simultaneously with a single interation of
2052 bld
.emit(BRW_OPCODE_DO
);
2054 /* Get the next live sample number into sample_id_reg */
2055 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2057 /* Set the flag register so that we can perform the send
2058 * message on all channels that have the same sample number
2060 bld
.CMP(bld
.null_reg_ud(),
2061 sample_src
, sample_id
,
2062 BRW_CONDITIONAL_EQ
);
2063 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2064 bld
.exec_all().group(1, 0)
2065 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2067 emit_pixel_interpolater_send(bld
,
2068 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2073 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2075 /* Continue the loop if there are any live channels left */
2076 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2078 bld
.emit(BRW_OPCODE_WHILE
));
2085 case nir_intrinsic_interp_var_at_offset
: {
2086 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2089 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2090 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2092 emit_pixel_interpolater_send(bld
,
2093 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2096 brw_imm_ud(off_x
| (off_y
<< 4)),
2099 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2100 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2101 BRW_REGISTER_TYPE_F
);
2102 for (int i
= 0; i
< 2; i
++) {
2103 fs_reg temp
= vgrf(glsl_type::float_type
);
2104 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2105 fs_reg itemp
= vgrf(glsl_type::int_type
);
2106 bld
.MOV(itemp
, temp
); /* float to int */
2108 /* Clamp the upper end of the range to +7/16.
2109 * ARB_gpu_shader5 requires that we support a maximum offset
2110 * of +0.5, which isn't representable in a S0.4 value -- if
2111 * we didn't clamp it, we'd end up with -8/16, which is the
2112 * opposite of what the shader author wanted.
2114 * This is legal due to ARB_gpu_shader5's quantization
2117 * "Not all values of <offset> may be supported; x and y
2118 * offsets may be rounded to fixed-point values with the
2119 * number of fraction bits given by the
2120 * implementation-dependent constant
2121 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2123 set_condmod(BRW_CONDITIONAL_L
,
2124 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2127 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2128 emit_pixel_interpolater_send(bld
,
2139 unreachable("Invalid intrinsic");
2142 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2143 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2144 src
.type
= dest
.type
;
2146 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2147 dest
= offset(dest
, bld
, 1);
2152 nir_emit_intrinsic(bld
, instr
);
2158 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2159 nir_intrinsic_instr
*instr
)
2161 assert(stage
== MESA_SHADER_COMPUTE
);
2162 struct brw_cs_prog_data
*cs_prog_data
=
2163 (struct brw_cs_prog_data
*) prog_data
;
2166 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2167 dest
= get_nir_dest(instr
->dest
);
2169 switch (instr
->intrinsic
) {
2170 case nir_intrinsic_barrier
:
2172 cs_prog_data
->uses_barrier
= true;
2175 case nir_intrinsic_load_local_invocation_id
:
2176 case nir_intrinsic_load_work_group_id
: {
2177 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2178 fs_reg val
= nir_system_values
[sv
];
2179 assert(val
.file
!= BAD_FILE
);
2180 dest
.type
= val
.type
;
2181 for (unsigned i
= 0; i
< 3; i
++)
2182 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2186 case nir_intrinsic_load_num_work_groups
: {
2187 const unsigned surface
=
2188 cs_prog_data
->binding_table
.work_groups_start
;
2190 cs_prog_data
->uses_num_work_groups
= true;
2192 fs_reg surf_index
= brw_imm_ud(surface
);
2193 brw_mark_surface_used(prog_data
, surface
);
2195 /* Read the 3 GLuint components of gl_NumWorkGroups */
2196 for (unsigned i
= 0; i
< 3; i
++) {
2197 fs_reg read_result
=
2198 emit_untyped_read(bld
, surf_index
,
2200 1 /* dims */, 1 /* size */,
2201 BRW_PREDICATE_NONE
);
2202 read_result
.type
= dest
.type
;
2203 bld
.MOV(dest
, read_result
);
2204 dest
= offset(dest
, bld
, 1);
2209 case nir_intrinsic_shared_atomic_add
:
2210 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2212 case nir_intrinsic_shared_atomic_imin
:
2213 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2215 case nir_intrinsic_shared_atomic_umin
:
2216 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2218 case nir_intrinsic_shared_atomic_imax
:
2219 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2221 case nir_intrinsic_shared_atomic_umax
:
2222 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2224 case nir_intrinsic_shared_atomic_and
:
2225 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2227 case nir_intrinsic_shared_atomic_or
:
2228 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2230 case nir_intrinsic_shared_atomic_xor
:
2231 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2233 case nir_intrinsic_shared_atomic_exchange
:
2234 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2236 case nir_intrinsic_shared_atomic_comp_swap
:
2237 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2241 nir_emit_intrinsic(bld
, instr
);
2247 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2250 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2251 dest
= get_nir_dest(instr
->dest
);
2253 switch (instr
->intrinsic
) {
2254 case nir_intrinsic_atomic_counter_inc
:
2255 case nir_intrinsic_atomic_counter_dec
:
2256 case nir_intrinsic_atomic_counter_read
: {
2257 using namespace surface_access
;
2259 /* Get the arguments of the atomic intrinsic. */
2260 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2261 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2262 instr
->const_index
[0]);
2265 /* Emit a surface read or atomic op. */
2266 switch (instr
->intrinsic
) {
2267 case nir_intrinsic_atomic_counter_read
:
2268 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2271 case nir_intrinsic_atomic_counter_inc
:
2272 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2273 fs_reg(), 1, 1, BRW_AOP_INC
);
2276 case nir_intrinsic_atomic_counter_dec
:
2277 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2278 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2282 unreachable("Unreachable");
2285 /* Assign the result. */
2286 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2288 /* Mark the surface as used. */
2289 brw_mark_surface_used(stage_prog_data
, surface
);
2293 case nir_intrinsic_image_load
:
2294 case nir_intrinsic_image_store
:
2295 case nir_intrinsic_image_atomic_add
:
2296 case nir_intrinsic_image_atomic_min
:
2297 case nir_intrinsic_image_atomic_max
:
2298 case nir_intrinsic_image_atomic_and
:
2299 case nir_intrinsic_image_atomic_or
:
2300 case nir_intrinsic_image_atomic_xor
:
2301 case nir_intrinsic_image_atomic_exchange
:
2302 case nir_intrinsic_image_atomic_comp_swap
: {
2303 using namespace image_access
;
2305 /* Get the referenced image variable and type. */
2306 const nir_variable
*var
= instr
->variables
[0]->var
;
2307 const glsl_type
*type
= var
->type
->without_array();
2308 const brw_reg_type base_type
= get_image_base_type(type
);
2310 /* Get some metadata from the image intrinsic. */
2311 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2312 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2313 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2314 const mesa_format format
=
2315 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2316 _mesa_get_shader_image_format(var
->data
.image
.format
));
2318 /* Get the arguments of the image intrinsic. */
2319 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2320 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2321 BRW_REGISTER_TYPE_UD
);
2322 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2323 retype(get_nir_src(instr
->src
[2]), base_type
) :
2325 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2326 retype(get_nir_src(instr
->src
[3]), base_type
) :
2330 /* Emit an image load, store or atomic op. */
2331 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2332 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2334 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2335 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2338 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2339 surf_dims
, arr_dims
, info
->dest_components
,
2340 get_image_atomic_op(instr
->intrinsic
, type
));
2342 /* Assign the result. */
2343 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2344 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2345 offset(tmp
, bld
, c
));
2349 case nir_intrinsic_memory_barrier_atomic_counter
:
2350 case nir_intrinsic_memory_barrier_buffer
:
2351 case nir_intrinsic_memory_barrier_image
:
2352 case nir_intrinsic_memory_barrier
: {
2353 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2354 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2359 case nir_intrinsic_group_memory_barrier
:
2360 case nir_intrinsic_memory_barrier_shared
:
2361 /* We treat these workgroup-level barriers as no-ops. This should be
2362 * safe at present and as long as:
2364 * - Memory access instructions are not subsequently reordered by the
2365 * compiler back-end.
2367 * - All threads from a given compute shader workgroup fit within a
2368 * single subslice and therefore talk to the same HDC shared unit
2369 * what supposedly guarantees ordering and coherency between threads
2370 * from the same workgroup. This may change in the future when we
2371 * start splitting workgroups across multiple subslices.
2373 * - The context is not in fault-and-stream mode, which could cause
2374 * memory transactions (including to SLM) prior to the barrier to be
2375 * replayed after the barrier if a pagefault occurs. This shouldn't
2376 * be a problem up to and including SKL because fault-and-stream is
2377 * not usable due to hardware issues, but that's likely to change in
2382 case nir_intrinsic_shader_clock
: {
2383 /* We cannot do anything if there is an event, so ignore it for now */
2384 fs_reg shader_clock
= get_timestamp(bld
);
2385 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2387 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2391 case nir_intrinsic_image_size
: {
2392 /* Get the referenced image variable and type. */
2393 const nir_variable
*var
= instr
->variables
[0]->var
;
2394 const glsl_type
*type
= var
->type
->without_array();
2396 /* Get the size of the image. */
2397 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2398 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2400 /* For 1DArray image types, the array index is stored in the Z component.
2401 * Fix this by swizzling the Z component to the Y component.
2403 const bool is_1d_array_image
=
2404 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2405 type
->sampler_array
;
2407 /* For CubeArray images, we should count the number of cubes instead
2408 * of the number of faces. Fix it by dividing the (Z component) by 6.
2410 const bool is_cube_array_image
=
2411 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2412 type
->sampler_array
;
2414 /* Copy all the components. */
2415 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2416 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2417 if ((int)c
>= type
->coordinate_components()) {
2418 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2420 } else if (c
== 1 && is_1d_array_image
) {
2421 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2422 offset(size
, bld
, 2));
2423 } else if (c
== 2 && is_cube_array_image
) {
2424 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2425 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2426 offset(size
, bld
, c
), brw_imm_d(6));
2428 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2429 offset(size
, bld
, c
));
2436 case nir_intrinsic_image_samples
:
2437 /* The driver does not support multi-sampled images. */
2438 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2441 case nir_intrinsic_load_uniform
: {
2442 /* Offsets are in bytes but they should always be multiples of 4 */
2443 assert(instr
->const_index
[0] % 4 == 0);
2445 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2447 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2449 /* Offsets are in bytes but they should always be multiples of 4 */
2450 assert(const_offset
->u
[0] % 4 == 0);
2451 src
.reg_offset
= const_offset
->u
[0] / 4;
2453 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2456 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2457 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2462 case nir_intrinsic_load_ubo
: {
2463 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2467 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2469 surf_index
= brw_imm_ud(index
);
2470 brw_mark_surface_used(prog_data
, index
);
2472 /* The block index is not a constant. Evaluate the index expression
2473 * per-channel and add the base UBO index; we have to select a value
2474 * from any live channel.
2476 surf_index
= vgrf(glsl_type::uint_type
);
2477 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2478 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2479 surf_index
= bld
.emit_uniformize(surf_index
);
2481 /* Assume this may touch any UBO. It would be nice to provide
2482 * a tighter bound, but the array information is already lowered away.
2484 brw_mark_surface_used(prog_data
,
2485 stage_prog_data
->binding_table
.ubo_start
+
2486 nir
->info
.num_ubos
- 1);
2489 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2490 if (const_offset
== NULL
) {
2491 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2492 BRW_REGISTER_TYPE_D
);
2494 for (int i
= 0; i
< instr
->num_components
; i
++)
2495 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2496 base_offset
, i
* 4);
2498 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2499 packed_consts
.type
= dest
.type
;
2501 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2502 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2503 surf_index
, const_offset_reg
);
2505 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2506 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2508 /* The std140 packing rules don't allow vectors to cross 16-byte
2509 * boundaries, and a reg is 32 bytes.
2511 assert(packed_consts
.subreg_offset
< 32);
2513 bld
.MOV(dest
, packed_consts
);
2514 dest
= offset(dest
, bld
, 1);
2520 case nir_intrinsic_load_ssbo
: {
2521 assert(devinfo
->gen
>= 7);
2523 nir_const_value
*const_uniform_block
=
2524 nir_src_as_const_value(instr
->src
[0]);
2527 if (const_uniform_block
) {
2528 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2529 const_uniform_block
->u
[0];
2530 surf_index
= brw_imm_ud(index
);
2531 brw_mark_surface_used(prog_data
, index
);
2533 surf_index
= vgrf(glsl_type::uint_type
);
2534 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2535 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2537 /* Assume this may touch any UBO. It would be nice to provide
2538 * a tighter bound, but the array information is already lowered away.
2540 brw_mark_surface_used(prog_data
,
2541 stage_prog_data
->binding_table
.ssbo_start
+
2542 nir
->info
.num_ssbos
- 1);
2546 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2548 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2550 offset_reg
= get_nir_src(instr
->src
[1]);
2553 /* Read the vector */
2554 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2556 instr
->num_components
,
2557 BRW_PREDICATE_NONE
);
2558 read_result
.type
= dest
.type
;
2559 for (int i
= 0; i
< instr
->num_components
; i
++)
2560 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2565 case nir_intrinsic_load_shared
: {
2566 assert(devinfo
->gen
>= 7);
2568 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2570 /* Get the offset to read from */
2572 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2574 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2576 offset_reg
= vgrf(glsl_type::uint_type
);
2578 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2579 brw_imm_ud(instr
->const_index
[0]));
2582 /* Read the vector */
2583 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2585 instr
->num_components
,
2586 BRW_PREDICATE_NONE
);
2587 read_result
.type
= dest
.type
;
2588 for (int i
= 0; i
< instr
->num_components
; i
++)
2589 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2594 case nir_intrinsic_store_shared
: {
2595 assert(devinfo
->gen
>= 7);
2598 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2601 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2604 unsigned writemask
= instr
->const_index
[1];
2606 /* Combine groups of consecutive enabled channels in one write
2607 * message. We use ffs to find the first enabled channel and then ffs on
2608 * the bit-inverse, down-shifted writemask to determine the length of
2609 * the block of enabled bits.
2612 unsigned first_component
= ffs(writemask
) - 1;
2613 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2616 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2618 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2619 4 * first_component
);
2621 offset_reg
= vgrf(glsl_type::uint_type
);
2623 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2624 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2627 emit_untyped_write(bld
, surf_index
, offset_reg
,
2628 offset(val_reg
, bld
, first_component
),
2629 1 /* dims */, length
,
2630 BRW_PREDICATE_NONE
);
2632 /* Clear the bits in the writemask that we just wrote, then try
2633 * again to see if more channels are left.
2635 writemask
&= (15 << (first_component
+ length
));
2641 case nir_intrinsic_load_input
: {
2643 if (stage
== MESA_SHADER_VERTEX
) {
2644 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2646 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2647 instr
->const_index
[0]);
2650 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2651 assert(const_offset
&& "Indirect input loads not allowed");
2652 src
= offset(src
, bld
, const_offset
->u
[0]);
2654 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2655 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2660 case nir_intrinsic_store_ssbo
: {
2661 assert(devinfo
->gen
>= 7);
2665 nir_const_value
*const_uniform_block
=
2666 nir_src_as_const_value(instr
->src
[1]);
2667 if (const_uniform_block
) {
2668 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2669 const_uniform_block
->u
[0];
2670 surf_index
= brw_imm_ud(index
);
2671 brw_mark_surface_used(prog_data
, index
);
2673 surf_index
= vgrf(glsl_type::uint_type
);
2674 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2675 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2677 brw_mark_surface_used(prog_data
,
2678 stage_prog_data
->binding_table
.ssbo_start
+
2679 nir
->info
.num_ssbos
- 1);
2683 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2686 unsigned writemask
= instr
->const_index
[0];
2688 /* Combine groups of consecutive enabled channels in one write
2689 * message. We use ffs to find the first enabled channel and then ffs on
2690 * the bit-inverse, down-shifted writemask to determine the length of
2691 * the block of enabled bits.
2694 unsigned first_component
= ffs(writemask
) - 1;
2695 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2698 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2700 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2702 offset_reg
= vgrf(glsl_type::uint_type
);
2704 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2705 brw_imm_ud(4 * first_component
));
2708 emit_untyped_write(bld
, surf_index
, offset_reg
,
2709 offset(val_reg
, bld
, first_component
),
2710 1 /* dims */, length
,
2711 BRW_PREDICATE_NONE
);
2713 /* Clear the bits in the writemask that we just wrote, then try
2714 * again to see if more channels are left.
2716 writemask
&= (15 << (first_component
+ length
));
2721 case nir_intrinsic_store_output
: {
2722 fs_reg src
= get_nir_src(instr
->src
[0]);
2723 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2724 instr
->const_index
[0]);
2726 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2727 assert(const_offset
&& "Indirect output stores not allowed");
2728 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2730 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2731 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2736 case nir_intrinsic_ssbo_atomic_add
:
2737 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2739 case nir_intrinsic_ssbo_atomic_imin
:
2740 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2742 case nir_intrinsic_ssbo_atomic_umin
:
2743 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2745 case nir_intrinsic_ssbo_atomic_imax
:
2746 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2748 case nir_intrinsic_ssbo_atomic_umax
:
2749 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2751 case nir_intrinsic_ssbo_atomic_and
:
2752 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2754 case nir_intrinsic_ssbo_atomic_or
:
2755 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2757 case nir_intrinsic_ssbo_atomic_xor
:
2758 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2760 case nir_intrinsic_ssbo_atomic_exchange
:
2761 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2763 case nir_intrinsic_ssbo_atomic_comp_swap
:
2764 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2767 case nir_intrinsic_get_buffer_size
: {
2768 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2769 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2770 int reg_width
= dispatch_width
/ 8;
2773 fs_reg source
= brw_imm_d(0);
2775 int mlen
= 1 * reg_width
;
2777 /* A resinfo's sampler message is used to get the buffer size.
2778 * The SIMD8's writeback message consists of four registers and
2779 * SIMD16's writeback message consists of 8 destination registers
2780 * (two per each component), although we are only interested on the
2781 * first component, where resinfo returns the buffer size for
2784 int regs_written
= 4 * mlen
;
2785 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2786 BRW_REGISTER_TYPE_UD
);
2787 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2788 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2789 BRW_REGISTER_TYPE_UD
);
2790 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2791 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2792 src_payload
, brw_imm_ud(index
));
2793 inst
->header_size
= 0;
2795 inst
->regs_written
= regs_written
;
2797 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2799 brw_mark_surface_used(prog_data
, index
);
2804 unreachable("unknown intrinsic");
2809 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2810 int op
, nir_intrinsic_instr
*instr
)
2813 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2814 dest
= get_nir_dest(instr
->dest
);
2817 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2818 if (const_surface
) {
2819 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2820 const_surface
->u
[0];
2821 surface
= brw_imm_ud(surf_index
);
2822 brw_mark_surface_used(prog_data
, surf_index
);
2824 surface
= vgrf(glsl_type::uint_type
);
2825 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2826 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2828 /* Assume this may touch any SSBO. This is the same we do for other
2829 * UBO/SSBO accesses with non-constant surface.
2831 brw_mark_surface_used(prog_data
,
2832 stage_prog_data
->binding_table
.ssbo_start
+
2833 nir
->info
.num_ssbos
- 1);
2836 fs_reg offset
= get_nir_src(instr
->src
[1]);
2837 fs_reg data1
= get_nir_src(instr
->src
[2]);
2839 if (op
== BRW_AOP_CMPWR
)
2840 data2
= get_nir_src(instr
->src
[3]);
2842 /* Emit the actual atomic operation operation */
2844 fs_reg atomic_result
=
2845 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2847 1 /* dims */, 1 /* rsize */,
2849 BRW_PREDICATE_NONE
);
2850 dest
.type
= atomic_result
.type
;
2851 bld
.MOV(dest
, atomic_result
);
2855 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2856 int op
, nir_intrinsic_instr
*instr
)
2859 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2860 dest
= get_nir_dest(instr
->dest
);
2862 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2863 fs_reg offset
= get_nir_src(instr
->src
[0]);
2864 fs_reg data1
= get_nir_src(instr
->src
[1]);
2866 if (op
== BRW_AOP_CMPWR
)
2867 data2
= get_nir_src(instr
->src
[2]);
2869 /* Emit the actual atomic operation operation */
2871 fs_reg atomic_result
=
2872 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2874 1 /* dims */, 1 /* rsize */,
2876 BRW_PREDICATE_NONE
);
2877 dest
.type
= atomic_result
.type
;
2878 bld
.MOV(dest
, atomic_result
);
2882 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2884 unsigned sampler
= instr
->sampler_index
;
2885 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2887 int gather_component
= instr
->component
;
2889 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2892 int lod_components
= 0;
2893 int UNUSED offset_components
= 0;
2895 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2897 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2898 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2899 switch (instr
->src
[i
].src_type
) {
2900 case nir_tex_src_bias
:
2901 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2903 case nir_tex_src_comparitor
:
2904 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2906 case nir_tex_src_coord
:
2907 switch (instr
->op
) {
2909 case nir_texop_txf_ms
:
2910 case nir_texop_samples_identical
:
2911 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2914 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2918 case nir_tex_src_ddx
:
2919 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2920 lod_components
= nir_tex_instr_src_size(instr
, i
);
2922 case nir_tex_src_ddy
:
2923 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2925 case nir_tex_src_lod
:
2926 switch (instr
->op
) {
2928 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2931 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2934 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2938 case nir_tex_src_ms_index
:
2939 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2941 case nir_tex_src_offset
:
2942 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2943 if (instr
->is_array
)
2944 offset_components
= instr
->coord_components
- 1;
2946 offset_components
= instr
->coord_components
;
2948 case nir_tex_src_projector
:
2949 unreachable("should be lowered");
2951 case nir_tex_src_sampler_offset
: {
2952 /* Figure out the highest possible sampler index and mark it as used */
2953 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2954 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2955 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2957 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2959 brw_mark_surface_used(prog_data
, max_used
);
2961 /* Emit code to evaluate the actual indexing expression */
2962 sampler_reg
= vgrf(glsl_type::uint_type
);
2963 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
2964 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2969 unreachable("unknown texture source");
2973 if (instr
->op
== nir_texop_txf_ms
||
2974 instr
->op
== nir_texop_samples_identical
) {
2975 if (devinfo
->gen
>= 7 &&
2976 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2977 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2979 mcs
= brw_imm_ud(0u);
2983 for (unsigned i
= 0; i
< 3; i
++) {
2984 if (instr
->const_offset
[i
] != 0) {
2985 assert(offset_components
== 0);
2986 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
2991 enum glsl_base_type dest_base_type
=
2992 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2994 const glsl_type
*dest_type
=
2995 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2998 ir_texture_opcode op
;
2999 switch (instr
->op
) {
3000 case nir_texop_lod
: op
= ir_lod
; break;
3001 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3002 case nir_texop_tex
: op
= ir_tex
; break;
3003 case nir_texop_tg4
: op
= ir_tg4
; break;
3004 case nir_texop_txb
: op
= ir_txb
; break;
3005 case nir_texop_txd
: op
= ir_txd
; break;
3006 case nir_texop_txf
: op
= ir_txf
; break;
3007 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3008 case nir_texop_txl
: op
= ir_txl
; break;
3009 case nir_texop_txs
: op
= ir_txs
; break;
3010 case nir_texop_texture_samples
: {
3011 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3012 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3013 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3016 inst
->header_size
= 1;
3017 inst
->base_mrf
= -1;
3020 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3022 unreachable("unknown texture opcode");
3025 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3026 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3027 tex_offset
, mcs
, gather_component
,
3028 is_cube_array
, sampler
, sampler_reg
);
3030 fs_reg dest
= get_nir_dest(instr
->dest
);
3031 dest
.type
= this->result
.type
;
3032 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3033 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3034 dest
, this->result
),
3035 (1 << num_components
) - 1);
3039 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3041 switch (instr
->type
) {
3042 case nir_jump_break
:
3043 bld
.emit(BRW_OPCODE_BREAK
);
3045 case nir_jump_continue
:
3046 bld
.emit(BRW_OPCODE_CONTINUE
);
3048 case nir_jump_return
:
3050 unreachable("unknown jump");