2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
32 nir_optimize(nir_shader
*nir
)
37 nir_lower_vars_to_ssa(nir
);
38 nir_validate_shader(nir
);
39 nir_lower_alu_to_scalar(nir
);
40 nir_validate_shader(nir
);
41 progress
|= nir_copy_prop(nir
);
42 nir_validate_shader(nir
);
43 nir_lower_phis_to_scalar(nir
);
44 nir_validate_shader(nir
);
45 progress
|= nir_copy_prop(nir
);
46 nir_validate_shader(nir
);
47 progress
|= nir_opt_dce(nir
);
48 nir_validate_shader(nir
);
49 progress
|= nir_opt_cse(nir
);
50 nir_validate_shader(nir
);
51 progress
|= nir_opt_peephole_select(nir
);
52 nir_validate_shader(nir
);
53 progress
|= nir_opt_algebraic(nir
);
54 nir_validate_shader(nir
);
55 progress
|= nir_opt_peephole_ffma(nir
);
56 nir_validate_shader(nir
);
57 progress
|= nir_opt_constant_folding(nir
);
58 nir_validate_shader(nir
);
59 progress
|= nir_opt_remove_phis(nir
);
60 nir_validate_shader(nir
);
65 count_nir_instrs_in_block(nir_block
*block
, void *state
)
67 int *count
= (int *) state
;
68 nir_foreach_instr(block
, instr
) {
75 count_nir_instrs(nir_shader
*nir
)
78 nir_foreach_overload(nir
, overload
) {
81 nir_foreach_block(overload
->impl
, count_nir_instrs_in_block
, &count
);
87 fs_visitor::emit_nir_code()
89 const nir_shader_compiler_options
*options
=
90 ctx
->Const
.ShaderCompilerOptions
[stage
].NirOptions
;
93 /* First, lower the GLSL IR or Mesa IR to NIR */
95 lower_output_reads(shader
->base
.ir
);
96 nir
= glsl_to_nir(&shader
->base
, options
);
98 nir
= prog_to_nir(prog
, options
);
99 nir_convert_to_ssa(nir
); /* turn registers into SSA */
101 nir_validate_shader(nir
);
103 nir_lower_global_vars_to_local(nir
);
104 nir_validate_shader(nir
);
106 nir_split_var_copies(nir
);
107 nir_validate_shader(nir
);
111 /* Lower a bunch of stuff */
112 nir_lower_var_copies(nir
);
113 nir_validate_shader(nir
);
115 /* Get rid of split copies */
119 nir_assign_var_locations_scalar_direct_first(nir
, &nir
->uniforms
,
120 &num_direct_uniforms
,
123 /* ARB programs generally create a giant array of "uniform" data, and allow
124 * indirect addressing without any boundaries. In the absence of bounds
125 * analysis, it's all or nothing. num_direct_uniforms is only useful when
126 * we have some direct and some indirect access; it doesn't matter here.
128 num_direct_uniforms
= 0;
130 nir_assign_var_locations_scalar(&nir
->inputs
, &nir
->num_inputs
);
131 nir_assign_var_locations_scalar(&nir
->outputs
, &nir
->num_outputs
);
134 nir_validate_shader(nir
);
136 nir_remove_dead_variables(nir
);
137 nir_validate_shader(nir
);
140 nir_lower_samplers(nir
, shader_prog
, shader
->base
.Program
);
141 nir_validate_shader(nir
);
144 nir_lower_system_values(nir
);
145 nir_validate_shader(nir
);
147 nir_lower_atomics(nir
);
148 nir_validate_shader(nir
);
152 nir_opt_algebraic_late(nir
);
153 nir_validate_shader(nir
);
155 nir_lower_locals_to_regs(nir
);
156 nir_validate_shader(nir
);
158 nir_lower_to_source_mods(nir
);
159 nir_validate_shader(nir
);
161 nir_validate_shader(nir
);
163 if (unlikely(debug_enabled
)) {
164 fprintf(stderr
, "NIR (SSA form) for %s shader:\n", stage_name
);
165 nir_print_shader(nir
, stderr
);
168 if (dispatch_width
== 8) {
169 static GLuint msg_id
= 0;
170 _mesa_gl_debug(&brw
->ctx
, &msg_id
,
171 MESA_DEBUG_SOURCE_SHADER_COMPILER
,
172 MESA_DEBUG_TYPE_OTHER
,
173 MESA_DEBUG_SEVERITY_NOTIFICATION
,
174 "%s NIR shader: %d inst\n",
176 count_nir_instrs(nir
));
179 nir_convert_from_ssa(nir
);
180 nir_validate_shader(nir
);
182 /* This is the last pass we run before we start emitting stuff. It
183 * determines when we need to insert boolean resolves on Gen <= 5. We
184 * run it last because it stashes data in instr->pass_flags and we don't
185 * want that to be squashed by other NIR passes.
188 brw_nir_analyze_boolean_resolves(nir
);
190 /* emit the arrays used for inputs and outputs - load/store intrinsics will
191 * be converted to reads/writes of these arrays
194 if (nir
->num_inputs
> 0) {
195 nir_inputs
= vgrf(nir
->num_inputs
);
196 nir_setup_inputs(nir
);
199 if (nir
->num_outputs
> 0) {
200 nir_outputs
= vgrf(nir
->num_outputs
);
201 nir_setup_outputs(nir
);
204 if (nir
->num_uniforms
> 0) {
205 nir_setup_uniforms(nir
);
208 nir_emit_system_values(nir
);
210 nir_globals
= ralloc_array(mem_ctx
, fs_reg
, nir
->reg_alloc
);
211 foreach_list_typed(nir_register
, reg
, node
, &nir
->registers
) {
212 unsigned array_elems
=
213 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
214 unsigned size
= array_elems
* reg
->num_components
;
215 nir_globals
[reg
->index
] = vgrf(size
);
218 /* get the main function and emit it */
219 nir_foreach_overload(nir
, overload
) {
220 assert(strcmp(overload
->function
->name
, "main") == 0);
221 assert(overload
->impl
);
222 nir_emit_impl(overload
->impl
);
225 if (unlikely(debug_enabled
)) {
226 fprintf(stderr
, "NIR (final form) for %s shader:\n", stage_name
);
227 nir_print_shader(nir
, stderr
);
234 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
236 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
237 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
238 fs_reg input
= offset(nir_inputs
, var
->data
.driver_location
);
242 case MESA_SHADER_VERTEX
: {
243 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
244 * stored in nir_variable::location.
246 * However, NIR's load_input intrinsics use a different index - an
247 * offset into a single contiguous array containing all inputs.
248 * This index corresponds to the nir_variable::driver_location field.
250 * So, we need to copy from fs_reg(ATTR, var->location) to
251 * offset(nir_inputs, var->data.driver_location).
253 unsigned components
= var
->type
->without_array()->components();
254 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
255 for (unsigned i
= 0; i
< array_length
; i
++) {
256 for (unsigned j
= 0; j
< components
; j
++) {
257 emit(MOV(retype(offset(input
, components
* i
+ j
), type
),
258 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
), j
)));
263 case MESA_SHADER_GEOMETRY
:
264 case MESA_SHADER_COMPUTE
:
265 unreachable("fs_visitor not used for these stages yet.");
267 case MESA_SHADER_FRAGMENT
:
268 if (var
->data
.location
== VARYING_SLOT_POS
) {
269 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
270 var
->data
.origin_upper_left
);
271 emit_percomp(MOV(input
, reg
), 0xF);
273 emit_general_interpolation(input
, var
->name
, var
->type
,
274 (glsl_interp_qualifier
) var
->data
.interpolation
,
275 var
->data
.location
, var
->data
.centroid
,
284 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
286 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
288 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
289 fs_reg reg
= offset(nir_outputs
, var
->data
.driver_location
);
291 int vector_elements
=
292 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
293 : var
->type
->vector_elements
;
295 if (stage
== MESA_SHADER_VERTEX
) {
296 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
297 int output
= var
->data
.location
+ i
;
298 this->outputs
[output
] = offset(reg
, 4 * i
);
299 this->output_components
[output
] = vector_elements
;
301 } else if (var
->data
.index
> 0) {
302 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
303 assert(var
->data
.index
== 1);
304 this->dual_src_output
= reg
;
305 this->do_dual_src
= true;
306 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
307 /* Writing gl_FragColor outputs to all color regions. */
308 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
309 this->outputs
[i
] = reg
;
310 this->output_components
[i
] = 4;
312 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
313 this->frag_depth
= reg
;
314 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
315 this->sample_mask
= reg
;
317 /* gl_FragData or a user-defined FS output */
318 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
319 var
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
321 /* General color output. */
322 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
323 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
324 this->outputs
[output
] = offset(reg
, vector_elements
* i
);
325 this->output_components
[output
] = vector_elements
;
332 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
334 uniforms
= shader
->num_uniforms
;
336 /* We split the uniform register file in half. The first half is
337 * entirely direct uniforms. The second half is indirect.
339 param_size
[0] = num_direct_uniforms
;
340 if (shader
->num_uniforms
> num_direct_uniforms
)
341 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
343 if (dispatch_width
!= 8)
347 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
348 /* UBO's and atomics don't take up space in the uniform file */
349 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
352 if (strncmp(var
->name
, "gl_", 3) == 0)
353 nir_setup_builtin_uniform(var
);
355 nir_setup_uniform(var
);
358 /* prog_to_nir doesn't create uniform variables; set param up directly. */
359 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
360 for (unsigned int i
= 0; i
< 4; i
++) {
361 stage_prog_data
->param
[4 * p
+ i
] =
362 &prog
->Parameters
->ParameterValues
[p
][i
];
369 fs_visitor::nir_setup_uniform(nir_variable
*var
)
371 int namelen
= strlen(var
->name
);
373 /* The data for our (non-builtin) uniforms is stored in a series of
374 * gl_uniform_driver_storage structs for each subcomponent that
375 * glGetUniformLocation() could name. We know it's been set up in the
376 * same order we'd walk the type, so walk the list of storage and find
377 * anything with our name, or the prefix of a component that starts with
380 unsigned index
= var
->data
.driver_location
;
381 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
382 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
384 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
385 (storage
->name
[namelen
] != 0 &&
386 storage
->name
[namelen
] != '.' &&
387 storage
->name
[namelen
] != '[')) {
391 unsigned slots
= storage
->type
->component_slots();
392 if (storage
->array_elements
)
393 slots
*= storage
->array_elements
;
395 for (unsigned i
= 0; i
< slots
; i
++) {
396 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
400 /* Make sure we actually initialized the right amount of stuff here. */
401 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
405 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
407 const nir_state_slot
*const slots
= var
->state_slots
;
408 assert(var
->state_slots
!= NULL
);
410 unsigned uniform_index
= var
->data
.driver_location
;
411 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
412 /* This state reference has already been setup by ir_to_mesa, but we'll
413 * get the same index back here.
415 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
416 (gl_state_index
*)slots
[i
].tokens
);
418 /* Add each of the unique swizzles of the element as a parameter.
419 * This'll end up matching the expected layout of the
420 * array/matrix/structure we're trying to fill in.
423 for (unsigned int j
= 0; j
< 4; j
++) {
424 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
425 if (swiz
== last_swiz
)
429 stage_prog_data
->param
[uniform_index
++] =
430 &prog
->Parameters
->ParameterValues
[index
][swiz
];
436 emit_system_values_block(nir_block
*block
, void *void_visitor
)
438 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
441 nir_foreach_instr(block
, instr
) {
442 if (instr
->type
!= nir_instr_type_intrinsic
)
445 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
446 switch (intrin
->intrinsic
) {
447 case nir_intrinsic_load_vertex_id
:
448 unreachable("should be lowered by lower_vertex_id().");
450 case nir_intrinsic_load_vertex_id_zero_base
:
451 assert(v
->stage
== MESA_SHADER_VERTEX
);
452 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
453 if (reg
->file
== BAD_FILE
)
454 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
457 case nir_intrinsic_load_base_vertex
:
458 assert(v
->stage
== MESA_SHADER_VERTEX
);
459 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
460 if (reg
->file
== BAD_FILE
)
461 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
464 case nir_intrinsic_load_instance_id
:
465 assert(v
->stage
== MESA_SHADER_VERTEX
);
466 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
467 if (reg
->file
== BAD_FILE
)
468 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
471 case nir_intrinsic_load_sample_pos
:
472 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
473 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
474 if (reg
->file
== BAD_FILE
)
475 *reg
= *v
->emit_samplepos_setup();
478 case nir_intrinsic_load_sample_id
:
479 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
480 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
481 if (reg
->file
== BAD_FILE
)
482 *reg
= *v
->emit_sampleid_setup();
485 case nir_intrinsic_load_sample_mask_in
:
486 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
487 assert(v
->brw
->gen
>= 7);
488 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
489 if (reg
->file
== BAD_FILE
)
490 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
491 BRW_REGISTER_TYPE_D
));
503 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
505 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
506 nir_foreach_overload(shader
, overload
) {
507 assert(strcmp(overload
->function
->name
, "main") == 0);
508 assert(overload
->impl
);
509 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
514 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
516 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
517 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
518 unsigned array_elems
=
519 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
520 unsigned size
= array_elems
* reg
->num_components
;
521 nir_locals
[reg
->index
] = vgrf(size
);
524 nir_emit_cf_list(&impl
->body
);
528 fs_visitor::nir_emit_cf_list(exec_list
*list
)
530 exec_list_validate(list
);
531 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
532 switch (node
->type
) {
534 nir_emit_if(nir_cf_node_as_if(node
));
537 case nir_cf_node_loop
:
538 nir_emit_loop(nir_cf_node_as_loop(node
));
541 case nir_cf_node_block
:
542 nir_emit_block(nir_cf_node_as_block(node
));
546 unreachable("Invalid CFG node block");
552 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
554 /* first, put the condition into f0 */
555 fs_inst
*inst
= emit(MOV(reg_null_d
,
556 retype(get_nir_src(if_stmt
->condition
),
557 BRW_REGISTER_TYPE_D
)));
558 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
560 emit(IF(BRW_PREDICATE_NORMAL
));
562 nir_emit_cf_list(&if_stmt
->then_list
);
564 /* note: if the else is empty, dead CF elimination will remove it */
565 emit(BRW_OPCODE_ELSE
);
567 nir_emit_cf_list(&if_stmt
->else_list
);
569 emit(BRW_OPCODE_ENDIF
);
571 if (!try_replace_with_sel() && brw
->gen
< 6) {
572 no16("Can't support (non-uniform) control flow on SIMD16\n");
577 fs_visitor::nir_emit_loop(nir_loop
*loop
)
580 no16("Can't support (non-uniform) control flow on SIMD16\n");
585 nir_emit_cf_list(&loop
->body
);
587 emit(BRW_OPCODE_WHILE
);
591 fs_visitor::nir_emit_block(nir_block
*block
)
593 nir_foreach_instr(block
, instr
) {
594 nir_emit_instr(instr
);
599 fs_visitor::nir_emit_instr(nir_instr
*instr
)
601 switch (instr
->type
) {
602 case nir_instr_type_alu
:
603 nir_emit_alu(nir_instr_as_alu(instr
));
606 case nir_instr_type_intrinsic
:
607 nir_emit_intrinsic(nir_instr_as_intrinsic(instr
));
610 case nir_instr_type_tex
:
611 nir_emit_texture(nir_instr_as_tex(instr
));
614 case nir_instr_type_load_const
:
615 /* We can hit these, but we do nothing now and use them as
620 case nir_instr_type_jump
:
621 nir_emit_jump(nir_instr_as_jump(instr
));
625 unreachable("unknown instruction type");
630 brw_type_for_nir_type(nir_alu_type type
)
633 case nir_type_unsigned
:
634 return BRW_REGISTER_TYPE_UD
;
637 return BRW_REGISTER_TYPE_D
;
639 return BRW_REGISTER_TYPE_F
;
641 unreachable("unknown type");
644 return BRW_REGISTER_TYPE_F
;
648 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
649 const fs_reg
&result
)
651 if (instr
->src
[0].src
.is_ssa
||
652 !instr
->src
[0].src
.reg
.reg
||
653 !instr
->src
[0].src
.reg
.reg
->parent_instr
)
656 if (instr
->src
[0].src
.reg
.reg
->parent_instr
->type
!=
657 nir_instr_type_intrinsic
)
660 nir_intrinsic_instr
*src0
=
661 nir_instr_as_intrinsic(instr
->src
[0].src
.reg
.reg
->parent_instr
);
663 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
666 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
667 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
670 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
671 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
674 fs_reg tmp
= vgrf(glsl_type::int_type
);
677 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
678 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
680 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
682 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
683 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
685 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
687 * This negation looks like it's safe in practice, because bits 0:4 will
688 * surely be TRIANGLES
691 if (value1
->f
[0] == -1.0f
) {
695 tmp
.type
= BRW_REGISTER_TYPE_W
;
696 tmp
.subreg_offset
= 2;
699 fs_inst
*or_inst
= emit(OR(tmp
, g0
, fs_reg(0x3f80)));
700 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
702 tmp
.type
= BRW_REGISTER_TYPE_D
;
703 tmp
.subreg_offset
= 0;
706 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
707 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
709 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
711 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
712 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
714 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
716 * This negation looks like it's safe in practice, because bits 0:4 will
717 * surely be TRIANGLES
720 if (value1
->f
[0] == -1.0f
) {
724 emit(OR(tmp
, g1_6
, fs_reg(0x3f800000)));
726 emit(AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000)));
732 fs_visitor::nir_emit_alu(nir_alu_instr
*instr
)
734 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
737 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
738 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
741 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
742 op
[i
] = get_nir_src(instr
->src
[i
].src
);
743 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
744 op
[i
].abs
= instr
->src
[i
].abs
;
745 op
[i
].negate
= instr
->src
[i
].negate
;
748 /* We get a bunch of mov's out of the from_ssa pass and they may still
749 * be vectorized. We'll handle them as a special-case. We'll also
750 * handle vecN here because it's basically the same thing.
758 fs_reg temp
= result
;
759 bool need_extra_copy
= false;
760 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
761 if (!instr
->src
[i
].src
.is_ssa
&&
762 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
763 need_extra_copy
= true;
764 temp
= retype(vgrf(4), result
.type
);
769 for (unsigned i
= 0; i
< 4; i
++) {
770 if (!(instr
->dest
.write_mask
& (1 << i
)))
773 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
774 inst
= emit(MOV(offset(temp
, i
),
775 offset(op
[0], instr
->src
[0].swizzle
[i
])));
777 inst
= emit(MOV(offset(temp
, i
),
778 offset(op
[i
], instr
->src
[i
].swizzle
[0])));
780 inst
->saturate
= instr
->dest
.saturate
;
783 /* In this case the source and destination registers were the same,
784 * so we need to insert an extra set of moves in order to deal with
787 if (need_extra_copy
) {
788 for (unsigned i
= 0; i
< 4; i
++) {
789 if (!(instr
->dest
.write_mask
& (1 << i
)))
792 emit(MOV(offset(result
, i
), offset(temp
, i
)));
801 /* At this point, we have dealt with any instruction that operates on
802 * more than a single channel. Therefore, we can just adjust the source
803 * and destination registers for that channel and emit the instruction.
805 unsigned channel
= 0;
806 if (nir_op_infos
[instr
->op
].output_size
== 0) {
807 /* Since NIR is doing the scalarizing for us, we should only ever see
808 * vectorized operations with a single channel.
810 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
811 channel
= ffs(instr
->dest
.write_mask
) - 1;
813 result
= offset(result
, channel
);
816 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
817 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
818 op
[i
] = offset(op
[i
], instr
->src
[i
].swizzle
[channel
]);
824 inst
= emit(MOV(result
, op
[0]));
825 inst
->saturate
= instr
->dest
.saturate
;
830 emit(MOV(result
, op
[0]));
834 /* AND(val, 0x80000000) gives the sign bit.
836 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
839 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
841 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
842 op
[0].type
= BRW_REGISTER_TYPE_UD
;
843 result
.type
= BRW_REGISTER_TYPE_UD
;
844 emit(AND(result_int
, op
[0], fs_reg(0x80000000u
)));
846 inst
= emit(OR(result_int
, result_int
, fs_reg(0x3f800000u
)));
847 inst
->predicate
= BRW_PREDICATE_NORMAL
;
848 if (instr
->dest
.saturate
) {
849 inst
= emit(MOV(result
, result
));
850 inst
->saturate
= true;
856 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
857 * -> non-negative val generates 0x00000000.
858 * Predicated OR sets 1 if val is positive.
860 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
861 emit(ASR(result
, op
[0], fs_reg(31)));
862 inst
= emit(OR(result
, result
, fs_reg(1)));
863 inst
->predicate
= BRW_PREDICATE_NORMAL
;
867 inst
= emit_math(SHADER_OPCODE_RCP
, result
, op
[0]);
868 inst
->saturate
= instr
->dest
.saturate
;
872 inst
= emit_math(SHADER_OPCODE_EXP2
, result
, op
[0]);
873 inst
->saturate
= instr
->dest
.saturate
;
877 inst
= emit_math(SHADER_OPCODE_LOG2
, result
, op
[0]);
878 inst
->saturate
= instr
->dest
.saturate
;
883 unreachable("not reached: should be handled by ir_explog_to_explog2");
886 case nir_op_fsin_reduced
:
887 inst
= emit_math(SHADER_OPCODE_SIN
, result
, op
[0]);
888 inst
->saturate
= instr
->dest
.saturate
;
892 case nir_op_fcos_reduced
:
893 inst
= emit_math(SHADER_OPCODE_COS
, result
, op
[0]);
894 inst
->saturate
= instr
->dest
.saturate
;
898 if (fs_key
->high_quality_derivatives
) {
899 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
901 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
905 case nir_op_fddx_fine
:
906 inst
= emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
909 case nir_op_fddx_coarse
:
910 inst
= emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
911 inst
->saturate
= instr
->dest
.saturate
;
914 if (fs_key
->high_quality_derivatives
) {
915 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
916 fs_reg(fs_key
->render_to_fbo
));
918 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
919 fs_reg(fs_key
->render_to_fbo
));
921 inst
->saturate
= instr
->dest
.saturate
;
923 case nir_op_fddy_fine
:
924 inst
= emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
925 fs_reg(fs_key
->render_to_fbo
));
926 inst
->saturate
= instr
->dest
.saturate
;
928 case nir_op_fddy_coarse
:
929 inst
= emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
930 fs_reg(fs_key
->render_to_fbo
));
931 inst
->saturate
= instr
->dest
.saturate
;
936 inst
= emit(ADD(result
, op
[0], op
[1]));
937 inst
->saturate
= instr
->dest
.saturate
;
941 inst
= emit(MUL(result
, op
[0], op
[1]));
942 inst
->saturate
= instr
->dest
.saturate
;
947 emit(MUL(result
, op
[0], op
[1]));
950 nir_const_value
*value0
= nir_src_as_const_value(instr
->src
[0].src
);
951 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
953 if (value0
&& value0
->u
[0] < (1 << 16)) {
955 emit(MUL(result
, op
[0], op
[1]));
957 emit(MUL(result
, op
[1], op
[0]));
960 } else if (value1
&& value1
->u
[0] < (1 << 16)) {
962 emit(MUL(result
, op
[1], op
[0]));
964 emit(MUL(result
, op
[0], op
[1]));
971 no16("SIMD16 explicit accumulator operands unsupported\n");
973 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
975 emit(MUL(acc
, op
[0], op
[1]));
976 emit(MACH(reg_null_d
, op
[0], op
[1]));
977 emit(MOV(result
, fs_reg(acc
)));
981 case nir_op_imul_high
:
982 case nir_op_umul_high
: {
984 no16("SIMD16 explicit accumulator operands unsupported\n");
986 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
988 emit(MUL(acc
, op
[0], op
[1]));
989 emit(MACH(result
, op
[0], op
[1]));
995 emit_math(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
998 case nir_op_uadd_carry
: {
1000 no16("SIMD16 explicit accumulator operands unsupported\n");
1002 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
1003 BRW_REGISTER_TYPE_UD
);
1005 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
1006 emit(MOV(result
, fs_reg(acc
)));
1010 case nir_op_usub_borrow
: {
1012 no16("SIMD16 explicit accumulator operands unsupported\n");
1014 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
1015 BRW_REGISTER_TYPE_UD
);
1017 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
1018 emit(MOV(result
, fs_reg(acc
)));
1023 emit_math(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
1029 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1035 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
1040 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
));
1045 emit(CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
));
1049 if (brw
->gen
>= 8) {
1050 resolve_source_modifiers(&op
[0]);
1052 emit(NOT(result
, op
[0]));
1055 if (brw
->gen
>= 8) {
1056 resolve_source_modifiers(&op
[0]);
1057 resolve_source_modifiers(&op
[1]);
1059 emit(XOR(result
, op
[0], op
[1]));
1062 if (brw
->gen
>= 8) {
1063 resolve_source_modifiers(&op
[0]);
1064 resolve_source_modifiers(&op
[1]);
1066 emit(OR(result
, op
[0], op
[1]));
1069 if (brw
->gen
>= 8) {
1070 resolve_source_modifiers(&op
[0]);
1071 resolve_source_modifiers(&op
[1]);
1073 emit(AND(result
, op
[0], op
[1]));
1085 case nir_op_ball_fequal2
:
1086 case nir_op_ball_iequal2
:
1087 case nir_op_ball_fequal3
:
1088 case nir_op_ball_iequal3
:
1089 case nir_op_ball_fequal4
:
1090 case nir_op_ball_iequal4
:
1091 case nir_op_bany_fnequal2
:
1092 case nir_op_bany_inequal2
:
1093 case nir_op_bany_fnequal3
:
1094 case nir_op_bany_inequal3
:
1095 case nir_op_bany_fnequal4
:
1096 case nir_op_bany_inequal4
:
1097 unreachable("Lowered by nir_lower_alu_reductions");
1099 case nir_op_fnoise1_1
:
1100 case nir_op_fnoise1_2
:
1101 case nir_op_fnoise1_3
:
1102 case nir_op_fnoise1_4
:
1103 case nir_op_fnoise2_1
:
1104 case nir_op_fnoise2_2
:
1105 case nir_op_fnoise2_3
:
1106 case nir_op_fnoise2_4
:
1107 case nir_op_fnoise3_1
:
1108 case nir_op_fnoise3_2
:
1109 case nir_op_fnoise3_3
:
1110 case nir_op_fnoise3_4
:
1111 case nir_op_fnoise4_1
:
1112 case nir_op_fnoise4_2
:
1113 case nir_op_fnoise4_3
:
1114 case nir_op_fnoise4_4
:
1115 unreachable("not reached: should be handled by lower_noise");
1118 unreachable("not reached: should be handled by ldexp_to_arith()");
1121 inst
= emit_math(SHADER_OPCODE_SQRT
, result
, op
[0]);
1122 inst
->saturate
= instr
->dest
.saturate
;
1126 inst
= emit_math(SHADER_OPCODE_RSQ
, result
, op
[0]);
1127 inst
->saturate
= instr
->dest
.saturate
;
1131 emit(AND(result
, op
[0], fs_reg(1)));
1134 emit(AND(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0], fs_reg(0x3f800000u
)));
1138 emit(CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
1141 emit(CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1145 inst
= emit(RNDZ(result
, op
[0]));
1146 inst
->saturate
= instr
->dest
.saturate
;
1149 case nir_op_fceil
: {
1150 op
[0].negate
= !op
[0].negate
;
1151 fs_reg temp
= vgrf(glsl_type::float_type
);
1152 emit(RNDD(temp
, op
[0]));
1154 inst
= emit(MOV(result
, temp
));
1155 inst
->saturate
= instr
->dest
.saturate
;
1159 inst
= emit(RNDD(result
, op
[0]));
1160 inst
->saturate
= instr
->dest
.saturate
;
1163 inst
= emit(FRC(result
, op
[0]));
1164 inst
->saturate
= instr
->dest
.saturate
;
1166 case nir_op_fround_even
:
1167 inst
= emit(RNDE(result
, op
[0]));
1168 inst
->saturate
= instr
->dest
.saturate
;
1174 if (brw
->gen
>= 6) {
1175 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1176 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1178 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_L
));
1179 inst
= emit(SEL(result
, op
[0], op
[1]));
1180 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1182 inst
->saturate
= instr
->dest
.saturate
;
1188 if (brw
->gen
>= 6) {
1189 inst
= emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1190 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1192 emit(CMP(reg_null_d
, op
[0], op
[1], BRW_CONDITIONAL_GE
));
1193 inst
= emit(SEL(result
, op
[0], op
[1]));
1194 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1196 inst
->saturate
= instr
->dest
.saturate
;
1199 case nir_op_pack_snorm_2x16
:
1200 case nir_op_pack_snorm_4x8
:
1201 case nir_op_pack_unorm_2x16
:
1202 case nir_op_pack_unorm_4x8
:
1203 case nir_op_unpack_snorm_2x16
:
1204 case nir_op_unpack_snorm_4x8
:
1205 case nir_op_unpack_unorm_2x16
:
1206 case nir_op_unpack_unorm_4x8
:
1207 case nir_op_unpack_half_2x16
:
1208 case nir_op_pack_half_2x16
:
1209 unreachable("not reached: should be handled by lower_packing_builtins");
1211 case nir_op_unpack_half_2x16_split_x
:
1212 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1213 inst
->saturate
= instr
->dest
.saturate
;
1215 case nir_op_unpack_half_2x16_split_y
:
1216 inst
= emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1217 inst
->saturate
= instr
->dest
.saturate
;
1221 inst
= emit_math(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1222 inst
->saturate
= instr
->dest
.saturate
;
1225 case nir_op_bitfield_reverse
:
1226 emit(BFREV(result
, op
[0]));
1229 case nir_op_bit_count
:
1230 emit(CBIT(result
, op
[0]));
1233 case nir_op_ufind_msb
:
1234 case nir_op_ifind_msb
: {
1235 emit(FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]));
1237 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1238 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1239 * subtract the result from 31 to convert the MSB count into an LSB count.
1242 emit(CMP(reg_null_d
, result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
1243 fs_reg
neg_result(result
);
1244 neg_result
.negate
= true;
1245 inst
= emit(ADD(result
, neg_result
, fs_reg(31)));
1246 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1250 case nir_op_find_lsb
:
1251 emit(FBL(result
, op
[0]));
1254 case nir_op_ubitfield_extract
:
1255 case nir_op_ibitfield_extract
:
1256 emit(BFE(result
, op
[2], op
[1], op
[0]));
1259 emit(BFI1(result
, op
[0], op
[1]));
1262 emit(BFI2(result
, op
[0], op
[1], op
[2]));
1265 case nir_op_bitfield_insert
:
1266 unreachable("not reached: should be handled by "
1267 "lower_instructions::bitfield_insert_to_bfm_bfi");
1270 emit(SHL(result
, op
[0], op
[1]));
1273 emit(ASR(result
, op
[0], op
[1]));
1276 emit(SHR(result
, op
[0], op
[1]));
1279 case nir_op_pack_half_2x16_split
:
1280 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1284 inst
= emit(MAD(result
, op
[2], op
[1], op
[0]));
1285 inst
->saturate
= instr
->dest
.saturate
;
1289 inst
= emit_lrp(result
, op
[0], op
[1], op
[2]);
1290 inst
->saturate
= instr
->dest
.saturate
;
1294 if (optimize_frontfacing_ternary(instr
, result
))
1297 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
1298 inst
= emit(SEL(result
, op
[1], op
[2]));
1299 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1303 unreachable("unhandled instruction");
1306 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1307 * to sign extend the low bit to 0/~0
1309 if (brw
->gen
<= 5 &&
1310 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1311 fs_reg masked
= vgrf(glsl_type::int_type
);
1312 emit(AND(masked
, result
, fs_reg(1)));
1313 masked
.negate
= true;
1314 emit(MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
));
1319 fs_visitor::get_nir_src(nir_src src
)
1322 assert(src
.ssa
->parent_instr
->type
== nir_instr_type_load_const
);
1323 nir_load_const_instr
*load
= nir_instr_as_load_const(src
.ssa
->parent_instr
);
1324 fs_reg reg
= vgrf(src
.ssa
->num_components
);
1325 reg
.type
= BRW_REGISTER_TYPE_D
;
1327 for (unsigned i
= 0; i
< src
.ssa
->num_components
; ++i
)
1328 emit(MOV(offset(reg
, i
), fs_reg(load
->value
.i
[i
])));
1333 if (src
.reg
.reg
->is_global
)
1334 reg
= nir_globals
[src
.reg
.reg
->index
];
1336 reg
= nir_locals
[src
.reg
.reg
->index
];
1338 /* to avoid floating-point denorm flushing problems, set the type by
1339 * default to D - instructions that need floating point semantics will set
1340 * this to F if they need to
1342 reg
= retype(offset(reg
, src
.reg
.base_offset
), BRW_REGISTER_TYPE_D
);
1343 if (src
.reg
.indirect
) {
1344 reg
.reladdr
= new(mem_ctx
) fs_reg();
1345 *reg
.reladdr
= retype(get_nir_src(*src
.reg
.indirect
),
1346 BRW_REGISTER_TYPE_D
);
1354 fs_visitor::get_nir_dest(nir_dest dest
)
1357 if (dest
.reg
.reg
->is_global
)
1358 reg
= nir_globals
[dest
.reg
.reg
->index
];
1360 reg
= nir_locals
[dest
.reg
.reg
->index
];
1362 reg
= offset(reg
, dest
.reg
.base_offset
);
1363 if (dest
.reg
.indirect
) {
1364 reg
.reladdr
= new(mem_ctx
) fs_reg();
1365 *reg
.reladdr
= retype(get_nir_src(*dest
.reg
.indirect
),
1366 BRW_REGISTER_TYPE_D
);
1373 fs_visitor::emit_percomp(fs_inst
*inst
, unsigned wr_mask
)
1375 for (unsigned i
= 0; i
< 4; i
++) {
1376 if (!((wr_mask
>> i
) & 1))
1379 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(*inst
);
1380 new_inst
->dst
= offset(new_inst
->dst
, i
);
1381 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1382 if (inst
->src
[j
].file
== GRF
)
1383 new_inst
->src
[j
] = offset(new_inst
->src
[j
], i
);
1390 fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr
*instr
)
1393 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1394 dest
= get_nir_dest(instr
->dest
);
1396 bool has_indirect
= false;
1398 switch (instr
->intrinsic
) {
1399 case nir_intrinsic_discard
:
1400 case nir_intrinsic_discard_if
: {
1401 /* We track our discarded pixels in f0.1. By predicating on it, we can
1402 * update just the flag bits that aren't yet discarded. If there's no
1403 * condition, we emit a CMP of g0 != g0, so all currently executing
1404 * channels will get turned off.
1407 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1408 cmp
= emit(CMP(reg_null_f
, get_nir_src(instr
->src
[0]),
1409 fs_reg(0), BRW_CONDITIONAL_Z
));
1411 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1412 BRW_REGISTER_TYPE_UW
));
1413 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
, BRW_CONDITIONAL_NZ
));
1415 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1416 cmp
->flag_subreg
= 1;
1418 if (brw
->gen
>= 6) {
1419 emit_discard_jump();
1424 case nir_intrinsic_atomic_counter_inc
:
1425 case nir_intrinsic_atomic_counter_dec
:
1426 case nir_intrinsic_atomic_counter_read
: {
1427 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1428 (unsigned) instr
->const_index
[0];
1429 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1431 switch (instr
->intrinsic
) {
1432 case nir_intrinsic_atomic_counter_inc
:
1433 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1434 fs_reg(), fs_reg());
1436 case nir_intrinsic_atomic_counter_dec
:
1437 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1438 fs_reg(), fs_reg());
1440 case nir_intrinsic_atomic_counter_read
:
1441 emit_untyped_surface_read(surf_index
, dest
, offset
);
1444 unreachable("Unreachable");
1449 case nir_intrinsic_load_front_face
:
1450 emit(MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1451 *emit_frontfacing_interpolation()));
1454 case nir_intrinsic_load_vertex_id
:
1455 unreachable("should be lowered by lower_vertex_id()");
1457 case nir_intrinsic_load_vertex_id_zero_base
: {
1458 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1459 assert(vertex_id
.file
!= BAD_FILE
);
1460 dest
.type
= vertex_id
.type
;
1461 emit(MOV(dest
, vertex_id
));
1465 case nir_intrinsic_load_base_vertex
: {
1466 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1467 assert(base_vertex
.file
!= BAD_FILE
);
1468 dest
.type
= base_vertex
.type
;
1469 emit(MOV(dest
, base_vertex
));
1473 case nir_intrinsic_load_instance_id
: {
1474 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1475 assert(instance_id
.file
!= BAD_FILE
);
1476 dest
.type
= instance_id
.type
;
1477 emit(MOV(dest
, instance_id
));
1481 case nir_intrinsic_load_sample_mask_in
: {
1482 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1483 assert(sample_mask_in
.file
!= BAD_FILE
);
1484 dest
.type
= sample_mask_in
.type
;
1485 emit(MOV(dest
, sample_mask_in
));
1489 case nir_intrinsic_load_sample_pos
: {
1490 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1491 assert(sample_pos
.file
!= BAD_FILE
);
1492 dest
.type
= sample_pos
.type
;
1493 emit(MOV(dest
, sample_pos
));
1494 emit(MOV(offset(dest
, 1), offset(sample_pos
, 1)));
1498 case nir_intrinsic_load_sample_id
: {
1499 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1500 assert(sample_id
.file
!= BAD_FILE
);
1501 dest
.type
= sample_id
.type
;
1502 emit(MOV(dest
, sample_id
));
1506 case nir_intrinsic_load_uniform_indirect
:
1507 has_indirect
= true;
1508 case nir_intrinsic_load_uniform
: {
1509 unsigned index
= instr
->const_index
[0];
1512 if (index
< num_direct_uniforms
) {
1513 uniform_reg
= fs_reg(UNIFORM
, 0);
1515 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1516 index
-= num_direct_uniforms
;
1519 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1520 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1521 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), index
);
1523 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1526 emit(MOV(dest
, src
));
1527 dest
= offset(dest
, 1);
1533 case nir_intrinsic_load_ubo_indirect
:
1534 has_indirect
= true;
1536 case nir_intrinsic_load_ubo
: {
1537 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1541 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1544 /* The block index is not a constant. Evaluate the index expression
1545 * per-channel and add the base UBO index; the generator will select
1546 * a value from any live channel.
1548 surf_index
= vgrf(glsl_type::uint_type
);
1549 emit(ADD(surf_index
, get_nir_src(instr
->src
[0]),
1550 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
1551 ->force_writemask_all
= true;
1553 /* Assume this may touch any UBO. It would be nice to provide
1554 * a tighter bound, but the array information is already lowered away.
1556 brw_mark_surface_used(prog_data
,
1557 stage_prog_data
->binding_table
.ubo_start
+
1558 shader_prog
->NumUniformBlocks
- 1);
1562 /* Turn the byte offset into a dword offset. */
1563 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1564 emit(SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1565 BRW_REGISTER_TYPE_D
),
1568 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1569 for (int i
= 0; i
< instr
->num_components
; i
++)
1570 emit(VARYING_PULL_CONSTANT_LOAD(offset(dest
, i
), surf_index
,
1571 base_offset
, vec4_offset
+ i
));
1573 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1574 packed_consts
.type
= dest
.type
;
1576 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1577 emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1578 surf_index
, const_offset_reg
);
1580 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1581 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1583 /* The std140 packing rules don't allow vectors to cross 16-byte
1584 * boundaries, and a reg is 32 bytes.
1586 assert(packed_consts
.subreg_offset
< 32);
1588 emit(MOV(dest
, packed_consts
));
1589 dest
= offset(dest
, 1);
1595 case nir_intrinsic_load_input_indirect
:
1596 has_indirect
= true;
1598 case nir_intrinsic_load_input
: {
1600 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1601 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1602 fs_reg src
= offset(retype(nir_inputs
, dest
.type
),
1603 instr
->const_index
[0] + index
);
1605 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1608 emit(MOV(dest
, src
));
1609 dest
= offset(dest
, 1);
1615 /* Handle ARB_gpu_shader5 interpolation intrinsics
1617 * It's worth a quick word of explanation as to why we handle the full
1618 * variable-based interpolation intrinsic rather than a lowered version
1619 * with like we do for other inputs. We have to do that because the way
1620 * we set up inputs doesn't allow us to use the already setup inputs for
1621 * interpolation. At the beginning of the shader, we go through all of
1622 * the input variables and do the initial interpolation and put it in
1623 * the nir_inputs array based on its location as determined in
1624 * nir_lower_io. If the input isn't used, dead code cleans up and
1625 * everything works fine. However, when we get to the ARB_gpu_shader5
1626 * interpolation intrinsics, we need to reinterpolate the input
1627 * differently. If we used an intrinsic that just had an index it would
1628 * only give us the offset into the nir_inputs array. However, this is
1629 * useless because that value is post-interpolation and we need
1630 * pre-interpolation. In order to get the actual location of the bits
1631 * we get from the vertex fetching hardware, we need the variable.
1633 case nir_intrinsic_interp_var_at_centroid
:
1634 case nir_intrinsic_interp_var_at_sample
:
1635 case nir_intrinsic_interp_var_at_offset
: {
1636 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
1637 * 8 channels at a time, same as the barycentric coords presented in
1638 * the FS payload. this requires a bit of extra work to support.
1640 no16("interpolate_at_* not yet supported in SIMD16 mode.");
1642 fs_reg dst_x
= vgrf(2);
1643 fs_reg dst_y
= offset(dst_x
, 1);
1645 /* For most messages, we need one reg of ignored data; the hardware
1646 * requires mlen==1 even when there is no payload. in the per-slot
1647 * offset case, we'll replace this with the proper source data.
1649 fs_reg src
= vgrf(glsl_type::float_type
);
1650 int mlen
= 1; /* one reg unless overriden */
1653 switch (instr
->intrinsic
) {
1654 case nir_intrinsic_interp_var_at_centroid
:
1655 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
1658 case nir_intrinsic_interp_var_at_sample
: {
1659 /* XXX: We should probably handle non-constant sample id's */
1660 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1661 assert(const_sample
);
1662 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1663 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
,
1668 case nir_intrinsic_interp_var_at_offset
: {
1669 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1672 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1673 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1675 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
1676 fs_reg(off_x
| (off_y
<< 4)));
1678 src
= vgrf(glsl_type::ivec2_type
);
1679 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1680 BRW_REGISTER_TYPE_F
);
1681 for (int i
= 0; i
< 2; i
++) {
1682 fs_reg temp
= vgrf(glsl_type::float_type
);
1683 emit(MUL(temp
, offset(offset_src
, i
), fs_reg(16.0f
)));
1684 fs_reg itemp
= vgrf(glsl_type::int_type
);
1685 emit(MOV(itemp
, temp
)); /* float to int */
1687 /* Clamp the upper end of the range to +7/16.
1688 * ARB_gpu_shader5 requires that we support a maximum offset
1689 * of +0.5, which isn't representable in a S0.4 value -- if
1690 * we didn't clamp it, we'd end up with -8/16, which is the
1691 * opposite of what the shader author wanted.
1693 * This is legal due to ARB_gpu_shader5's quantization
1696 * "Not all values of <offset> may be supported; x and y
1697 * offsets may be rounded to fixed-point values with the
1698 * number of fraction bits given by the
1699 * implementation-dependent constant
1700 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1703 emit(BRW_OPCODE_SEL
, offset(src
, i
), itemp
, fs_reg(7))
1704 ->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
1708 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
1715 unreachable("Invalid intrinsic");
1719 inst
->regs_written
= 2; /* 2 floats per slot returned */
1720 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1721 INTERP_QUALIFIER_NOPERSPECTIVE
;
1723 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1724 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1725 src
.type
= dest
.type
;
1727 emit(FS_OPCODE_LINTERP
, dest
, dst_x
, dst_y
, src
);
1728 dest
= offset(dest
, 1);
1733 case nir_intrinsic_store_output_indirect
:
1734 has_indirect
= true;
1735 case nir_intrinsic_store_output
: {
1736 fs_reg src
= get_nir_src(instr
->src
[0]);
1738 for (int i
= 0; i
< instr
->const_index
[1]; i
++) {
1739 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1740 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
),
1741 instr
->const_index
[0] + index
);
1743 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1745 emit(MOV(new_dest
, src
));
1746 src
= offset(src
, 1);
1753 unreachable("unknown intrinsic");
1758 fs_visitor::nir_emit_texture(nir_tex_instr
*instr
)
1760 unsigned sampler
= instr
->sampler_index
;
1761 fs_reg
sampler_reg(sampler
);
1763 /* FINISHME: We're failing to recompile our programs when the sampler is
1764 * updated. This only matters for the texture rectangle scale parameters
1765 * (pre-gen6, or gen6+ with GL_CLAMP).
1767 int texunit
= prog
->SamplerUnits
[sampler
];
1769 int gather_component
= instr
->component
;
1771 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1773 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1776 int lod_components
= 0, offset_components
= 0;
1778 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1781 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1782 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1783 switch (instr
->src
[i
].src_type
) {
1784 case nir_tex_src_bias
:
1785 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1787 case nir_tex_src_comparitor
:
1788 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1790 case nir_tex_src_coord
:
1791 switch (instr
->op
) {
1793 case nir_texop_txf_ms
:
1794 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1797 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1801 case nir_tex_src_ddx
:
1802 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1803 lod_components
= nir_tex_instr_src_size(instr
, i
);
1805 case nir_tex_src_ddy
:
1806 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1808 case nir_tex_src_lod
:
1809 switch (instr
->op
) {
1811 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1814 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1817 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1821 case nir_tex_src_ms_index
:
1822 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1824 case nir_tex_src_offset
:
1825 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1826 if (instr
->is_array
)
1827 offset_components
= instr
->coord_components
- 1;
1829 offset_components
= instr
->coord_components
;
1831 case nir_tex_src_projector
:
1832 projector
= retype(src
, BRW_REGISTER_TYPE_F
);
1835 case nir_tex_src_sampler_offset
: {
1836 /* Figure out the highest possible sampler index and mark it as used */
1837 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1838 if (instr
->op
== nir_texop_tg4
&& brw
->gen
< 8) {
1839 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1841 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1843 brw_mark_surface_used(prog_data
, max_used
);
1845 /* Emit code to evaluate the actual indexing expression */
1846 sampler_reg
= vgrf(glsl_type::uint_type
);
1847 emit(ADD(sampler_reg
, src
, fs_reg(sampler
)))
1848 ->force_writemask_all
= true;
1853 unreachable("unknown texture source");
1857 if (projector
.file
!= BAD_FILE
) {
1858 fs_reg invproj
= vgrf(glsl_type::float_type
);
1859 emit_math(SHADER_OPCODE_RCP
, invproj
, projector
);
1860 for (int i
= 0; i
< 3; i
++)
1861 emit(MUL(offset(coordinate
, i
), offset(coordinate
, i
), invproj
));
1864 if (instr
->op
== nir_texop_txf_ms
) {
1865 if (brw
->gen
>= 7 &&
1866 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1867 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1873 for (unsigned i
= 0; i
< 3; i
++) {
1874 if (instr
->const_offset
[i
] != 0) {
1875 assert(offset_components
== 0);
1876 tex_offset
= fs_reg(brw_texture_offset(ctx
, instr
->const_offset
, 3));
1881 enum glsl_base_type dest_base_type
;
1882 switch (instr
->dest_type
) {
1883 case nir_type_float
:
1884 dest_base_type
= GLSL_TYPE_FLOAT
;
1887 dest_base_type
= GLSL_TYPE_INT
;
1889 case nir_type_unsigned
:
1890 dest_base_type
= GLSL_TYPE_UINT
;
1893 unreachable("bad type");
1896 const glsl_type
*dest_type
=
1897 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1900 ir_texture_opcode op
;
1901 switch (instr
->op
) {
1902 case nir_texop_lod
: op
= ir_lod
; break;
1903 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1904 case nir_texop_tex
: op
= ir_tex
; break;
1905 case nir_texop_tg4
: op
= ir_tg4
; break;
1906 case nir_texop_txb
: op
= ir_txb
; break;
1907 case nir_texop_txd
: op
= ir_txd
; break;
1908 case nir_texop_txf
: op
= ir_txf
; break;
1909 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1910 case nir_texop_txl
: op
= ir_txl
; break;
1911 case nir_texop_txs
: op
= ir_txs
; break;
1913 unreachable("unknown texture opcode");
1916 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1917 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1918 tex_offset
, mcs
, gather_component
,
1919 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1921 fs_reg dest
= get_nir_dest(instr
->dest
);
1922 dest
.type
= this->result
.type
;
1923 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1924 emit_percomp(MOV(dest
, this->result
), (1 << num_components
) - 1);
1928 fs_visitor::nir_emit_jump(nir_jump_instr
*instr
)
1930 switch (instr
->type
) {
1931 case nir_jump_break
:
1932 emit(BRW_OPCODE_BREAK
);
1934 case nir_jump_continue
:
1935 emit(BRW_OPCODE_CONTINUE
);
1937 case nir_jump_return
:
1939 unreachable("unknown jump");