2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
66 var
->data
.origin_upper_left
);
67 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
69 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
70 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
71 reg
.type
= BRW_REGISTER_TYPE_D
;
72 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
73 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
74 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
75 reg
.type
= BRW_REGISTER_TYPE_D
;
76 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
78 int location
= var
->data
.location
;
79 emit_general_interpolation(&input
, var
->name
, var
->type
,
80 (glsl_interp_qualifier
) var
->data
.interpolation
,
81 &location
, var
->data
.centroid
,
88 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
89 const glsl_type
*type
,
92 if (type
->is_array() || type
->is_matrix()) {
93 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
94 const unsigned length
= glsl_get_length(type
);
96 for (unsigned i
= 0; i
< length
; i
++) {
97 nir_setup_single_output_varying(reg
, elem_type
, location
);
99 } else if (type
->is_record()) {
100 for (unsigned i
= 0; i
< type
->length
; i
++) {
101 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
102 nir_setup_single_output_varying(reg
, field_type
, location
);
105 assert(type
->is_scalar() || type
->is_vector());
106 this->outputs
[*location
] = *reg
;
107 this->output_components
[*location
] = type
->vector_elements
;
108 *reg
= offset(*reg
, bld
, 4);
114 fs_visitor::nir_setup_outputs()
116 if (stage
== MESA_SHADER_TESS_CTRL
)
119 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
121 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
123 nir_foreach_variable(var
, &nir
->outputs
) {
124 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 case MESA_SHADER_VERTEX
:
128 case MESA_SHADER_TESS_EVAL
:
129 case MESA_SHADER_GEOMETRY
: {
130 unsigned location
= var
->data
.location
;
131 nir_setup_single_output_varying(®
, var
->type
, &location
);
134 case MESA_SHADER_FRAGMENT
:
135 if (key
->force_dual_color_blend
&&
136 var
->data
.location
== FRAG_RESULT_DATA1
) {
137 this->dual_src_output
= reg
;
138 this->do_dual_src
= true;
139 } else if (var
->data
.index
> 0) {
140 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
141 assert(var
->data
.index
== 1);
142 this->dual_src_output
= reg
;
143 this->do_dual_src
= true;
144 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
145 /* Writing gl_FragColor outputs to all color regions. */
146 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
147 this->outputs
[i
] = reg
;
148 this->output_components
[i
] = 4;
150 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
151 this->frag_depth
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
153 this->frag_stencil
= reg
;
154 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
155 this->sample_mask
= reg
;
157 int vector_elements
= var
->type
->without_array()->vector_elements
;
159 /* gl_FragData or a user-defined FS output */
160 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
161 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
163 /* General color output. */
164 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
165 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
166 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
167 this->output_components
[output
] = vector_elements
;
172 unreachable("unhandled shader stage");
178 fs_visitor::nir_setup_uniforms()
180 if (dispatch_width
!= 8)
183 uniforms
= nir
->num_uniforms
/ 4;
187 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
191 nir_foreach_instr(instr
, block
) {
192 if (instr
->type
!= nir_instr_type_intrinsic
)
195 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
196 switch (intrin
->intrinsic
) {
197 case nir_intrinsic_load_vertex_id
:
198 unreachable("should be lowered by lower_vertex_id().");
200 case nir_intrinsic_load_vertex_id_zero_base
:
201 assert(v
->stage
== MESA_SHADER_VERTEX
);
202 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
203 if (reg
->file
== BAD_FILE
)
204 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
207 case nir_intrinsic_load_base_vertex
:
208 assert(v
->stage
== MESA_SHADER_VERTEX
);
209 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
210 if (reg
->file
== BAD_FILE
)
211 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
214 case nir_intrinsic_load_instance_id
:
215 assert(v
->stage
== MESA_SHADER_VERTEX
);
216 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
217 if (reg
->file
== BAD_FILE
)
218 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
221 case nir_intrinsic_load_base_instance
:
222 assert(v
->stage
== MESA_SHADER_VERTEX
);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
228 case nir_intrinsic_load_draw_id
:
229 assert(v
->stage
== MESA_SHADER_VERTEX
);
230 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
231 if (reg
->file
== BAD_FILE
)
232 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
235 case nir_intrinsic_load_invocation_id
:
236 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
238 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
240 if (reg
->file
== BAD_FILE
) {
241 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
242 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
243 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
244 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
249 case nir_intrinsic_load_sample_pos
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
252 if (reg
->file
== BAD_FILE
)
253 *reg
= *v
->emit_samplepos_setup();
256 case nir_intrinsic_load_sample_id
:
257 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
258 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
259 if (reg
->file
== BAD_FILE
)
260 *reg
= *v
->emit_sampleid_setup();
263 case nir_intrinsic_load_sample_mask_in
:
264 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
265 assert(v
->devinfo
->gen
>= 7);
266 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
267 if (reg
->file
== BAD_FILE
)
268 *reg
= *v
->emit_samplemaskin_setup();
271 case nir_intrinsic_load_local_invocation_id
:
272 assert(v
->stage
== MESA_SHADER_COMPUTE
);
273 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
274 if (reg
->file
== BAD_FILE
)
275 *reg
= *v
->emit_cs_local_invocation_id_setup();
278 case nir_intrinsic_load_work_group_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_work_group_id_setup();
285 case nir_intrinsic_load_helper_invocation
:
286 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
288 if (reg
->file
== BAD_FILE
) {
289 const fs_builder abld
=
290 v
->bld
.annotate("gl_HelperInvocation", NULL
);
292 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
293 * pixel mask is in g1.7 of the thread payload.
295 * We move the per-channel pixel enable bit to the low bit of each
296 * channel by shifting the byte containing the pixel mask by the
297 * vector immediate 0x76543210UV.
299 * The region of <1,8,0> reads only 1 byte (the pixel masks for
300 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
301 * masks for 2 and 3) in SIMD16.
303 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
305 stride(byte_offset(retype(brw_vec1_grf(1, 0),
306 BRW_REGISTER_TYPE_UB
), 28),
308 brw_imm_uv(0x76543210));
310 /* A set bit in the pixel mask means the channel is enabled, but
311 * that is the opposite of gl_HelperInvocation so we need to invert
314 * The negate source-modifier bit of logical instructions on Gen8+
315 * performs 1's complement negation, so we can use that instead of
318 fs_reg inverted
= negate(shifted
);
319 if (v
->devinfo
->gen
< 8) {
320 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
321 abld
.NOT(inverted
, shifted
);
324 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
325 * with 1 and negating.
327 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
328 abld
.AND(anded
, inverted
, brw_imm_uw(1));
330 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
331 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
345 fs_visitor::nir_emit_system_values()
347 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
348 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
349 nir_system_values
[i
] = fs_reg();
352 nir_foreach_function(function
, nir
) {
353 assert(strcmp(function
->name
, "main") == 0);
354 assert(function
->impl
);
355 nir_foreach_block(block
, function
->impl
) {
356 emit_system_values_block(block
, this);
362 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
364 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
365 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
366 nir_locals
[i
] = fs_reg();
369 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
370 unsigned array_elems
=
371 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
372 unsigned size
= array_elems
* reg
->num_components
;
373 const brw_reg_type reg_type
=
374 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
375 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
378 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
381 nir_emit_cf_list(&impl
->body
);
385 fs_visitor::nir_emit_cf_list(exec_list
*list
)
387 exec_list_validate(list
);
388 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
389 switch (node
->type
) {
391 nir_emit_if(nir_cf_node_as_if(node
));
394 case nir_cf_node_loop
:
395 nir_emit_loop(nir_cf_node_as_loop(node
));
398 case nir_cf_node_block
:
399 nir_emit_block(nir_cf_node_as_block(node
));
403 unreachable("Invalid CFG node block");
409 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
411 /* first, put the condition into f0 */
412 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
413 retype(get_nir_src(if_stmt
->condition
),
414 BRW_REGISTER_TYPE_D
));
415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
417 bld
.IF(BRW_PREDICATE_NORMAL
);
419 nir_emit_cf_list(&if_stmt
->then_list
);
421 /* note: if the else is empty, dead CF elimination will remove it */
422 bld
.emit(BRW_OPCODE_ELSE
);
424 nir_emit_cf_list(&if_stmt
->else_list
);
426 bld
.emit(BRW_OPCODE_ENDIF
);
430 fs_visitor::nir_emit_loop(nir_loop
*loop
)
432 bld
.emit(BRW_OPCODE_DO
);
434 nir_emit_cf_list(&loop
->body
);
436 bld
.emit(BRW_OPCODE_WHILE
);
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
457 case nir_instr_type_intrinsic
:
459 case MESA_SHADER_VERTEX
:
460 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_TESS_CTRL
:
463 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_EVAL
:
466 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_GEOMETRY
:
469 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_FRAGMENT
:
472 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_COMPUTE
:
475 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 unreachable("unsupported shader stage");
482 case nir_instr_type_tex
:
483 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
486 case nir_instr_type_load_const
:
487 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
490 case nir_instr_type_ssa_undef
:
491 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
494 case nir_instr_type_jump
:
495 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
499 unreachable("unknown instruction type");
504 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
508 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
509 const fs_reg
&result
)
511 if (!instr
->src
[0].src
.is_ssa
||
512 !instr
->src
[0].src
.ssa
->parent_instr
)
515 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
518 nir_alu_instr
*src0
=
519 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
521 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
522 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
525 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
526 assert(element
!= NULL
);
528 enum opcode extract_op
;
529 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
530 assert(element
->u32
[0] <= 1);
531 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
533 assert(element
->u32
[0] <= 3);
534 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
537 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
538 op0
.type
= brw_type_for_nir_type(
539 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
540 nir_src_bit_size(src0
->src
[0].src
)));
541 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
543 set_saturate(instr
->dest
.saturate
,
544 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
549 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
550 const fs_reg
&result
)
552 if (!instr
->src
[0].src
.is_ssa
||
553 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
556 nir_intrinsic_instr
*src0
=
557 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
559 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
562 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
563 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
566 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
567 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
570 fs_reg tmp
= vgrf(glsl_type::int_type
);
572 if (devinfo
->gen
>= 6) {
573 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
574 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
576 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
578 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
579 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
581 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
583 * This negation looks like it's safe in practice, because bits 0:4 will
584 * surely be TRIANGLES
587 if (value1
->f32
[0] == -1.0f
) {
591 tmp
.type
= BRW_REGISTER_TYPE_W
;
592 tmp
.subreg_offset
= 2;
595 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
597 tmp
.type
= BRW_REGISTER_TYPE_D
;
598 tmp
.subreg_offset
= 0;
601 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
602 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
604 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
606 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
607 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
609 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
611 * This negation looks like it's safe in practice, because bits 0:4 will
612 * surely be TRIANGLES
615 if (value1
->f32
[0] == -1.0f
) {
619 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
621 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
627 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
629 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
632 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
633 result
.type
= brw_type_for_nir_type(
634 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
635 nir_dest_bit_size(instr
->dest
.dest
)));
638 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 op
[i
] = get_nir_src(instr
->src
[i
].src
);
640 op
[i
].type
= brw_type_for_nir_type(
641 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
642 nir_src_bit_size(instr
->src
[i
].src
)));
643 op
[i
].abs
= instr
->src
[i
].abs
;
644 op
[i
].negate
= instr
->src
[i
].negate
;
647 /* We get a bunch of mov's out of the from_ssa pass and they may still
648 * be vectorized. We'll handle them as a special-case. We'll also
649 * handle vecN here because it's basically the same thing.
657 fs_reg temp
= result
;
658 bool need_extra_copy
= false;
659 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
660 if (!instr
->src
[i
].src
.is_ssa
&&
661 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
662 need_extra_copy
= true;
663 temp
= bld
.vgrf(result
.type
, 4);
668 for (unsigned i
= 0; i
< 4; i
++) {
669 if (!(instr
->dest
.write_mask
& (1 << i
)))
672 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
673 inst
= bld
.MOV(offset(temp
, bld
, i
),
674 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
676 inst
= bld
.MOV(offset(temp
, bld
, i
),
677 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
679 inst
->saturate
= instr
->dest
.saturate
;
682 /* In this case the source and destination registers were the same,
683 * so we need to insert an extra set of moves in order to deal with
686 if (need_extra_copy
) {
687 for (unsigned i
= 0; i
< 4; i
++) {
688 if (!(instr
->dest
.write_mask
& (1 << i
)))
691 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
700 /* At this point, we have dealt with any instruction that operates on
701 * more than a single channel. Therefore, we can just adjust the source
702 * and destination registers for that channel and emit the instruction.
704 unsigned channel
= 0;
705 if (nir_op_infos
[instr
->op
].output_size
== 0) {
706 /* Since NIR is doing the scalarizing for us, we should only ever see
707 * vectorized operations with a single channel.
709 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
710 channel
= ffs(instr
->dest
.write_mask
) - 1;
712 result
= offset(result
, bld
, channel
);
715 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
716 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
717 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
723 if (optimize_extract_to_float(instr
, result
))
730 inst
= bld
.MOV(result
, op
[0]);
731 inst
->saturate
= instr
->dest
.saturate
;
736 bld
.MOV(result
, op
[0]);
740 if (type_sz(op
[0].type
) < 8) {
741 /* AND(val, 0x80000000) gives the sign bit.
743 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
746 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
748 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
749 op
[0].type
= BRW_REGISTER_TYPE_UD
;
750 result
.type
= BRW_REGISTER_TYPE_UD
;
751 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
753 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
754 inst
->predicate
= BRW_PREDICATE_NORMAL
;
755 if (instr
->dest
.saturate
) {
756 inst
= bld
.MOV(result
, result
);
757 inst
->saturate
= true;
760 /* For doubles we do the same but we need to consider:
762 * - 2-src instructions can't operate with 64-bit immediates
763 * - The sign is encoded in the high 32-bit of each DF
764 * - CMP with DF requires special handling in SIMD16
765 * - We need to produce a DF result.
768 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
769 * a register and compare with that.
771 fs_reg tmp
= vgrf(glsl_type::double_type
);
772 bld
.MOV(tmp
, brw_imm_df(0.0));
774 /* A direct DF CMP using the flag register (null dst) won't work in
775 * SIMD16 because the CMP will be split in two by lower_simd_width,
776 * resulting in two CMP instructions with the same dst (NULL),
777 * leading to dead code elimination of the first one. In SIMD8,
778 * however, there is no need to split the CMP and we can save some
781 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
782 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
784 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
785 * so we store the result of the comparison in a vgrf instead and
786 * then we generate a UD comparison from that that won't have to
787 * be split by lower_simd_width. This is what NIR does to handle
788 * double comparisons in the general case.
790 if (bld
.dispatch_width() == 16 ) {
791 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
792 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
793 bld
.CMP(bld
.null_reg_ud(),
794 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
797 /* Get the high 32-bit of each double component where the sign is */
798 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
799 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
801 /* Get the sign bit */
802 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
804 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
805 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
806 inst
->predicate
= BRW_PREDICATE_NORMAL
;
808 /* Convert from 32-bit float to 64-bit double */
809 result
.type
= BRW_REGISTER_TYPE_DF
;
810 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
812 if (instr
->dest
.saturate
) {
813 inst
= bld
.MOV(result
, result
);
814 inst
->saturate
= true;
821 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
822 * -> non-negative val generates 0x00000000.
823 * Predicated OR sets 1 if val is positive.
825 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
826 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
827 bld
.ASR(result
, op
[0], brw_imm_d(31));
828 inst
= bld
.OR(result
, result
, brw_imm_d(1));
829 inst
->predicate
= BRW_PREDICATE_NORMAL
;
833 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
834 inst
->saturate
= instr
->dest
.saturate
;
838 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
839 inst
->saturate
= instr
->dest
.saturate
;
843 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
844 inst
->saturate
= instr
->dest
.saturate
;
848 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
849 inst
->saturate
= instr
->dest
.saturate
;
853 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
854 inst
->saturate
= instr
->dest
.saturate
;
858 if (fs_key
->high_quality_derivatives
) {
859 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
861 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
863 inst
->saturate
= instr
->dest
.saturate
;
865 case nir_op_fddx_fine
:
866 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
867 inst
->saturate
= instr
->dest
.saturate
;
869 case nir_op_fddx_coarse
:
870 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
871 inst
->saturate
= instr
->dest
.saturate
;
874 if (fs_key
->high_quality_derivatives
) {
875 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
876 brw_imm_d(fs_key
->render_to_fbo
));
878 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
879 brw_imm_d(fs_key
->render_to_fbo
));
881 inst
->saturate
= instr
->dest
.saturate
;
883 case nir_op_fddy_fine
:
884 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
885 brw_imm_d(fs_key
->render_to_fbo
));
886 inst
->saturate
= instr
->dest
.saturate
;
888 case nir_op_fddy_coarse
:
889 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
890 brw_imm_d(fs_key
->render_to_fbo
));
891 inst
->saturate
= instr
->dest
.saturate
;
895 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
897 inst
= bld
.ADD(result
, op
[0], op
[1]);
898 inst
->saturate
= instr
->dest
.saturate
;
902 inst
= bld
.MUL(result
, op
[0], op
[1]);
903 inst
->saturate
= instr
->dest
.saturate
;
907 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
908 bld
.MUL(result
, op
[0], op
[1]);
911 case nir_op_imul_high
:
912 case nir_op_umul_high
:
913 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
914 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
919 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
920 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
923 case nir_op_uadd_carry
:
924 unreachable("Should have been lowered by carry_to_arith().");
926 case nir_op_usub_borrow
:
927 unreachable("Should have been lowered by borrow_to_arith().");
931 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
932 * appears that our hardware just does the right thing for signed
935 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
936 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
940 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
941 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
943 /* Math instructions don't support conditional mod */
944 inst
= bld
.MOV(bld
.null_reg_d(), result
);
945 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
947 /* Now, we need to determine if signs of the sources are different.
948 * When we XOR the sources, the top bit is 0 if they are the same and 1
949 * if they are different. We can then use a conditional modifier to
950 * turn that into a predicate. This leads us to an XOR.l instruction.
952 * Technically, according to the PRM, you're not allowed to use .l on a
953 * XOR instruction. However, emperical experiments and Curro's reading
954 * of the simulator source both indicate that it's safe.
956 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
957 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
958 inst
->predicate
= BRW_PREDICATE_NORMAL
;
959 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
961 /* If the result of the initial remainder operation is non-zero and the
962 * two sources have different signs, add in a copy of op[1] to get the
963 * final integer modulus value.
965 inst
= bld
.ADD(result
, result
, op
[1]);
966 inst
->predicate
= BRW_PREDICATE_NORMAL
;
974 fs_reg dest
= result
;
975 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
976 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
978 brw_conditional_mod cond
;
981 cond
= BRW_CONDITIONAL_L
;
984 cond
= BRW_CONDITIONAL_GE
;
987 cond
= BRW_CONDITIONAL_Z
;
990 cond
= BRW_CONDITIONAL_NZ
;
993 unreachable("bad opcode");
995 bld
.CMP(dest
, op
[0], op
[1], cond
);
996 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
997 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1004 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1005 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1010 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1011 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1015 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1016 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1020 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1021 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1025 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1026 if (devinfo
->gen
>= 8) {
1027 op
[0] = resolve_source_modifiers(op
[0]);
1029 bld
.NOT(result
, op
[0]);
1032 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1033 if (devinfo
->gen
>= 8) {
1034 op
[0] = resolve_source_modifiers(op
[0]);
1035 op
[1] = resolve_source_modifiers(op
[1]);
1037 bld
.XOR(result
, op
[0], op
[1]);
1040 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1041 if (devinfo
->gen
>= 8) {
1042 op
[0] = resolve_source_modifiers(op
[0]);
1043 op
[1] = resolve_source_modifiers(op
[1]);
1045 bld
.OR(result
, op
[0], op
[1]);
1048 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1049 if (devinfo
->gen
>= 8) {
1050 op
[0] = resolve_source_modifiers(op
[0]);
1051 op
[1] = resolve_source_modifiers(op
[1]);
1053 bld
.AND(result
, op
[0], op
[1]);
1059 case nir_op_ball_fequal2
:
1060 case nir_op_ball_iequal2
:
1061 case nir_op_ball_fequal3
:
1062 case nir_op_ball_iequal3
:
1063 case nir_op_ball_fequal4
:
1064 case nir_op_ball_iequal4
:
1065 case nir_op_bany_fnequal2
:
1066 case nir_op_bany_inequal2
:
1067 case nir_op_bany_fnequal3
:
1068 case nir_op_bany_inequal3
:
1069 case nir_op_bany_fnequal4
:
1070 case nir_op_bany_inequal4
:
1071 unreachable("Lowered by nir_lower_alu_reductions");
1073 case nir_op_fnoise1_1
:
1074 case nir_op_fnoise1_2
:
1075 case nir_op_fnoise1_3
:
1076 case nir_op_fnoise1_4
:
1077 case nir_op_fnoise2_1
:
1078 case nir_op_fnoise2_2
:
1079 case nir_op_fnoise2_3
:
1080 case nir_op_fnoise2_4
:
1081 case nir_op_fnoise3_1
:
1082 case nir_op_fnoise3_2
:
1083 case nir_op_fnoise3_3
:
1084 case nir_op_fnoise3_4
:
1085 case nir_op_fnoise4_1
:
1086 case nir_op_fnoise4_2
:
1087 case nir_op_fnoise4_3
:
1088 case nir_op_fnoise4_4
:
1089 unreachable("not reached: should be handled by lower_noise");
1092 unreachable("not reached: should be handled by ldexp_to_arith()");
1095 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1096 inst
->saturate
= instr
->dest
.saturate
;
1100 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1101 inst
->saturate
= instr
->dest
.saturate
;
1106 bld
.MOV(result
, negate(op
[0]));
1110 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1113 /* two-argument instructions can't take 64-bit immediates */
1114 fs_reg zero
= vgrf(glsl_type::double_type
);
1115 bld
.MOV(zero
, brw_imm_df(0.0));
1116 /* A SIMD16 execution needs to be split in two instructions, so use
1117 * a vgrf instead of the flag register as dst so instruction splitting
1120 fs_reg tmp
= vgrf(glsl_type::double_type
);
1121 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1122 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1126 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1130 inst
= bld
.RNDZ(result
, op
[0]);
1131 inst
->saturate
= instr
->dest
.saturate
;
1134 case nir_op_fceil
: {
1135 op
[0].negate
= !op
[0].negate
;
1136 fs_reg temp
= vgrf(glsl_type::float_type
);
1137 bld
.RNDD(temp
, op
[0]);
1139 inst
= bld
.MOV(result
, temp
);
1140 inst
->saturate
= instr
->dest
.saturate
;
1144 inst
= bld
.RNDD(result
, op
[0]);
1145 inst
->saturate
= instr
->dest
.saturate
;
1148 inst
= bld
.FRC(result
, op
[0]);
1149 inst
->saturate
= instr
->dest
.saturate
;
1151 case nir_op_fround_even
:
1152 inst
= bld
.RNDE(result
, op
[0]);
1153 inst
->saturate
= instr
->dest
.saturate
;
1156 case nir_op_fquantize2f16
: {
1157 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1158 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1159 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1161 /* The destination stride must be at least as big as the source stride. */
1162 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1165 /* Check for denormal */
1166 fs_reg abs_src0
= op
[0];
1167 abs_src0
.abs
= true;
1168 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1170 /* Get the appropriately signed zero */
1171 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1172 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1173 brw_imm_ud(0x80000000));
1174 /* Do the actual F32 -> F16 -> F32 conversion */
1175 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1176 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1177 /* Select that or zero based on normal status */
1178 inst
= bld
.SEL(result
, zero
, tmp32
);
1179 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1180 inst
->saturate
= instr
->dest
.saturate
;
1186 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1188 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1189 inst
->saturate
= instr
->dest
.saturate
;
1194 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1196 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1197 inst
->saturate
= instr
->dest
.saturate
;
1200 case nir_op_pack_snorm_2x16
:
1201 case nir_op_pack_snorm_4x8
:
1202 case nir_op_pack_unorm_2x16
:
1203 case nir_op_pack_unorm_4x8
:
1204 case nir_op_unpack_snorm_2x16
:
1205 case nir_op_unpack_snorm_4x8
:
1206 case nir_op_unpack_unorm_2x16
:
1207 case nir_op_unpack_unorm_4x8
:
1208 case nir_op_unpack_half_2x16
:
1209 case nir_op_pack_half_2x16
:
1210 unreachable("not reached: should be handled by lower_packing_builtins");
1212 case nir_op_unpack_half_2x16_split_x
:
1213 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1214 inst
->saturate
= instr
->dest
.saturate
;
1216 case nir_op_unpack_half_2x16_split_y
:
1217 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1218 inst
->saturate
= instr
->dest
.saturate
;
1221 case nir_op_pack_double_2x32_split
:
1222 /* Optimize the common case where we are re-packing a double with
1223 * the result of a previous double unpack. In this case we can take the
1224 * 32-bit value to use in the re-pack from the original double and bypass
1225 * the unpack operation.
1227 for (int i
= 0; i
< 2; i
++) {
1228 if (instr
->src
[i
].src
.is_ssa
)
1231 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1232 if (parent_instr
->type
== nir_instr_type_alu
)
1235 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1236 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1237 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1240 if (!alu_parent
->src
[0].src
.is_ssa
)
1243 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1244 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1245 alu_parent
->src
[0].swizzle
[channel
]);
1246 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1247 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1249 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1251 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1254 case nir_op_unpack_double_2x32_split_x
:
1255 case nir_op_unpack_double_2x32_split_y
: {
1256 /* Optimize the common case where we are unpacking from a double we have
1257 * previously packed. In this case we can just bypass the pack operation
1258 * and source directly from its arguments.
1260 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1261 if (instr
->src
[0].src
.is_ssa
) {
1262 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1263 if (parent_instr
->type
== nir_instr_type_alu
) {
1264 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1265 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1266 alu_parent
->src
[index
].src
.is_ssa
) {
1267 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1268 BRW_REGISTER_TYPE_UD
);
1270 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1271 bld
.MOV(result
, op
[0]);
1277 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1278 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1280 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1285 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1286 inst
->saturate
= instr
->dest
.saturate
;
1289 case nir_op_bitfield_reverse
:
1290 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1291 bld
.BFREV(result
, op
[0]);
1294 case nir_op_bit_count
:
1295 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1296 bld
.CBIT(result
, op
[0]);
1299 case nir_op_ufind_msb
:
1300 case nir_op_ifind_msb
: {
1301 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1302 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1304 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1305 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1306 * subtract the result from 31 to convert the MSB count into an LSB count.
1308 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1310 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1311 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1312 inst
->src
[0].negate
= true;
1316 case nir_op_find_lsb
:
1317 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1318 bld
.FBL(result
, op
[0]);
1321 case nir_op_ubitfield_extract
:
1322 case nir_op_ibitfield_extract
:
1323 unreachable("should have been lowered");
1326 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1327 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1330 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 bld
.BFI1(result
, op
[0], op
[1]);
1334 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1335 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1338 case nir_op_bitfield_insert
:
1339 unreachable("not reached: should have been lowered");
1342 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1343 bld
.SHL(result
, op
[0], op
[1]);
1346 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1347 bld
.ASR(result
, op
[0], op
[1]);
1350 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1351 bld
.SHR(result
, op
[0], op
[1]);
1354 case nir_op_pack_half_2x16_split
:
1355 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1359 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1360 inst
->saturate
= instr
->dest
.saturate
;
1364 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1365 inst
->saturate
= instr
->dest
.saturate
;
1369 if (optimize_frontfacing_ternary(instr
, result
))
1372 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1373 inst
= bld
.SEL(result
, op
[1], op
[2]);
1374 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1377 case nir_op_extract_u8
:
1378 case nir_op_extract_i8
: {
1379 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1380 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1381 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1385 case nir_op_extract_u16
:
1386 case nir_op_extract_i16
: {
1387 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1388 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1389 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1394 unreachable("unhandled instruction");
1397 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1398 * to sign extend the low bit to 0/~0
1400 if (devinfo
->gen
<= 5 &&
1401 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1402 fs_reg masked
= vgrf(glsl_type::int_type
);
1403 bld
.AND(masked
, result
, brw_imm_d(1));
1404 masked
.negate
= true;
1405 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1410 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1411 nir_load_const_instr
*instr
)
1413 const brw_reg_type reg_type
=
1414 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1415 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1417 switch (instr
->def
.bit_size
) {
1419 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1420 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1424 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1425 bld
.MOV(offset(reg
, bld
, i
), brw_imm_df(instr
->value
.f64
[i
]));
1429 unreachable("Invalid bit size");
1432 nir_ssa_values
[instr
->def
.index
] = reg
;
1436 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1438 const brw_reg_type reg_type
=
1439 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1440 nir_ssa_values
[instr
->def
.index
] =
1441 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1445 fs_visitor::get_nir_src(nir_src src
)
1449 reg
= nir_ssa_values
[src
.ssa
->index
];
1451 /* We don't handle indirects on locals */
1452 assert(src
.reg
.indirect
== NULL
);
1453 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1454 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1457 /* to avoid floating-point denorm flushing problems, set the type by
1458 * default to D - instructions that need floating point semantics will set
1459 * this to F if they need to
1461 return retype(reg
, BRW_REGISTER_TYPE_D
);
1465 fs_visitor::get_nir_dest(nir_dest dest
)
1468 const brw_reg_type reg_type
=
1469 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1470 nir_ssa_values
[dest
.ssa
.index
] =
1471 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1472 return nir_ssa_values
[dest
.ssa
.index
];
1474 /* We don't handle indirects on locals */
1475 assert(dest
.reg
.indirect
== NULL
);
1476 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1477 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1482 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1484 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1485 BRW_REGISTER_TYPE_UD
);
1487 unsigned indirect_max
= 0;
1489 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1490 tail
= tail
->child
) {
1491 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1492 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1493 const unsigned size
= glsl_get_length(tail
->type
);
1494 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1495 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1496 image
= offset(image
, bld
, base
* element_size
);
1498 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1499 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1501 /* Accessing an invalid surface index with the dataport can result
1502 * in a hang. According to the spec "if the index used to
1503 * select an individual element is negative or greater than or
1504 * equal to the size of the array, the results of the operation
1505 * are undefined but may not lead to termination" -- which is one
1506 * of the possible outcomes of the hang. Clamp the index to
1507 * prevent access outside of the array bounds.
1509 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1510 BRW_REGISTER_TYPE_UD
),
1511 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1513 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1515 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1516 if (indirect
.file
== BAD_FILE
) {
1519 bld
.ADD(indirect
, indirect
, tmp
);
1524 if (indirect
.file
== BAD_FILE
) {
1527 /* Emit a pile of MOVs to load the uniform into a temporary. The
1528 * dead-code elimination pass will get rid of what we don't use.
1530 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1531 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1532 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1533 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1534 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1541 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1544 for (unsigned i
= 0; i
< 4; i
++) {
1545 if (!((wr_mask
>> i
) & 1))
1548 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1549 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1550 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1551 if (new_inst
->src
[j
].file
== VGRF
)
1552 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1559 * Get the matching channel register datatype for an image intrinsic of the
1560 * specified GLSL image type.
1563 get_image_base_type(const glsl_type
*type
)
1565 switch ((glsl_base_type
)type
->sampled_type
) {
1566 case GLSL_TYPE_UINT
:
1567 return BRW_REGISTER_TYPE_UD
;
1569 return BRW_REGISTER_TYPE_D
;
1570 case GLSL_TYPE_FLOAT
:
1571 return BRW_REGISTER_TYPE_F
;
1573 unreachable("Not reached.");
1578 * Get the appropriate atomic op for an image atomic intrinsic.
1581 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1584 case nir_intrinsic_image_atomic_add
:
1586 case nir_intrinsic_image_atomic_min
:
1587 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1588 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1589 case nir_intrinsic_image_atomic_max
:
1590 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1591 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1592 case nir_intrinsic_image_atomic_and
:
1594 case nir_intrinsic_image_atomic_or
:
1596 case nir_intrinsic_image_atomic_xor
:
1598 case nir_intrinsic_image_atomic_exchange
:
1600 case nir_intrinsic_image_atomic_comp_swap
:
1601 return BRW_AOP_CMPWR
;
1603 unreachable("Not reachable.");
1608 emit_pixel_interpolater_send(const fs_builder
&bld
,
1613 glsl_interp_qualifier interpolation
)
1619 if (src
.file
== BAD_FILE
) {
1621 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1625 mlen
= 2 * bld
.dispatch_width() / 8;
1628 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1630 /* 2 floats per slot returned */
1631 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1632 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1638 * Computes 1 << x, given a D/UD register containing some value x.
1641 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1643 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1645 fs_reg result
= bld
.vgrf(x
.type
, 1);
1646 fs_reg one
= bld
.vgrf(x
.type
, 1);
1648 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1649 bld
.SHL(result
, one
, x
);
1654 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1656 assert(stage
== MESA_SHADER_GEOMETRY
);
1658 struct brw_gs_prog_data
*gs_prog_data
=
1659 (struct brw_gs_prog_data
*) prog_data
;
1661 /* We can only do EndPrimitive() functionality when the control data
1662 * consists of cut bits. Fortunately, the only time it isn't is when the
1663 * output type is points, in which case EndPrimitive() is a no-op.
1665 if (gs_prog_data
->control_data_format
!=
1666 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1670 /* Cut bits use one bit per vertex. */
1671 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1673 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1674 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1676 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1677 * vertex n, 0 otherwise. So all we need to do here is mark bit
1678 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1679 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1680 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1682 * Note that if EndPrimitive() is called before emitting any vertices, this
1683 * will cause us to set bit 31 of the control_data_bits register to 1.
1684 * That's fine because:
1686 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1687 * output, so the hardware will ignore cut bit 31.
1689 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1690 * last vertex, so setting cut bit 31 has no effect (since the primitive
1691 * is automatically ended when the GS terminates).
1693 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1694 * control_data_bits register to 0 when the first vertex is emitted.
1697 const fs_builder abld
= bld
.annotate("end primitive");
1699 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1700 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1701 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1702 fs_reg mask
= intexp2(abld
, prev_count
);
1703 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1704 * attention to the lower 5 bits of its second source argument, so on this
1705 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1706 * ((vertex_count - 1) % 32).
1708 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1712 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1714 assert(stage
== MESA_SHADER_GEOMETRY
);
1715 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1717 struct brw_gs_prog_data
*gs_prog_data
=
1718 (struct brw_gs_prog_data
*) prog_data
;
1720 const fs_builder abld
= bld
.annotate("emit control data bits");
1721 const fs_builder fwa_bld
= bld
.exec_all();
1723 /* We use a single UD register to accumulate control data bits (32 bits
1724 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1727 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1728 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1729 * use the Channel Mask phase to enable/disable which DWord within that
1730 * group to write. (Remember, different SIMD8 channels may have emitted
1731 * different numbers of vertices, so we may need per-slot offsets.)
1733 * Channel masking presents an annoying problem: we may have to replicate
1734 * the data up to 4 times:
1736 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1738 * To avoid penalizing shaders that emit a small number of vertices, we
1739 * can avoid these sometimes: if the size of the control data header is
1740 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1741 * land in the same 128-bit group, so we can skip per-slot offsets.
1743 * Similarly, if the control data header is <= 32 bits, there is only one
1744 * DWord, so we can skip channel masks.
1746 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1748 fs_reg channel_mask
, per_slot_offset
;
1750 if (gs_compile
->control_data_header_size_bits
> 32) {
1751 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1752 channel_mask
= vgrf(glsl_type::uint_type
);
1755 if (gs_compile
->control_data_header_size_bits
> 128) {
1756 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1757 per_slot_offset
= vgrf(glsl_type::uint_type
);
1760 /* Figure out which DWord we're trying to write to using the formula:
1762 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1764 * Since bits_per_vertex is a power of two, and is known at compile
1765 * time, this can be optimized to:
1767 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1769 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1770 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1771 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1772 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1773 unsigned log2_bits_per_vertex
=
1774 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1775 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1777 if (per_slot_offset
.file
!= BAD_FILE
) {
1778 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1779 * the appropriate OWord within the control data header.
1781 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1784 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1785 * write to the appropriate DWORD within the OWORD.
1787 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1788 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1789 channel_mask
= intexp2(fwa_bld
, channel
);
1790 /* Then the channel masks need to be in bits 23:16. */
1791 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1794 /* Store the control data bits in the message payload and send it. */
1796 if (channel_mask
.file
!= BAD_FILE
)
1797 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1798 if (per_slot_offset
.file
!= BAD_FILE
)
1801 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1802 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1804 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1805 if (per_slot_offset
.file
!= BAD_FILE
)
1806 sources
[i
++] = per_slot_offset
;
1807 if (channel_mask
.file
!= BAD_FILE
)
1808 sources
[i
++] = channel_mask
;
1810 sources
[i
++] = this->control_data_bits
;
1813 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1814 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1816 /* We need to increment Global Offset by 256-bits to make room for
1817 * Broadwell's extra "Vertex Count" payload at the beginning of the
1818 * URB entry. Since this is an OWord message, Global Offset is counted
1819 * in 128-bit units, so we must set it to 2.
1821 if (gs_prog_data
->static_vertex_count
== -1)
1826 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1829 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1831 /* Note: we are calling this *before* increasing vertex_count, so
1832 * this->vertex_count == vertex_count - 1 in the formula above.
1835 /* Stream mode uses 2 bits per vertex */
1836 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1838 /* Must be a valid stream */
1839 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1841 /* Control data bits are initialized to 0 so we don't have to set any
1842 * bits when sending vertices to stream 0.
1847 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1849 /* reg::sid = stream_id */
1850 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1851 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1853 /* reg:shift_count = 2 * (vertex_count - 1) */
1854 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1855 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1857 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1858 * attention to the lower 5 bits of its second source argument, so on this
1859 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1860 * stream_id << ((2 * (vertex_count - 1)) % 32).
1862 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1863 abld
.SHL(mask
, sid
, shift_count
);
1864 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1868 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1871 assert(stage
== MESA_SHADER_GEOMETRY
);
1873 struct brw_gs_prog_data
*gs_prog_data
=
1874 (struct brw_gs_prog_data
*) prog_data
;
1876 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1877 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1879 /* Haswell and later hardware ignores the "Render Stream Select" bits
1880 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1881 * and instead sends all primitives down the pipeline for rasterization.
1882 * If the SOL stage is enabled, "Render Stream Select" is honored and
1883 * primitives bound to non-zero streams are discarded after stream output.
1885 * Since the only purpose of primives sent to non-zero streams is to
1886 * be recorded by transform feedback, we can simply discard all geometry
1887 * bound to these streams when transform feedback is disabled.
1889 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1892 /* If we're outputting 32 control data bits or less, then we can wait
1893 * until the shader is over to output them all. Otherwise we need to
1894 * output them as we go. Now is the time to do it, since we're about to
1895 * output the vertex_count'th vertex, so it's guaranteed that the
1896 * control data bits associated with the (vertex_count - 1)th vertex are
1899 if (gs_compile
->control_data_header_size_bits
> 32) {
1900 const fs_builder abld
=
1901 bld
.annotate("emit vertex: emit control data bits");
1903 /* Only emit control data bits if we've finished accumulating a batch
1904 * of 32 bits. This is the case when:
1906 * (vertex_count * bits_per_vertex) % 32 == 0
1908 * (in other words, when the last 5 bits of vertex_count *
1909 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1910 * integer n (which is always the case, since bits_per_vertex is
1911 * always 1 or 2), this is equivalent to requiring that the last 5-n
1912 * bits of vertex_count are 0:
1914 * vertex_count & (2^(5-n) - 1) == 0
1916 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1919 * vertex_count & (32 / bits_per_vertex - 1) == 0
1921 * TODO: If vertex_count is an immediate, we could do some of this math
1922 * at compile time...
1925 abld
.AND(bld
.null_reg_d(), vertex_count
,
1926 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1927 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1929 abld
.IF(BRW_PREDICATE_NORMAL
);
1930 /* If vertex_count is 0, then no control data bits have been
1931 * accumulated yet, so we can skip emitting them.
1933 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1934 BRW_CONDITIONAL_NEQ
);
1935 abld
.IF(BRW_PREDICATE_NORMAL
);
1936 emit_gs_control_data_bits(vertex_count
);
1937 abld
.emit(BRW_OPCODE_ENDIF
);
1939 /* Reset control_data_bits to 0 so we can start accumulating a new
1942 * Note: in the case where vertex_count == 0, this neutralizes the
1943 * effect of any call to EndPrimitive() that the shader may have
1944 * made before outputting its first vertex.
1946 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1947 inst
->force_writemask_all
= true;
1948 abld
.emit(BRW_OPCODE_ENDIF
);
1951 emit_urb_writes(vertex_count
);
1953 /* In stream mode we have to set control data bits for all vertices
1954 * unless we have disabled control data bits completely (which we do
1955 * do for GL_POINTS outputs that don't use streams).
1957 if (gs_compile
->control_data_header_size_bits
> 0 &&
1958 gs_prog_data
->control_data_format
==
1959 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1960 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1965 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1966 const nir_src
&vertex_src
,
1967 unsigned base_offset
,
1968 const nir_src
&offset_src
,
1969 unsigned num_components
)
1971 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1973 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1974 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1975 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1977 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1978 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1979 * gl_PointSize is available as a GS input, however, so it must be that.
1981 const bool is_point_size
= (base_offset
== 0);
1983 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1984 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1985 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1986 vertex_const
->u32
[0] * push_reg_count
;
1987 /* This input was pushed into registers. */
1988 if (is_point_size
) {
1989 /* gl_PointSize comes in .w */
1990 assert(imm_offset
== 0);
1991 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1993 for (unsigned i
= 0; i
< num_components
; i
++) {
1994 bld
.MOV(offset(dst
, bld
, i
),
1995 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1999 /* Resort to the pull model. Ensure the VUE handles are provided. */
2000 gs_prog_data
->base
.include_vue_handles
= true;
2002 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2006 /* The vertex index is constant; just select the proper URB handle. */
2008 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2009 BRW_REGISTER_TYPE_UD
);
2011 /* The vertex index is non-constant. We need to use indirect
2012 * addressing to fetch the proper URB handle.
2014 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2015 * indicating that channel <n> should read the handle from
2016 * DWord <n>. We convert that to bytes by multiplying by 4.
2018 * Next, we convert the vertex index to bytes by multiplying
2019 * by 32 (shifting by 5), and add the two together. This is
2020 * the final indirect byte offset.
2022 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2023 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2024 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2025 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2026 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2028 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2029 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2030 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2031 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2032 /* Convert vertex_index to bytes (multiply by 32) */
2033 bld
.SHL(vertex_offset_bytes
,
2034 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2036 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2038 /* Use first_icp_handle as the base offset. There is one register
2039 * of URB handles per vertex, so inform the register allocator that
2040 * we might read up to nir->info.gs.vertices_in registers.
2042 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2043 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2044 fs_reg(icp_offset_bytes
),
2045 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2050 /* Constant indexing - use global offset. */
2051 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2052 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2053 inst
->base_mrf
= -1;
2055 inst
->regs_written
= num_components
;
2057 /* Indirect indexing - use per-slot offsets as well. */
2058 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
2059 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2060 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2062 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2063 inst
->offset
= base_offset
;
2064 inst
->base_mrf
= -1;
2066 inst
->regs_written
= num_components
;
2069 if (is_point_size
) {
2070 /* Read the whole VUE header (because of alignment) and read .w. */
2071 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2073 inst
->regs_written
= 4;
2074 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2080 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2082 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2083 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2086 /* The only constant offset we should find is 0. brw_nir.c's
2087 * add_const_offset_to_base() will fold other constant offsets
2088 * into instr->const_index[0].
2090 assert(const_value
->u32
[0] == 0);
2094 return get_nir_src(*offset_src
);
2098 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2099 nir_intrinsic_instr
*instr
)
2101 assert(stage
== MESA_SHADER_VERTEX
);
2104 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2105 dest
= get_nir_dest(instr
->dest
);
2107 switch (instr
->intrinsic
) {
2108 case nir_intrinsic_load_vertex_id
:
2109 unreachable("should be lowered by lower_vertex_id()");
2111 case nir_intrinsic_load_vertex_id_zero_base
:
2112 case nir_intrinsic_load_base_vertex
:
2113 case nir_intrinsic_load_instance_id
:
2114 case nir_intrinsic_load_base_instance
:
2115 case nir_intrinsic_load_draw_id
: {
2116 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2117 fs_reg val
= nir_system_values
[sv
];
2118 assert(val
.file
!= BAD_FILE
);
2119 dest
.type
= val
.type
;
2125 nir_emit_intrinsic(bld
, instr
);
2131 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2132 nir_intrinsic_instr
*instr
)
2134 assert(stage
== MESA_SHADER_TESS_CTRL
);
2135 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2136 struct brw_tcs_prog_data
*tcs_prog_data
=
2137 (struct brw_tcs_prog_data
*) prog_data
;
2140 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2141 dst
= get_nir_dest(instr
->dest
);
2143 switch (instr
->intrinsic
) {
2144 case nir_intrinsic_load_primitive_id
:
2145 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2147 case nir_intrinsic_load_invocation_id
:
2148 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2150 case nir_intrinsic_load_patch_vertices_in
:
2151 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2152 brw_imm_d(tcs_key
->input_vertices
));
2155 case nir_intrinsic_barrier
: {
2156 if (tcs_prog_data
->instances
== 1)
2159 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2160 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2162 const fs_builder fwa_bld
= bld
.exec_all();
2164 /* Zero the message header */
2165 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2167 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2168 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2169 brw_imm_ud(INTEL_MASK(16, 13)));
2171 /* Shift it up to bits 27:24. */
2172 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2174 /* Set the Barrier Count and the enable bit */
2175 fwa_bld
.OR(m0_2
, m0_2
,
2176 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2178 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2182 case nir_intrinsic_load_input
:
2183 unreachable("nir_lower_io should never give us these.");
2186 case nir_intrinsic_load_per_vertex_input
: {
2187 fs_reg indirect_offset
= get_indirect_offset(instr
);
2188 unsigned imm_offset
= instr
->const_index
[0];
2190 const nir_src
&vertex_src
= instr
->src
[0];
2191 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2198 /* Emit a MOV to resolve <0,1,0> regioning. */
2199 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2201 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2202 vertex_const
->i32
[0] & 7),
2203 BRW_REGISTER_TYPE_UD
));
2204 } else if (tcs_prog_data
->instances
== 1 &&
2205 vertex_src
.is_ssa
&&
2206 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2207 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2208 /* For the common case of only 1 instance, an array index of
2209 * gl_InvocationID means reading g1. Skip all the indirect work.
2211 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2213 /* The vertex index is non-constant. We need to use indirect
2214 * addressing to fetch the proper URB handle.
2216 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2218 /* Each ICP handle is a single DWord (4 bytes) */
2219 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2220 bld
.SHL(vertex_offset_bytes
,
2221 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2224 /* Start at g1. We might read up to 4 registers. */
2225 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2226 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2227 brw_imm_ud(4 * REG_SIZE
));
2230 if (indirect_offset
.file
== BAD_FILE
) {
2231 /* Constant indexing - use global offset. */
2232 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2233 inst
->offset
= imm_offset
;
2235 inst
->base_mrf
= -1;
2236 inst
->regs_written
= instr
->num_components
;
2238 /* Indirect indexing - use per-slot offsets as well. */
2239 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2240 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2241 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2243 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2244 inst
->offset
= imm_offset
;
2245 inst
->base_mrf
= -1;
2247 inst
->regs_written
= instr
->num_components
;
2250 /* Copy the temporary to the destination to deal with writemasking.
2252 * Also attempt to deal with gl_PointSize being in the .w component.
2254 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2255 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2256 inst
->regs_written
= 4;
2257 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2262 case nir_intrinsic_load_output
:
2263 case nir_intrinsic_load_per_vertex_output
: {
2264 fs_reg indirect_offset
= get_indirect_offset(instr
);
2265 unsigned imm_offset
= instr
->const_index
[0];
2268 if (indirect_offset
.file
== BAD_FILE
) {
2269 /* Replicate the patch handle to all enabled channels */
2270 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2271 bld
.MOV(patch_handle
,
2272 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2274 if (imm_offset
== 0) {
2275 /* This is a read of gl_TessLevelInner[], which lives in the
2276 * Patch URB header. The layout depends on the domain.
2278 dst
.type
= BRW_REGISTER_TYPE_F
;
2279 switch (tcs_key
->tes_primitive_mode
) {
2281 /* DWords 3-2 (reversed) */
2282 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2284 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2287 inst
->base_mrf
= -1;
2288 inst
->regs_written
= 4;
2290 /* dst.xy = tmp.wz */
2291 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2292 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2296 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2297 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2300 inst
->base_mrf
= -1;
2301 inst
->regs_written
= 1;
2304 /* All channels are undefined. */
2307 unreachable("Bogus tessellation domain");
2309 } else if (imm_offset
== 1) {
2310 /* This is a read of gl_TessLevelOuter[], which lives in the
2311 * Patch URB header. The layout depends on the domain.
2313 dst
.type
= BRW_REGISTER_TYPE_F
;
2315 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2316 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2319 inst
->base_mrf
= -1;
2320 inst
->regs_written
= 4;
2322 /* Reswizzle: WZYX */
2324 offset(tmp
, bld
, 3),
2325 offset(tmp
, bld
, 2),
2326 offset(tmp
, bld
, 1),
2327 offset(tmp
, bld
, 0),
2330 unsigned num_components
;
2331 switch (tcs_key
->tes_primitive_mode
) {
2339 /* Isolines are not reversed; swizzle .zw -> .xy */
2340 srcs
[0] = offset(tmp
, bld
, 2);
2341 srcs
[1] = offset(tmp
, bld
, 3);
2345 unreachable("Bogus tessellation domain");
2347 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2349 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2350 inst
->offset
= imm_offset
;
2352 inst
->base_mrf
= -1;
2353 inst
->regs_written
= instr
->num_components
;
2356 /* Indirect indexing - use per-slot offsets as well. */
2357 const fs_reg srcs
[] = {
2358 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2361 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2362 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2364 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2365 inst
->offset
= imm_offset
;
2367 inst
->base_mrf
= -1;
2368 inst
->regs_written
= instr
->num_components
;
2373 case nir_intrinsic_store_output
:
2374 case nir_intrinsic_store_per_vertex_output
: {
2375 fs_reg value
= get_nir_src(instr
->src
[0]);
2376 fs_reg indirect_offset
= get_indirect_offset(instr
);
2377 unsigned imm_offset
= instr
->const_index
[0];
2378 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2379 unsigned mask
= instr
->const_index
[1];
2380 unsigned header_regs
= 0;
2382 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2384 if (indirect_offset
.file
!= BAD_FILE
) {
2385 srcs
[header_regs
++] = indirect_offset
;
2386 } else if (!is_passthrough_shader
) {
2387 if (imm_offset
== 0) {
2388 value
.type
= BRW_REGISTER_TYPE_F
;
2390 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2392 /* This is a write to gl_TessLevelInner[], which lives in the
2393 * Patch URB header. The layout depends on the domain.
2395 switch (tcs_key
->tes_primitive_mode
) {
2397 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2398 * We use an XXYX swizzle to reverse put .xy in the .wz
2399 * channels, and use a .zw writemask.
2401 mask
= writemask_for_backwards_vector(mask
);
2402 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2405 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2406 * writemask to X and bump the URB offset by 1.
2411 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2414 unreachable("Bogus tessellation domain");
2416 } else if (imm_offset
== 1) {
2417 /* This is a write to gl_TessLevelOuter[] which lives in the
2418 * Patch URB Header at DWords 4-7. However, it's reversed, so
2419 * instead of .xyzw we have .wzyx.
2421 value
.type
= BRW_REGISTER_TYPE_F
;
2423 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2425 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2426 /* Isolines .xy should be stored in .zw, in order. */
2427 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2430 /* Other domains are reversed; store .wzyx instead of .xyzw */
2431 swiz
= BRW_SWIZZLE_WZYX
;
2432 mask
= writemask_for_backwards_vector(mask
);
2440 unsigned num_components
= _mesa_fls(mask
);
2443 if (mask
!= WRITEMASK_XYZW
) {
2444 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2445 opcode
= indirect_offset
.file
!= BAD_FILE
?
2446 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2447 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2449 opcode
= indirect_offset
.file
!= BAD_FILE
?
2450 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2451 SHADER_OPCODE_URB_WRITE_SIMD8
;
2454 for (unsigned i
= 0; i
< num_components
; i
++) {
2455 if (mask
& (1 << i
))
2456 srcs
[header_regs
+ i
] = offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2459 unsigned mlen
= header_regs
+ num_components
;
2462 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2463 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2465 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2466 inst
->offset
= imm_offset
;
2468 inst
->base_mrf
= -1;
2473 nir_emit_intrinsic(bld
, instr
);
2479 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2480 nir_intrinsic_instr
*instr
)
2482 assert(stage
== MESA_SHADER_TESS_EVAL
);
2483 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2486 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2487 dest
= get_nir_dest(instr
->dest
);
2489 switch (instr
->intrinsic
) {
2490 case nir_intrinsic_load_primitive_id
:
2491 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2493 case nir_intrinsic_load_tess_coord
:
2494 /* gl_TessCoord is part of the payload in g1-3 */
2495 for (unsigned i
= 0; i
< 3; i
++) {
2496 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2500 case nir_intrinsic_load_tess_level_outer
:
2501 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2502 * appears as a push-model input. So, we can simply use the ATTR file
2503 * rather than issuing URB read messages. The data is stored in the
2504 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2507 switch (tes_prog_data
->domain
) {
2508 case BRW_TESS_DOMAIN_QUAD
:
2509 for (unsigned i
= 0; i
< 4; i
++)
2510 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2512 case BRW_TESS_DOMAIN_TRI
:
2513 for (unsigned i
= 0; i
< 3; i
++)
2514 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2516 case BRW_TESS_DOMAIN_ISOLINE
:
2517 for (unsigned i
= 0; i
< 2; i
++)
2518 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2523 case nir_intrinsic_load_tess_level_inner
:
2524 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2525 * appears as a push-model input. So, we can simply use the ATTR file
2526 * rather than issuing URB read messages.
2528 switch (tes_prog_data
->domain
) {
2529 case BRW_TESS_DOMAIN_QUAD
:
2530 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2531 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2533 case BRW_TESS_DOMAIN_TRI
:
2534 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2536 case BRW_TESS_DOMAIN_ISOLINE
:
2537 /* ignore - value is undefined */
2542 case nir_intrinsic_load_input
:
2543 case nir_intrinsic_load_per_vertex_input
: {
2544 fs_reg indirect_offset
= get_indirect_offset(instr
);
2545 unsigned imm_offset
= instr
->const_index
[0];
2548 if (indirect_offset
.file
== BAD_FILE
) {
2549 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2550 * which is 16 registers (since each holds 2 vec4 slots).
2552 const unsigned max_push_slots
= 32;
2553 if (imm_offset
< max_push_slots
) {
2554 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2555 for (int i
= 0; i
< instr
->num_components
; i
++) {
2556 bld
.MOV(offset(dest
, bld
, i
),
2557 component(src
, 4 * (imm_offset
% 2) + i
));
2559 tes_prog_data
->base
.urb_read_length
=
2560 MAX2(tes_prog_data
->base
.urb_read_length
,
2561 DIV_ROUND_UP(imm_offset
+ 1, 2));
2563 /* Replicate the patch handle to all enabled channels */
2564 const fs_reg srcs
[] = {
2565 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2567 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2568 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2570 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2572 inst
->offset
= imm_offset
;
2573 inst
->base_mrf
= -1;
2574 inst
->regs_written
= instr
->num_components
;
2577 /* Indirect indexing - use per-slot offsets as well. */
2578 const fs_reg srcs
[] = {
2579 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2582 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2583 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2585 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2587 inst
->offset
= imm_offset
;
2588 inst
->base_mrf
= -1;
2589 inst
->regs_written
= instr
->num_components
;
2594 nir_emit_intrinsic(bld
, instr
);
2600 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2601 nir_intrinsic_instr
*instr
)
2603 assert(stage
== MESA_SHADER_GEOMETRY
);
2604 fs_reg indirect_offset
;
2607 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2608 dest
= get_nir_dest(instr
->dest
);
2610 switch (instr
->intrinsic
) {
2611 case nir_intrinsic_load_primitive_id
:
2612 assert(stage
== MESA_SHADER_GEOMETRY
);
2613 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2614 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2615 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2618 case nir_intrinsic_load_input
:
2619 unreachable("load_input intrinsics are invalid for the GS stage");
2621 case nir_intrinsic_load_per_vertex_input
:
2622 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2623 instr
->src
[1], instr
->num_components
);
2626 case nir_intrinsic_emit_vertex_with_counter
:
2627 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2630 case nir_intrinsic_end_primitive_with_counter
:
2631 emit_gs_end_primitive(instr
->src
[0]);
2634 case nir_intrinsic_set_vertex_count
:
2635 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2638 case nir_intrinsic_load_invocation_id
: {
2639 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2640 assert(val
.file
!= BAD_FILE
);
2641 dest
.type
= val
.type
;
2647 nir_emit_intrinsic(bld
, instr
);
2653 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2654 nir_intrinsic_instr
*instr
)
2656 assert(stage
== MESA_SHADER_FRAGMENT
);
2657 struct brw_wm_prog_data
*wm_prog_data
=
2658 (struct brw_wm_prog_data
*) prog_data
;
2659 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
2662 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2663 dest
= get_nir_dest(instr
->dest
);
2665 switch (instr
->intrinsic
) {
2666 case nir_intrinsic_load_front_face
:
2667 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2668 *emit_frontfacing_interpolation());
2671 case nir_intrinsic_load_sample_pos
: {
2672 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2673 assert(sample_pos
.file
!= BAD_FILE
);
2674 dest
.type
= sample_pos
.type
;
2675 bld
.MOV(dest
, sample_pos
);
2676 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2680 case nir_intrinsic_load_helper_invocation
:
2681 case nir_intrinsic_load_sample_mask_in
:
2682 case nir_intrinsic_load_sample_id
: {
2683 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2684 fs_reg val
= nir_system_values
[sv
];
2685 assert(val
.file
!= BAD_FILE
);
2686 dest
.type
= val
.type
;
2691 case nir_intrinsic_discard
:
2692 case nir_intrinsic_discard_if
: {
2693 /* We track our discarded pixels in f0.1. By predicating on it, we can
2694 * update just the flag bits that aren't yet discarded. If there's no
2695 * condition, we emit a CMP of g0 != g0, so all currently executing
2696 * channels will get turned off.
2699 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2700 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2701 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2703 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2704 BRW_REGISTER_TYPE_UW
));
2705 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2707 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2708 cmp
->flag_subreg
= 1;
2710 if (devinfo
->gen
>= 6) {
2711 emit_discard_jump();
2716 case nir_intrinsic_interp_var_at_centroid
:
2717 case nir_intrinsic_interp_var_at_sample
:
2718 case nir_intrinsic_interp_var_at_offset
: {
2719 /* Handle ARB_gpu_shader5 interpolation intrinsics
2721 * It's worth a quick word of explanation as to why we handle the full
2722 * variable-based interpolation intrinsic rather than a lowered version
2723 * with like we do for other inputs. We have to do that because the way
2724 * we set up inputs doesn't allow us to use the already setup inputs for
2725 * interpolation. At the beginning of the shader, we go through all of
2726 * the input variables and do the initial interpolation and put it in
2727 * the nir_inputs array based on its location as determined in
2728 * nir_lower_io. If the input isn't used, dead code cleans up and
2729 * everything works fine. However, when we get to the ARB_gpu_shader5
2730 * interpolation intrinsics, we need to reinterpolate the input
2731 * differently. If we used an intrinsic that just had an index it would
2732 * only give us the offset into the nir_inputs array. However, this is
2733 * useless because that value is post-interpolation and we need
2734 * pre-interpolation. In order to get the actual location of the bits
2735 * we get from the vertex fetching hardware, we need the variable.
2737 wm_prog_data
->pulls_bary
= true;
2739 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2740 const glsl_interp_qualifier interpolation
=
2741 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2743 switch (instr
->intrinsic
) {
2744 case nir_intrinsic_interp_var_at_centroid
:
2745 emit_pixel_interpolater_send(bld
,
2746 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2753 case nir_intrinsic_interp_var_at_sample
: {
2754 if (!wm_key
->multisample_fbo
) {
2755 /* From the ARB_gpu_shader5 specification:
2756 * "If multisample buffers are not available, the input varying
2757 * will be evaluated at the center of the pixel."
2759 emit_pixel_interpolater_send(bld
,
2760 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2768 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2771 unsigned msg_data
= const_sample
->i32
[0] << 4;
2773 emit_pixel_interpolater_send(bld
,
2774 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2777 brw_imm_ud(msg_data
),
2780 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2781 BRW_REGISTER_TYPE_UD
);
2783 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2784 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2785 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2786 bld
.exec_all().group(1, 0)
2787 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2788 emit_pixel_interpolater_send(bld
,
2789 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2795 /* Make a loop that sends a message to the pixel interpolater
2796 * for the sample number in each live channel. If there are
2797 * multiple channels with the same sample number then these
2798 * will be handled simultaneously with a single interation of
2801 bld
.emit(BRW_OPCODE_DO
);
2803 /* Get the next live sample number into sample_id_reg */
2804 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2806 /* Set the flag register so that we can perform the send
2807 * message on all channels that have the same sample number
2809 bld
.CMP(bld
.null_reg_ud(),
2810 sample_src
, sample_id
,
2811 BRW_CONDITIONAL_EQ
);
2812 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2813 bld
.exec_all().group(1, 0)
2814 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2816 emit_pixel_interpolater_send(bld
,
2817 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2822 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2824 /* Continue the loop if there are any live channels left */
2825 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2827 bld
.emit(BRW_OPCODE_WHILE
));
2834 case nir_intrinsic_interp_var_at_offset
: {
2835 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2838 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2839 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2841 emit_pixel_interpolater_send(bld
,
2842 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2845 brw_imm_ud(off_x
| (off_y
<< 4)),
2848 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2849 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2850 BRW_REGISTER_TYPE_F
);
2851 for (int i
= 0; i
< 2; i
++) {
2852 fs_reg temp
= vgrf(glsl_type::float_type
);
2853 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2854 fs_reg itemp
= vgrf(glsl_type::int_type
);
2855 bld
.MOV(itemp
, temp
); /* float to int */
2857 /* Clamp the upper end of the range to +7/16.
2858 * ARB_gpu_shader5 requires that we support a maximum offset
2859 * of +0.5, which isn't representable in a S0.4 value -- if
2860 * we didn't clamp it, we'd end up with -8/16, which is the
2861 * opposite of what the shader author wanted.
2863 * This is legal due to ARB_gpu_shader5's quantization
2866 * "Not all values of <offset> may be supported; x and y
2867 * offsets may be rounded to fixed-point values with the
2868 * number of fraction bits given by the
2869 * implementation-dependent constant
2870 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2872 set_condmod(BRW_CONDITIONAL_L
,
2873 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2876 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2877 emit_pixel_interpolater_send(bld
,
2888 unreachable("Invalid intrinsic");
2891 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2892 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2893 src
.type
= dest
.type
;
2895 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2896 dest
= offset(dest
, bld
, 1);
2901 nir_emit_intrinsic(bld
, instr
);
2907 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2908 nir_intrinsic_instr
*instr
)
2910 assert(stage
== MESA_SHADER_COMPUTE
);
2911 struct brw_cs_prog_data
*cs_prog_data
=
2912 (struct brw_cs_prog_data
*) prog_data
;
2915 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2916 dest
= get_nir_dest(instr
->dest
);
2918 switch (instr
->intrinsic
) {
2919 case nir_intrinsic_barrier
:
2921 cs_prog_data
->uses_barrier
= true;
2924 case nir_intrinsic_load_local_invocation_id
:
2925 case nir_intrinsic_load_work_group_id
: {
2926 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2927 fs_reg val
= nir_system_values
[sv
];
2928 assert(val
.file
!= BAD_FILE
);
2929 dest
.type
= val
.type
;
2930 for (unsigned i
= 0; i
< 3; i
++)
2931 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2935 case nir_intrinsic_load_num_work_groups
: {
2936 const unsigned surface
=
2937 cs_prog_data
->binding_table
.work_groups_start
;
2939 cs_prog_data
->uses_num_work_groups
= true;
2941 fs_reg surf_index
= brw_imm_ud(surface
);
2942 brw_mark_surface_used(prog_data
, surface
);
2944 /* Read the 3 GLuint components of gl_NumWorkGroups */
2945 for (unsigned i
= 0; i
< 3; i
++) {
2946 fs_reg read_result
=
2947 emit_untyped_read(bld
, surf_index
,
2949 1 /* dims */, 1 /* size */,
2950 BRW_PREDICATE_NONE
);
2951 read_result
.type
= dest
.type
;
2952 bld
.MOV(dest
, read_result
);
2953 dest
= offset(dest
, bld
, 1);
2958 case nir_intrinsic_shared_atomic_add
:
2959 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2961 case nir_intrinsic_shared_atomic_imin
:
2962 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2964 case nir_intrinsic_shared_atomic_umin
:
2965 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2967 case nir_intrinsic_shared_atomic_imax
:
2968 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2970 case nir_intrinsic_shared_atomic_umax
:
2971 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2973 case nir_intrinsic_shared_atomic_and
:
2974 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2976 case nir_intrinsic_shared_atomic_or
:
2977 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2979 case nir_intrinsic_shared_atomic_xor
:
2980 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2982 case nir_intrinsic_shared_atomic_exchange
:
2983 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2985 case nir_intrinsic_shared_atomic_comp_swap
:
2986 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2989 case nir_intrinsic_load_shared
: {
2990 assert(devinfo
->gen
>= 7);
2992 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2994 /* Get the offset to read from */
2996 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2998 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3000 offset_reg
= vgrf(glsl_type::uint_type
);
3002 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3003 brw_imm_ud(instr
->const_index
[0]));
3006 /* Read the vector */
3007 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
3009 instr
->num_components
,
3010 BRW_PREDICATE_NONE
);
3011 read_result
.type
= dest
.type
;
3012 for (int i
= 0; i
< instr
->num_components
; i
++)
3013 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3018 case nir_intrinsic_store_shared
: {
3019 assert(devinfo
->gen
>= 7);
3022 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3025 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3028 unsigned writemask
= instr
->const_index
[1];
3030 /* Combine groups of consecutive enabled channels in one write
3031 * message. We use ffs to find the first enabled channel and then ffs on
3032 * the bit-inverse, down-shifted writemask to determine the length of
3033 * the block of enabled bits.
3036 unsigned first_component
= ffs(writemask
) - 1;
3037 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3040 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3042 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3043 4 * first_component
);
3045 offset_reg
= vgrf(glsl_type::uint_type
);
3047 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3048 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
3051 emit_untyped_write(bld
, surf_index
, offset_reg
,
3052 offset(val_reg
, bld
, first_component
),
3053 1 /* dims */, length
,
3054 BRW_PREDICATE_NONE
);
3056 /* Clear the bits in the writemask that we just wrote, then try
3057 * again to see if more channels are left.
3059 writemask
&= (15 << (first_component
+ length
));
3066 nir_emit_intrinsic(bld
, instr
);
3072 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3075 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3076 dest
= get_nir_dest(instr
->dest
);
3078 switch (instr
->intrinsic
) {
3079 case nir_intrinsic_atomic_counter_inc
:
3080 case nir_intrinsic_atomic_counter_dec
:
3081 case nir_intrinsic_atomic_counter_read
: {
3082 /* Get the arguments of the atomic intrinsic. */
3083 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3084 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3085 instr
->const_index
[0]);
3088 /* Emit a surface read or atomic op. */
3089 switch (instr
->intrinsic
) {
3090 case nir_intrinsic_atomic_counter_read
:
3091 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3094 case nir_intrinsic_atomic_counter_inc
:
3095 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3096 fs_reg(), 1, 1, BRW_AOP_INC
);
3099 case nir_intrinsic_atomic_counter_dec
:
3100 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3101 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3105 unreachable("Unreachable");
3108 /* Assign the result. */
3109 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3111 /* Mark the surface as used. */
3112 brw_mark_surface_used(stage_prog_data
, surface
);
3116 case nir_intrinsic_image_load
:
3117 case nir_intrinsic_image_store
:
3118 case nir_intrinsic_image_atomic_add
:
3119 case nir_intrinsic_image_atomic_min
:
3120 case nir_intrinsic_image_atomic_max
:
3121 case nir_intrinsic_image_atomic_and
:
3122 case nir_intrinsic_image_atomic_or
:
3123 case nir_intrinsic_image_atomic_xor
:
3124 case nir_intrinsic_image_atomic_exchange
:
3125 case nir_intrinsic_image_atomic_comp_swap
: {
3126 using namespace image_access
;
3128 /* Get the referenced image variable and type. */
3129 const nir_variable
*var
= instr
->variables
[0]->var
;
3130 const glsl_type
*type
= var
->type
->without_array();
3131 const brw_reg_type base_type
= get_image_base_type(type
);
3133 /* Get some metadata from the image intrinsic. */
3134 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3135 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3136 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3137 const unsigned format
= var
->data
.image
.format
;
3139 /* Get the arguments of the image intrinsic. */
3140 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3141 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3142 BRW_REGISTER_TYPE_UD
);
3143 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3144 retype(get_nir_src(instr
->src
[2]), base_type
) :
3146 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3147 retype(get_nir_src(instr
->src
[3]), base_type
) :
3151 /* Emit an image load, store or atomic op. */
3152 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3153 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3155 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3156 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3157 var
->data
.image
.write_only
? GL_NONE
: format
);
3160 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3161 surf_dims
, arr_dims
, info
->dest_components
,
3162 get_image_atomic_op(instr
->intrinsic
, type
));
3164 /* Assign the result. */
3165 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3166 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3167 offset(tmp
, bld
, c
));
3171 case nir_intrinsic_memory_barrier_atomic_counter
:
3172 case nir_intrinsic_memory_barrier_buffer
:
3173 case nir_intrinsic_memory_barrier_image
:
3174 case nir_intrinsic_memory_barrier
: {
3175 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
3176 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3181 case nir_intrinsic_group_memory_barrier
:
3182 case nir_intrinsic_memory_barrier_shared
:
3183 /* We treat these workgroup-level barriers as no-ops. This should be
3184 * safe at present and as long as:
3186 * - Memory access instructions are not subsequently reordered by the
3187 * compiler back-end.
3189 * - All threads from a given compute shader workgroup fit within a
3190 * single subslice and therefore talk to the same HDC shared unit
3191 * what supposedly guarantees ordering and coherency between threads
3192 * from the same workgroup. This may change in the future when we
3193 * start splitting workgroups across multiple subslices.
3195 * - The context is not in fault-and-stream mode, which could cause
3196 * memory transactions (including to SLM) prior to the barrier to be
3197 * replayed after the barrier if a pagefault occurs. This shouldn't
3198 * be a problem up to and including SKL because fault-and-stream is
3199 * not usable due to hardware issues, but that's likely to change in
3204 case nir_intrinsic_shader_clock
: {
3205 /* We cannot do anything if there is an event, so ignore it for now */
3206 fs_reg shader_clock
= get_timestamp(bld
);
3207 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3209 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3213 case nir_intrinsic_image_size
: {
3214 /* Get the referenced image variable and type. */
3215 const nir_variable
*var
= instr
->variables
[0]->var
;
3216 const glsl_type
*type
= var
->type
->without_array();
3218 /* Get the size of the image. */
3219 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3220 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3222 /* For 1DArray image types, the array index is stored in the Z component.
3223 * Fix this by swizzling the Z component to the Y component.
3225 const bool is_1d_array_image
=
3226 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3227 type
->sampler_array
;
3229 /* For CubeArray images, we should count the number of cubes instead
3230 * of the number of faces. Fix it by dividing the (Z component) by 6.
3232 const bool is_cube_array_image
=
3233 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3234 type
->sampler_array
;
3236 /* Copy all the components. */
3237 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3238 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3239 if ((int)c
>= type
->coordinate_components()) {
3240 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3242 } else if (c
== 1 && is_1d_array_image
) {
3243 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3244 offset(size
, bld
, 2));
3245 } else if (c
== 2 && is_cube_array_image
) {
3246 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3247 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3248 offset(size
, bld
, c
), brw_imm_d(6));
3250 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3251 offset(size
, bld
, c
));
3258 case nir_intrinsic_image_samples
:
3259 /* The driver does not support multi-sampled images. */
3260 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3263 case nir_intrinsic_load_uniform
: {
3264 /* Offsets are in bytes but they should always be multiples of 4 */
3265 assert(instr
->const_index
[0] % 4 == 0);
3267 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3269 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3271 /* Offsets are in bytes but they should always be multiples of 4 */
3272 assert(const_offset
->u32
[0] % 4 == 0);
3273 src
.reg_offset
= const_offset
->u32
[0] / 4;
3275 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3276 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3279 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3280 BRW_REGISTER_TYPE_UD
);
3282 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3283 * go past the end of the uniform. In order to keep the n'th
3284 * component from running past, we subtract off the size of all but
3285 * one component of the vector.
3287 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
3288 unsigned read_size
= instr
->const_index
[1] -
3289 (instr
->num_components
- 1) * 4;
3291 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3292 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3293 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3294 indirect
, brw_imm_ud(read_size
));
3300 case nir_intrinsic_load_ubo
: {
3301 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3305 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3306 const_index
->u32
[0];
3307 surf_index
= brw_imm_ud(index
);
3308 brw_mark_surface_used(prog_data
, index
);
3310 /* The block index is not a constant. Evaluate the index expression
3311 * per-channel and add the base UBO index; we have to select a value
3312 * from any live channel.
3314 surf_index
= vgrf(glsl_type::uint_type
);
3315 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3316 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3317 surf_index
= bld
.emit_uniformize(surf_index
);
3319 /* Assume this may touch any UBO. It would be nice to provide
3320 * a tighter bound, but the array information is already lowered away.
3322 brw_mark_surface_used(prog_data
,
3323 stage_prog_data
->binding_table
.ubo_start
+
3324 nir
->info
.num_ubos
- 1);
3327 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3328 if (const_offset
== NULL
) {
3329 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3330 BRW_REGISTER_TYPE_UD
);
3332 for (int i
= 0; i
< instr
->num_components
; i
++)
3333 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3334 base_offset
, i
* 4);
3336 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
3337 packed_consts
.type
= dest
.type
;
3339 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
3340 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
3341 surf_index
, const_offset_reg
);
3343 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3344 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
3346 /* The std140 packing rules don't allow vectors to cross 16-byte
3347 * boundaries, and a reg is 32 bytes.
3349 assert(packed_consts
.subreg_offset
< 32);
3351 bld
.MOV(dest
, packed_consts
);
3352 dest
= offset(dest
, bld
, 1);
3358 case nir_intrinsic_load_ssbo
: {
3359 assert(devinfo
->gen
>= 7);
3361 nir_const_value
*const_uniform_block
=
3362 nir_src_as_const_value(instr
->src
[0]);
3365 if (const_uniform_block
) {
3366 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3367 const_uniform_block
->u32
[0];
3368 surf_index
= brw_imm_ud(index
);
3369 brw_mark_surface_used(prog_data
, index
);
3371 surf_index
= vgrf(glsl_type::uint_type
);
3372 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3373 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3375 /* Assume this may touch any UBO. It would be nice to provide
3376 * a tighter bound, but the array information is already lowered away.
3378 brw_mark_surface_used(prog_data
,
3379 stage_prog_data
->binding_table
.ssbo_start
+
3380 nir
->info
.num_ssbos
- 1);
3384 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3386 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3388 offset_reg
= get_nir_src(instr
->src
[1]);
3391 /* Read the vector */
3392 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
3394 instr
->num_components
,
3395 BRW_PREDICATE_NONE
);
3396 read_result
.type
= dest
.type
;
3397 for (int i
= 0; i
< instr
->num_components
; i
++)
3398 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3403 case nir_intrinsic_load_input
: {
3405 if (stage
== MESA_SHADER_VERTEX
) {
3406 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3408 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3409 instr
->const_index
[0]);
3412 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3413 assert(const_offset
&& "Indirect input loads not allowed");
3414 src
= offset(src
, bld
, const_offset
->u32
[0]);
3416 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3417 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3422 case nir_intrinsic_store_ssbo
: {
3423 assert(devinfo
->gen
>= 7);
3427 nir_const_value
*const_uniform_block
=
3428 nir_src_as_const_value(instr
->src
[1]);
3429 if (const_uniform_block
) {
3430 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3431 const_uniform_block
->u32
[0];
3432 surf_index
= brw_imm_ud(index
);
3433 brw_mark_surface_used(prog_data
, index
);
3435 surf_index
= vgrf(glsl_type::uint_type
);
3436 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3437 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3439 brw_mark_surface_used(prog_data
,
3440 stage_prog_data
->binding_table
.ssbo_start
+
3441 nir
->info
.num_ssbos
- 1);
3445 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3448 unsigned writemask
= instr
->const_index
[0];
3450 /* Combine groups of consecutive enabled channels in one write
3451 * message. We use ffs to find the first enabled channel and then ffs on
3452 * the bit-inverse, down-shifted writemask to determine the length of
3453 * the block of enabled bits.
3456 unsigned first_component
= ffs(writemask
) - 1;
3457 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3460 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3462 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
3464 offset_reg
= vgrf(glsl_type::uint_type
);
3466 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3467 brw_imm_ud(4 * first_component
));
3470 emit_untyped_write(bld
, surf_index
, offset_reg
,
3471 offset(val_reg
, bld
, first_component
),
3472 1 /* dims */, length
,
3473 BRW_PREDICATE_NONE
);
3475 /* Clear the bits in the writemask that we just wrote, then try
3476 * again to see if more channels are left.
3478 writemask
&= (15 << (first_component
+ length
));
3483 case nir_intrinsic_store_output
: {
3484 fs_reg src
= get_nir_src(instr
->src
[0]);
3485 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3486 instr
->const_index
[0]);
3488 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3489 assert(const_offset
&& "Indirect output stores not allowed");
3490 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3492 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3493 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
3498 case nir_intrinsic_ssbo_atomic_add
:
3499 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
3501 case nir_intrinsic_ssbo_atomic_imin
:
3502 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
3504 case nir_intrinsic_ssbo_atomic_umin
:
3505 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
3507 case nir_intrinsic_ssbo_atomic_imax
:
3508 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
3510 case nir_intrinsic_ssbo_atomic_umax
:
3511 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
3513 case nir_intrinsic_ssbo_atomic_and
:
3514 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
3516 case nir_intrinsic_ssbo_atomic_or
:
3517 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
3519 case nir_intrinsic_ssbo_atomic_xor
:
3520 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
3522 case nir_intrinsic_ssbo_atomic_exchange
:
3523 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
3525 case nir_intrinsic_ssbo_atomic_comp_swap
:
3526 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3529 case nir_intrinsic_get_buffer_size
: {
3530 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
3531 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
3532 int reg_width
= dispatch_width
/ 8;
3535 fs_reg source
= brw_imm_d(0);
3537 int mlen
= 1 * reg_width
;
3539 /* A resinfo's sampler message is used to get the buffer size.
3540 * The SIMD8's writeback message consists of four registers and
3541 * SIMD16's writeback message consists of 8 destination registers
3542 * (two per each component), although we are only interested on the
3543 * first component, where resinfo returns the buffer size for
3546 int regs_written
= 4 * mlen
;
3547 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
3548 BRW_REGISTER_TYPE_UD
);
3549 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
3550 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
3551 BRW_REGISTER_TYPE_UD
);
3552 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
3553 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
3554 src_payload
, brw_imm_ud(index
));
3555 inst
->header_size
= 0;
3557 inst
->regs_written
= regs_written
;
3559 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
3561 brw_mark_surface_used(prog_data
, index
);
3566 unreachable("unknown intrinsic");
3571 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
3572 int op
, nir_intrinsic_instr
*instr
)
3575 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3576 dest
= get_nir_dest(instr
->dest
);
3579 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3580 if (const_surface
) {
3581 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3582 const_surface
->u32
[0];
3583 surface
= brw_imm_ud(surf_index
);
3584 brw_mark_surface_used(prog_data
, surf_index
);
3586 surface
= vgrf(glsl_type::uint_type
);
3587 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3588 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3590 /* Assume this may touch any SSBO. This is the same we do for other
3591 * UBO/SSBO accesses with non-constant surface.
3593 brw_mark_surface_used(prog_data
,
3594 stage_prog_data
->binding_table
.ssbo_start
+
3595 nir
->info
.num_ssbos
- 1);
3598 fs_reg offset
= get_nir_src(instr
->src
[1]);
3599 fs_reg data1
= get_nir_src(instr
->src
[2]);
3601 if (op
== BRW_AOP_CMPWR
)
3602 data2
= get_nir_src(instr
->src
[3]);
3604 /* Emit the actual atomic operation operation */
3606 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3608 1 /* dims */, 1 /* rsize */,
3610 BRW_PREDICATE_NONE
);
3611 dest
.type
= atomic_result
.type
;
3612 bld
.MOV(dest
, atomic_result
);
3616 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3617 int op
, nir_intrinsic_instr
*instr
)
3620 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3621 dest
= get_nir_dest(instr
->dest
);
3623 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3624 fs_reg offset
= get_nir_src(instr
->src
[0]);
3625 fs_reg data1
= get_nir_src(instr
->src
[1]);
3627 if (op
== BRW_AOP_CMPWR
)
3628 data2
= get_nir_src(instr
->src
[2]);
3630 /* Emit the actual atomic operation operation */
3632 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3634 1 /* dims */, 1 /* rsize */,
3636 BRW_PREDICATE_NONE
);
3637 dest
.type
= atomic_result
.type
;
3638 bld
.MOV(dest
, atomic_result
);
3642 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3644 unsigned texture
= instr
->texture_index
;
3645 unsigned sampler
= instr
->sampler_index
;
3647 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3649 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
3650 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
3652 int lod_components
= 0;
3654 /* The hardware requires a LOD for buffer textures */
3655 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3656 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
3658 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3659 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3660 switch (instr
->src
[i
].src_type
) {
3661 case nir_tex_src_bias
:
3662 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3664 case nir_tex_src_comparitor
:
3665 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
3667 case nir_tex_src_coord
:
3668 switch (instr
->op
) {
3670 case nir_texop_txf_ms
:
3671 case nir_texop_samples_identical
:
3672 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
3675 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
3679 case nir_tex_src_ddx
:
3680 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3681 lod_components
= nir_tex_instr_src_size(instr
, i
);
3683 case nir_tex_src_ddy
:
3684 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
3686 case nir_tex_src_lod
:
3687 switch (instr
->op
) {
3689 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3692 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_D
);
3695 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3699 case nir_tex_src_ms_index
:
3700 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3703 case nir_tex_src_offset
: {
3704 nir_const_value
*const_offset
=
3705 nir_src_as_const_value(instr
->src
[i
].src
);
3707 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
3708 if (header_bits
!= 0)
3709 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
3711 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
3712 retype(src
, BRW_REGISTER_TYPE_D
);
3717 case nir_tex_src_projector
:
3718 unreachable("should be lowered");
3720 case nir_tex_src_texture_offset
: {
3721 /* Figure out the highest possible texture index and mark it as used */
3722 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3723 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3724 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3726 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3728 brw_mark_surface_used(prog_data
, max_used
);
3730 /* Emit code to evaluate the actual indexing expression */
3731 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3732 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
3733 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
3737 case nir_tex_src_sampler_offset
: {
3738 /* Emit code to evaluate the actual indexing expression */
3739 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3740 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
3741 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
3746 unreachable("unknown texture source");
3750 if (instr
->op
== nir_texop_txf_ms
||
3751 instr
->op
== nir_texop_samples_identical
) {
3752 if (devinfo
->gen
>= 7 &&
3753 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3754 srcs
[TEX_LOGICAL_SRC_MCS
] =
3755 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
3756 instr
->coord_components
,
3757 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3759 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
3763 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
3764 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
3766 if (instr
->op
== nir_texop_query_levels
) {
3767 /* textureQueryLevels() is implemented in terms of TXS so we need to
3768 * pass a valid LOD argument.
3770 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
3771 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
3775 switch (instr
->op
) {
3777 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
3780 opcode
= FS_OPCODE_TXB_LOGICAL
;
3783 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
3786 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
3789 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
3791 case nir_texop_txf_ms
:
3792 if ((key_tex
->msaa_16
& (1 << sampler
)))
3793 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
3795 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
3797 case nir_texop_query_levels
:
3799 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
3802 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
3805 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
3806 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
3807 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
3809 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
3811 case nir_texop_texture_samples
: {
3812 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3814 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 4);
3815 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, tmp
,
3816 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3817 srcs
[TEX_LOGICAL_SRC_SURFACE
],
3818 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3820 inst
->header_size
= 1;
3821 inst
->base_mrf
= -1;
3822 inst
->regs_written
= 4 * (dispatch_width
/ 8);
3824 /* Pick off the one component we care about */
3828 case nir_texop_samples_identical
: {
3829 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3831 /* If mcs is an immediate value, it means there is no MCS. In that case
3832 * just return false.
3834 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
3835 bld
.MOV(dst
, brw_imm_ud(0u));
3836 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
3837 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3838 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
3839 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
3840 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
3842 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
3843 BRW_CONDITIONAL_EQ
);
3848 unreachable("unknown texture opcode");
3851 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
3852 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
3854 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
3855 if (devinfo
->gen
>= 9 &&
3856 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
3857 unsigned write_mask
= instr
->dest
.is_ssa
?
3858 nir_ssa_def_components_read(&instr
->dest
.ssa
):
3859 (1 << dest_size
) - 1;
3860 assert(write_mask
!= 0); /* dead code should have been eliminated */
3861 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
3863 inst
->regs_written
= 4 * dispatch_width
/ 8;
3866 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
3867 inst
->shadow_compare
= true;
3869 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
3870 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
3872 if (instr
->op
== nir_texop_tg4
) {
3873 if (instr
->component
== 1 &&
3874 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
3875 /* gather4 sampler is broken for green channel on RG32F --
3876 * we must ask for blue instead.
3878 inst
->offset
|= 2 << 16;
3880 inst
->offset
|= instr
->component
<< 16;
3883 if (devinfo
->gen
== 6)
3884 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
3888 for (unsigned i
= 0; i
< dest_size
; i
++)
3889 nir_dest
[i
] = offset(dst
, bld
, i
);
3891 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3894 if (instr
->op
== nir_texop_query_levels
) {
3895 /* # levels is in .w */
3896 nir_dest
[0] = offset(dst
, bld
, 3);
3897 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
3898 (devinfo
->gen
< 7 || is_cube_array
)) {
3899 fs_reg depth
= offset(dst
, bld
, 2);
3900 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
3902 if (is_cube_array
) {
3903 /* fixup #layers for cube map arrays */
3904 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
3905 } else if (devinfo
->gen
< 7) {
3906 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
3907 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
3910 nir_dest
[2] = fixed_depth
;
3913 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
3917 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3919 switch (instr
->type
) {
3920 case nir_jump_break
:
3921 bld
.emit(BRW_OPCODE_BREAK
);
3923 case nir_jump_continue
:
3924 bld
.emit(BRW_OPCODE_CONTINUE
);
3926 case nir_jump_return
:
3928 unreachable("unknown jump");