2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
66 var
->data
.origin_upper_left
);
67 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
69 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
70 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
71 reg
.type
= BRW_REGISTER_TYPE_D
;
72 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
73 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
74 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
75 reg
.type
= BRW_REGISTER_TYPE_D
;
76 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
78 int location
= var
->data
.location
;
79 emit_general_interpolation(&input
, var
->name
, var
->type
,
80 (glsl_interp_qualifier
) var
->data
.interpolation
,
81 &location
, var
->data
.centroid
,
88 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
89 const glsl_type
*type
,
92 if (type
->is_array() || type
->is_matrix()) {
93 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
94 const unsigned length
= glsl_get_length(type
);
96 for (unsigned i
= 0; i
< length
; i
++) {
97 nir_setup_single_output_varying(reg
, elem_type
, location
);
99 } else if (type
->is_record()) {
100 for (unsigned i
= 0; i
< type
->length
; i
++) {
101 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
102 nir_setup_single_output_varying(reg
, field_type
, location
);
105 assert(type
->is_scalar() || type
->is_vector());
106 this->outputs
[*location
] = *reg
;
107 this->output_components
[*location
] = type
->vector_elements
;
108 *reg
= offset(*reg
, bld
, 4);
114 fs_visitor::nir_setup_outputs()
116 if (stage
== MESA_SHADER_TESS_CTRL
)
119 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
121 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
123 nir_foreach_variable(var
, &nir
->outputs
) {
124 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 case MESA_SHADER_VERTEX
:
128 case MESA_SHADER_TESS_EVAL
:
129 case MESA_SHADER_GEOMETRY
: {
130 unsigned location
= var
->data
.location
;
131 nir_setup_single_output_varying(®
, var
->type
, &location
);
134 case MESA_SHADER_FRAGMENT
:
135 if (key
->force_dual_color_blend
&&
136 var
->data
.location
== FRAG_RESULT_DATA1
) {
137 this->dual_src_output
= reg
;
138 this->do_dual_src
= true;
139 } else if (var
->data
.index
> 0) {
140 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
141 assert(var
->data
.index
== 1);
142 this->dual_src_output
= reg
;
143 this->do_dual_src
= true;
144 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
145 /* Writing gl_FragColor outputs to all color regions. */
146 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
147 this->outputs
[i
] = reg
;
148 this->output_components
[i
] = 4;
150 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
151 this->frag_depth
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
153 this->frag_stencil
= reg
;
154 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
155 this->sample_mask
= reg
;
157 int vector_elements
= var
->type
->without_array()->vector_elements
;
159 /* gl_FragData or a user-defined FS output */
160 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
161 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
163 /* General color output. */
164 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
165 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
166 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
167 this->output_components
[output
] = vector_elements
;
172 unreachable("unhandled shader stage");
178 fs_visitor::nir_setup_uniforms()
180 if (dispatch_width
!= 8)
183 uniforms
= nir
->num_uniforms
/ 4;
187 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
191 nir_foreach_instr(instr
, block
) {
192 if (instr
->type
!= nir_instr_type_intrinsic
)
195 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
196 switch (intrin
->intrinsic
) {
197 case nir_intrinsic_load_vertex_id
:
198 unreachable("should be lowered by lower_vertex_id().");
200 case nir_intrinsic_load_vertex_id_zero_base
:
201 assert(v
->stage
== MESA_SHADER_VERTEX
);
202 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
203 if (reg
->file
== BAD_FILE
)
204 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
207 case nir_intrinsic_load_base_vertex
:
208 assert(v
->stage
== MESA_SHADER_VERTEX
);
209 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
210 if (reg
->file
== BAD_FILE
)
211 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
214 case nir_intrinsic_load_instance_id
:
215 assert(v
->stage
== MESA_SHADER_VERTEX
);
216 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
217 if (reg
->file
== BAD_FILE
)
218 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
221 case nir_intrinsic_load_base_instance
:
222 assert(v
->stage
== MESA_SHADER_VERTEX
);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
228 case nir_intrinsic_load_draw_id
:
229 assert(v
->stage
== MESA_SHADER_VERTEX
);
230 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
231 if (reg
->file
== BAD_FILE
)
232 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
235 case nir_intrinsic_load_invocation_id
:
236 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
238 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
240 if (reg
->file
== BAD_FILE
) {
241 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
242 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
243 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
244 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
249 case nir_intrinsic_load_sample_pos
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
252 if (reg
->file
== BAD_FILE
)
253 *reg
= *v
->emit_samplepos_setup();
256 case nir_intrinsic_load_sample_id
:
257 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
258 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
259 if (reg
->file
== BAD_FILE
)
260 *reg
= *v
->emit_sampleid_setup();
263 case nir_intrinsic_load_sample_mask_in
:
264 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
265 assert(v
->devinfo
->gen
>= 7);
266 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
267 if (reg
->file
== BAD_FILE
)
268 *reg
= *v
->emit_samplemaskin_setup();
271 case nir_intrinsic_load_local_invocation_id
:
272 assert(v
->stage
== MESA_SHADER_COMPUTE
);
273 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
274 if (reg
->file
== BAD_FILE
)
275 *reg
= *v
->emit_cs_local_invocation_id_setup();
278 case nir_intrinsic_load_work_group_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_work_group_id_setup();
285 case nir_intrinsic_load_helper_invocation
:
286 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
288 if (reg
->file
== BAD_FILE
) {
289 const fs_builder abld
=
290 v
->bld
.annotate("gl_HelperInvocation", NULL
);
292 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
293 * pixel mask is in g1.7 of the thread payload.
295 * We move the per-channel pixel enable bit to the low bit of each
296 * channel by shifting the byte containing the pixel mask by the
297 * vector immediate 0x76543210UV.
299 * The region of <1,8,0> reads only 1 byte (the pixel masks for
300 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
301 * masks for 2 and 3) in SIMD16.
303 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
305 stride(byte_offset(retype(brw_vec1_grf(1, 0),
306 BRW_REGISTER_TYPE_UB
), 28),
308 brw_imm_uv(0x76543210));
310 /* A set bit in the pixel mask means the channel is enabled, but
311 * that is the opposite of gl_HelperInvocation so we need to invert
314 * The negate source-modifier bit of logical instructions on Gen8+
315 * performs 1's complement negation, so we can use that instead of
318 fs_reg inverted
= negate(shifted
);
319 if (v
->devinfo
->gen
< 8) {
320 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
321 abld
.NOT(inverted
, shifted
);
324 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
325 * with 1 and negating.
327 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
328 abld
.AND(anded
, inverted
, brw_imm_uw(1));
330 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
331 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
345 fs_visitor::nir_emit_system_values()
347 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
348 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
349 nir_system_values
[i
] = fs_reg();
352 nir_foreach_function(function
, nir
) {
353 assert(strcmp(function
->name
, "main") == 0);
354 assert(function
->impl
);
355 nir_foreach_block(block
, function
->impl
) {
356 emit_system_values_block(block
, this);
362 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
364 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
365 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
366 nir_locals
[i
] = fs_reg();
369 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
370 unsigned array_elems
=
371 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
372 unsigned size
= array_elems
* reg
->num_components
;
373 const brw_reg_type reg_type
=
374 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
375 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
378 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
381 nir_emit_cf_list(&impl
->body
);
385 fs_visitor::nir_emit_cf_list(exec_list
*list
)
387 exec_list_validate(list
);
388 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
389 switch (node
->type
) {
391 nir_emit_if(nir_cf_node_as_if(node
));
394 case nir_cf_node_loop
:
395 nir_emit_loop(nir_cf_node_as_loop(node
));
398 case nir_cf_node_block
:
399 nir_emit_block(nir_cf_node_as_block(node
));
403 unreachable("Invalid CFG node block");
409 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
411 /* first, put the condition into f0 */
412 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
413 retype(get_nir_src(if_stmt
->condition
),
414 BRW_REGISTER_TYPE_D
));
415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
417 bld
.IF(BRW_PREDICATE_NORMAL
);
419 nir_emit_cf_list(&if_stmt
->then_list
);
421 /* note: if the else is empty, dead CF elimination will remove it */
422 bld
.emit(BRW_OPCODE_ELSE
);
424 nir_emit_cf_list(&if_stmt
->else_list
);
426 bld
.emit(BRW_OPCODE_ENDIF
);
430 fs_visitor::nir_emit_loop(nir_loop
*loop
)
432 bld
.emit(BRW_OPCODE_DO
);
434 nir_emit_cf_list(&loop
->body
);
436 bld
.emit(BRW_OPCODE_WHILE
);
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
457 case nir_instr_type_intrinsic
:
459 case MESA_SHADER_VERTEX
:
460 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_TESS_CTRL
:
463 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_EVAL
:
466 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_GEOMETRY
:
469 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_FRAGMENT
:
472 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_COMPUTE
:
475 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 unreachable("unsupported shader stage");
482 case nir_instr_type_tex
:
483 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
486 case nir_instr_type_load_const
:
487 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
490 case nir_instr_type_ssa_undef
:
491 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
494 case nir_instr_type_jump
:
495 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
499 unreachable("unknown instruction type");
504 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
508 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
509 const fs_reg
&result
)
511 if (!instr
->src
[0].src
.is_ssa
||
512 !instr
->src
[0].src
.ssa
->parent_instr
)
515 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
518 nir_alu_instr
*src0
=
519 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
521 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
522 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
525 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
526 assert(element
!= NULL
);
528 enum opcode extract_op
;
529 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
530 assert(element
->u32
[0] <= 1);
531 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
533 assert(element
->u32
[0] <= 3);
534 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
537 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
538 op0
.type
= brw_type_for_nir_type(
539 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
540 nir_src_bit_size(src0
->src
[0].src
)));
541 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
543 set_saturate(instr
->dest
.saturate
,
544 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
549 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
550 const fs_reg
&result
)
552 if (!instr
->src
[0].src
.is_ssa
||
553 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
556 nir_intrinsic_instr
*src0
=
557 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
559 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
562 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
563 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
566 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
567 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
570 fs_reg tmp
= vgrf(glsl_type::int_type
);
572 if (devinfo
->gen
>= 6) {
573 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
574 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
576 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
578 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
579 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
581 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
583 * This negation looks like it's safe in practice, because bits 0:4 will
584 * surely be TRIANGLES
587 if (value1
->f32
[0] == -1.0f
) {
591 tmp
.type
= BRW_REGISTER_TYPE_W
;
592 tmp
.subreg_offset
= 2;
595 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
597 tmp
.type
= BRW_REGISTER_TYPE_D
;
598 tmp
.subreg_offset
= 0;
601 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
602 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
604 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
606 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
607 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
609 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
611 * This negation looks like it's safe in practice, because bits 0:4 will
612 * surely be TRIANGLES
615 if (value1
->f32
[0] == -1.0f
) {
619 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
621 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
627 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
629 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
632 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
633 result
.type
= brw_type_for_nir_type(
634 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
635 nir_dest_bit_size(instr
->dest
.dest
)));
638 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 op
[i
] = get_nir_src(instr
->src
[i
].src
);
640 op
[i
].type
= brw_type_for_nir_type(
641 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
642 nir_src_bit_size(instr
->src
[i
].src
)));
643 op
[i
].abs
= instr
->src
[i
].abs
;
644 op
[i
].negate
= instr
->src
[i
].negate
;
647 /* We get a bunch of mov's out of the from_ssa pass and they may still
648 * be vectorized. We'll handle them as a special-case. We'll also
649 * handle vecN here because it's basically the same thing.
657 fs_reg temp
= result
;
658 bool need_extra_copy
= false;
659 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
660 if (!instr
->src
[i
].src
.is_ssa
&&
661 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
662 need_extra_copy
= true;
663 temp
= bld
.vgrf(result
.type
, 4);
668 for (unsigned i
= 0; i
< 4; i
++) {
669 if (!(instr
->dest
.write_mask
& (1 << i
)))
672 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
673 inst
= bld
.MOV(offset(temp
, bld
, i
),
674 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
676 inst
= bld
.MOV(offset(temp
, bld
, i
),
677 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
679 inst
->saturate
= instr
->dest
.saturate
;
682 /* In this case the source and destination registers were the same,
683 * so we need to insert an extra set of moves in order to deal with
686 if (need_extra_copy
) {
687 for (unsigned i
= 0; i
< 4; i
++) {
688 if (!(instr
->dest
.write_mask
& (1 << i
)))
691 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
700 /* At this point, we have dealt with any instruction that operates on
701 * more than a single channel. Therefore, we can just adjust the source
702 * and destination registers for that channel and emit the instruction.
704 unsigned channel
= 0;
705 if (nir_op_infos
[instr
->op
].output_size
== 0) {
706 /* Since NIR is doing the scalarizing for us, we should only ever see
707 * vectorized operations with a single channel.
709 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
710 channel
= ffs(instr
->dest
.write_mask
) - 1;
712 result
= offset(result
, bld
, channel
);
715 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
716 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
717 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
723 if (optimize_extract_to_float(instr
, result
))
726 inst
= bld
.MOV(result
, op
[0]);
727 inst
->saturate
= instr
->dest
.saturate
;
732 bld
.MOV(result
, op
[0]);
736 /* AND(val, 0x80000000) gives the sign bit.
738 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
741 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
743 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
744 op
[0].type
= BRW_REGISTER_TYPE_UD
;
745 result
.type
= BRW_REGISTER_TYPE_UD
;
746 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
748 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
749 inst
->predicate
= BRW_PREDICATE_NORMAL
;
750 if (instr
->dest
.saturate
) {
751 inst
= bld
.MOV(result
, result
);
752 inst
->saturate
= true;
758 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
759 * -> non-negative val generates 0x00000000.
760 * Predicated OR sets 1 if val is positive.
762 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
763 bld
.ASR(result
, op
[0], brw_imm_d(31));
764 inst
= bld
.OR(result
, result
, brw_imm_d(1));
765 inst
->predicate
= BRW_PREDICATE_NORMAL
;
769 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
770 inst
->saturate
= instr
->dest
.saturate
;
774 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
775 inst
->saturate
= instr
->dest
.saturate
;
779 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
780 inst
->saturate
= instr
->dest
.saturate
;
784 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
785 inst
->saturate
= instr
->dest
.saturate
;
789 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
790 inst
->saturate
= instr
->dest
.saturate
;
794 if (fs_key
->high_quality_derivatives
) {
795 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
797 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
799 inst
->saturate
= instr
->dest
.saturate
;
801 case nir_op_fddx_fine
:
802 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
803 inst
->saturate
= instr
->dest
.saturate
;
805 case nir_op_fddx_coarse
:
806 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
807 inst
->saturate
= instr
->dest
.saturate
;
810 if (fs_key
->high_quality_derivatives
) {
811 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
812 brw_imm_d(fs_key
->render_to_fbo
));
814 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
815 brw_imm_d(fs_key
->render_to_fbo
));
817 inst
->saturate
= instr
->dest
.saturate
;
819 case nir_op_fddy_fine
:
820 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
821 brw_imm_d(fs_key
->render_to_fbo
));
822 inst
->saturate
= instr
->dest
.saturate
;
824 case nir_op_fddy_coarse
:
825 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
826 brw_imm_d(fs_key
->render_to_fbo
));
827 inst
->saturate
= instr
->dest
.saturate
;
832 inst
= bld
.ADD(result
, op
[0], op
[1]);
833 inst
->saturate
= instr
->dest
.saturate
;
837 inst
= bld
.MUL(result
, op
[0], op
[1]);
838 inst
->saturate
= instr
->dest
.saturate
;
842 bld
.MUL(result
, op
[0], op
[1]);
845 case nir_op_imul_high
:
846 case nir_op_umul_high
:
847 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
852 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
855 case nir_op_uadd_carry
:
856 unreachable("Should have been lowered by carry_to_arith().");
858 case nir_op_usub_borrow
:
859 unreachable("Should have been lowered by borrow_to_arith().");
863 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
864 * appears that our hardware just does the right thing for signed
867 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
871 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
872 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
874 /* Math instructions don't support conditional mod */
875 inst
= bld
.MOV(bld
.null_reg_d(), result
);
876 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
878 /* Now, we need to determine if signs of the sources are different.
879 * When we XOR the sources, the top bit is 0 if they are the same and 1
880 * if they are different. We can then use a conditional modifier to
881 * turn that into a predicate. This leads us to an XOR.l instruction.
883 * Technically, according to the PRM, you're not allowed to use .l on a
884 * XOR instruction. However, emperical experiments and Curro's reading
885 * of the simulator source both indicate that it's safe.
887 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
888 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
889 inst
->predicate
= BRW_PREDICATE_NORMAL
;
890 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
892 /* If the result of the initial remainder operation is non-zero and the
893 * two sources have different signs, add in a copy of op[1] to get the
894 * final integer modulus value.
896 inst
= bld
.ADD(result
, result
, op
[1]);
897 inst
->predicate
= BRW_PREDICATE_NORMAL
;
904 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
910 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
915 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
920 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
924 if (devinfo
->gen
>= 8) {
925 op
[0] = resolve_source_modifiers(op
[0]);
927 bld
.NOT(result
, op
[0]);
930 if (devinfo
->gen
>= 8) {
931 op
[0] = resolve_source_modifiers(op
[0]);
932 op
[1] = resolve_source_modifiers(op
[1]);
934 bld
.XOR(result
, op
[0], op
[1]);
937 if (devinfo
->gen
>= 8) {
938 op
[0] = resolve_source_modifiers(op
[0]);
939 op
[1] = resolve_source_modifiers(op
[1]);
941 bld
.OR(result
, op
[0], op
[1]);
944 if (devinfo
->gen
>= 8) {
945 op
[0] = resolve_source_modifiers(op
[0]);
946 op
[1] = resolve_source_modifiers(op
[1]);
948 bld
.AND(result
, op
[0], op
[1]);
954 case nir_op_ball_fequal2
:
955 case nir_op_ball_iequal2
:
956 case nir_op_ball_fequal3
:
957 case nir_op_ball_iequal3
:
958 case nir_op_ball_fequal4
:
959 case nir_op_ball_iequal4
:
960 case nir_op_bany_fnequal2
:
961 case nir_op_bany_inequal2
:
962 case nir_op_bany_fnequal3
:
963 case nir_op_bany_inequal3
:
964 case nir_op_bany_fnequal4
:
965 case nir_op_bany_inequal4
:
966 unreachable("Lowered by nir_lower_alu_reductions");
968 case nir_op_fnoise1_1
:
969 case nir_op_fnoise1_2
:
970 case nir_op_fnoise1_3
:
971 case nir_op_fnoise1_4
:
972 case nir_op_fnoise2_1
:
973 case nir_op_fnoise2_2
:
974 case nir_op_fnoise2_3
:
975 case nir_op_fnoise2_4
:
976 case nir_op_fnoise3_1
:
977 case nir_op_fnoise3_2
:
978 case nir_op_fnoise3_3
:
979 case nir_op_fnoise3_4
:
980 case nir_op_fnoise4_1
:
981 case nir_op_fnoise4_2
:
982 case nir_op_fnoise4_3
:
983 case nir_op_fnoise4_4
:
984 unreachable("not reached: should be handled by lower_noise");
987 unreachable("not reached: should be handled by ldexp_to_arith()");
990 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
991 inst
->saturate
= instr
->dest
.saturate
;
995 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
996 inst
->saturate
= instr
->dest
.saturate
;
1001 bld
.MOV(result
, negate(op
[0]));
1005 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1008 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1012 inst
= bld
.RNDZ(result
, op
[0]);
1013 inst
->saturate
= instr
->dest
.saturate
;
1016 case nir_op_fceil
: {
1017 op
[0].negate
= !op
[0].negate
;
1018 fs_reg temp
= vgrf(glsl_type::float_type
);
1019 bld
.RNDD(temp
, op
[0]);
1021 inst
= bld
.MOV(result
, temp
);
1022 inst
->saturate
= instr
->dest
.saturate
;
1026 inst
= bld
.RNDD(result
, op
[0]);
1027 inst
->saturate
= instr
->dest
.saturate
;
1030 inst
= bld
.FRC(result
, op
[0]);
1031 inst
->saturate
= instr
->dest
.saturate
;
1033 case nir_op_fround_even
:
1034 inst
= bld
.RNDE(result
, op
[0]);
1035 inst
->saturate
= instr
->dest
.saturate
;
1038 case nir_op_fquantize2f16
: {
1039 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1040 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1041 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1043 /* The destination stride must be at least as big as the source stride. */
1044 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1047 /* Check for denormal */
1048 fs_reg abs_src0
= op
[0];
1049 abs_src0
.abs
= true;
1050 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1052 /* Get the appropriately signed zero */
1053 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1054 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1055 brw_imm_ud(0x80000000));
1056 /* Do the actual F32 -> F16 -> F32 conversion */
1057 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1058 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1059 /* Select that or zero based on normal status */
1060 inst
= bld
.SEL(result
, zero
, tmp32
);
1061 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1062 inst
->saturate
= instr
->dest
.saturate
;
1069 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1070 inst
->saturate
= instr
->dest
.saturate
;
1076 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1077 inst
->saturate
= instr
->dest
.saturate
;
1080 case nir_op_pack_snorm_2x16
:
1081 case nir_op_pack_snorm_4x8
:
1082 case nir_op_pack_unorm_2x16
:
1083 case nir_op_pack_unorm_4x8
:
1084 case nir_op_unpack_snorm_2x16
:
1085 case nir_op_unpack_snorm_4x8
:
1086 case nir_op_unpack_unorm_2x16
:
1087 case nir_op_unpack_unorm_4x8
:
1088 case nir_op_unpack_half_2x16
:
1089 case nir_op_pack_half_2x16
:
1090 unreachable("not reached: should be handled by lower_packing_builtins");
1092 case nir_op_unpack_half_2x16_split_x
:
1093 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1094 inst
->saturate
= instr
->dest
.saturate
;
1096 case nir_op_unpack_half_2x16_split_y
:
1097 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1098 inst
->saturate
= instr
->dest
.saturate
;
1102 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1103 inst
->saturate
= instr
->dest
.saturate
;
1106 case nir_op_bitfield_reverse
:
1107 bld
.BFREV(result
, op
[0]);
1110 case nir_op_bit_count
:
1111 bld
.CBIT(result
, op
[0]);
1114 case nir_op_ufind_msb
:
1115 case nir_op_ifind_msb
: {
1116 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1118 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1119 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1120 * subtract the result from 31 to convert the MSB count into an LSB count.
1122 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1124 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1125 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1126 inst
->src
[0].negate
= true;
1130 case nir_op_find_lsb
:
1131 bld
.FBL(result
, op
[0]);
1134 case nir_op_ubitfield_extract
:
1135 case nir_op_ibitfield_extract
:
1136 unreachable("should have been lowered");
1139 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1142 bld
.BFI1(result
, op
[0], op
[1]);
1145 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1148 case nir_op_bitfield_insert
:
1149 unreachable("not reached: should have been lowered");
1152 bld
.SHL(result
, op
[0], op
[1]);
1155 bld
.ASR(result
, op
[0], op
[1]);
1158 bld
.SHR(result
, op
[0], op
[1]);
1161 case nir_op_pack_half_2x16_split
:
1162 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1166 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1167 inst
->saturate
= instr
->dest
.saturate
;
1171 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1172 inst
->saturate
= instr
->dest
.saturate
;
1176 if (optimize_frontfacing_ternary(instr
, result
))
1179 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1180 inst
= bld
.SEL(result
, op
[1], op
[2]);
1181 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1184 case nir_op_extract_u8
:
1185 case nir_op_extract_i8
: {
1186 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1187 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1188 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1192 case nir_op_extract_u16
:
1193 case nir_op_extract_i16
: {
1194 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1195 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1196 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1201 unreachable("unhandled instruction");
1204 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1205 * to sign extend the low bit to 0/~0
1207 if (devinfo
->gen
<= 5 &&
1208 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1209 fs_reg masked
= vgrf(glsl_type::int_type
);
1210 bld
.AND(masked
, result
, brw_imm_d(1));
1211 masked
.negate
= true;
1212 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1217 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1218 nir_load_const_instr
*instr
)
1220 const brw_reg_type reg_type
=
1221 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1222 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1224 switch (instr
->def
.bit_size
) {
1226 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1227 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1231 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1232 bld
.MOV(offset(reg
, bld
, i
), brw_imm_df(instr
->value
.f64
[i
]));
1236 unreachable("Invalid bit size");
1239 nir_ssa_values
[instr
->def
.index
] = reg
;
1243 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1245 const brw_reg_type reg_type
=
1246 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1247 nir_ssa_values
[instr
->def
.index
] =
1248 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1252 fs_visitor::get_nir_src(nir_src src
)
1256 reg
= nir_ssa_values
[src
.ssa
->index
];
1258 /* We don't handle indirects on locals */
1259 assert(src
.reg
.indirect
== NULL
);
1260 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1261 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1264 /* to avoid floating-point denorm flushing problems, set the type by
1265 * default to D - instructions that need floating point semantics will set
1266 * this to F if they need to
1268 return retype(reg
, BRW_REGISTER_TYPE_D
);
1272 fs_visitor::get_nir_dest(nir_dest dest
)
1275 const brw_reg_type reg_type
=
1276 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1277 nir_ssa_values
[dest
.ssa
.index
] =
1278 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1279 return nir_ssa_values
[dest
.ssa
.index
];
1281 /* We don't handle indirects on locals */
1282 assert(dest
.reg
.indirect
== NULL
);
1283 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1284 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1289 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1291 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1292 BRW_REGISTER_TYPE_UD
);
1294 unsigned indirect_max
= 0;
1296 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1297 tail
= tail
->child
) {
1298 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1299 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1300 const unsigned size
= glsl_get_length(tail
->type
);
1301 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1302 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1303 image
= offset(image
, bld
, base
* element_size
);
1305 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1306 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1308 /* Accessing an invalid surface index with the dataport can result
1309 * in a hang. According to the spec "if the index used to
1310 * select an individual element is negative or greater than or
1311 * equal to the size of the array, the results of the operation
1312 * are undefined but may not lead to termination" -- which is one
1313 * of the possible outcomes of the hang. Clamp the index to
1314 * prevent access outside of the array bounds.
1316 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1317 BRW_REGISTER_TYPE_UD
),
1318 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1320 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1322 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1323 if (indirect
.file
== BAD_FILE
) {
1326 bld
.ADD(indirect
, indirect
, tmp
);
1331 if (indirect
.file
== BAD_FILE
) {
1334 /* Emit a pile of MOVs to load the uniform into a temporary. The
1335 * dead-code elimination pass will get rid of what we don't use.
1337 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1338 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1339 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1340 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1341 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1348 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1351 for (unsigned i
= 0; i
< 4; i
++) {
1352 if (!((wr_mask
>> i
) & 1))
1355 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1356 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1357 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1358 if (new_inst
->src
[j
].file
== VGRF
)
1359 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1366 * Get the matching channel register datatype for an image intrinsic of the
1367 * specified GLSL image type.
1370 get_image_base_type(const glsl_type
*type
)
1372 switch ((glsl_base_type
)type
->sampled_type
) {
1373 case GLSL_TYPE_UINT
:
1374 return BRW_REGISTER_TYPE_UD
;
1376 return BRW_REGISTER_TYPE_D
;
1377 case GLSL_TYPE_FLOAT
:
1378 return BRW_REGISTER_TYPE_F
;
1380 unreachable("Not reached.");
1385 * Get the appropriate atomic op for an image atomic intrinsic.
1388 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1391 case nir_intrinsic_image_atomic_add
:
1393 case nir_intrinsic_image_atomic_min
:
1394 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1395 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1396 case nir_intrinsic_image_atomic_max
:
1397 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1398 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1399 case nir_intrinsic_image_atomic_and
:
1401 case nir_intrinsic_image_atomic_or
:
1403 case nir_intrinsic_image_atomic_xor
:
1405 case nir_intrinsic_image_atomic_exchange
:
1407 case nir_intrinsic_image_atomic_comp_swap
:
1408 return BRW_AOP_CMPWR
;
1410 unreachable("Not reachable.");
1415 emit_pixel_interpolater_send(const fs_builder
&bld
,
1420 glsl_interp_qualifier interpolation
)
1426 if (src
.file
== BAD_FILE
) {
1428 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1432 mlen
= 2 * bld
.dispatch_width() / 8;
1435 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1437 /* 2 floats per slot returned */
1438 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1439 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1445 * Computes 1 << x, given a D/UD register containing some value x.
1448 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1450 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1452 fs_reg result
= bld
.vgrf(x
.type
, 1);
1453 fs_reg one
= bld
.vgrf(x
.type
, 1);
1455 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1456 bld
.SHL(result
, one
, x
);
1461 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1463 assert(stage
== MESA_SHADER_GEOMETRY
);
1465 struct brw_gs_prog_data
*gs_prog_data
=
1466 (struct brw_gs_prog_data
*) prog_data
;
1468 /* We can only do EndPrimitive() functionality when the control data
1469 * consists of cut bits. Fortunately, the only time it isn't is when the
1470 * output type is points, in which case EndPrimitive() is a no-op.
1472 if (gs_prog_data
->control_data_format
!=
1473 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1477 /* Cut bits use one bit per vertex. */
1478 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1480 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1481 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1483 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1484 * vertex n, 0 otherwise. So all we need to do here is mark bit
1485 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1486 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1487 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1489 * Note that if EndPrimitive() is called before emitting any vertices, this
1490 * will cause us to set bit 31 of the control_data_bits register to 1.
1491 * That's fine because:
1493 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1494 * output, so the hardware will ignore cut bit 31.
1496 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1497 * last vertex, so setting cut bit 31 has no effect (since the primitive
1498 * is automatically ended when the GS terminates).
1500 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1501 * control_data_bits register to 0 when the first vertex is emitted.
1504 const fs_builder abld
= bld
.annotate("end primitive");
1506 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1507 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1508 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1509 fs_reg mask
= intexp2(abld
, prev_count
);
1510 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1511 * attention to the lower 5 bits of its second source argument, so on this
1512 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1513 * ((vertex_count - 1) % 32).
1515 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1519 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1521 assert(stage
== MESA_SHADER_GEOMETRY
);
1522 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1524 struct brw_gs_prog_data
*gs_prog_data
=
1525 (struct brw_gs_prog_data
*) prog_data
;
1527 const fs_builder abld
= bld
.annotate("emit control data bits");
1528 const fs_builder fwa_bld
= bld
.exec_all();
1530 /* We use a single UD register to accumulate control data bits (32 bits
1531 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1534 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1535 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1536 * use the Channel Mask phase to enable/disable which DWord within that
1537 * group to write. (Remember, different SIMD8 channels may have emitted
1538 * different numbers of vertices, so we may need per-slot offsets.)
1540 * Channel masking presents an annoying problem: we may have to replicate
1541 * the data up to 4 times:
1543 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1545 * To avoid penalizing shaders that emit a small number of vertices, we
1546 * can avoid these sometimes: if the size of the control data header is
1547 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1548 * land in the same 128-bit group, so we can skip per-slot offsets.
1550 * Similarly, if the control data header is <= 32 bits, there is only one
1551 * DWord, so we can skip channel masks.
1553 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1555 fs_reg channel_mask
, per_slot_offset
;
1557 if (gs_compile
->control_data_header_size_bits
> 32) {
1558 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1559 channel_mask
= vgrf(glsl_type::uint_type
);
1562 if (gs_compile
->control_data_header_size_bits
> 128) {
1563 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1564 per_slot_offset
= vgrf(glsl_type::uint_type
);
1567 /* Figure out which DWord we're trying to write to using the formula:
1569 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1571 * Since bits_per_vertex is a power of two, and is known at compile
1572 * time, this can be optimized to:
1574 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1576 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1577 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1578 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1579 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1580 unsigned log2_bits_per_vertex
=
1581 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1582 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1584 if (per_slot_offset
.file
!= BAD_FILE
) {
1585 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1586 * the appropriate OWord within the control data header.
1588 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1591 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1592 * write to the appropriate DWORD within the OWORD.
1594 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1595 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1596 channel_mask
= intexp2(fwa_bld
, channel
);
1597 /* Then the channel masks need to be in bits 23:16. */
1598 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1601 /* Store the control data bits in the message payload and send it. */
1603 if (channel_mask
.file
!= BAD_FILE
)
1604 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1605 if (per_slot_offset
.file
!= BAD_FILE
)
1608 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1609 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1611 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1612 if (per_slot_offset
.file
!= BAD_FILE
)
1613 sources
[i
++] = per_slot_offset
;
1614 if (channel_mask
.file
!= BAD_FILE
)
1615 sources
[i
++] = channel_mask
;
1617 sources
[i
++] = this->control_data_bits
;
1620 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1621 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1623 /* We need to increment Global Offset by 256-bits to make room for
1624 * Broadwell's extra "Vertex Count" payload at the beginning of the
1625 * URB entry. Since this is an OWord message, Global Offset is counted
1626 * in 128-bit units, so we must set it to 2.
1628 if (gs_prog_data
->static_vertex_count
== -1)
1633 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1636 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1638 /* Note: we are calling this *before* increasing vertex_count, so
1639 * this->vertex_count == vertex_count - 1 in the formula above.
1642 /* Stream mode uses 2 bits per vertex */
1643 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1645 /* Must be a valid stream */
1646 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1648 /* Control data bits are initialized to 0 so we don't have to set any
1649 * bits when sending vertices to stream 0.
1654 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1656 /* reg::sid = stream_id */
1657 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1658 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1660 /* reg:shift_count = 2 * (vertex_count - 1) */
1661 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1662 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1664 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1665 * attention to the lower 5 bits of its second source argument, so on this
1666 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1667 * stream_id << ((2 * (vertex_count - 1)) % 32).
1669 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1670 abld
.SHL(mask
, sid
, shift_count
);
1671 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1675 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1678 assert(stage
== MESA_SHADER_GEOMETRY
);
1680 struct brw_gs_prog_data
*gs_prog_data
=
1681 (struct brw_gs_prog_data
*) prog_data
;
1683 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1684 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1686 /* Haswell and later hardware ignores the "Render Stream Select" bits
1687 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1688 * and instead sends all primitives down the pipeline for rasterization.
1689 * If the SOL stage is enabled, "Render Stream Select" is honored and
1690 * primitives bound to non-zero streams are discarded after stream output.
1692 * Since the only purpose of primives sent to non-zero streams is to
1693 * be recorded by transform feedback, we can simply discard all geometry
1694 * bound to these streams when transform feedback is disabled.
1696 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1699 /* If we're outputting 32 control data bits or less, then we can wait
1700 * until the shader is over to output them all. Otherwise we need to
1701 * output them as we go. Now is the time to do it, since we're about to
1702 * output the vertex_count'th vertex, so it's guaranteed that the
1703 * control data bits associated with the (vertex_count - 1)th vertex are
1706 if (gs_compile
->control_data_header_size_bits
> 32) {
1707 const fs_builder abld
=
1708 bld
.annotate("emit vertex: emit control data bits");
1710 /* Only emit control data bits if we've finished accumulating a batch
1711 * of 32 bits. This is the case when:
1713 * (vertex_count * bits_per_vertex) % 32 == 0
1715 * (in other words, when the last 5 bits of vertex_count *
1716 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1717 * integer n (which is always the case, since bits_per_vertex is
1718 * always 1 or 2), this is equivalent to requiring that the last 5-n
1719 * bits of vertex_count are 0:
1721 * vertex_count & (2^(5-n) - 1) == 0
1723 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1726 * vertex_count & (32 / bits_per_vertex - 1) == 0
1728 * TODO: If vertex_count is an immediate, we could do some of this math
1729 * at compile time...
1732 abld
.AND(bld
.null_reg_d(), vertex_count
,
1733 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1734 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1736 abld
.IF(BRW_PREDICATE_NORMAL
);
1737 /* If vertex_count is 0, then no control data bits have been
1738 * accumulated yet, so we can skip emitting them.
1740 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1741 BRW_CONDITIONAL_NEQ
);
1742 abld
.IF(BRW_PREDICATE_NORMAL
);
1743 emit_gs_control_data_bits(vertex_count
);
1744 abld
.emit(BRW_OPCODE_ENDIF
);
1746 /* Reset control_data_bits to 0 so we can start accumulating a new
1749 * Note: in the case where vertex_count == 0, this neutralizes the
1750 * effect of any call to EndPrimitive() that the shader may have
1751 * made before outputting its first vertex.
1753 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1754 inst
->force_writemask_all
= true;
1755 abld
.emit(BRW_OPCODE_ENDIF
);
1758 emit_urb_writes(vertex_count
);
1760 /* In stream mode we have to set control data bits for all vertices
1761 * unless we have disabled control data bits completely (which we do
1762 * do for GL_POINTS outputs that don't use streams).
1764 if (gs_compile
->control_data_header_size_bits
> 0 &&
1765 gs_prog_data
->control_data_format
==
1766 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1767 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1772 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1773 const nir_src
&vertex_src
,
1774 unsigned base_offset
,
1775 const nir_src
&offset_src
,
1776 unsigned num_components
)
1778 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1780 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1781 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1782 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1784 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1785 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1786 * gl_PointSize is available as a GS input, however, so it must be that.
1788 const bool is_point_size
= (base_offset
== 0);
1790 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1791 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1792 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1793 vertex_const
->u32
[0] * push_reg_count
;
1794 /* This input was pushed into registers. */
1795 if (is_point_size
) {
1796 /* gl_PointSize comes in .w */
1797 assert(imm_offset
== 0);
1798 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1800 for (unsigned i
= 0; i
< num_components
; i
++) {
1801 bld
.MOV(offset(dst
, bld
, i
),
1802 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1806 /* Resort to the pull model. Ensure the VUE handles are provided. */
1807 gs_prog_data
->base
.include_vue_handles
= true;
1809 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1813 /* The vertex index is constant; just select the proper URB handle. */
1815 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1816 BRW_REGISTER_TYPE_UD
);
1818 /* The vertex index is non-constant. We need to use indirect
1819 * addressing to fetch the proper URB handle.
1821 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1822 * indicating that channel <n> should read the handle from
1823 * DWord <n>. We convert that to bytes by multiplying by 4.
1825 * Next, we convert the vertex index to bytes by multiplying
1826 * by 32 (shifting by 5), and add the two together. This is
1827 * the final indirect byte offset.
1829 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1830 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1831 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1832 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1833 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1835 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1836 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1837 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1838 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1839 /* Convert vertex_index to bytes (multiply by 32) */
1840 bld
.SHL(vertex_offset_bytes
,
1841 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1843 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1845 /* Use first_icp_handle as the base offset. There is one register
1846 * of URB handles per vertex, so inform the register allocator that
1847 * we might read up to nir->info.gs.vertices_in registers.
1849 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1850 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1851 fs_reg(icp_offset_bytes
),
1852 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1857 /* Constant indexing - use global offset. */
1858 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1859 inst
->offset
= base_offset
+ offset_const
->u32
[0];
1860 inst
->base_mrf
= -1;
1862 inst
->regs_written
= num_components
;
1864 /* Indirect indexing - use per-slot offsets as well. */
1865 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1866 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1867 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1869 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1870 inst
->offset
= base_offset
;
1871 inst
->base_mrf
= -1;
1873 inst
->regs_written
= num_components
;
1876 if (is_point_size
) {
1877 /* Read the whole VUE header (because of alignment) and read .w. */
1878 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1880 inst
->regs_written
= 4;
1881 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1887 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1889 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1890 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1893 /* The only constant offset we should find is 0. brw_nir.c's
1894 * add_const_offset_to_base() will fold other constant offsets
1895 * into instr->const_index[0].
1897 assert(const_value
->u32
[0] == 0);
1901 return get_nir_src(*offset_src
);
1905 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1906 nir_intrinsic_instr
*instr
)
1908 assert(stage
== MESA_SHADER_VERTEX
);
1911 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1912 dest
= get_nir_dest(instr
->dest
);
1914 switch (instr
->intrinsic
) {
1915 case nir_intrinsic_load_vertex_id
:
1916 unreachable("should be lowered by lower_vertex_id()");
1918 case nir_intrinsic_load_vertex_id_zero_base
:
1919 case nir_intrinsic_load_base_vertex
:
1920 case nir_intrinsic_load_instance_id
:
1921 case nir_intrinsic_load_base_instance
:
1922 case nir_intrinsic_load_draw_id
: {
1923 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1924 fs_reg val
= nir_system_values
[sv
];
1925 assert(val
.file
!= BAD_FILE
);
1926 dest
.type
= val
.type
;
1932 nir_emit_intrinsic(bld
, instr
);
1938 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
1939 nir_intrinsic_instr
*instr
)
1941 assert(stage
== MESA_SHADER_TESS_CTRL
);
1942 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
1943 struct brw_tcs_prog_data
*tcs_prog_data
=
1944 (struct brw_tcs_prog_data
*) prog_data
;
1947 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1948 dst
= get_nir_dest(instr
->dest
);
1950 switch (instr
->intrinsic
) {
1951 case nir_intrinsic_load_primitive_id
:
1952 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
1954 case nir_intrinsic_load_invocation_id
:
1955 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
1957 case nir_intrinsic_load_patch_vertices_in
:
1958 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
1959 brw_imm_d(tcs_key
->input_vertices
));
1962 case nir_intrinsic_barrier
: {
1963 if (tcs_prog_data
->instances
== 1)
1966 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1967 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
1969 const fs_builder fwa_bld
= bld
.exec_all();
1971 /* Zero the message header */
1972 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
1974 /* Copy "Barrier ID" from r0.2, bits 16:13 */
1975 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
1976 brw_imm_ud(INTEL_MASK(16, 13)));
1978 /* Shift it up to bits 27:24. */
1979 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
1981 /* Set the Barrier Count and the enable bit */
1982 fwa_bld
.OR(m0_2
, m0_2
,
1983 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
1985 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
1989 case nir_intrinsic_load_input
:
1990 unreachable("nir_lower_io should never give us these.");
1993 case nir_intrinsic_load_per_vertex_input
: {
1994 fs_reg indirect_offset
= get_indirect_offset(instr
);
1995 unsigned imm_offset
= instr
->const_index
[0];
1997 const nir_src
&vertex_src
= instr
->src
[0];
1998 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2005 /* Emit a MOV to resolve <0,1,0> regioning. */
2006 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2008 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2009 vertex_const
->i32
[0] & 7),
2010 BRW_REGISTER_TYPE_UD
));
2011 } else if (tcs_prog_data
->instances
== 1 &&
2012 vertex_src
.is_ssa
&&
2013 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2014 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2015 /* For the common case of only 1 instance, an array index of
2016 * gl_InvocationID means reading g1. Skip all the indirect work.
2018 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2020 /* The vertex index is non-constant. We need to use indirect
2021 * addressing to fetch the proper URB handle.
2023 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2025 /* Each ICP handle is a single DWord (4 bytes) */
2026 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2027 bld
.SHL(vertex_offset_bytes
,
2028 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2031 /* Start at g1. We might read up to 4 registers. */
2032 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2033 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2034 brw_imm_ud(4 * REG_SIZE
));
2037 if (indirect_offset
.file
== BAD_FILE
) {
2038 /* Constant indexing - use global offset. */
2039 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2040 inst
->offset
= imm_offset
;
2042 inst
->base_mrf
= -1;
2043 inst
->regs_written
= instr
->num_components
;
2045 /* Indirect indexing - use per-slot offsets as well. */
2046 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2047 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2048 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2050 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2051 inst
->offset
= imm_offset
;
2052 inst
->base_mrf
= -1;
2054 inst
->regs_written
= instr
->num_components
;
2057 /* Copy the temporary to the destination to deal with writemasking.
2059 * Also attempt to deal with gl_PointSize being in the .w component.
2061 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2062 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2063 inst
->regs_written
= 4;
2064 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2069 case nir_intrinsic_load_output
:
2070 case nir_intrinsic_load_per_vertex_output
: {
2071 fs_reg indirect_offset
= get_indirect_offset(instr
);
2072 unsigned imm_offset
= instr
->const_index
[0];
2075 if (indirect_offset
.file
== BAD_FILE
) {
2076 /* Replicate the patch handle to all enabled channels */
2077 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2078 bld
.MOV(patch_handle
,
2079 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2081 if (imm_offset
== 0) {
2082 /* This is a read of gl_TessLevelInner[], which lives in the
2083 * Patch URB header. The layout depends on the domain.
2085 dst
.type
= BRW_REGISTER_TYPE_F
;
2086 switch (tcs_key
->tes_primitive_mode
) {
2088 /* DWords 3-2 (reversed) */
2089 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2091 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2094 inst
->base_mrf
= -1;
2095 inst
->regs_written
= 4;
2097 /* dst.xy = tmp.wz */
2098 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2099 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2103 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2104 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2107 inst
->base_mrf
= -1;
2108 inst
->regs_written
= 1;
2111 /* All channels are undefined. */
2114 unreachable("Bogus tessellation domain");
2116 } else if (imm_offset
== 1) {
2117 /* This is a read of gl_TessLevelOuter[], which lives in the
2118 * Patch URB header. The layout depends on the domain.
2120 dst
.type
= BRW_REGISTER_TYPE_F
;
2122 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2123 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2126 inst
->base_mrf
= -1;
2127 inst
->regs_written
= 4;
2129 /* Reswizzle: WZYX */
2131 offset(tmp
, bld
, 3),
2132 offset(tmp
, bld
, 2),
2133 offset(tmp
, bld
, 1),
2134 offset(tmp
, bld
, 0),
2137 unsigned num_components
;
2138 switch (tcs_key
->tes_primitive_mode
) {
2146 /* Isolines are not reversed; swizzle .zw -> .xy */
2147 srcs
[0] = offset(tmp
, bld
, 2);
2148 srcs
[1] = offset(tmp
, bld
, 3);
2152 unreachable("Bogus tessellation domain");
2154 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2156 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2157 inst
->offset
= imm_offset
;
2159 inst
->base_mrf
= -1;
2160 inst
->regs_written
= instr
->num_components
;
2163 /* Indirect indexing - use per-slot offsets as well. */
2164 const fs_reg srcs
[] = {
2165 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2168 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2169 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2171 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2172 inst
->offset
= imm_offset
;
2174 inst
->base_mrf
= -1;
2175 inst
->regs_written
= instr
->num_components
;
2180 case nir_intrinsic_store_output
:
2181 case nir_intrinsic_store_per_vertex_output
: {
2182 fs_reg value
= get_nir_src(instr
->src
[0]);
2183 fs_reg indirect_offset
= get_indirect_offset(instr
);
2184 unsigned imm_offset
= instr
->const_index
[0];
2185 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2186 unsigned mask
= instr
->const_index
[1];
2187 unsigned header_regs
= 0;
2189 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2191 if (indirect_offset
.file
!= BAD_FILE
) {
2192 srcs
[header_regs
++] = indirect_offset
;
2193 } else if (!is_passthrough_shader
) {
2194 if (imm_offset
== 0) {
2195 value
.type
= BRW_REGISTER_TYPE_F
;
2197 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2199 /* This is a write to gl_TessLevelInner[], which lives in the
2200 * Patch URB header. The layout depends on the domain.
2202 switch (tcs_key
->tes_primitive_mode
) {
2204 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2205 * We use an XXYX swizzle to reverse put .xy in the .wz
2206 * channels, and use a .zw writemask.
2208 mask
= writemask_for_backwards_vector(mask
);
2209 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2212 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2213 * writemask to X and bump the URB offset by 1.
2218 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2221 unreachable("Bogus tessellation domain");
2223 } else if (imm_offset
== 1) {
2224 /* This is a write to gl_TessLevelOuter[] which lives in the
2225 * Patch URB Header at DWords 4-7. However, it's reversed, so
2226 * instead of .xyzw we have .wzyx.
2228 value
.type
= BRW_REGISTER_TYPE_F
;
2230 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2232 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2233 /* Isolines .xy should be stored in .zw, in order. */
2234 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2237 /* Other domains are reversed; store .wzyx instead of .xyzw */
2238 swiz
= BRW_SWIZZLE_WZYX
;
2239 mask
= writemask_for_backwards_vector(mask
);
2247 unsigned num_components
= _mesa_fls(mask
);
2250 if (mask
!= WRITEMASK_XYZW
) {
2251 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2252 opcode
= indirect_offset
.file
!= BAD_FILE
?
2253 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2254 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2256 opcode
= indirect_offset
.file
!= BAD_FILE
?
2257 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2258 SHADER_OPCODE_URB_WRITE_SIMD8
;
2261 for (unsigned i
= 0; i
< num_components
; i
++) {
2262 if (mask
& (1 << i
))
2263 srcs
[header_regs
+ i
] = offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2266 unsigned mlen
= header_regs
+ num_components
;
2269 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2270 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2272 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2273 inst
->offset
= imm_offset
;
2275 inst
->base_mrf
= -1;
2280 nir_emit_intrinsic(bld
, instr
);
2286 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2287 nir_intrinsic_instr
*instr
)
2289 assert(stage
== MESA_SHADER_TESS_EVAL
);
2290 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2293 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2294 dest
= get_nir_dest(instr
->dest
);
2296 switch (instr
->intrinsic
) {
2297 case nir_intrinsic_load_primitive_id
:
2298 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2300 case nir_intrinsic_load_tess_coord
:
2301 /* gl_TessCoord is part of the payload in g1-3 */
2302 for (unsigned i
= 0; i
< 3; i
++) {
2303 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2307 case nir_intrinsic_load_tess_level_outer
:
2308 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2309 * appears as a push-model input. So, we can simply use the ATTR file
2310 * rather than issuing URB read messages. The data is stored in the
2311 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2314 switch (tes_prog_data
->domain
) {
2315 case BRW_TESS_DOMAIN_QUAD
:
2316 for (unsigned i
= 0; i
< 4; i
++)
2317 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2319 case BRW_TESS_DOMAIN_TRI
:
2320 for (unsigned i
= 0; i
< 3; i
++)
2321 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2323 case BRW_TESS_DOMAIN_ISOLINE
:
2324 for (unsigned i
= 0; i
< 2; i
++)
2325 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2330 case nir_intrinsic_load_tess_level_inner
:
2331 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2332 * appears as a push-model input. So, we can simply use the ATTR file
2333 * rather than issuing URB read messages.
2335 switch (tes_prog_data
->domain
) {
2336 case BRW_TESS_DOMAIN_QUAD
:
2337 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2338 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2340 case BRW_TESS_DOMAIN_TRI
:
2341 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2343 case BRW_TESS_DOMAIN_ISOLINE
:
2344 /* ignore - value is undefined */
2349 case nir_intrinsic_load_input
:
2350 case nir_intrinsic_load_per_vertex_input
: {
2351 fs_reg indirect_offset
= get_indirect_offset(instr
);
2352 unsigned imm_offset
= instr
->const_index
[0];
2355 if (indirect_offset
.file
== BAD_FILE
) {
2356 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2357 * which is 16 registers (since each holds 2 vec4 slots).
2359 const unsigned max_push_slots
= 32;
2360 if (imm_offset
< max_push_slots
) {
2361 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2362 for (int i
= 0; i
< instr
->num_components
; i
++) {
2363 bld
.MOV(offset(dest
, bld
, i
),
2364 component(src
, 4 * (imm_offset
% 2) + i
));
2366 tes_prog_data
->base
.urb_read_length
=
2367 MAX2(tes_prog_data
->base
.urb_read_length
,
2368 DIV_ROUND_UP(imm_offset
+ 1, 2));
2370 /* Replicate the patch handle to all enabled channels */
2371 const fs_reg srcs
[] = {
2372 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2374 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2375 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2377 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2379 inst
->offset
= imm_offset
;
2380 inst
->base_mrf
= -1;
2381 inst
->regs_written
= instr
->num_components
;
2384 /* Indirect indexing - use per-slot offsets as well. */
2385 const fs_reg srcs
[] = {
2386 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2389 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2390 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2392 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2394 inst
->offset
= imm_offset
;
2395 inst
->base_mrf
= -1;
2396 inst
->regs_written
= instr
->num_components
;
2401 nir_emit_intrinsic(bld
, instr
);
2407 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2408 nir_intrinsic_instr
*instr
)
2410 assert(stage
== MESA_SHADER_GEOMETRY
);
2411 fs_reg indirect_offset
;
2414 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2415 dest
= get_nir_dest(instr
->dest
);
2417 switch (instr
->intrinsic
) {
2418 case nir_intrinsic_load_primitive_id
:
2419 assert(stage
== MESA_SHADER_GEOMETRY
);
2420 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2421 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2422 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2425 case nir_intrinsic_load_input
:
2426 unreachable("load_input intrinsics are invalid for the GS stage");
2428 case nir_intrinsic_load_per_vertex_input
:
2429 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2430 instr
->src
[1], instr
->num_components
);
2433 case nir_intrinsic_emit_vertex_with_counter
:
2434 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2437 case nir_intrinsic_end_primitive_with_counter
:
2438 emit_gs_end_primitive(instr
->src
[0]);
2441 case nir_intrinsic_set_vertex_count
:
2442 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2445 case nir_intrinsic_load_invocation_id
: {
2446 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2447 assert(val
.file
!= BAD_FILE
);
2448 dest
.type
= val
.type
;
2454 nir_emit_intrinsic(bld
, instr
);
2460 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2461 nir_intrinsic_instr
*instr
)
2463 assert(stage
== MESA_SHADER_FRAGMENT
);
2464 struct brw_wm_prog_data
*wm_prog_data
=
2465 (struct brw_wm_prog_data
*) prog_data
;
2466 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
2469 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2470 dest
= get_nir_dest(instr
->dest
);
2472 switch (instr
->intrinsic
) {
2473 case nir_intrinsic_load_front_face
:
2474 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2475 *emit_frontfacing_interpolation());
2478 case nir_intrinsic_load_sample_pos
: {
2479 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2480 assert(sample_pos
.file
!= BAD_FILE
);
2481 dest
.type
= sample_pos
.type
;
2482 bld
.MOV(dest
, sample_pos
);
2483 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2487 case nir_intrinsic_load_helper_invocation
:
2488 case nir_intrinsic_load_sample_mask_in
:
2489 case nir_intrinsic_load_sample_id
: {
2490 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2491 fs_reg val
= nir_system_values
[sv
];
2492 assert(val
.file
!= BAD_FILE
);
2493 dest
.type
= val
.type
;
2498 case nir_intrinsic_discard
:
2499 case nir_intrinsic_discard_if
: {
2500 /* We track our discarded pixels in f0.1. By predicating on it, we can
2501 * update just the flag bits that aren't yet discarded. If there's no
2502 * condition, we emit a CMP of g0 != g0, so all currently executing
2503 * channels will get turned off.
2506 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2507 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2508 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2510 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2511 BRW_REGISTER_TYPE_UW
));
2512 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2514 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2515 cmp
->flag_subreg
= 1;
2517 if (devinfo
->gen
>= 6) {
2518 emit_discard_jump();
2523 case nir_intrinsic_interp_var_at_centroid
:
2524 case nir_intrinsic_interp_var_at_sample
:
2525 case nir_intrinsic_interp_var_at_offset
: {
2526 /* Handle ARB_gpu_shader5 interpolation intrinsics
2528 * It's worth a quick word of explanation as to why we handle the full
2529 * variable-based interpolation intrinsic rather than a lowered version
2530 * with like we do for other inputs. We have to do that because the way
2531 * we set up inputs doesn't allow us to use the already setup inputs for
2532 * interpolation. At the beginning of the shader, we go through all of
2533 * the input variables and do the initial interpolation and put it in
2534 * the nir_inputs array based on its location as determined in
2535 * nir_lower_io. If the input isn't used, dead code cleans up and
2536 * everything works fine. However, when we get to the ARB_gpu_shader5
2537 * interpolation intrinsics, we need to reinterpolate the input
2538 * differently. If we used an intrinsic that just had an index it would
2539 * only give us the offset into the nir_inputs array. However, this is
2540 * useless because that value is post-interpolation and we need
2541 * pre-interpolation. In order to get the actual location of the bits
2542 * we get from the vertex fetching hardware, we need the variable.
2544 wm_prog_data
->pulls_bary
= true;
2546 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2547 const glsl_interp_qualifier interpolation
=
2548 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2550 switch (instr
->intrinsic
) {
2551 case nir_intrinsic_interp_var_at_centroid
:
2552 emit_pixel_interpolater_send(bld
,
2553 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2560 case nir_intrinsic_interp_var_at_sample
: {
2561 if (!wm_key
->multisample_fbo
) {
2562 /* From the ARB_gpu_shader5 specification:
2563 * "If multisample buffers are not available, the input varying
2564 * will be evaluated at the center of the pixel."
2566 emit_pixel_interpolater_send(bld
,
2567 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2575 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2578 unsigned msg_data
= const_sample
->i32
[0] << 4;
2580 emit_pixel_interpolater_send(bld
,
2581 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2584 brw_imm_ud(msg_data
),
2587 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2588 BRW_REGISTER_TYPE_UD
);
2590 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2591 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2592 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2593 bld
.exec_all().group(1, 0)
2594 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2595 emit_pixel_interpolater_send(bld
,
2596 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2602 /* Make a loop that sends a message to the pixel interpolater
2603 * for the sample number in each live channel. If there are
2604 * multiple channels with the same sample number then these
2605 * will be handled simultaneously with a single interation of
2608 bld
.emit(BRW_OPCODE_DO
);
2610 /* Get the next live sample number into sample_id_reg */
2611 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2613 /* Set the flag register so that we can perform the send
2614 * message on all channels that have the same sample number
2616 bld
.CMP(bld
.null_reg_ud(),
2617 sample_src
, sample_id
,
2618 BRW_CONDITIONAL_EQ
);
2619 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2620 bld
.exec_all().group(1, 0)
2621 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2623 emit_pixel_interpolater_send(bld
,
2624 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2629 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2631 /* Continue the loop if there are any live channels left */
2632 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2634 bld
.emit(BRW_OPCODE_WHILE
));
2641 case nir_intrinsic_interp_var_at_offset
: {
2642 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2645 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2646 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2648 emit_pixel_interpolater_send(bld
,
2649 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2652 brw_imm_ud(off_x
| (off_y
<< 4)),
2655 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2656 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2657 BRW_REGISTER_TYPE_F
);
2658 for (int i
= 0; i
< 2; i
++) {
2659 fs_reg temp
= vgrf(glsl_type::float_type
);
2660 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2661 fs_reg itemp
= vgrf(glsl_type::int_type
);
2662 bld
.MOV(itemp
, temp
); /* float to int */
2664 /* Clamp the upper end of the range to +7/16.
2665 * ARB_gpu_shader5 requires that we support a maximum offset
2666 * of +0.5, which isn't representable in a S0.4 value -- if
2667 * we didn't clamp it, we'd end up with -8/16, which is the
2668 * opposite of what the shader author wanted.
2670 * This is legal due to ARB_gpu_shader5's quantization
2673 * "Not all values of <offset> may be supported; x and y
2674 * offsets may be rounded to fixed-point values with the
2675 * number of fraction bits given by the
2676 * implementation-dependent constant
2677 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2679 set_condmod(BRW_CONDITIONAL_L
,
2680 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2683 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2684 emit_pixel_interpolater_send(bld
,
2695 unreachable("Invalid intrinsic");
2698 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2699 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2700 src
.type
= dest
.type
;
2702 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2703 dest
= offset(dest
, bld
, 1);
2708 nir_emit_intrinsic(bld
, instr
);
2714 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2715 nir_intrinsic_instr
*instr
)
2717 assert(stage
== MESA_SHADER_COMPUTE
);
2718 struct brw_cs_prog_data
*cs_prog_data
=
2719 (struct brw_cs_prog_data
*) prog_data
;
2722 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2723 dest
= get_nir_dest(instr
->dest
);
2725 switch (instr
->intrinsic
) {
2726 case nir_intrinsic_barrier
:
2728 cs_prog_data
->uses_barrier
= true;
2731 case nir_intrinsic_load_local_invocation_id
:
2732 case nir_intrinsic_load_work_group_id
: {
2733 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2734 fs_reg val
= nir_system_values
[sv
];
2735 assert(val
.file
!= BAD_FILE
);
2736 dest
.type
= val
.type
;
2737 for (unsigned i
= 0; i
< 3; i
++)
2738 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2742 case nir_intrinsic_load_num_work_groups
: {
2743 const unsigned surface
=
2744 cs_prog_data
->binding_table
.work_groups_start
;
2746 cs_prog_data
->uses_num_work_groups
= true;
2748 fs_reg surf_index
= brw_imm_ud(surface
);
2749 brw_mark_surface_used(prog_data
, surface
);
2751 /* Read the 3 GLuint components of gl_NumWorkGroups */
2752 for (unsigned i
= 0; i
< 3; i
++) {
2753 fs_reg read_result
=
2754 emit_untyped_read(bld
, surf_index
,
2756 1 /* dims */, 1 /* size */,
2757 BRW_PREDICATE_NONE
);
2758 read_result
.type
= dest
.type
;
2759 bld
.MOV(dest
, read_result
);
2760 dest
= offset(dest
, bld
, 1);
2765 case nir_intrinsic_shared_atomic_add
:
2766 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2768 case nir_intrinsic_shared_atomic_imin
:
2769 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2771 case nir_intrinsic_shared_atomic_umin
:
2772 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2774 case nir_intrinsic_shared_atomic_imax
:
2775 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2777 case nir_intrinsic_shared_atomic_umax
:
2778 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2780 case nir_intrinsic_shared_atomic_and
:
2781 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2783 case nir_intrinsic_shared_atomic_or
:
2784 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2786 case nir_intrinsic_shared_atomic_xor
:
2787 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2789 case nir_intrinsic_shared_atomic_exchange
:
2790 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2792 case nir_intrinsic_shared_atomic_comp_swap
:
2793 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2796 case nir_intrinsic_load_shared
: {
2797 assert(devinfo
->gen
>= 7);
2799 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2801 /* Get the offset to read from */
2803 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2805 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
2807 offset_reg
= vgrf(glsl_type::uint_type
);
2809 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2810 brw_imm_ud(instr
->const_index
[0]));
2813 /* Read the vector */
2814 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2816 instr
->num_components
,
2817 BRW_PREDICATE_NONE
);
2818 read_result
.type
= dest
.type
;
2819 for (int i
= 0; i
< instr
->num_components
; i
++)
2820 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2825 case nir_intrinsic_store_shared
: {
2826 assert(devinfo
->gen
>= 7);
2829 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2832 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2835 unsigned writemask
= instr
->const_index
[1];
2837 /* Combine groups of consecutive enabled channels in one write
2838 * message. We use ffs to find the first enabled channel and then ffs on
2839 * the bit-inverse, down-shifted writemask to determine the length of
2840 * the block of enabled bits.
2843 unsigned first_component
= ffs(writemask
) - 1;
2844 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2847 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2849 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
2850 4 * first_component
);
2852 offset_reg
= vgrf(glsl_type::uint_type
);
2854 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2855 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2858 emit_untyped_write(bld
, surf_index
, offset_reg
,
2859 offset(val_reg
, bld
, first_component
),
2860 1 /* dims */, length
,
2861 BRW_PREDICATE_NONE
);
2863 /* Clear the bits in the writemask that we just wrote, then try
2864 * again to see if more channels are left.
2866 writemask
&= (15 << (first_component
+ length
));
2873 nir_emit_intrinsic(bld
, instr
);
2879 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2882 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2883 dest
= get_nir_dest(instr
->dest
);
2885 switch (instr
->intrinsic
) {
2886 case nir_intrinsic_atomic_counter_inc
:
2887 case nir_intrinsic_atomic_counter_dec
:
2888 case nir_intrinsic_atomic_counter_read
: {
2889 /* Get the arguments of the atomic intrinsic. */
2890 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2891 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2892 instr
->const_index
[0]);
2895 /* Emit a surface read or atomic op. */
2896 switch (instr
->intrinsic
) {
2897 case nir_intrinsic_atomic_counter_read
:
2898 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2901 case nir_intrinsic_atomic_counter_inc
:
2902 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2903 fs_reg(), 1, 1, BRW_AOP_INC
);
2906 case nir_intrinsic_atomic_counter_dec
:
2907 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2908 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2912 unreachable("Unreachable");
2915 /* Assign the result. */
2916 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2918 /* Mark the surface as used. */
2919 brw_mark_surface_used(stage_prog_data
, surface
);
2923 case nir_intrinsic_image_load
:
2924 case nir_intrinsic_image_store
:
2925 case nir_intrinsic_image_atomic_add
:
2926 case nir_intrinsic_image_atomic_min
:
2927 case nir_intrinsic_image_atomic_max
:
2928 case nir_intrinsic_image_atomic_and
:
2929 case nir_intrinsic_image_atomic_or
:
2930 case nir_intrinsic_image_atomic_xor
:
2931 case nir_intrinsic_image_atomic_exchange
:
2932 case nir_intrinsic_image_atomic_comp_swap
: {
2933 using namespace image_access
;
2935 /* Get the referenced image variable and type. */
2936 const nir_variable
*var
= instr
->variables
[0]->var
;
2937 const glsl_type
*type
= var
->type
->without_array();
2938 const brw_reg_type base_type
= get_image_base_type(type
);
2940 /* Get some metadata from the image intrinsic. */
2941 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2942 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2943 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2944 const unsigned format
= var
->data
.image
.format
;
2946 /* Get the arguments of the image intrinsic. */
2947 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2948 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2949 BRW_REGISTER_TYPE_UD
);
2950 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2951 retype(get_nir_src(instr
->src
[2]), base_type
) :
2953 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2954 retype(get_nir_src(instr
->src
[3]), base_type
) :
2958 /* Emit an image load, store or atomic op. */
2959 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2960 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2962 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2963 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
2964 var
->data
.image
.write_only
? GL_NONE
: format
);
2967 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2968 surf_dims
, arr_dims
, info
->dest_components
,
2969 get_image_atomic_op(instr
->intrinsic
, type
));
2971 /* Assign the result. */
2972 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2973 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2974 offset(tmp
, bld
, c
));
2978 case nir_intrinsic_memory_barrier_atomic_counter
:
2979 case nir_intrinsic_memory_barrier_buffer
:
2980 case nir_intrinsic_memory_barrier_image
:
2981 case nir_intrinsic_memory_barrier
: {
2982 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2983 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2988 case nir_intrinsic_group_memory_barrier
:
2989 case nir_intrinsic_memory_barrier_shared
:
2990 /* We treat these workgroup-level barriers as no-ops. This should be
2991 * safe at present and as long as:
2993 * - Memory access instructions are not subsequently reordered by the
2994 * compiler back-end.
2996 * - All threads from a given compute shader workgroup fit within a
2997 * single subslice and therefore talk to the same HDC shared unit
2998 * what supposedly guarantees ordering and coherency between threads
2999 * from the same workgroup. This may change in the future when we
3000 * start splitting workgroups across multiple subslices.
3002 * - The context is not in fault-and-stream mode, which could cause
3003 * memory transactions (including to SLM) prior to the barrier to be
3004 * replayed after the barrier if a pagefault occurs. This shouldn't
3005 * be a problem up to and including SKL because fault-and-stream is
3006 * not usable due to hardware issues, but that's likely to change in
3011 case nir_intrinsic_shader_clock
: {
3012 /* We cannot do anything if there is an event, so ignore it for now */
3013 fs_reg shader_clock
= get_timestamp(bld
);
3014 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3016 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3020 case nir_intrinsic_image_size
: {
3021 /* Get the referenced image variable and type. */
3022 const nir_variable
*var
= instr
->variables
[0]->var
;
3023 const glsl_type
*type
= var
->type
->without_array();
3025 /* Get the size of the image. */
3026 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3027 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3029 /* For 1DArray image types, the array index is stored in the Z component.
3030 * Fix this by swizzling the Z component to the Y component.
3032 const bool is_1d_array_image
=
3033 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3034 type
->sampler_array
;
3036 /* For CubeArray images, we should count the number of cubes instead
3037 * of the number of faces. Fix it by dividing the (Z component) by 6.
3039 const bool is_cube_array_image
=
3040 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3041 type
->sampler_array
;
3043 /* Copy all the components. */
3044 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3045 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3046 if ((int)c
>= type
->coordinate_components()) {
3047 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3049 } else if (c
== 1 && is_1d_array_image
) {
3050 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3051 offset(size
, bld
, 2));
3052 } else if (c
== 2 && is_cube_array_image
) {
3053 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3054 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3055 offset(size
, bld
, c
), brw_imm_d(6));
3057 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3058 offset(size
, bld
, c
));
3065 case nir_intrinsic_image_samples
:
3066 /* The driver does not support multi-sampled images. */
3067 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3070 case nir_intrinsic_load_uniform
: {
3071 /* Offsets are in bytes but they should always be multiples of 4 */
3072 assert(instr
->const_index
[0] % 4 == 0);
3074 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3076 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3078 /* Offsets are in bytes but they should always be multiples of 4 */
3079 assert(const_offset
->u32
[0] % 4 == 0);
3080 src
.reg_offset
= const_offset
->u32
[0] / 4;
3082 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3083 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3086 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3087 BRW_REGISTER_TYPE_UD
);
3089 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3090 * go past the end of the uniform. In order to keep the n'th
3091 * component from running past, we subtract off the size of all but
3092 * one component of the vector.
3094 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
3095 unsigned read_size
= instr
->const_index
[1] -
3096 (instr
->num_components
- 1) * 4;
3098 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3099 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3100 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3101 indirect
, brw_imm_ud(read_size
));
3107 case nir_intrinsic_load_ubo
: {
3108 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3112 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3113 const_index
->u32
[0];
3114 surf_index
= brw_imm_ud(index
);
3115 brw_mark_surface_used(prog_data
, index
);
3117 /* The block index is not a constant. Evaluate the index expression
3118 * per-channel and add the base UBO index; we have to select a value
3119 * from any live channel.
3121 surf_index
= vgrf(glsl_type::uint_type
);
3122 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3123 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3124 surf_index
= bld
.emit_uniformize(surf_index
);
3126 /* Assume this may touch any UBO. It would be nice to provide
3127 * a tighter bound, but the array information is already lowered away.
3129 brw_mark_surface_used(prog_data
,
3130 stage_prog_data
->binding_table
.ubo_start
+
3131 nir
->info
.num_ubos
- 1);
3134 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3135 if (const_offset
== NULL
) {
3136 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3137 BRW_REGISTER_TYPE_UD
);
3139 for (int i
= 0; i
< instr
->num_components
; i
++)
3140 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3141 base_offset
, i
* 4);
3143 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
3144 packed_consts
.type
= dest
.type
;
3146 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
3147 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
3148 surf_index
, const_offset_reg
);
3150 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3151 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
3153 /* The std140 packing rules don't allow vectors to cross 16-byte
3154 * boundaries, and a reg is 32 bytes.
3156 assert(packed_consts
.subreg_offset
< 32);
3158 bld
.MOV(dest
, packed_consts
);
3159 dest
= offset(dest
, bld
, 1);
3165 case nir_intrinsic_load_ssbo
: {
3166 assert(devinfo
->gen
>= 7);
3168 nir_const_value
*const_uniform_block
=
3169 nir_src_as_const_value(instr
->src
[0]);
3172 if (const_uniform_block
) {
3173 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3174 const_uniform_block
->u32
[0];
3175 surf_index
= brw_imm_ud(index
);
3176 brw_mark_surface_used(prog_data
, index
);
3178 surf_index
= vgrf(glsl_type::uint_type
);
3179 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3180 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3182 /* Assume this may touch any UBO. It would be nice to provide
3183 * a tighter bound, but the array information is already lowered away.
3185 brw_mark_surface_used(prog_data
,
3186 stage_prog_data
->binding_table
.ssbo_start
+
3187 nir
->info
.num_ssbos
- 1);
3191 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3193 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3195 offset_reg
= get_nir_src(instr
->src
[1]);
3198 /* Read the vector */
3199 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
3201 instr
->num_components
,
3202 BRW_PREDICATE_NONE
);
3203 read_result
.type
= dest
.type
;
3204 for (int i
= 0; i
< instr
->num_components
; i
++)
3205 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3210 case nir_intrinsic_load_input
: {
3212 if (stage
== MESA_SHADER_VERTEX
) {
3213 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3215 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3216 instr
->const_index
[0]);
3219 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3220 assert(const_offset
&& "Indirect input loads not allowed");
3221 src
= offset(src
, bld
, const_offset
->u32
[0]);
3223 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3224 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3229 case nir_intrinsic_store_ssbo
: {
3230 assert(devinfo
->gen
>= 7);
3234 nir_const_value
*const_uniform_block
=
3235 nir_src_as_const_value(instr
->src
[1]);
3236 if (const_uniform_block
) {
3237 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3238 const_uniform_block
->u32
[0];
3239 surf_index
= brw_imm_ud(index
);
3240 brw_mark_surface_used(prog_data
, index
);
3242 surf_index
= vgrf(glsl_type::uint_type
);
3243 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3244 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3246 brw_mark_surface_used(prog_data
,
3247 stage_prog_data
->binding_table
.ssbo_start
+
3248 nir
->info
.num_ssbos
- 1);
3252 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3255 unsigned writemask
= instr
->const_index
[0];
3257 /* Combine groups of consecutive enabled channels in one write
3258 * message. We use ffs to find the first enabled channel and then ffs on
3259 * the bit-inverse, down-shifted writemask to determine the length of
3260 * the block of enabled bits.
3263 unsigned first_component
= ffs(writemask
) - 1;
3264 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3267 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3269 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
3271 offset_reg
= vgrf(glsl_type::uint_type
);
3273 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3274 brw_imm_ud(4 * first_component
));
3277 emit_untyped_write(bld
, surf_index
, offset_reg
,
3278 offset(val_reg
, bld
, first_component
),
3279 1 /* dims */, length
,
3280 BRW_PREDICATE_NONE
);
3282 /* Clear the bits in the writemask that we just wrote, then try
3283 * again to see if more channels are left.
3285 writemask
&= (15 << (first_component
+ length
));
3290 case nir_intrinsic_store_output
: {
3291 fs_reg src
= get_nir_src(instr
->src
[0]);
3292 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3293 instr
->const_index
[0]);
3295 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3296 assert(const_offset
&& "Indirect output stores not allowed");
3297 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3299 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3300 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
3305 case nir_intrinsic_ssbo_atomic_add
:
3306 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
3308 case nir_intrinsic_ssbo_atomic_imin
:
3309 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
3311 case nir_intrinsic_ssbo_atomic_umin
:
3312 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
3314 case nir_intrinsic_ssbo_atomic_imax
:
3315 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
3317 case nir_intrinsic_ssbo_atomic_umax
:
3318 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
3320 case nir_intrinsic_ssbo_atomic_and
:
3321 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
3323 case nir_intrinsic_ssbo_atomic_or
:
3324 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
3326 case nir_intrinsic_ssbo_atomic_xor
:
3327 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
3329 case nir_intrinsic_ssbo_atomic_exchange
:
3330 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
3332 case nir_intrinsic_ssbo_atomic_comp_swap
:
3333 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3336 case nir_intrinsic_get_buffer_size
: {
3337 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
3338 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
3339 int reg_width
= dispatch_width
/ 8;
3342 fs_reg source
= brw_imm_d(0);
3344 int mlen
= 1 * reg_width
;
3346 /* A resinfo's sampler message is used to get the buffer size.
3347 * The SIMD8's writeback message consists of four registers and
3348 * SIMD16's writeback message consists of 8 destination registers
3349 * (two per each component), although we are only interested on the
3350 * first component, where resinfo returns the buffer size for
3353 int regs_written
= 4 * mlen
;
3354 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
3355 BRW_REGISTER_TYPE_UD
);
3356 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
3357 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
3358 BRW_REGISTER_TYPE_UD
);
3359 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
3360 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
3361 src_payload
, brw_imm_ud(index
));
3362 inst
->header_size
= 0;
3364 inst
->regs_written
= regs_written
;
3366 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
3368 brw_mark_surface_used(prog_data
, index
);
3373 unreachable("unknown intrinsic");
3378 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
3379 int op
, nir_intrinsic_instr
*instr
)
3382 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3383 dest
= get_nir_dest(instr
->dest
);
3386 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3387 if (const_surface
) {
3388 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3389 const_surface
->u32
[0];
3390 surface
= brw_imm_ud(surf_index
);
3391 brw_mark_surface_used(prog_data
, surf_index
);
3393 surface
= vgrf(glsl_type::uint_type
);
3394 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3395 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3397 /* Assume this may touch any SSBO. This is the same we do for other
3398 * UBO/SSBO accesses with non-constant surface.
3400 brw_mark_surface_used(prog_data
,
3401 stage_prog_data
->binding_table
.ssbo_start
+
3402 nir
->info
.num_ssbos
- 1);
3405 fs_reg offset
= get_nir_src(instr
->src
[1]);
3406 fs_reg data1
= get_nir_src(instr
->src
[2]);
3408 if (op
== BRW_AOP_CMPWR
)
3409 data2
= get_nir_src(instr
->src
[3]);
3411 /* Emit the actual atomic operation operation */
3413 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3415 1 /* dims */, 1 /* rsize */,
3417 BRW_PREDICATE_NONE
);
3418 dest
.type
= atomic_result
.type
;
3419 bld
.MOV(dest
, atomic_result
);
3423 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3424 int op
, nir_intrinsic_instr
*instr
)
3427 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3428 dest
= get_nir_dest(instr
->dest
);
3430 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3431 fs_reg offset
= get_nir_src(instr
->src
[0]);
3432 fs_reg data1
= get_nir_src(instr
->src
[1]);
3434 if (op
== BRW_AOP_CMPWR
)
3435 data2
= get_nir_src(instr
->src
[2]);
3437 /* Emit the actual atomic operation operation */
3439 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3441 1 /* dims */, 1 /* rsize */,
3443 BRW_PREDICATE_NONE
);
3444 dest
.type
= atomic_result
.type
;
3445 bld
.MOV(dest
, atomic_result
);
3449 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3451 unsigned texture
= instr
->texture_index
;
3452 unsigned sampler
= instr
->sampler_index
;
3454 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3456 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
3457 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
3459 int lod_components
= 0;
3461 /* The hardware requires a LOD for buffer textures */
3462 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3463 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
3465 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3466 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3467 switch (instr
->src
[i
].src_type
) {
3468 case nir_tex_src_bias
:
3469 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3471 case nir_tex_src_comparitor
:
3472 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
3474 case nir_tex_src_coord
:
3475 switch (instr
->op
) {
3477 case nir_texop_txf_ms
:
3478 case nir_texop_samples_identical
:
3479 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
3482 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
3486 case nir_tex_src_ddx
:
3487 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3488 lod_components
= nir_tex_instr_src_size(instr
, i
);
3490 case nir_tex_src_ddy
:
3491 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
3493 case nir_tex_src_lod
:
3494 switch (instr
->op
) {
3496 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3499 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_D
);
3502 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3506 case nir_tex_src_ms_index
:
3507 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3510 case nir_tex_src_offset
: {
3511 nir_const_value
*const_offset
=
3512 nir_src_as_const_value(instr
->src
[i
].src
);
3514 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
3515 if (header_bits
!= 0)
3516 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
3518 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
3519 retype(src
, BRW_REGISTER_TYPE_D
);
3524 case nir_tex_src_projector
:
3525 unreachable("should be lowered");
3527 case nir_tex_src_texture_offset
: {
3528 /* Figure out the highest possible texture index and mark it as used */
3529 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3530 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3531 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3533 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3535 brw_mark_surface_used(prog_data
, max_used
);
3537 /* Emit code to evaluate the actual indexing expression */
3538 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3539 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
3540 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
3544 case nir_tex_src_sampler_offset
: {
3545 /* Emit code to evaluate the actual indexing expression */
3546 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3547 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
3548 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
3553 unreachable("unknown texture source");
3557 if (instr
->op
== nir_texop_txf_ms
||
3558 instr
->op
== nir_texop_samples_identical
) {
3559 if (devinfo
->gen
>= 7 &&
3560 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3561 srcs
[TEX_LOGICAL_SRC_MCS
] =
3562 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
3563 instr
->coord_components
,
3564 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3566 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
3570 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
3571 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
3573 if (instr
->op
== nir_texop_query_levels
) {
3574 /* textureQueryLevels() is implemented in terms of TXS so we need to
3575 * pass a valid LOD argument.
3577 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
3578 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
3582 switch (instr
->op
) {
3584 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
3587 opcode
= FS_OPCODE_TXB_LOGICAL
;
3590 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
3593 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
3596 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
3598 case nir_texop_txf_ms
:
3599 if ((key_tex
->msaa_16
& (1 << sampler
)))
3600 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
3602 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
3604 case nir_texop_query_levels
:
3606 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
3609 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
3612 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
3613 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
3614 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
3616 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
3618 case nir_texop_texture_samples
: {
3619 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3621 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 4);
3622 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, tmp
,
3623 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3624 srcs
[TEX_LOGICAL_SRC_SURFACE
],
3625 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3627 inst
->header_size
= 1;
3628 inst
->base_mrf
= -1;
3629 inst
->regs_written
= 4 * (dispatch_width
/ 8);
3631 /* Pick off the one component we care about */
3635 case nir_texop_samples_identical
: {
3636 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3638 /* If mcs is an immediate value, it means there is no MCS. In that case
3639 * just return false.
3641 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
3642 bld
.MOV(dst
, brw_imm_ud(0u));
3643 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
3644 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3645 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
3646 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
3647 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
3649 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
3650 BRW_CONDITIONAL_EQ
);
3655 unreachable("unknown texture opcode");
3658 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
3659 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
3661 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
3662 if (devinfo
->gen
>= 9 &&
3663 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
3664 unsigned write_mask
= instr
->dest
.is_ssa
?
3665 nir_ssa_def_components_read(&instr
->dest
.ssa
):
3666 (1 << dest_size
) - 1;
3667 assert(write_mask
!= 0); /* dead code should have been eliminated */
3668 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
3670 inst
->regs_written
= 4 * dispatch_width
/ 8;
3673 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
3674 inst
->shadow_compare
= true;
3676 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
3677 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
3679 if (instr
->op
== nir_texop_tg4
) {
3680 if (instr
->component
== 1 &&
3681 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
3682 /* gather4 sampler is broken for green channel on RG32F --
3683 * we must ask for blue instead.
3685 inst
->offset
|= 2 << 16;
3687 inst
->offset
|= instr
->component
<< 16;
3690 if (devinfo
->gen
== 6)
3691 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
3695 for (unsigned i
= 0; i
< dest_size
; i
++)
3696 nir_dest
[i
] = offset(dst
, bld
, i
);
3698 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3701 if (instr
->op
== nir_texop_query_levels
) {
3702 /* # levels is in .w */
3703 nir_dest
[0] = offset(dst
, bld
, 3);
3704 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
3705 (devinfo
->gen
< 7 || is_cube_array
)) {
3706 fs_reg depth
= offset(dst
, bld
, 2);
3707 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
3709 if (is_cube_array
) {
3710 /* fixup #layers for cube map arrays */
3711 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
3712 } else if (devinfo
->gen
< 7) {
3713 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
3714 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
3717 nir_dest
[2] = fixed_depth
;
3720 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
3724 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3726 switch (instr
->type
) {
3727 case nir_jump_break
:
3728 bld
.emit(BRW_OPCODE_BREAK
);
3730 case nir_jump_continue
:
3731 bld
.emit(BRW_OPCODE_CONTINUE
);
3733 case nir_jump_return
:
3735 unreachable("unknown jump");