2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_outputs()
54 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
57 nir_foreach_variable(var
, &nir
->outputs
) {
58 const unsigned vec4s
=
59 var
->data
.compact
? DIV_ROUND_UP(glsl_get_length(var
->type
), 4)
60 : type_size_vec4(var
->type
);
61 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4 * vec4s
);
62 for (unsigned i
= 0; i
< vec4s
; i
++) {
63 if (outputs
[var
->data
.driver_location
+ i
].file
== BAD_FILE
)
64 outputs
[var
->data
.driver_location
+ i
] = offset(reg
, bld
, 4 * i
);
70 fs_visitor::nir_setup_uniforms()
72 if (dispatch_width
!= min_dispatch_width
)
75 uniforms
= nir
->num_uniforms
/ 4;
79 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
83 nir_foreach_instr(instr
, block
) {
84 if (instr
->type
!= nir_instr_type_intrinsic
)
87 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
88 switch (intrin
->intrinsic
) {
89 case nir_intrinsic_load_vertex_id
:
90 unreachable("should be lowered by lower_vertex_id().");
92 case nir_intrinsic_load_vertex_id_zero_base
:
93 assert(v
->stage
== MESA_SHADER_VERTEX
);
94 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
95 if (reg
->file
== BAD_FILE
)
96 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
99 case nir_intrinsic_load_base_vertex
:
100 assert(v
->stage
== MESA_SHADER_VERTEX
);
101 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
102 if (reg
->file
== BAD_FILE
)
103 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
106 case nir_intrinsic_load_instance_id
:
107 assert(v
->stage
== MESA_SHADER_VERTEX
);
108 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
109 if (reg
->file
== BAD_FILE
)
110 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
113 case nir_intrinsic_load_base_instance
:
114 assert(v
->stage
== MESA_SHADER_VERTEX
);
115 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
116 if (reg
->file
== BAD_FILE
)
117 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
120 case nir_intrinsic_load_draw_id
:
121 assert(v
->stage
== MESA_SHADER_VERTEX
);
122 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
123 if (reg
->file
== BAD_FILE
)
124 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
127 case nir_intrinsic_load_invocation_id
:
128 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
130 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
131 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
132 if (reg
->file
== BAD_FILE
) {
133 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
134 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
135 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
136 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
141 case nir_intrinsic_load_sample_pos
:
142 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
143 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
144 if (reg
->file
== BAD_FILE
)
145 *reg
= *v
->emit_samplepos_setup();
148 case nir_intrinsic_load_sample_id
:
149 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
150 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
151 if (reg
->file
== BAD_FILE
)
152 *reg
= *v
->emit_sampleid_setup();
155 case nir_intrinsic_load_sample_mask_in
:
156 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
157 assert(v
->devinfo
->gen
>= 7);
158 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
159 if (reg
->file
== BAD_FILE
)
160 *reg
= *v
->emit_samplemaskin_setup();
163 case nir_intrinsic_load_work_group_id
:
164 assert(v
->stage
== MESA_SHADER_COMPUTE
);
165 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
166 if (reg
->file
== BAD_FILE
)
167 *reg
= *v
->emit_cs_work_group_id_setup();
170 case nir_intrinsic_load_helper_invocation
:
171 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
172 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
173 if (reg
->file
== BAD_FILE
) {
174 const fs_builder abld
=
175 v
->bld
.annotate("gl_HelperInvocation", NULL
);
177 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
178 * pixel mask is in g1.7 of the thread payload.
180 * We move the per-channel pixel enable bit to the low bit of each
181 * channel by shifting the byte containing the pixel mask by the
182 * vector immediate 0x76543210UV.
184 * The region of <1,8,0> reads only 1 byte (the pixel masks for
185 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
186 * masks for 2 and 3) in SIMD16.
188 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
190 stride(byte_offset(retype(brw_vec1_grf(1, 0),
191 BRW_REGISTER_TYPE_UB
), 28),
193 brw_imm_v(0x76543210));
195 /* A set bit in the pixel mask means the channel is enabled, but
196 * that is the opposite of gl_HelperInvocation so we need to invert
199 * The negate source-modifier bit of logical instructions on Gen8+
200 * performs 1's complement negation, so we can use that instead of
203 fs_reg inverted
= negate(shifted
);
204 if (v
->devinfo
->gen
< 8) {
205 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
206 abld
.NOT(inverted
, shifted
);
209 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
210 * with 1 and negating.
212 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
213 abld
.AND(anded
, inverted
, brw_imm_uw(1));
215 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
216 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
230 fs_visitor::nir_emit_system_values()
232 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
233 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
234 nir_system_values
[i
] = fs_reg();
237 nir_foreach_function(function
, nir
) {
238 assert(strcmp(function
->name
, "main") == 0);
239 assert(function
->impl
);
240 nir_foreach_block(block
, function
->impl
) {
241 emit_system_values_block(block
, this);
247 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
249 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
250 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
251 nir_locals
[i
] = fs_reg();
254 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
255 unsigned array_elems
=
256 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
257 unsigned size
= array_elems
* reg
->num_components
;
258 const brw_reg_type reg_type
=
259 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
260 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
263 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
266 nir_emit_cf_list(&impl
->body
);
270 fs_visitor::nir_emit_cf_list(exec_list
*list
)
272 exec_list_validate(list
);
273 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
274 switch (node
->type
) {
276 nir_emit_if(nir_cf_node_as_if(node
));
279 case nir_cf_node_loop
:
280 nir_emit_loop(nir_cf_node_as_loop(node
));
283 case nir_cf_node_block
:
284 nir_emit_block(nir_cf_node_as_block(node
));
288 unreachable("Invalid CFG node block");
294 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
296 /* first, put the condition into f0 */
297 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
298 retype(get_nir_src(if_stmt
->condition
),
299 BRW_REGISTER_TYPE_D
));
300 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
302 bld
.IF(BRW_PREDICATE_NORMAL
);
304 nir_emit_cf_list(&if_stmt
->then_list
);
306 /* note: if the else is empty, dead CF elimination will remove it */
307 bld
.emit(BRW_OPCODE_ELSE
);
309 nir_emit_cf_list(&if_stmt
->else_list
);
311 bld
.emit(BRW_OPCODE_ENDIF
);
315 fs_visitor::nir_emit_loop(nir_loop
*loop
)
317 bld
.emit(BRW_OPCODE_DO
);
319 nir_emit_cf_list(&loop
->body
);
321 bld
.emit(BRW_OPCODE_WHILE
);
325 fs_visitor::nir_emit_block(nir_block
*block
)
327 nir_foreach_instr(instr
, block
) {
328 nir_emit_instr(instr
);
333 fs_visitor::nir_emit_instr(nir_instr
*instr
)
335 const fs_builder abld
= bld
.annotate(NULL
, instr
);
337 switch (instr
->type
) {
338 case nir_instr_type_alu
:
339 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
342 case nir_instr_type_intrinsic
:
344 case MESA_SHADER_VERTEX
:
345 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
347 case MESA_SHADER_TESS_CTRL
:
348 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
350 case MESA_SHADER_TESS_EVAL
:
351 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
353 case MESA_SHADER_GEOMETRY
:
354 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
356 case MESA_SHADER_FRAGMENT
:
357 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
359 case MESA_SHADER_COMPUTE
:
360 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
363 unreachable("unsupported shader stage");
367 case nir_instr_type_tex
:
368 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
371 case nir_instr_type_load_const
:
372 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
375 case nir_instr_type_ssa_undef
:
376 /* We create a new VGRF for undefs on every use (by handling
377 * them in get_nir_src()), rather than for each definition.
378 * This helps register coalescing eliminate MOVs from undef.
382 case nir_instr_type_jump
:
383 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
387 unreachable("unknown instruction type");
392 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
396 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
397 const fs_reg
&result
)
399 if (!instr
->src
[0].src
.is_ssa
||
400 !instr
->src
[0].src
.ssa
->parent_instr
)
403 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
406 nir_alu_instr
*src0
=
407 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
409 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
410 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
413 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
414 assert(element
!= NULL
);
416 /* Element type to extract.*/
417 const brw_reg_type type
= brw_int_type(
418 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
419 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
421 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
422 op0
.type
= brw_type_for_nir_type(
423 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
424 nir_src_bit_size(src0
->src
[0].src
)));
425 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
427 set_saturate(instr
->dest
.saturate
,
428 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
433 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
434 const fs_reg
&result
)
436 if (!instr
->src
[0].src
.is_ssa
||
437 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
440 nir_intrinsic_instr
*src0
=
441 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
443 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
446 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
447 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
450 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
451 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
454 fs_reg tmp
= vgrf(glsl_type::int_type
);
456 if (devinfo
->gen
>= 6) {
457 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
458 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
460 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
462 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
463 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
465 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
467 * This negation looks like it's safe in practice, because bits 0:4 will
468 * surely be TRIANGLES
471 if (value1
->f32
[0] == -1.0f
) {
475 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
476 g0
, brw_imm_uw(0x3f80));
478 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
479 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
481 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
483 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
484 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
486 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
488 * This negation looks like it's safe in practice, because bits 0:4 will
489 * surely be TRIANGLES
492 if (value1
->f32
[0] == -1.0f
) {
496 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
498 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
504 emit_find_msb_using_lzd(const fs_builder
&bld
,
505 const fs_reg
&result
,
513 /* LZD of an absolute value source almost always does the right
514 * thing. There are two problem values:
516 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
517 * 0. However, findMSB(int(0x80000000)) == 30.
519 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
520 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
522 * For a value of zero or negative one, -1 will be returned.
524 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
525 * findMSB(-(1<<x)) should return x-1.
527 * For all negative number cases, including 0x80000000 and
528 * 0xffffffff, the correct value is obtained from LZD if instead of
529 * negating the (already negative) value the logical-not is used. A
530 * conditonal logical-not can be achieved in two instructions.
532 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
534 bld
.ASR(temp
, src
, brw_imm_d(31));
535 bld
.XOR(temp
, temp
, src
);
538 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
539 retype(temp
, BRW_REGISTER_TYPE_UD
));
541 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
542 * from the LSB side. Subtract the result from 31 to convert the MSB
543 * count into an LSB count. If no bits are set, LZD will return 32.
544 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
546 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
547 inst
->src
[0].negate
= true;
551 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
553 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
556 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
557 result
.type
= brw_type_for_nir_type(
558 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
559 nir_dest_bit_size(instr
->dest
.dest
)));
562 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
563 op
[i
] = get_nir_src(instr
->src
[i
].src
);
564 op
[i
].type
= brw_type_for_nir_type(
565 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
566 nir_src_bit_size(instr
->src
[i
].src
)));
567 op
[i
].abs
= instr
->src
[i
].abs
;
568 op
[i
].negate
= instr
->src
[i
].negate
;
571 /* We get a bunch of mov's out of the from_ssa pass and they may still
572 * be vectorized. We'll handle them as a special-case. We'll also
573 * handle vecN here because it's basically the same thing.
581 fs_reg temp
= result
;
582 bool need_extra_copy
= false;
583 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
584 if (!instr
->src
[i
].src
.is_ssa
&&
585 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
586 need_extra_copy
= true;
587 temp
= bld
.vgrf(result
.type
, 4);
592 for (unsigned i
= 0; i
< 4; i
++) {
593 if (!(instr
->dest
.write_mask
& (1 << i
)))
596 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
597 inst
= bld
.MOV(offset(temp
, bld
, i
),
598 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
600 inst
= bld
.MOV(offset(temp
, bld
, i
),
601 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
603 inst
->saturate
= instr
->dest
.saturate
;
606 /* In this case the source and destination registers were the same,
607 * so we need to insert an extra set of moves in order to deal with
610 if (need_extra_copy
) {
611 for (unsigned i
= 0; i
< 4; i
++) {
612 if (!(instr
->dest
.write_mask
& (1 << i
)))
615 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
624 /* At this point, we have dealt with any instruction that operates on
625 * more than a single channel. Therefore, we can just adjust the source
626 * and destination registers for that channel and emit the instruction.
628 unsigned channel
= 0;
629 if (nir_op_infos
[instr
->op
].output_size
== 0) {
630 /* Since NIR is doing the scalarizing for us, we should only ever see
631 * vectorized operations with a single channel.
633 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
634 channel
= ffs(instr
->dest
.write_mask
) - 1;
636 result
= offset(result
, bld
, channel
);
639 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
640 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
641 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
647 if (optimize_extract_to_float(instr
, result
))
649 inst
= bld
.MOV(result
, op
[0]);
650 inst
->saturate
= instr
->dest
.saturate
;
663 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
665 * "When source or destination is 64b (...), regioning in Align1
666 * must follow these rules:
668 * 1. Source and destination horizontal stride must be aligned to
672 * This means that 32-bit to 64-bit conversions need to have the 32-bit
673 * data elements aligned to 64-bit. This restriction does not apply to
676 if (nir_dest_bit_size(instr
->dest
.dest
) == 64 &&
677 nir_src_bit_size(instr
->src
[0].src
) == 32 &&
678 (devinfo
->is_cherryview
|| devinfo
->is_broxton
)) {
679 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
680 tmp
= subscript(tmp
, op
[0].type
, 0);
681 inst
= bld
.MOV(tmp
, op
[0]);
682 inst
= bld
.MOV(result
, tmp
);
683 inst
->saturate
= instr
->dest
.saturate
;
690 if (instr
->op
== nir_op_b2i64
) {
691 bld
.MOV(result
, negate(op
[0]));
693 inst
= bld
.MOV(result
, op
[0]);
694 inst
->saturate
= instr
->dest
.saturate
;
700 bld
.MOV(result
, op
[0]);
704 if (type_sz(op
[0].type
) < 8) {
705 /* AND(val, 0x80000000) gives the sign bit.
707 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
710 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
712 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
713 op
[0].type
= BRW_REGISTER_TYPE_UD
;
714 result
.type
= BRW_REGISTER_TYPE_UD
;
715 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
717 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
718 inst
->predicate
= BRW_PREDICATE_NORMAL
;
719 if (instr
->dest
.saturate
) {
720 inst
= bld
.MOV(result
, result
);
721 inst
->saturate
= true;
724 /* For doubles we do the same but we need to consider:
726 * - 2-src instructions can't operate with 64-bit immediates
727 * - The sign is encoded in the high 32-bit of each DF
728 * - CMP with DF requires special handling in SIMD16
729 * - We need to produce a DF result.
732 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
733 * a register and compare with that.
735 fs_reg tmp
= vgrf(glsl_type::double_type
);
736 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
738 /* A direct DF CMP using the flag register (null dst) won't work in
739 * SIMD16 because the CMP will be split in two by lower_simd_width,
740 * resulting in two CMP instructions with the same dst (NULL),
741 * leading to dead code elimination of the first one. In SIMD8,
742 * however, there is no need to split the CMP and we can save some
745 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
746 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
748 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
749 * so we store the result of the comparison in a vgrf instead and
750 * then we generate a UD comparison from that that won't have to
751 * be split by lower_simd_width. This is what NIR does to handle
752 * double comparisons in the general case.
754 if (bld
.dispatch_width() == 16 ) {
755 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
756 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
757 bld
.CMP(bld
.null_reg_ud(),
758 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
761 /* Get the high 32-bit of each double component where the sign is */
762 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
763 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
765 /* Get the sign bit */
766 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
768 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
769 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
770 inst
->predicate
= BRW_PREDICATE_NORMAL
;
772 /* Convert from 32-bit float to 64-bit double */
773 result
.type
= BRW_REGISTER_TYPE_DF
;
774 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
776 if (instr
->dest
.saturate
) {
777 inst
= bld
.MOV(result
, result
);
778 inst
->saturate
= true;
785 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
786 * -> non-negative val generates 0x00000000.
787 * Predicated OR sets 1 if val is positive.
789 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
790 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
791 bld
.ASR(result
, op
[0], brw_imm_d(31));
792 inst
= bld
.OR(result
, result
, brw_imm_d(1));
793 inst
->predicate
= BRW_PREDICATE_NORMAL
;
797 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
798 inst
->saturate
= instr
->dest
.saturate
;
802 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
803 inst
->saturate
= instr
->dest
.saturate
;
807 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
808 inst
->saturate
= instr
->dest
.saturate
;
812 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
813 inst
->saturate
= instr
->dest
.saturate
;
817 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
818 inst
->saturate
= instr
->dest
.saturate
;
822 if (fs_key
->high_quality_derivatives
) {
823 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
825 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
827 inst
->saturate
= instr
->dest
.saturate
;
829 case nir_op_fddx_fine
:
830 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
831 inst
->saturate
= instr
->dest
.saturate
;
833 case nir_op_fddx_coarse
:
834 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
835 inst
->saturate
= instr
->dest
.saturate
;
838 if (fs_key
->high_quality_derivatives
) {
839 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
841 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
843 inst
->saturate
= instr
->dest
.saturate
;
845 case nir_op_fddy_fine
:
846 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
847 inst
->saturate
= instr
->dest
.saturate
;
849 case nir_op_fddy_coarse
:
850 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
851 inst
->saturate
= instr
->dest
.saturate
;
855 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
857 inst
= bld
.ADD(result
, op
[0], op
[1]);
858 inst
->saturate
= instr
->dest
.saturate
;
862 inst
= bld
.MUL(result
, op
[0], op
[1]);
863 inst
->saturate
= instr
->dest
.saturate
;
867 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
868 bld
.MUL(result
, op
[0], op
[1]);
871 case nir_op_imul_high
:
872 case nir_op_umul_high
:
873 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
874 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
879 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
880 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
883 case nir_op_uadd_carry
:
884 unreachable("Should have been lowered by carry_to_arith().");
886 case nir_op_usub_borrow
:
887 unreachable("Should have been lowered by borrow_to_arith().");
891 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
892 * appears that our hardware just does the right thing for signed
895 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
896 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
900 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
901 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
903 /* Math instructions don't support conditional mod */
904 inst
= bld
.MOV(bld
.null_reg_d(), result
);
905 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
907 /* Now, we need to determine if signs of the sources are different.
908 * When we XOR the sources, the top bit is 0 if they are the same and 1
909 * if they are different. We can then use a conditional modifier to
910 * turn that into a predicate. This leads us to an XOR.l instruction.
912 * Technically, according to the PRM, you're not allowed to use .l on a
913 * XOR instruction. However, emperical experiments and Curro's reading
914 * of the simulator source both indicate that it's safe.
916 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
917 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
918 inst
->predicate
= BRW_PREDICATE_NORMAL
;
919 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
921 /* If the result of the initial remainder operation is non-zero and the
922 * two sources have different signs, add in a copy of op[1] to get the
923 * final integer modulus value.
925 inst
= bld
.ADD(result
, result
, op
[1]);
926 inst
->predicate
= BRW_PREDICATE_NORMAL
;
934 fs_reg dest
= result
;
935 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
936 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
938 brw_conditional_mod cond
;
941 cond
= BRW_CONDITIONAL_L
;
944 cond
= BRW_CONDITIONAL_GE
;
947 cond
= BRW_CONDITIONAL_Z
;
950 cond
= BRW_CONDITIONAL_NZ
;
953 unreachable("bad opcode");
955 bld
.CMP(dest
, op
[0], op
[1], cond
);
956 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
957 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
964 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
965 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
970 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
971 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
975 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
976 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
980 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
981 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
985 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
986 if (devinfo
->gen
>= 8) {
987 op
[0] = resolve_source_modifiers(op
[0]);
989 bld
.NOT(result
, op
[0]);
992 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
993 if (devinfo
->gen
>= 8) {
994 op
[0] = resolve_source_modifiers(op
[0]);
995 op
[1] = resolve_source_modifiers(op
[1]);
997 bld
.XOR(result
, op
[0], op
[1]);
1000 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1001 if (devinfo
->gen
>= 8) {
1002 op
[0] = resolve_source_modifiers(op
[0]);
1003 op
[1] = resolve_source_modifiers(op
[1]);
1005 bld
.OR(result
, op
[0], op
[1]);
1008 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1009 if (devinfo
->gen
>= 8) {
1010 op
[0] = resolve_source_modifiers(op
[0]);
1011 op
[1] = resolve_source_modifiers(op
[1]);
1013 bld
.AND(result
, op
[0], op
[1]);
1019 case nir_op_ball_fequal2
:
1020 case nir_op_ball_iequal2
:
1021 case nir_op_ball_fequal3
:
1022 case nir_op_ball_iequal3
:
1023 case nir_op_ball_fequal4
:
1024 case nir_op_ball_iequal4
:
1025 case nir_op_bany_fnequal2
:
1026 case nir_op_bany_inequal2
:
1027 case nir_op_bany_fnequal3
:
1028 case nir_op_bany_inequal3
:
1029 case nir_op_bany_fnequal4
:
1030 case nir_op_bany_inequal4
:
1031 unreachable("Lowered by nir_lower_alu_reductions");
1033 case nir_op_fnoise1_1
:
1034 case nir_op_fnoise1_2
:
1035 case nir_op_fnoise1_3
:
1036 case nir_op_fnoise1_4
:
1037 case nir_op_fnoise2_1
:
1038 case nir_op_fnoise2_2
:
1039 case nir_op_fnoise2_3
:
1040 case nir_op_fnoise2_4
:
1041 case nir_op_fnoise3_1
:
1042 case nir_op_fnoise3_2
:
1043 case nir_op_fnoise3_3
:
1044 case nir_op_fnoise3_4
:
1045 case nir_op_fnoise4_1
:
1046 case nir_op_fnoise4_2
:
1047 case nir_op_fnoise4_3
:
1048 case nir_op_fnoise4_4
:
1049 unreachable("not reached: should be handled by lower_noise");
1052 unreachable("not reached: should be handled by ldexp_to_arith()");
1055 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1056 inst
->saturate
= instr
->dest
.saturate
;
1060 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1061 inst
->saturate
= instr
->dest
.saturate
;
1066 bld
.MOV(result
, negate(op
[0]));
1070 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1073 /* two-argument instructions can't take 64-bit immediates */
1074 fs_reg zero
= vgrf(glsl_type::double_type
);
1075 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1076 /* A SIMD16 execution needs to be split in two instructions, so use
1077 * a vgrf instead of the flag register as dst so instruction splitting
1080 fs_reg tmp
= vgrf(glsl_type::double_type
);
1081 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1082 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1086 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1090 inst
= bld
.RNDZ(result
, op
[0]);
1091 inst
->saturate
= instr
->dest
.saturate
;
1094 case nir_op_fceil
: {
1095 op
[0].negate
= !op
[0].negate
;
1096 fs_reg temp
= vgrf(glsl_type::float_type
);
1097 bld
.RNDD(temp
, op
[0]);
1099 inst
= bld
.MOV(result
, temp
);
1100 inst
->saturate
= instr
->dest
.saturate
;
1104 inst
= bld
.RNDD(result
, op
[0]);
1105 inst
->saturate
= instr
->dest
.saturate
;
1108 inst
= bld
.FRC(result
, op
[0]);
1109 inst
->saturate
= instr
->dest
.saturate
;
1111 case nir_op_fround_even
:
1112 inst
= bld
.RNDE(result
, op
[0]);
1113 inst
->saturate
= instr
->dest
.saturate
;
1116 case nir_op_fquantize2f16
: {
1117 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1118 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1119 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1121 /* The destination stride must be at least as big as the source stride. */
1122 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1125 /* Check for denormal */
1126 fs_reg abs_src0
= op
[0];
1127 abs_src0
.abs
= true;
1128 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1130 /* Get the appropriately signed zero */
1131 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1132 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1133 brw_imm_ud(0x80000000));
1134 /* Do the actual F32 -> F16 -> F32 conversion */
1135 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1136 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1137 /* Select that or zero based on normal status */
1138 inst
= bld
.SEL(result
, zero
, tmp32
);
1139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1140 inst
->saturate
= instr
->dest
.saturate
;
1146 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1148 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1149 inst
->saturate
= instr
->dest
.saturate
;
1154 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1156 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1157 inst
->saturate
= instr
->dest
.saturate
;
1160 case nir_op_pack_snorm_2x16
:
1161 case nir_op_pack_snorm_4x8
:
1162 case nir_op_pack_unorm_2x16
:
1163 case nir_op_pack_unorm_4x8
:
1164 case nir_op_unpack_snorm_2x16
:
1165 case nir_op_unpack_snorm_4x8
:
1166 case nir_op_unpack_unorm_2x16
:
1167 case nir_op_unpack_unorm_4x8
:
1168 case nir_op_unpack_half_2x16
:
1169 case nir_op_pack_half_2x16
:
1170 unreachable("not reached: should be handled by lower_packing_builtins");
1172 case nir_op_unpack_half_2x16_split_x
:
1173 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1174 inst
->saturate
= instr
->dest
.saturate
;
1176 case nir_op_unpack_half_2x16_split_y
:
1177 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1178 inst
->saturate
= instr
->dest
.saturate
;
1181 case nir_op_pack_double_2x32_split
:
1182 /* Optimize the common case where we are re-packing a double with
1183 * the result of a previous double unpack. In this case we can take the
1184 * 32-bit value to use in the re-pack from the original double and bypass
1185 * the unpack operation.
1187 for (int i
= 0; i
< 2; i
++) {
1188 if (instr
->src
[i
].src
.is_ssa
)
1191 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1192 if (parent_instr
->type
== nir_instr_type_alu
)
1195 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1196 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1197 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1200 if (!alu_parent
->src
[0].src
.is_ssa
)
1203 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1204 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1205 alu_parent
->src
[0].swizzle
[channel
]);
1206 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1207 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1209 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1211 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1214 case nir_op_unpack_double_2x32_split_x
:
1215 case nir_op_unpack_double_2x32_split_y
: {
1216 /* Optimize the common case where we are unpacking from a double we have
1217 * previously packed. In this case we can just bypass the pack operation
1218 * and source directly from its arguments.
1220 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1221 if (instr
->src
[0].src
.is_ssa
) {
1222 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1223 if (parent_instr
->type
== nir_instr_type_alu
) {
1224 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1225 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1226 alu_parent
->src
[index
].src
.is_ssa
) {
1227 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1228 BRW_REGISTER_TYPE_UD
);
1230 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1231 bld
.MOV(result
, op
[0]);
1237 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1238 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1240 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1244 case nir_op_pack_int_2x32_split
:
1245 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1248 case nir_op_unpack_int_2x32_split_x
:
1249 case nir_op_unpack_int_2x32_split_y
: {
1250 if (instr
->op
== nir_op_unpack_int_2x32_split_x
)
1251 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1253 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1258 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1259 inst
->saturate
= instr
->dest
.saturate
;
1262 case nir_op_bitfield_reverse
:
1263 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1264 bld
.BFREV(result
, op
[0]);
1267 case nir_op_bit_count
:
1268 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1269 bld
.CBIT(result
, op
[0]);
1272 case nir_op_ufind_msb
: {
1273 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1274 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1278 case nir_op_ifind_msb
: {
1279 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1281 if (devinfo
->gen
< 7) {
1282 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1284 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1286 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1287 * count from the LSB side. If FBH didn't return an error
1288 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1289 * count into an LSB count.
1291 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1293 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1294 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1295 inst
->src
[0].negate
= true;
1300 case nir_op_find_lsb
:
1301 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1303 if (devinfo
->gen
< 7) {
1304 fs_reg temp
= vgrf(glsl_type::int_type
);
1306 /* (x & -x) generates a value that consists of only the LSB of x.
1307 * For all powers of 2, findMSB(y) == findLSB(y).
1309 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1310 fs_reg negated_src
= src
;
1312 /* One must be negated, and the other must be non-negated. It
1313 * doesn't matter which is which.
1315 negated_src
.negate
= true;
1318 bld
.AND(temp
, src
, negated_src
);
1319 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1321 bld
.FBL(result
, op
[0]);
1325 case nir_op_ubitfield_extract
:
1326 case nir_op_ibitfield_extract
:
1327 unreachable("should have been lowered");
1330 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1331 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1334 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1335 bld
.BFI1(result
, op
[0], op
[1]);
1338 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1339 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1342 case nir_op_bitfield_insert
:
1343 unreachable("not reached: should have been lowered");
1346 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1347 bld
.SHL(result
, op
[0], op
[1]);
1350 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1351 bld
.ASR(result
, op
[0], op
[1]);
1354 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1355 bld
.SHR(result
, op
[0], op
[1]);
1358 case nir_op_pack_half_2x16_split
:
1359 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1363 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1364 inst
->saturate
= instr
->dest
.saturate
;
1368 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1369 inst
->saturate
= instr
->dest
.saturate
;
1373 if (optimize_frontfacing_ternary(instr
, result
))
1376 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1377 inst
= bld
.SEL(result
, op
[1], op
[2]);
1378 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1381 case nir_op_extract_u8
:
1382 case nir_op_extract_i8
: {
1383 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1384 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1385 assert(byte
!= NULL
);
1386 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1390 case nir_op_extract_u16
:
1391 case nir_op_extract_i16
: {
1392 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1393 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1394 assert(word
!= NULL
);
1395 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1400 unreachable("unhandled instruction");
1403 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1404 * to sign extend the low bit to 0/~0
1406 if (devinfo
->gen
<= 5 &&
1407 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1408 fs_reg masked
= vgrf(glsl_type::int_type
);
1409 bld
.AND(masked
, result
, brw_imm_d(1));
1410 masked
.negate
= true;
1411 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1416 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1417 nir_load_const_instr
*instr
)
1419 const brw_reg_type reg_type
=
1420 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1421 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1423 switch (instr
->def
.bit_size
) {
1425 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1426 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1430 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1431 bld
.MOV(offset(reg
, bld
, i
),
1432 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1436 unreachable("Invalid bit size");
1439 nir_ssa_values
[instr
->def
.index
] = reg
;
1443 fs_visitor::get_nir_src(const nir_src
&src
)
1447 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1448 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1449 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1450 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1452 reg
= nir_ssa_values
[src
.ssa
->index
];
1455 /* We don't handle indirects on locals */
1456 assert(src
.reg
.indirect
== NULL
);
1457 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1458 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1461 /* to avoid floating-point denorm flushing problems, set the type by
1462 * default to D - instructions that need floating point semantics will set
1463 * this to F if they need to
1465 return retype(reg
, BRW_REGISTER_TYPE_D
);
1469 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1472 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1474 nir_const_value
*val
= nir_src_as_const_value(src
);
1475 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1479 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1482 const brw_reg_type reg_type
=
1483 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1484 nir_ssa_values
[dest
.ssa
.index
] =
1485 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1486 return nir_ssa_values
[dest
.ssa
.index
];
1488 /* We don't handle indirects on locals */
1489 assert(dest
.reg
.indirect
== NULL
);
1490 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1491 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1496 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1498 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1499 BRW_REGISTER_TYPE_UD
);
1501 unsigned indirect_max
= 0;
1503 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1504 tail
= tail
->child
) {
1505 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1506 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1507 const unsigned size
= glsl_get_length(tail
->type
);
1508 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1509 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1510 image
= offset(image
, bld
, base
* element_size
);
1512 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1513 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1515 /* Accessing an invalid surface index with the dataport can result
1516 * in a hang. According to the spec "if the index used to
1517 * select an individual element is negative or greater than or
1518 * equal to the size of the array, the results of the operation
1519 * are undefined but may not lead to termination" -- which is one
1520 * of the possible outcomes of the hang. Clamp the index to
1521 * prevent access outside of the array bounds.
1523 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1524 BRW_REGISTER_TYPE_UD
),
1525 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1527 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1529 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1530 if (indirect
.file
== BAD_FILE
) {
1533 bld
.ADD(indirect
, indirect
, tmp
);
1538 if (indirect
.file
== BAD_FILE
) {
1541 /* Emit a pile of MOVs to load the uniform into a temporary. The
1542 * dead-code elimination pass will get rid of what we don't use.
1544 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1545 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1546 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1547 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1548 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1555 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1558 for (unsigned i
= 0; i
< 4; i
++) {
1559 if (!((wr_mask
>> i
) & 1))
1562 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1563 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1564 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1565 if (new_inst
->src
[j
].file
== VGRF
)
1566 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1573 * Get the matching channel register datatype for an image intrinsic of the
1574 * specified GLSL image type.
1577 get_image_base_type(const glsl_type
*type
)
1579 switch ((glsl_base_type
)type
->sampled_type
) {
1580 case GLSL_TYPE_UINT
:
1581 return BRW_REGISTER_TYPE_UD
;
1583 return BRW_REGISTER_TYPE_D
;
1584 case GLSL_TYPE_FLOAT
:
1585 return BRW_REGISTER_TYPE_F
;
1587 unreachable("Not reached.");
1592 * Get the appropriate atomic op for an image atomic intrinsic.
1595 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1598 case nir_intrinsic_image_atomic_add
:
1600 case nir_intrinsic_image_atomic_min
:
1601 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1602 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1603 case nir_intrinsic_image_atomic_max
:
1604 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1605 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1606 case nir_intrinsic_image_atomic_and
:
1608 case nir_intrinsic_image_atomic_or
:
1610 case nir_intrinsic_image_atomic_xor
:
1612 case nir_intrinsic_image_atomic_exchange
:
1614 case nir_intrinsic_image_atomic_comp_swap
:
1615 return BRW_AOP_CMPWR
;
1617 unreachable("Not reachable.");
1622 emit_pixel_interpolater_send(const fs_builder
&bld
,
1627 glsl_interp_mode interpolation
)
1629 struct brw_wm_prog_data
*wm_prog_data
=
1630 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1635 if (src
.file
== BAD_FILE
) {
1637 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1641 mlen
= 2 * bld
.dispatch_width() / 8;
1644 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1646 /* 2 floats per slot returned */
1647 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1648 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1650 wm_prog_data
->pulls_bary
= true;
1656 * Computes 1 << x, given a D/UD register containing some value x.
1659 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1661 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1663 fs_reg result
= bld
.vgrf(x
.type
, 1);
1664 fs_reg one
= bld
.vgrf(x
.type
, 1);
1666 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1667 bld
.SHL(result
, one
, x
);
1672 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1674 assert(stage
== MESA_SHADER_GEOMETRY
);
1676 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1678 if (gs_compile
->control_data_header_size_bits
== 0)
1681 /* We can only do EndPrimitive() functionality when the control data
1682 * consists of cut bits. Fortunately, the only time it isn't is when the
1683 * output type is points, in which case EndPrimitive() is a no-op.
1685 if (gs_prog_data
->control_data_format
!=
1686 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1690 /* Cut bits use one bit per vertex. */
1691 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1693 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1694 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1696 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1697 * vertex n, 0 otherwise. So all we need to do here is mark bit
1698 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1699 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1700 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1702 * Note that if EndPrimitive() is called before emitting any vertices, this
1703 * will cause us to set bit 31 of the control_data_bits register to 1.
1704 * That's fine because:
1706 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1707 * output, so the hardware will ignore cut bit 31.
1709 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1710 * last vertex, so setting cut bit 31 has no effect (since the primitive
1711 * is automatically ended when the GS terminates).
1713 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1714 * control_data_bits register to 0 when the first vertex is emitted.
1717 const fs_builder abld
= bld
.annotate("end primitive");
1719 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1720 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1721 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1722 fs_reg mask
= intexp2(abld
, prev_count
);
1723 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1724 * attention to the lower 5 bits of its second source argument, so on this
1725 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1726 * ((vertex_count - 1) % 32).
1728 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1732 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1734 assert(stage
== MESA_SHADER_GEOMETRY
);
1735 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1737 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1739 const fs_builder abld
= bld
.annotate("emit control data bits");
1740 const fs_builder fwa_bld
= bld
.exec_all();
1742 /* We use a single UD register to accumulate control data bits (32 bits
1743 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1746 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1747 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1748 * use the Channel Mask phase to enable/disable which DWord within that
1749 * group to write. (Remember, different SIMD8 channels may have emitted
1750 * different numbers of vertices, so we may need per-slot offsets.)
1752 * Channel masking presents an annoying problem: we may have to replicate
1753 * the data up to 4 times:
1755 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1757 * To avoid penalizing shaders that emit a small number of vertices, we
1758 * can avoid these sometimes: if the size of the control data header is
1759 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1760 * land in the same 128-bit group, so we can skip per-slot offsets.
1762 * Similarly, if the control data header is <= 32 bits, there is only one
1763 * DWord, so we can skip channel masks.
1765 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1767 fs_reg channel_mask
, per_slot_offset
;
1769 if (gs_compile
->control_data_header_size_bits
> 32) {
1770 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1771 channel_mask
= vgrf(glsl_type::uint_type
);
1774 if (gs_compile
->control_data_header_size_bits
> 128) {
1775 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1776 per_slot_offset
= vgrf(glsl_type::uint_type
);
1779 /* Figure out which DWord we're trying to write to using the formula:
1781 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1783 * Since bits_per_vertex is a power of two, and is known at compile
1784 * time, this can be optimized to:
1786 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1788 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1789 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1790 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1791 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1792 unsigned log2_bits_per_vertex
=
1793 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1794 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1796 if (per_slot_offset
.file
!= BAD_FILE
) {
1797 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1798 * the appropriate OWord within the control data header.
1800 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1803 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1804 * write to the appropriate DWORD within the OWORD.
1806 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1807 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1808 channel_mask
= intexp2(fwa_bld
, channel
);
1809 /* Then the channel masks need to be in bits 23:16. */
1810 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1813 /* Store the control data bits in the message payload and send it. */
1815 if (channel_mask
.file
!= BAD_FILE
)
1816 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1817 if (per_slot_offset
.file
!= BAD_FILE
)
1820 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1821 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1823 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1824 if (per_slot_offset
.file
!= BAD_FILE
)
1825 sources
[i
++] = per_slot_offset
;
1826 if (channel_mask
.file
!= BAD_FILE
)
1827 sources
[i
++] = channel_mask
;
1829 sources
[i
++] = this->control_data_bits
;
1832 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1833 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1835 /* We need to increment Global Offset by 256-bits to make room for
1836 * Broadwell's extra "Vertex Count" payload at the beginning of the
1837 * URB entry. Since this is an OWord message, Global Offset is counted
1838 * in 128-bit units, so we must set it to 2.
1840 if (gs_prog_data
->static_vertex_count
== -1)
1845 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1848 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1850 /* Note: we are calling this *before* increasing vertex_count, so
1851 * this->vertex_count == vertex_count - 1 in the formula above.
1854 /* Stream mode uses 2 bits per vertex */
1855 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1857 /* Must be a valid stream */
1858 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1860 /* Control data bits are initialized to 0 so we don't have to set any
1861 * bits when sending vertices to stream 0.
1866 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1868 /* reg::sid = stream_id */
1869 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1870 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1872 /* reg:shift_count = 2 * (vertex_count - 1) */
1873 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1874 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1876 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1877 * attention to the lower 5 bits of its second source argument, so on this
1878 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1879 * stream_id << ((2 * (vertex_count - 1)) % 32).
1881 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1882 abld
.SHL(mask
, sid
, shift_count
);
1883 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1887 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1890 assert(stage
== MESA_SHADER_GEOMETRY
);
1892 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1894 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1895 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1897 /* Haswell and later hardware ignores the "Render Stream Select" bits
1898 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1899 * and instead sends all primitives down the pipeline for rasterization.
1900 * If the SOL stage is enabled, "Render Stream Select" is honored and
1901 * primitives bound to non-zero streams are discarded after stream output.
1903 * Since the only purpose of primives sent to non-zero streams is to
1904 * be recorded by transform feedback, we can simply discard all geometry
1905 * bound to these streams when transform feedback is disabled.
1907 if (stream_id
> 0 && !nir
->info
->has_transform_feedback_varyings
)
1910 /* If we're outputting 32 control data bits or less, then we can wait
1911 * until the shader is over to output them all. Otherwise we need to
1912 * output them as we go. Now is the time to do it, since we're about to
1913 * output the vertex_count'th vertex, so it's guaranteed that the
1914 * control data bits associated with the (vertex_count - 1)th vertex are
1917 if (gs_compile
->control_data_header_size_bits
> 32) {
1918 const fs_builder abld
=
1919 bld
.annotate("emit vertex: emit control data bits");
1921 /* Only emit control data bits if we've finished accumulating a batch
1922 * of 32 bits. This is the case when:
1924 * (vertex_count * bits_per_vertex) % 32 == 0
1926 * (in other words, when the last 5 bits of vertex_count *
1927 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1928 * integer n (which is always the case, since bits_per_vertex is
1929 * always 1 or 2), this is equivalent to requiring that the last 5-n
1930 * bits of vertex_count are 0:
1932 * vertex_count & (2^(5-n) - 1) == 0
1934 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1937 * vertex_count & (32 / bits_per_vertex - 1) == 0
1939 * TODO: If vertex_count is an immediate, we could do some of this math
1940 * at compile time...
1943 abld
.AND(bld
.null_reg_d(), vertex_count
,
1944 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1945 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1947 abld
.IF(BRW_PREDICATE_NORMAL
);
1948 /* If vertex_count is 0, then no control data bits have been
1949 * accumulated yet, so we can skip emitting them.
1951 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1952 BRW_CONDITIONAL_NEQ
);
1953 abld
.IF(BRW_PREDICATE_NORMAL
);
1954 emit_gs_control_data_bits(vertex_count
);
1955 abld
.emit(BRW_OPCODE_ENDIF
);
1957 /* Reset control_data_bits to 0 so we can start accumulating a new
1960 * Note: in the case where vertex_count == 0, this neutralizes the
1961 * effect of any call to EndPrimitive() that the shader may have
1962 * made before outputting its first vertex.
1964 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1965 inst
->force_writemask_all
= true;
1966 abld
.emit(BRW_OPCODE_ENDIF
);
1969 emit_urb_writes(vertex_count
);
1971 /* In stream mode we have to set control data bits for all vertices
1972 * unless we have disabled control data bits completely (which we do
1973 * do for GL_POINTS outputs that don't use streams).
1975 if (gs_compile
->control_data_header_size_bits
> 0 &&
1976 gs_prog_data
->control_data_format
==
1977 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1978 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1983 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1984 const nir_src
&vertex_src
,
1985 unsigned base_offset
,
1986 const nir_src
&offset_src
,
1987 unsigned num_components
,
1988 unsigned first_component
)
1990 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1992 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1993 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1994 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1996 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1997 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1998 * gl_PointSize is available as a GS input, however, so it must be that.
2000 const bool is_point_size
= (base_offset
== 0);
2002 /* TODO: figure out push input layout for invocations == 1 */
2003 if (gs_prog_data
->invocations
== 1 &&
2004 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2005 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2006 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2007 vertex_const
->u32
[0] * push_reg_count
;
2008 /* This input was pushed into registers. */
2009 if (is_point_size
) {
2010 /* gl_PointSize comes in .w */
2011 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2013 for (unsigned i
= 0; i
< num_components
; i
++) {
2014 bld
.MOV(offset(dst
, bld
, i
),
2015 fs_reg(ATTR
, imm_offset
+ i
+ first_component
, dst
.type
));
2021 /* Resort to the pull model. Ensure the VUE handles are provided. */
2022 gs_prog_data
->base
.include_vue_handles
= true;
2024 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2025 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2027 if (gs_prog_data
->invocations
== 1) {
2029 /* The vertex index is constant; just select the proper URB handle. */
2031 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2032 BRW_REGISTER_TYPE_UD
);
2034 /* The vertex index is non-constant. We need to use indirect
2035 * addressing to fetch the proper URB handle.
2037 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2038 * indicating that channel <n> should read the handle from
2039 * DWord <n>. We convert that to bytes by multiplying by 4.
2041 * Next, we convert the vertex index to bytes by multiplying
2042 * by 32 (shifting by 5), and add the two together. This is
2043 * the final indirect byte offset.
2045 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2046 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2047 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2048 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2050 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2051 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2052 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2053 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2054 /* Convert vertex_index to bytes (multiply by 32) */
2055 bld
.SHL(vertex_offset_bytes
,
2056 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2058 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2060 /* Use first_icp_handle as the base offset. There is one register
2061 * of URB handles per vertex, so inform the register allocator that
2062 * we might read up to nir->info->gs.vertices_in registers.
2064 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2065 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2066 fs_reg(icp_offset_bytes
),
2067 brw_imm_ud(nir
->info
->gs
.vertices_in
* REG_SIZE
));
2070 assert(gs_prog_data
->invocations
> 1);
2073 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2075 retype(brw_vec1_grf(first_icp_handle
+
2076 vertex_const
->i32
[0] / 8,
2077 vertex_const
->i32
[0] % 8),
2078 BRW_REGISTER_TYPE_UD
));
2080 /* The vertex index is non-constant. We need to use indirect
2081 * addressing to fetch the proper URB handle.
2084 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2086 /* Convert vertex_index to bytes (multiply by 4) */
2087 bld
.SHL(icp_offset_bytes
,
2088 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2091 /* Use first_icp_handle as the base offset. There is one DWord
2092 * of URB handles per vertex, so inform the register allocator that
2093 * we might read up to ceil(nir->info->gs.vertices_in / 8) registers.
2095 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2096 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2097 fs_reg(icp_offset_bytes
),
2098 brw_imm_ud(DIV_ROUND_UP(nir
->info
->gs
.vertices_in
, 8) *
2105 fs_reg tmp_dst
= dst
;
2106 fs_reg indirect_offset
= get_nir_src(offset_src
);
2107 unsigned num_iterations
= 1;
2108 unsigned orig_num_components
= num_components
;
2110 if (type_sz(dst
.type
) == 8) {
2111 if (num_components
> 2) {
2115 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2117 first_component
= first_component
/ 2;
2120 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2122 /* Constant indexing - use global offset. */
2123 if (first_component
!= 0) {
2124 unsigned read_components
= num_components
+ first_component
;
2125 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2126 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2127 inst
->size_written
= read_components
*
2128 tmp
.component_size(inst
->exec_size
);
2129 for (unsigned i
= 0; i
< num_components
; i
++) {
2130 bld
.MOV(offset(tmp_dst
, bld
, i
),
2131 offset(tmp
, bld
, i
+ first_component
));
2134 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2136 inst
->size_written
= num_components
*
2137 tmp_dst
.component_size(inst
->exec_size
);
2139 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2142 /* Indirect indexing - use per-slot offsets as well. */
2143 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2144 unsigned read_components
= num_components
+ first_component
;
2145 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2146 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2147 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2148 if (first_component
!= 0) {
2149 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2151 inst
->size_written
= read_components
*
2152 tmp
.component_size(inst
->exec_size
);
2153 for (unsigned i
= 0; i
< num_components
; i
++) {
2154 bld
.MOV(offset(tmp_dst
, bld
, i
),
2155 offset(tmp
, bld
, i
+ first_component
));
2158 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2160 inst
->size_written
= num_components
*
2161 tmp_dst
.component_size(inst
->exec_size
);
2163 inst
->offset
= base_offset
;
2167 if (type_sz(dst
.type
) == 8) {
2168 shuffle_32bit_load_result_to_64bit_data(
2169 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2171 for (unsigned c
= 0; c
< num_components
; c
++)
2172 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2175 if (num_iterations
> 1) {
2176 num_components
= orig_num_components
- 2;
2180 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2181 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2182 indirect_offset
= new_indirect
;
2187 if (is_point_size
) {
2188 /* Read the whole VUE header (because of alignment) and read .w. */
2189 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2191 inst
->size_written
= 4 * REG_SIZE
;
2192 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2197 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2199 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2200 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2203 /* The only constant offset we should find is 0. brw_nir.c's
2204 * add_const_offset_to_base() will fold other constant offsets
2205 * into instr->const_index[0].
2207 assert(const_value
->u32
[0] == 0);
2211 return get_nir_src(*offset_src
);
2215 do_untyped_vector_read(const fs_builder
&bld
,
2217 const fs_reg surf_index
,
2218 const fs_reg offset_reg
,
2219 unsigned num_components
)
2221 if (type_sz(dest
.type
) == 4) {
2222 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2225 BRW_PREDICATE_NONE
);
2226 read_result
.type
= dest
.type
;
2227 for (unsigned i
= 0; i
< num_components
; i
++)
2228 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2229 } else if (type_sz(dest
.type
) == 8) {
2230 /* Reading a dvec, so we need to:
2232 * 1. Multiply num_components by 2, to account for the fact that we
2233 * need to read 64-bit components.
2234 * 2. Shuffle the result of the load to form valid 64-bit elements
2235 * 3. Emit a second load (for components z/w) if needed.
2237 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2238 bld
.MOV(read_offset
, offset_reg
);
2240 int iters
= num_components
<= 2 ? 1 : 2;
2242 /* Load the dvec, the first iteration loads components x/y, the second
2243 * iteration, if needed, loads components z/w
2245 for (int it
= 0; it
< iters
; it
++) {
2246 /* Compute number of components to read in this iteration */
2247 int iter_components
= MIN2(2, num_components
);
2248 num_components
-= iter_components
;
2250 /* Read. Since this message reads 32-bit components, we need to
2251 * read twice as many components.
2253 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2255 iter_components
* 2,
2256 BRW_PREDICATE_NONE
);
2258 /* Shuffle the 32-bit load result into valid 64-bit data */
2259 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2260 shuffle_32bit_load_result_to_64bit_data(
2261 bld
, packed_result
, read_result
, iter_components
);
2263 /* Move each component to its destination */
2264 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2265 for (int c
= 0; c
< iter_components
; c
++) {
2266 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2267 offset(packed_result
, bld
, c
));
2270 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2273 unreachable("Unsupported type");
2278 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2279 nir_intrinsic_instr
*instr
)
2281 assert(stage
== MESA_SHADER_VERTEX
);
2284 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2285 dest
= get_nir_dest(instr
->dest
);
2287 switch (instr
->intrinsic
) {
2288 case nir_intrinsic_load_vertex_id
:
2289 unreachable("should be lowered by lower_vertex_id()");
2291 case nir_intrinsic_load_vertex_id_zero_base
:
2292 case nir_intrinsic_load_base_vertex
:
2293 case nir_intrinsic_load_instance_id
:
2294 case nir_intrinsic_load_base_instance
:
2295 case nir_intrinsic_load_draw_id
: {
2296 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2297 fs_reg val
= nir_system_values
[sv
];
2298 assert(val
.file
!= BAD_FILE
);
2299 dest
.type
= val
.type
;
2304 case nir_intrinsic_load_input
: {
2305 fs_reg src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2306 unsigned first_component
= nir_intrinsic_component(instr
);
2307 unsigned num_components
= instr
->num_components
;
2308 enum brw_reg_type type
= dest
.type
;
2310 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2311 assert(const_offset
&& "Indirect input loads not allowed");
2312 src
= offset(src
, bld
, const_offset
->u32
[0]);
2314 for (unsigned j
= 0; j
< num_components
; j
++) {
2315 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2318 if (type
== BRW_REGISTER_TYPE_DF
) {
2319 /* Once the double vector is read, set again its original register
2320 * type to continue with normal execution.
2322 src
= retype(src
, type
);
2323 dest
= retype(dest
, type
);
2326 if (type_sz(src
.type
) == 8) {
2327 shuffle_32bit_load_result_to_64bit_data(bld
,
2329 retype(dest
, BRW_REGISTER_TYPE_F
),
2330 instr
->num_components
);
2336 nir_emit_intrinsic(bld
, instr
);
2342 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2343 nir_intrinsic_instr
*instr
)
2345 assert(stage
== MESA_SHADER_TESS_CTRL
);
2346 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2347 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2350 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2351 dst
= get_nir_dest(instr
->dest
);
2353 switch (instr
->intrinsic
) {
2354 case nir_intrinsic_load_primitive_id
:
2355 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2357 case nir_intrinsic_load_invocation_id
:
2358 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2360 case nir_intrinsic_load_patch_vertices_in
:
2361 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2362 brw_imm_d(tcs_key
->input_vertices
));
2365 case nir_intrinsic_barrier
: {
2366 if (tcs_prog_data
->instances
== 1)
2369 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2370 fs_reg m0_2
= component(m0
, 2);
2372 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2374 /* Zero the message header */
2375 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2377 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2378 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2379 brw_imm_ud(INTEL_MASK(16, 13)));
2381 /* Shift it up to bits 27:24. */
2382 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2384 /* Set the Barrier Count and the enable bit */
2385 chanbld
.OR(m0_2
, m0_2
,
2386 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2388 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2392 case nir_intrinsic_load_input
:
2393 unreachable("nir_lower_io should never give us these.");
2396 case nir_intrinsic_load_per_vertex_input
: {
2397 fs_reg indirect_offset
= get_indirect_offset(instr
);
2398 unsigned imm_offset
= instr
->const_index
[0];
2400 const nir_src
&vertex_src
= instr
->src
[0];
2401 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2408 /* Emit a MOV to resolve <0,1,0> regioning. */
2409 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2411 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2412 vertex_const
->i32
[0] & 7),
2413 BRW_REGISTER_TYPE_UD
));
2414 } else if (tcs_prog_data
->instances
== 1 &&
2415 vertex_src
.is_ssa
&&
2416 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2417 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2418 /* For the common case of only 1 instance, an array index of
2419 * gl_InvocationID means reading g1. Skip all the indirect work.
2421 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2423 /* The vertex index is non-constant. We need to use indirect
2424 * addressing to fetch the proper URB handle.
2426 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2428 /* Each ICP handle is a single DWord (4 bytes) */
2429 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2430 bld
.SHL(vertex_offset_bytes
,
2431 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2434 /* Start at g1. We might read up to 4 registers. */
2435 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2436 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2437 brw_imm_ud(4 * REG_SIZE
));
2440 /* We can only read two double components with each URB read, so
2441 * we send two read messages in that case, each one loading up to
2442 * two double components.
2444 unsigned num_iterations
= 1;
2445 unsigned num_components
= instr
->num_components
;
2446 unsigned first_component
= nir_intrinsic_component(instr
);
2447 fs_reg orig_dst
= dst
;
2448 if (type_sz(dst
.type
) == 8) {
2449 first_component
= first_component
/ 2;
2450 if (instr
->num_components
> 2) {
2455 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2459 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2460 if (indirect_offset
.file
== BAD_FILE
) {
2461 /* Constant indexing - use global offset. */
2462 if (first_component
!= 0) {
2463 unsigned read_components
= num_components
+ first_component
;
2464 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2465 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2466 for (unsigned i
= 0; i
< num_components
; i
++) {
2467 bld
.MOV(offset(dst
, bld
, i
),
2468 offset(tmp
, bld
, i
+ first_component
));
2471 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2473 inst
->offset
= imm_offset
;
2476 /* Indirect indexing - use per-slot offsets as well. */
2477 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2478 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2479 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2480 if (first_component
!= 0) {
2481 unsigned read_components
= num_components
+ first_component
;
2482 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2483 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2485 for (unsigned i
= 0; i
< num_components
; i
++) {
2486 bld
.MOV(offset(dst
, bld
, i
),
2487 offset(tmp
, bld
, i
+ first_component
));
2490 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2493 inst
->offset
= imm_offset
;
2496 inst
->size_written
= (num_components
+ first_component
) *
2497 inst
->dst
.component_size(inst
->exec_size
);
2499 /* If we are reading 64-bit data using 32-bit read messages we need
2500 * build proper 64-bit data elements by shuffling the low and high
2501 * 32-bit components around like we do for other things like UBOs
2504 if (type_sz(dst
.type
) == 8) {
2505 shuffle_32bit_load_result_to_64bit_data(
2506 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2508 for (unsigned c
= 0; c
< num_components
; c
++) {
2509 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2510 offset(dst
, bld
, c
));
2514 /* Copy the temporary to the destination to deal with writemasking.
2516 * Also attempt to deal with gl_PointSize being in the .w component.
2518 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2519 assert(type_sz(dst
.type
) < 8);
2520 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2521 inst
->size_written
= 4 * REG_SIZE
;
2522 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2525 /* If we are loading double data and we need a second read message
2526 * adjust the write offset
2528 if (num_iterations
> 1) {
2529 num_components
= instr
->num_components
- 2;
2536 case nir_intrinsic_load_output
:
2537 case nir_intrinsic_load_per_vertex_output
: {
2538 fs_reg indirect_offset
= get_indirect_offset(instr
);
2539 unsigned imm_offset
= instr
->const_index
[0];
2540 unsigned first_component
= nir_intrinsic_component(instr
);
2543 if (indirect_offset
.file
== BAD_FILE
) {
2544 /* Replicate the patch handle to all enabled channels */
2545 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2546 bld
.MOV(patch_handle
,
2547 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2550 if (first_component
!= 0) {
2551 unsigned read_components
=
2552 instr
->num_components
+ first_component
;
2553 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2554 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2556 inst
->size_written
= read_components
* REG_SIZE
;
2557 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2558 bld
.MOV(offset(dst
, bld
, i
),
2559 offset(tmp
, bld
, i
+ first_component
));
2562 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2564 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2566 inst
->offset
= imm_offset
;
2570 /* Indirect indexing - use per-slot offsets as well. */
2571 const fs_reg srcs
[] = {
2572 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2575 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2576 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2577 if (first_component
!= 0) {
2578 unsigned read_components
=
2579 instr
->num_components
+ first_component
;
2580 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2581 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2583 inst
->size_written
= read_components
* REG_SIZE
;
2584 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2585 bld
.MOV(offset(dst
, bld
, i
),
2586 offset(tmp
, bld
, i
+ first_component
));
2589 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2591 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2593 inst
->offset
= imm_offset
;
2599 case nir_intrinsic_store_output
:
2600 case nir_intrinsic_store_per_vertex_output
: {
2601 fs_reg value
= get_nir_src(instr
->src
[0]);
2602 bool is_64bit
= (instr
->src
[0].is_ssa
?
2603 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2604 fs_reg indirect_offset
= get_indirect_offset(instr
);
2605 unsigned imm_offset
= instr
->const_index
[0];
2606 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2607 unsigned mask
= instr
->const_index
[1];
2608 unsigned header_regs
= 0;
2610 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2612 if (indirect_offset
.file
!= BAD_FILE
) {
2613 srcs
[header_regs
++] = indirect_offset
;
2619 unsigned num_components
= util_last_bit(mask
);
2622 /* We can only pack two 64-bit components in a single message, so send
2623 * 2 messages if we have more components
2625 unsigned num_iterations
= 1;
2626 unsigned iter_components
= num_components
;
2627 unsigned first_component
= nir_intrinsic_component(instr
);
2629 first_component
= first_component
/ 2;
2630 if (instr
->num_components
> 2) {
2632 iter_components
= 2;
2636 /* 64-bit data needs to me shuffled before we can write it to the URB.
2637 * We will use this temporary to shuffle the components in each
2641 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2643 mask
= mask
<< first_component
;
2645 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2646 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2647 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2648 opcode
= indirect_offset
.file
!= BAD_FILE
?
2649 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2650 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2651 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2652 /* Expand the 64-bit mask to 32-bit channels. We only handle
2653 * two channels in each iteration, so we only care about X/Y.
2655 unsigned mask32
= 0;
2656 if (mask
& WRITEMASK_X
)
2657 mask32
|= WRITEMASK_XY
;
2658 if (mask
& WRITEMASK_Y
)
2659 mask32
|= WRITEMASK_ZW
;
2661 /* If the mask does not include any of the channels X or Y there
2662 * is nothing to do in this iteration. Move on to the next couple
2663 * of 64-bit channels.
2671 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2672 opcode
= indirect_offset
.file
!= BAD_FILE
?
2673 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2674 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2676 opcode
= indirect_offset
.file
!= BAD_FILE
?
2677 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2678 SHADER_OPCODE_URB_WRITE_SIMD8
;
2681 for (unsigned i
= 0; i
< iter_components
; i
++) {
2682 if (!(mask
& (1 << (i
+ first_component
))))
2686 srcs
[header_regs
+ i
+ first_component
] =
2687 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2689 /* We need to shuffle the 64-bit data to match the layout
2690 * expected by our 32-bit URB write messages. We use a temporary
2693 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2694 shuffle_64bit_data_for_32bit_write(bld
,
2695 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2696 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2699 /* Now copy the data to the destination */
2700 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2701 unsigned idx
= 2 * i
;
2702 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2703 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2704 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2705 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2706 offset(dest
, bld
, 1);
2711 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2712 (is_64bit
? 2 * first_component
: first_component
);
2714 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2715 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2717 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2718 inst
->offset
= imm_offset
;
2721 /* If this is a 64-bit attribute, select the next two 64-bit channels
2722 * to be handled in the next iteration.
2733 nir_emit_intrinsic(bld
, instr
);
2739 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2740 nir_intrinsic_instr
*instr
)
2742 assert(stage
== MESA_SHADER_TESS_EVAL
);
2743 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2746 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2747 dest
= get_nir_dest(instr
->dest
);
2749 switch (instr
->intrinsic
) {
2750 case nir_intrinsic_load_primitive_id
:
2751 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2753 case nir_intrinsic_load_tess_coord
:
2754 /* gl_TessCoord is part of the payload in g1-3 */
2755 for (unsigned i
= 0; i
< 3; i
++) {
2756 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2760 case nir_intrinsic_load_input
:
2761 case nir_intrinsic_load_per_vertex_input
: {
2762 fs_reg indirect_offset
= get_indirect_offset(instr
);
2763 unsigned imm_offset
= instr
->const_index
[0];
2764 unsigned first_component
= nir_intrinsic_component(instr
);
2766 if (type_sz(dest
.type
) == 8) {
2767 first_component
= first_component
/ 2;
2771 if (indirect_offset
.file
== BAD_FILE
) {
2772 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2773 * which is 16 registers (since each holds 2 vec4 slots).
2775 const unsigned max_push_slots
= 32;
2776 if (imm_offset
< max_push_slots
) {
2777 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2778 for (int i
= 0; i
< instr
->num_components
; i
++) {
2779 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2780 i
+ first_component
;
2781 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2783 tes_prog_data
->base
.urb_read_length
=
2784 MAX2(tes_prog_data
->base
.urb_read_length
,
2785 DIV_ROUND_UP(imm_offset
+ 1, 2));
2787 /* Replicate the patch handle to all enabled channels */
2788 const fs_reg srcs
[] = {
2789 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2791 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2792 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2794 if (first_component
!= 0) {
2795 unsigned read_components
=
2796 instr
->num_components
+ first_component
;
2797 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2798 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2800 inst
->size_written
= read_components
* REG_SIZE
;
2801 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2802 bld
.MOV(offset(dest
, bld
, i
),
2803 offset(tmp
, bld
, i
+ first_component
));
2806 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2808 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2811 inst
->offset
= imm_offset
;
2814 /* Indirect indexing - use per-slot offsets as well. */
2816 /* We can only read two double components with each URB read, so
2817 * we send two read messages in that case, each one loading up to
2818 * two double components.
2820 unsigned num_iterations
= 1;
2821 unsigned num_components
= instr
->num_components
;
2822 fs_reg orig_dest
= dest
;
2823 if (type_sz(dest
.type
) == 8) {
2824 if (instr
->num_components
> 2) {
2828 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
2832 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2833 const fs_reg srcs
[] = {
2834 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2837 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2838 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2840 if (first_component
!= 0) {
2841 unsigned read_components
=
2842 num_components
+ first_component
;
2843 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2844 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2846 for (unsigned i
= 0; i
< num_components
; i
++) {
2847 bld
.MOV(offset(dest
, bld
, i
),
2848 offset(tmp
, bld
, i
+ first_component
));
2851 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
2855 inst
->offset
= imm_offset
;
2856 inst
->size_written
= (num_components
+ first_component
) *
2857 inst
->dst
.component_size(inst
->exec_size
);
2859 /* If we are reading 64-bit data using 32-bit read messages we need
2860 * build proper 64-bit data elements by shuffling the low and high
2861 * 32-bit components around like we do for other things like UBOs
2864 if (type_sz(dest
.type
) == 8) {
2865 shuffle_32bit_load_result_to_64bit_data(
2866 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
2868 for (unsigned c
= 0; c
< num_components
; c
++) {
2869 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
2870 offset(dest
, bld
, c
));
2874 /* If we are loading double data and we need a second read message
2877 if (num_iterations
> 1) {
2878 num_components
= instr
->num_components
- 2;
2886 nir_emit_intrinsic(bld
, instr
);
2892 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2893 nir_intrinsic_instr
*instr
)
2895 assert(stage
== MESA_SHADER_GEOMETRY
);
2896 fs_reg indirect_offset
;
2899 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2900 dest
= get_nir_dest(instr
->dest
);
2902 switch (instr
->intrinsic
) {
2903 case nir_intrinsic_load_primitive_id
:
2904 assert(stage
== MESA_SHADER_GEOMETRY
);
2905 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
2906 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2907 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2910 case nir_intrinsic_load_input
:
2911 unreachable("load_input intrinsics are invalid for the GS stage");
2913 case nir_intrinsic_load_per_vertex_input
:
2914 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2915 instr
->src
[1], instr
->num_components
,
2916 nir_intrinsic_component(instr
));
2919 case nir_intrinsic_emit_vertex_with_counter
:
2920 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2923 case nir_intrinsic_end_primitive_with_counter
:
2924 emit_gs_end_primitive(instr
->src
[0]);
2927 case nir_intrinsic_set_vertex_count
:
2928 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2931 case nir_intrinsic_load_invocation_id
: {
2932 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2933 assert(val
.file
!= BAD_FILE
);
2934 dest
.type
= val
.type
;
2940 nir_emit_intrinsic(bld
, instr
);
2946 * Fetch the current render target layer index.
2949 fetch_render_target_array_index(const fs_builder
&bld
)
2951 if (bld
.shader
->devinfo
->gen
>= 6) {
2952 /* The render target array index is provided in the thread payload as
2953 * bits 26:16 of r0.0.
2955 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2956 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
2960 /* Pre-SNB we only ever render into the first layer of the framebuffer
2961 * since layered rendering is not implemented.
2963 return brw_imm_ud(0);
2968 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
2969 * framebuffer at the current fragment coordinates and sample index.
2972 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
2975 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
2977 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
2978 const brw_wm_prog_key
*wm_key
=
2979 reinterpret_cast<const brw_wm_prog_key
*>(key
);
2980 assert(!wm_key
->coherent_fb_fetch
);
2981 const struct brw_wm_prog_data
*wm_prog_data
=
2982 brw_wm_prog_data(stage_prog_data
);
2984 /* Calculate the surface index relative to the start of the texture binding
2985 * table block, since that's what the texturing messages expect.
2987 const unsigned surface
= target
+
2988 wm_prog_data
->binding_table
.render_target_read_start
-
2989 wm_prog_data
->base
.binding_table
.texture_start
;
2991 brw_mark_surface_used(
2992 bld
.shader
->stage_prog_data
,
2993 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
2995 /* Calculate the fragment coordinates. */
2996 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
2997 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
2998 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
2999 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3001 /* Calculate the sample index and MCS payload when multisampling. Luckily
3002 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3003 * shouldn't be necessary to recompile based on whether the framebuffer is
3006 if (wm_key
->multisample_fbo
&&
3007 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3008 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3010 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3011 const fs_reg mcs
= wm_key
->multisample_fbo
?
3012 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3014 /* Use either a normal or a CMS texel fetch message depending on whether
3015 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3016 * message just in case the framebuffer uses 16x multisampling, it should
3017 * be equivalent to the normal CMS fetch for lower multisampling modes.
3019 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3020 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3021 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3023 /* Emit the instruction. */
3024 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3026 brw_imm_ud(surface
), brw_imm_ud(0),
3027 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3028 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3030 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3031 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3037 * Actual coherent framebuffer read implemented using the native render target
3038 * read message. Requires SKL+.
3041 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3043 assert(bld
.shader
->devinfo
->gen
>= 9);
3044 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3045 inst
->target
= target
;
3046 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3052 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3054 if (n
&& regs
[0].file
!= BAD_FILE
) {
3058 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3060 for (unsigned i
= 0; i
< n
; i
++)
3068 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3070 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3071 const brw_wm_prog_key
*const key
=
3072 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3073 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3074 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3076 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3077 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3079 else if (l
== FRAG_RESULT_COLOR
)
3080 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3081 MAX2(key
->nr_color_regions
, 1));
3083 else if (l
== FRAG_RESULT_DEPTH
)
3084 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3086 else if (l
== FRAG_RESULT_STENCIL
)
3087 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3089 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3090 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3092 else if (l
>= FRAG_RESULT_DATA0
&&
3093 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3094 return alloc_temporary(v
->bld
, 4,
3095 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3098 unreachable("Invalid location");
3102 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3103 nir_intrinsic_instr
*instr
)
3105 assert(stage
== MESA_SHADER_FRAGMENT
);
3108 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3109 dest
= get_nir_dest(instr
->dest
);
3111 switch (instr
->intrinsic
) {
3112 case nir_intrinsic_load_front_face
:
3113 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3114 *emit_frontfacing_interpolation());
3117 case nir_intrinsic_load_sample_pos
: {
3118 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3119 assert(sample_pos
.file
!= BAD_FILE
);
3120 dest
.type
= sample_pos
.type
;
3121 bld
.MOV(dest
, sample_pos
);
3122 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3126 case nir_intrinsic_load_layer_id
:
3127 dest
.type
= BRW_REGISTER_TYPE_UD
;
3128 bld
.MOV(dest
, fetch_render_target_array_index(bld
));
3131 case nir_intrinsic_load_helper_invocation
:
3132 case nir_intrinsic_load_sample_mask_in
:
3133 case nir_intrinsic_load_sample_id
: {
3134 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3135 fs_reg val
= nir_system_values
[sv
];
3136 assert(val
.file
!= BAD_FILE
);
3137 dest
.type
= val
.type
;
3142 case nir_intrinsic_store_output
: {
3143 const fs_reg src
= get_nir_src(instr
->src
[0]);
3144 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3145 assert(const_offset
&& "Indirect output stores not allowed");
3146 const unsigned location
= nir_intrinsic_base(instr
) +
3147 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3148 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3151 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3152 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3153 offset(src
, bld
, j
));
3158 case nir_intrinsic_load_output
: {
3159 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3160 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3161 assert(l
>= FRAG_RESULT_DATA0
);
3162 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3163 assert(const_offset
&& "Indirect output loads not allowed");
3164 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3165 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3167 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3168 emit_coherent_fb_read(bld
, tmp
, target
);
3170 emit_non_coherent_fb_read(bld
, tmp
, target
);
3172 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3173 bld
.MOV(offset(dest
, bld
, j
),
3174 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3180 case nir_intrinsic_discard
:
3181 case nir_intrinsic_discard_if
: {
3182 /* We track our discarded pixels in f0.1. By predicating on it, we can
3183 * update just the flag bits that aren't yet discarded. If there's no
3184 * condition, we emit a CMP of g0 != g0, so all currently executing
3185 * channels will get turned off.
3188 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3189 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3190 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3192 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3193 BRW_REGISTER_TYPE_UW
));
3194 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3196 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3197 cmp
->flag_subreg
= 1;
3199 if (devinfo
->gen
>= 6) {
3200 emit_discard_jump();
3205 case nir_intrinsic_load_input
: {
3206 /* load_input is only used for flat inputs */
3207 unsigned base
= nir_intrinsic_base(instr
);
3208 unsigned component
= nir_intrinsic_component(instr
);
3209 unsigned num_components
= instr
->num_components
;
3210 enum brw_reg_type type
= dest
.type
;
3212 /* Special case fields in the VUE header */
3213 if (base
== VARYING_SLOT_LAYER
)
3215 else if (base
== VARYING_SLOT_VIEWPORT
)
3218 if (nir_dest_bit_size(instr
->dest
) == 64) {
3219 /* const_index is in 32-bit type size units that could not be aligned
3220 * with DF. We need to read the double vector as if it was a float
3221 * vector of twice the number of components to fetch the right data.
3223 type
= BRW_REGISTER_TYPE_F
;
3224 num_components
*= 2;
3227 for (unsigned int i
= 0; i
< num_components
; i
++) {
3228 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3229 interp
= suboffset(interp
, 3);
3230 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3231 retype(fs_reg(interp
), type
));
3234 if (nir_dest_bit_size(instr
->dest
) == 64) {
3235 shuffle_32bit_load_result_to_64bit_data(bld
,
3238 instr
->num_components
);
3243 case nir_intrinsic_load_barycentric_pixel
:
3244 case nir_intrinsic_load_barycentric_centroid
:
3245 case nir_intrinsic_load_barycentric_sample
:
3246 /* Do nothing - load_interpolated_input handling will handle it later. */
3249 case nir_intrinsic_load_barycentric_at_sample
: {
3250 const glsl_interp_mode interpolation
=
3251 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3253 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3256 unsigned msg_data
= const_sample
->i32
[0] << 4;
3258 emit_pixel_interpolater_send(bld
,
3259 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3262 brw_imm_ud(msg_data
),
3265 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3266 BRW_REGISTER_TYPE_UD
);
3268 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3269 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3270 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3271 bld
.exec_all().group(1, 0)
3272 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3273 emit_pixel_interpolater_send(bld
,
3274 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3280 /* Make a loop that sends a message to the pixel interpolater
3281 * for the sample number in each live channel. If there are
3282 * multiple channels with the same sample number then these
3283 * will be handled simultaneously with a single interation of
3286 bld
.emit(BRW_OPCODE_DO
);
3288 /* Get the next live sample number into sample_id_reg */
3289 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3291 /* Set the flag register so that we can perform the send
3292 * message on all channels that have the same sample number
3294 bld
.CMP(bld
.null_reg_ud(),
3295 sample_src
, sample_id
,
3296 BRW_CONDITIONAL_EQ
);
3297 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3298 bld
.exec_all().group(1, 0)
3299 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3301 emit_pixel_interpolater_send(bld
,
3302 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3307 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3309 /* Continue the loop if there are any live channels left */
3310 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3312 bld
.emit(BRW_OPCODE_WHILE
));
3318 case nir_intrinsic_load_barycentric_at_offset
: {
3319 const glsl_interp_mode interpolation
=
3320 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3322 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3325 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3326 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3328 emit_pixel_interpolater_send(bld
,
3329 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3332 brw_imm_ud(off_x
| (off_y
<< 4)),
3335 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3336 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3337 BRW_REGISTER_TYPE_F
);
3338 for (int i
= 0; i
< 2; i
++) {
3339 fs_reg temp
= vgrf(glsl_type::float_type
);
3340 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3341 fs_reg itemp
= vgrf(glsl_type::int_type
);
3343 bld
.MOV(itemp
, temp
);
3345 /* Clamp the upper end of the range to +7/16.
3346 * ARB_gpu_shader5 requires that we support a maximum offset
3347 * of +0.5, which isn't representable in a S0.4 value -- if
3348 * we didn't clamp it, we'd end up with -8/16, which is the
3349 * opposite of what the shader author wanted.
3351 * This is legal due to ARB_gpu_shader5's quantization
3354 * "Not all values of <offset> may be supported; x and y
3355 * offsets may be rounded to fixed-point values with the
3356 * number of fraction bits given by the
3357 * implementation-dependent constant
3358 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3360 set_condmod(BRW_CONDITIONAL_L
,
3361 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3364 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3365 emit_pixel_interpolater_send(bld
,
3375 case nir_intrinsic_load_interpolated_input
: {
3376 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3377 emit_fragcoord_interpolation(dest
);
3381 assert(instr
->src
[0].ssa
&&
3382 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3383 nir_intrinsic_instr
*bary_intrinsic
=
3384 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3385 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3386 enum glsl_interp_mode interp_mode
=
3387 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3390 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3391 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3392 /* Use the result of the PI message */
3393 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3395 /* Use the delta_xy values computed from the payload */
3396 enum brw_barycentric_mode bary
=
3397 brw_barycentric_mode(interp_mode
, bary_intrin
);
3399 dst_xy
= this->delta_xy
[bary
];
3402 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3404 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3405 nir_intrinsic_component(instr
) + i
));
3406 interp
.type
= BRW_REGISTER_TYPE_F
;
3407 dest
.type
= BRW_REGISTER_TYPE_F
;
3409 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3410 fs_reg tmp
= vgrf(glsl_type::float_type
);
3411 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3412 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3414 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3421 nir_emit_intrinsic(bld
, instr
);
3427 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3428 nir_intrinsic_instr
*instr
)
3430 assert(stage
== MESA_SHADER_COMPUTE
);
3431 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3434 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3435 dest
= get_nir_dest(instr
->dest
);
3437 switch (instr
->intrinsic
) {
3438 case nir_intrinsic_barrier
:
3440 cs_prog_data
->uses_barrier
= true;
3443 case nir_intrinsic_load_local_invocation_id
:
3444 case nir_intrinsic_load_work_group_id
: {
3445 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3446 fs_reg val
= nir_system_values
[sv
];
3447 assert(val
.file
!= BAD_FILE
);
3448 dest
.type
= val
.type
;
3449 for (unsigned i
= 0; i
< 3; i
++)
3450 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3454 case nir_intrinsic_load_num_work_groups
: {
3455 const unsigned surface
=
3456 cs_prog_data
->binding_table
.work_groups_start
;
3458 cs_prog_data
->uses_num_work_groups
= true;
3460 fs_reg surf_index
= brw_imm_ud(surface
);
3461 brw_mark_surface_used(prog_data
, surface
);
3463 /* Read the 3 GLuint components of gl_NumWorkGroups */
3464 for (unsigned i
= 0; i
< 3; i
++) {
3465 fs_reg read_result
=
3466 emit_untyped_read(bld
, surf_index
,
3468 1 /* dims */, 1 /* size */,
3469 BRW_PREDICATE_NONE
);
3470 read_result
.type
= dest
.type
;
3471 bld
.MOV(dest
, read_result
);
3472 dest
= offset(dest
, bld
, 1);
3477 case nir_intrinsic_shared_atomic_add
:
3478 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3480 case nir_intrinsic_shared_atomic_imin
:
3481 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3483 case nir_intrinsic_shared_atomic_umin
:
3484 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3486 case nir_intrinsic_shared_atomic_imax
:
3487 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3489 case nir_intrinsic_shared_atomic_umax
:
3490 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3492 case nir_intrinsic_shared_atomic_and
:
3493 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3495 case nir_intrinsic_shared_atomic_or
:
3496 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3498 case nir_intrinsic_shared_atomic_xor
:
3499 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3501 case nir_intrinsic_shared_atomic_exchange
:
3502 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3504 case nir_intrinsic_shared_atomic_comp_swap
:
3505 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3508 case nir_intrinsic_load_shared
: {
3509 assert(devinfo
->gen
>= 7);
3511 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3513 /* Get the offset to read from */
3515 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3517 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3519 offset_reg
= vgrf(glsl_type::uint_type
);
3521 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3522 brw_imm_ud(instr
->const_index
[0]));
3525 /* Read the vector */
3526 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3527 instr
->num_components
);
3531 case nir_intrinsic_store_shared
: {
3532 assert(devinfo
->gen
>= 7);
3535 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3538 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3541 unsigned writemask
= instr
->const_index
[1];
3543 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3544 * since the untyped writes below operate in units of 32-bits, which
3545 * means that we need to write twice as many components each time.
3546 * Also, we have to suffle 64-bit data to be in the appropriate layout
3547 * expected by our 32-bit write messages.
3549 unsigned type_size
= 4;
3550 unsigned bit_size
= instr
->src
[0].is_ssa
?
3551 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3552 if (bit_size
== 64) {
3555 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3556 shuffle_64bit_data_for_32bit_write(
3558 retype(tmp
, BRW_REGISTER_TYPE_F
),
3559 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3560 instr
->num_components
);
3564 unsigned type_slots
= type_size
/ 4;
3566 /* Combine groups of consecutive enabled channels in one write
3567 * message. We use ffs to find the first enabled channel and then ffs on
3568 * the bit-inverse, down-shifted writemask to determine the length of
3569 * the block of enabled bits.
3572 unsigned first_component
= ffs(writemask
) - 1;
3573 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3575 /* We can't write more than 2 64-bit components at once. Limit the
3576 * length of the write to what we can do and let the next iteration
3580 length
= MIN2(2, length
);
3583 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3585 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3586 type_size
* first_component
);
3588 offset_reg
= vgrf(glsl_type::uint_type
);
3590 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3591 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3594 emit_untyped_write(bld
, surf_index
, offset_reg
,
3595 offset(val_reg
, bld
, first_component
* type_slots
),
3596 1 /* dims */, length
* type_slots
,
3597 BRW_PREDICATE_NONE
);
3599 /* Clear the bits in the writemask that we just wrote, then try
3600 * again to see if more channels are left.
3602 writemask
&= (15 << (first_component
+ length
));
3609 nir_emit_intrinsic(bld
, instr
);
3615 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3618 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3619 dest
= get_nir_dest(instr
->dest
);
3621 switch (instr
->intrinsic
) {
3622 case nir_intrinsic_atomic_counter_inc
:
3623 case nir_intrinsic_atomic_counter_dec
:
3624 case nir_intrinsic_atomic_counter_read
:
3625 case nir_intrinsic_atomic_counter_add
:
3626 case nir_intrinsic_atomic_counter_min
:
3627 case nir_intrinsic_atomic_counter_max
:
3628 case nir_intrinsic_atomic_counter_and
:
3629 case nir_intrinsic_atomic_counter_or
:
3630 case nir_intrinsic_atomic_counter_xor
:
3631 case nir_intrinsic_atomic_counter_exchange
:
3632 case nir_intrinsic_atomic_counter_comp_swap
: {
3633 if (stage
== MESA_SHADER_FRAGMENT
&&
3634 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3635 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3637 /* Get some metadata from the image intrinsic. */
3638 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3640 /* Get the arguments of the atomic intrinsic. */
3641 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3642 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3643 instr
->const_index
[0]);
3644 const fs_reg src0
= (info
->num_srcs
>= 2
3645 ? get_nir_src(instr
->src
[1]) : fs_reg());
3646 const fs_reg src1
= (info
->num_srcs
>= 3
3647 ? get_nir_src(instr
->src
[2]) : fs_reg());
3650 assert(info
->num_srcs
<= 3);
3652 /* Emit a surface read or atomic op. */
3653 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3654 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3656 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3658 get_atomic_counter_op(instr
->intrinsic
));
3661 /* Assign the result. */
3662 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3664 /* Mark the surface as used. */
3665 brw_mark_surface_used(stage_prog_data
, surface
);
3669 case nir_intrinsic_image_load
:
3670 case nir_intrinsic_image_store
:
3671 case nir_intrinsic_image_atomic_add
:
3672 case nir_intrinsic_image_atomic_min
:
3673 case nir_intrinsic_image_atomic_max
:
3674 case nir_intrinsic_image_atomic_and
:
3675 case nir_intrinsic_image_atomic_or
:
3676 case nir_intrinsic_image_atomic_xor
:
3677 case nir_intrinsic_image_atomic_exchange
:
3678 case nir_intrinsic_image_atomic_comp_swap
: {
3679 using namespace image_access
;
3681 if (stage
== MESA_SHADER_FRAGMENT
&&
3682 instr
->intrinsic
!= nir_intrinsic_image_load
)
3683 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3685 /* Get the referenced image variable and type. */
3686 const nir_variable
*var
= instr
->variables
[0]->var
;
3687 const glsl_type
*type
= var
->type
->without_array();
3688 const brw_reg_type base_type
= get_image_base_type(type
);
3690 /* Get some metadata from the image intrinsic. */
3691 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3692 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3693 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3694 const unsigned format
= var
->data
.image
.format
;
3696 /* Get the arguments of the image intrinsic. */
3697 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3698 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3699 BRW_REGISTER_TYPE_UD
);
3700 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3701 retype(get_nir_src(instr
->src
[2]), base_type
) :
3703 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3704 retype(get_nir_src(instr
->src
[3]), base_type
) :
3708 /* Emit an image load, store or atomic op. */
3709 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3710 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3712 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3713 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3714 var
->data
.image
.write_only
? GL_NONE
: format
);
3717 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3718 surf_dims
, arr_dims
, info
->dest_components
,
3719 get_image_atomic_op(instr
->intrinsic
, type
));
3721 /* Assign the result. */
3722 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3723 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3724 offset(tmp
, bld
, c
));
3728 case nir_intrinsic_memory_barrier_atomic_counter
:
3729 case nir_intrinsic_memory_barrier_buffer
:
3730 case nir_intrinsic_memory_barrier_image
:
3731 case nir_intrinsic_memory_barrier
: {
3732 const fs_builder ubld
= bld
.group(8, 0);
3733 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3734 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3735 ->size_written
= 2 * REG_SIZE
;
3739 case nir_intrinsic_group_memory_barrier
:
3740 case nir_intrinsic_memory_barrier_shared
:
3741 /* We treat these workgroup-level barriers as no-ops. This should be
3742 * safe at present and as long as:
3744 * - Memory access instructions are not subsequently reordered by the
3745 * compiler back-end.
3747 * - All threads from a given compute shader workgroup fit within a
3748 * single subslice and therefore talk to the same HDC shared unit
3749 * what supposedly guarantees ordering and coherency between threads
3750 * from the same workgroup. This may change in the future when we
3751 * start splitting workgroups across multiple subslices.
3753 * - The context is not in fault-and-stream mode, which could cause
3754 * memory transactions (including to SLM) prior to the barrier to be
3755 * replayed after the barrier if a pagefault occurs. This shouldn't
3756 * be a problem up to and including SKL because fault-and-stream is
3757 * not usable due to hardware issues, but that's likely to change in
3762 case nir_intrinsic_shader_clock
: {
3763 /* We cannot do anything if there is an event, so ignore it for now */
3764 const fs_reg shader_clock
= get_timestamp(bld
);
3765 const fs_reg srcs
[] = { component(shader_clock
, 0),
3766 component(shader_clock
, 1) };
3767 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3771 case nir_intrinsic_image_size
: {
3772 /* Get the referenced image variable and type. */
3773 const nir_variable
*var
= instr
->variables
[0]->var
;
3774 const glsl_type
*type
= var
->type
->without_array();
3776 /* Get the size of the image. */
3777 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3778 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3780 /* For 1DArray image types, the array index is stored in the Z component.
3781 * Fix this by swizzling the Z component to the Y component.
3783 const bool is_1d_array_image
=
3784 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3785 type
->sampler_array
;
3787 /* For CubeArray images, we should count the number of cubes instead
3788 * of the number of faces. Fix it by dividing the (Z component) by 6.
3790 const bool is_cube_array_image
=
3791 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3792 type
->sampler_array
;
3794 /* Copy all the components. */
3795 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3796 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3797 if ((int)c
>= type
->coordinate_components()) {
3798 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3800 } else if (c
== 1 && is_1d_array_image
) {
3801 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3802 offset(size
, bld
, 2));
3803 } else if (c
== 2 && is_cube_array_image
) {
3804 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3805 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3806 offset(size
, bld
, c
), brw_imm_d(6));
3808 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3809 offset(size
, bld
, c
));
3816 case nir_intrinsic_image_samples
:
3817 /* The driver does not support multi-sampled images. */
3818 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3821 case nir_intrinsic_load_uniform
: {
3822 /* Offsets are in bytes but they should always be multiples of 4 */
3823 assert(instr
->const_index
[0] % 4 == 0);
3825 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3827 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3829 /* Offsets are in bytes but they should always be multiples of 4 */
3830 assert(const_offset
->u32
[0] % 4 == 0);
3831 src
.offset
= const_offset
->u32
[0];
3833 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3834 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3837 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3838 BRW_REGISTER_TYPE_UD
);
3840 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3841 * go past the end of the uniform. In order to keep the n'th
3842 * component from running past, we subtract off the size of all but
3843 * one component of the vector.
3845 assert(instr
->const_index
[1] >=
3846 instr
->num_components
* (int) type_sz(dest
.type
));
3847 unsigned read_size
= instr
->const_index
[1] -
3848 (instr
->num_components
- 1) * type_sz(dest
.type
);
3850 fs_reg indirect_chv_high_32bit
;
3851 bool is_chv_bxt_64bit
=
3852 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
3853 type_sz(dest
.type
) == 8;
3854 if (is_chv_bxt_64bit
) {
3855 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
3856 /* Calculate indirect address to read high 32 bits */
3857 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
3860 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3861 if (!is_chv_bxt_64bit
) {
3862 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3863 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3864 indirect
, brw_imm_ud(read_size
));
3866 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3867 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
3868 offset(src
, bld
, j
),
3869 indirect
, brw_imm_ud(read_size
));
3871 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3872 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
3873 offset(src
, bld
, j
),
3874 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
3881 case nir_intrinsic_load_ubo
: {
3882 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3886 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3887 const_index
->u32
[0];
3888 surf_index
= brw_imm_ud(index
);
3889 brw_mark_surface_used(prog_data
, index
);
3891 /* The block index is not a constant. Evaluate the index expression
3892 * per-channel and add the base UBO index; we have to select a value
3893 * from any live channel.
3895 surf_index
= vgrf(glsl_type::uint_type
);
3896 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3897 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3898 surf_index
= bld
.emit_uniformize(surf_index
);
3900 /* Assume this may touch any UBO. It would be nice to provide
3901 * a tighter bound, but the array information is already lowered away.
3903 brw_mark_surface_used(prog_data
,
3904 stage_prog_data
->binding_table
.ubo_start
+
3905 nir
->info
->num_ubos
- 1);
3908 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3909 if (const_offset
== NULL
) {
3910 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3911 BRW_REGISTER_TYPE_UD
);
3913 for (int i
= 0; i
< instr
->num_components
; i
++)
3914 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3915 base_offset
, i
* type_sz(dest
.type
));
3917 /* Even if we are loading doubles, a pull constant load will load
3918 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3919 * need to load a full dvec4 we will have to emit 2 loads. This is
3920 * similar to demote_pull_constants(), except that in that case we
3921 * see individual accesses to each component of the vector and then
3922 * we let CSE deal with duplicate loads. Here we see a vector access
3923 * and we have to split it if necessary.
3925 const unsigned type_size
= type_sz(dest
.type
);
3926 const unsigned block_sz
= 64; /* Fetch one cacheline at a time. */
3927 const fs_builder ubld
= bld
.exec_all().group(block_sz
/ 4, 0);
3928 const fs_reg packed_consts
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3930 for (unsigned c
= 0; c
< instr
->num_components
;) {
3931 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
3932 /* Number of usable components in the next block-aligned load. */
3933 const unsigned count
= MIN2(instr
->num_components
- c
,
3934 (block_sz
- base
% block_sz
) / type_size
);
3936 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3937 packed_consts
, surf_index
,
3938 brw_imm_ud(base
& ~(block_sz
- 1)));
3940 const fs_reg consts
=
3941 retype(byte_offset(packed_consts
, base
& (block_sz
- 1)),
3944 for (unsigned d
= 0; d
< count
; d
++)
3945 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
3953 case nir_intrinsic_load_ssbo
: {
3954 assert(devinfo
->gen
>= 7);
3956 nir_const_value
*const_uniform_block
=
3957 nir_src_as_const_value(instr
->src
[0]);
3960 if (const_uniform_block
) {
3961 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3962 const_uniform_block
->u32
[0];
3963 surf_index
= brw_imm_ud(index
);
3964 brw_mark_surface_used(prog_data
, index
);
3966 surf_index
= vgrf(glsl_type::uint_type
);
3967 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3968 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3970 /* Assume this may touch any UBO. It would be nice to provide
3971 * a tighter bound, but the array information is already lowered away.
3973 brw_mark_surface_used(prog_data
,
3974 stage_prog_data
->binding_table
.ssbo_start
+
3975 nir
->info
->num_ssbos
- 1);
3979 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3981 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3983 offset_reg
= get_nir_src(instr
->src
[1]);
3986 /* Read the vector */
3987 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3988 instr
->num_components
);
3993 case nir_intrinsic_store_ssbo
: {
3994 assert(devinfo
->gen
>= 7);
3996 if (stage
== MESA_SHADER_FRAGMENT
)
3997 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4001 nir_const_value
*const_uniform_block
=
4002 nir_src_as_const_value(instr
->src
[1]);
4003 if (const_uniform_block
) {
4004 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4005 const_uniform_block
->u32
[0];
4006 surf_index
= brw_imm_ud(index
);
4007 brw_mark_surface_used(prog_data
, index
);
4009 surf_index
= vgrf(glsl_type::uint_type
);
4010 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4011 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4013 brw_mark_surface_used(prog_data
,
4014 stage_prog_data
->binding_table
.ssbo_start
+
4015 nir
->info
->num_ssbos
- 1);
4019 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4022 unsigned writemask
= instr
->const_index
[0];
4024 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4025 * since the untyped writes below operate in units of 32-bits, which
4026 * means that we need to write twice as many components each time.
4027 * Also, we have to suffle 64-bit data to be in the appropriate layout
4028 * expected by our 32-bit write messages.
4030 unsigned type_size
= 4;
4031 unsigned bit_size
= instr
->src
[0].is_ssa
?
4032 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4033 if (bit_size
== 64) {
4036 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4037 shuffle_64bit_data_for_32bit_write(bld
,
4038 retype(tmp
, BRW_REGISTER_TYPE_F
),
4039 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4040 instr
->num_components
);
4044 unsigned type_slots
= type_size
/ 4;
4046 /* Combine groups of consecutive enabled channels in one write
4047 * message. We use ffs to find the first enabled channel and then ffs on
4048 * the bit-inverse, down-shifted writemask to determine the length of
4049 * the block of enabled bits.
4052 unsigned first_component
= ffs(writemask
) - 1;
4053 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4055 /* We can't write more than 2 64-bit components at once. Limit the
4056 * length of the write to what we can do and let the next iteration
4060 length
= MIN2(2, length
);
4063 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4065 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4066 type_size
* first_component
);
4068 offset_reg
= vgrf(glsl_type::uint_type
);
4070 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4071 brw_imm_ud(type_size
* first_component
));
4075 emit_untyped_write(bld
, surf_index
, offset_reg
,
4076 offset(val_reg
, bld
, first_component
* type_slots
),
4077 1 /* dims */, length
* type_slots
,
4078 BRW_PREDICATE_NONE
);
4080 /* Clear the bits in the writemask that we just wrote, then try
4081 * again to see if more channels are left.
4083 writemask
&= (15 << (first_component
+ length
));
4088 case nir_intrinsic_store_output
: {
4089 fs_reg src
= get_nir_src(instr
->src
[0]);
4091 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4092 assert(const_offset
&& "Indirect output stores not allowed");
4093 fs_reg new_dest
= retype(offset(outputs
[instr
->const_index
[0]], bld
,
4094 4 * const_offset
->u32
[0]), src
.type
);
4096 unsigned num_components
= instr
->num_components
;
4097 unsigned first_component
= nir_intrinsic_component(instr
);
4098 unsigned bit_size
= instr
->src
[0].is_ssa
?
4099 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4100 if (bit_size
== 64) {
4102 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4103 BRW_REGISTER_TYPE_F
);
4104 shuffle_64bit_data_for_32bit_write(
4105 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4106 src
= retype(tmp
, src
.type
);
4107 num_components
*= 2;
4110 for (unsigned j
= 0; j
< num_components
; j
++) {
4111 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4112 offset(src
, bld
, j
));
4117 case nir_intrinsic_ssbo_atomic_add
:
4118 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4120 case nir_intrinsic_ssbo_atomic_imin
:
4121 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4123 case nir_intrinsic_ssbo_atomic_umin
:
4124 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4126 case nir_intrinsic_ssbo_atomic_imax
:
4127 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4129 case nir_intrinsic_ssbo_atomic_umax
:
4130 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4132 case nir_intrinsic_ssbo_atomic_and
:
4133 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4135 case nir_intrinsic_ssbo_atomic_or
:
4136 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4138 case nir_intrinsic_ssbo_atomic_xor
:
4139 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4141 case nir_intrinsic_ssbo_atomic_exchange
:
4142 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4144 case nir_intrinsic_ssbo_atomic_comp_swap
:
4145 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4148 case nir_intrinsic_get_buffer_size
: {
4149 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4150 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4152 /* A resinfo's sampler message is used to get the buffer size. The
4153 * SIMD8's writeback message consists of four registers and SIMD16's
4154 * writeback message consists of 8 destination registers (two per each
4155 * component). Because we are only interested on the first channel of
4156 * the first returned component, where resinfo returns the buffer size
4157 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4158 * the dispatch width.
4160 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4161 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4162 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4165 ubld
.MOV(src_payload
, brw_imm_d(0));
4167 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4168 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4169 src_payload
, brw_imm_ud(index
));
4170 inst
->header_size
= 0;
4172 inst
->size_written
= 4 * REG_SIZE
;
4174 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4175 brw_mark_surface_used(prog_data
, index
);
4179 case nir_intrinsic_load_channel_num
: {
4180 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4181 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4182 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4183 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4184 if (dispatch_width
> 8)
4185 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4186 if (dispatch_width
> 16) {
4187 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4188 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4195 unreachable("unknown intrinsic");
4200 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4201 int op
, nir_intrinsic_instr
*instr
)
4203 if (stage
== MESA_SHADER_FRAGMENT
)
4204 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4207 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4208 dest
= get_nir_dest(instr
->dest
);
4211 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4212 if (const_surface
) {
4213 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4214 const_surface
->u32
[0];
4215 surface
= brw_imm_ud(surf_index
);
4216 brw_mark_surface_used(prog_data
, surf_index
);
4218 surface
= vgrf(glsl_type::uint_type
);
4219 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4220 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4222 /* Assume this may touch any SSBO. This is the same we do for other
4223 * UBO/SSBO accesses with non-constant surface.
4225 brw_mark_surface_used(prog_data
,
4226 stage_prog_data
->binding_table
.ssbo_start
+
4227 nir
->info
->num_ssbos
- 1);
4230 fs_reg offset
= get_nir_src(instr
->src
[1]);
4231 fs_reg data1
= get_nir_src(instr
->src
[2]);
4233 if (op
== BRW_AOP_CMPWR
)
4234 data2
= get_nir_src(instr
->src
[3]);
4236 /* Emit the actual atomic operation */
4238 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4240 1 /* dims */, 1 /* rsize */,
4242 BRW_PREDICATE_NONE
);
4243 dest
.type
= atomic_result
.type
;
4244 bld
.MOV(dest
, atomic_result
);
4248 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4249 int op
, nir_intrinsic_instr
*instr
)
4252 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4253 dest
= get_nir_dest(instr
->dest
);
4255 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4257 fs_reg data1
= get_nir_src(instr
->src
[1]);
4259 if (op
== BRW_AOP_CMPWR
)
4260 data2
= get_nir_src(instr
->src
[2]);
4262 /* Get the offset */
4263 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4265 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4267 offset
= vgrf(glsl_type::uint_type
);
4269 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4270 brw_imm_ud(instr
->const_index
[0]));
4273 /* Emit the actual atomic operation operation */
4275 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4277 1 /* dims */, 1 /* rsize */,
4279 BRW_PREDICATE_NONE
);
4280 dest
.type
= atomic_result
.type
;
4281 bld
.MOV(dest
, atomic_result
);
4285 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4287 unsigned texture
= instr
->texture_index
;
4288 unsigned sampler
= instr
->sampler_index
;
4290 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4292 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4293 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4295 int lod_components
= 0;
4297 /* The hardware requires a LOD for buffer textures */
4298 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4299 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4301 uint32_t header_bits
= 0;
4302 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4303 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4304 switch (instr
->src
[i
].src_type
) {
4305 case nir_tex_src_bias
:
4306 srcs
[TEX_LOGICAL_SRC_LOD
] =
4307 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4309 case nir_tex_src_comparator
:
4310 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4312 case nir_tex_src_coord
:
4313 switch (instr
->op
) {
4315 case nir_texop_txf_ms
:
4316 case nir_texop_txf_ms_mcs
:
4317 case nir_texop_samples_identical
:
4318 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4321 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4325 case nir_tex_src_ddx
:
4326 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4327 lod_components
= nir_tex_instr_src_size(instr
, i
);
4329 case nir_tex_src_ddy
:
4330 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4332 case nir_tex_src_lod
:
4333 switch (instr
->op
) {
4335 srcs
[TEX_LOGICAL_SRC_LOD
] =
4336 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4339 srcs
[TEX_LOGICAL_SRC_LOD
] =
4340 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4343 srcs
[TEX_LOGICAL_SRC_LOD
] =
4344 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4348 case nir_tex_src_ms_index
:
4349 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4352 case nir_tex_src_offset
: {
4353 nir_const_value
*const_offset
=
4354 nir_src_as_const_value(instr
->src
[i
].src
);
4355 unsigned offset_bits
= 0;
4357 brw_texture_offset(const_offset
->i32
,
4358 nir_tex_instr_src_size(instr
, i
),
4360 header_bits
|= offset_bits
;
4362 srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
] =
4363 retype(src
, BRW_REGISTER_TYPE_D
);
4368 case nir_tex_src_projector
:
4369 unreachable("should be lowered");
4371 case nir_tex_src_texture_offset
: {
4372 /* Figure out the highest possible texture index and mark it as used */
4373 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4374 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4375 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4377 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4379 brw_mark_surface_used(prog_data
, max_used
);
4381 /* Emit code to evaluate the actual indexing expression */
4382 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4383 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4384 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4388 case nir_tex_src_sampler_offset
: {
4389 /* Emit code to evaluate the actual indexing expression */
4390 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4391 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4392 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4396 case nir_tex_src_ms_mcs
:
4397 assert(instr
->op
== nir_texop_txf_ms
);
4398 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4401 case nir_tex_src_plane
: {
4402 nir_const_value
*const_plane
=
4403 nir_src_as_const_value(instr
->src
[i
].src
);
4404 const uint32_t plane
= const_plane
->u32
[0];
4405 const uint32_t texture_index
=
4406 instr
->texture_index
+
4407 stage_prog_data
->binding_table
.plane_start
[plane
] -
4408 stage_prog_data
->binding_table
.texture_start
;
4410 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4415 unreachable("unknown texture source");
4419 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4420 (instr
->op
== nir_texop_txf_ms
||
4421 instr
->op
== nir_texop_samples_identical
)) {
4422 if (devinfo
->gen
>= 7 &&
4423 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4424 srcs
[TEX_LOGICAL_SRC_MCS
] =
4425 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4426 instr
->coord_components
,
4427 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4429 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4433 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4434 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4436 if (instr
->op
== nir_texop_query_levels
||
4437 (instr
->op
== nir_texop_tex
&& stage
!= MESA_SHADER_FRAGMENT
)) {
4438 /* textureQueryLevels() and texture() are implemented in terms of TXS
4439 * and TXL respectively, so we need to pass a valid LOD argument.
4441 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4442 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4446 switch (instr
->op
) {
4448 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4449 SHADER_OPCODE_TXL_LOGICAL
);
4452 opcode
= FS_OPCODE_TXB_LOGICAL
;
4455 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4458 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4461 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4463 case nir_texop_txf_ms
:
4464 if ((key_tex
->msaa_16
& (1 << sampler
)))
4465 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4467 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4469 case nir_texop_txf_ms_mcs
:
4470 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4472 case nir_texop_query_levels
:
4474 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4477 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4480 if (srcs
[TEX_LOGICAL_SRC_TG4_OFFSET
].file
!= BAD_FILE
)
4481 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4483 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4485 case nir_texop_texture_samples
:
4486 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4488 case nir_texop_samples_identical
: {
4489 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4491 /* If mcs is an immediate value, it means there is no MCS. In that case
4492 * just return false.
4494 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4495 bld
.MOV(dst
, brw_imm_ud(0u));
4496 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4497 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4498 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4499 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4500 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4502 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4503 BRW_CONDITIONAL_EQ
);
4508 unreachable("unknown texture opcode");
4511 if (instr
->op
== nir_texop_tg4
) {
4512 if (instr
->component
== 1 &&
4513 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4514 /* gather4 sampler is broken for green channel on RG32F --
4515 * we must ask for blue instead.
4517 header_bits
|= 2 << 16;
4519 header_bits
|= instr
->component
<< 16;
4523 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4524 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4525 inst
->offset
= header_bits
;
4527 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4528 if (devinfo
->gen
>= 9 &&
4529 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4530 unsigned write_mask
= instr
->dest
.is_ssa
?
4531 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4532 (1 << dest_size
) - 1;
4533 assert(write_mask
!= 0); /* dead code should have been eliminated */
4534 inst
->size_written
= util_last_bit(write_mask
) *
4535 inst
->dst
.component_size(inst
->exec_size
);
4537 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4540 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4541 inst
->shadow_compare
= true;
4543 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
== 6)
4544 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4547 for (unsigned i
= 0; i
< dest_size
; i
++)
4548 nir_dest
[i
] = offset(dst
, bld
, i
);
4550 if (instr
->op
== nir_texop_query_levels
) {
4551 /* # levels is in .w */
4552 nir_dest
[0] = offset(dst
, bld
, 3);
4553 } else if (instr
->op
== nir_texop_txs
&&
4554 dest_size
>= 3 && devinfo
->gen
< 7) {
4555 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4556 fs_reg depth
= offset(dst
, bld
, 2);
4557 nir_dest
[2] = vgrf(glsl_type::int_type
);
4558 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4561 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4565 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4567 switch (instr
->type
) {
4568 case nir_jump_break
:
4569 bld
.emit(BRW_OPCODE_BREAK
);
4571 case nir_jump_continue
:
4572 bld
.emit(BRW_OPCODE_CONTINUE
);
4574 case nir_jump_return
:
4576 unreachable("unknown jump");
4581 * This helper takes the result of a load operation that reads 32-bit elements
4589 * and shuffles the data to get this:
4596 * Which is exactly what we want if the load is reading 64-bit components
4597 * like doubles, where x represents the low 32-bit of the x double component
4598 * and y represents the high 32-bit of the x double component (likewise with
4599 * z and w for double component y). The parameter @components represents
4600 * the number of 64-bit components present in @src. This would typically be
4601 * 2 at most, since we can only fit 2 double elements in the result of a
4604 * Notice that @dst and @src can be the same register.
4607 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4610 uint32_t components
)
4612 assert(type_sz(src
.type
) == 4);
4613 assert(type_sz(dst
.type
) == 8);
4615 /* A temporary that we will use to shuffle the 32-bit data of each
4616 * component in the vector into valid 64-bit data. We can't write directly
4617 * to dst because dst can be (and would usually be) the same as src
4618 * and in that case the first MOV in the loop below would overwrite the
4619 * data read in the second MOV.
4621 fs_reg tmp
= bld
.vgrf(dst
.type
);
4623 for (unsigned i
= 0; i
< components
; i
++) {
4624 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4626 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4627 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4629 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4634 * This helper does the inverse operation of
4635 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4637 * We need to do this when we are going to use untyped write messsages that
4638 * operate with 32-bit components in order to arrange our 64-bit data to be
4639 * in the expected layout.
4641 * Notice that callers of this function, unlike in the case of the inverse
4642 * operation, would typically need to call this with dst and src being
4643 * different registers, since they would otherwise corrupt the original
4644 * 64-bit data they are about to write. Because of this the function checks
4645 * that the src and dst regions involved in the operation do not overlap.
4648 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4651 uint32_t components
)
4653 assert(type_sz(src
.type
) == 8);
4654 assert(type_sz(dst
.type
) == 4);
4656 assert(!regions_overlap(
4657 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4658 src
, components
* src
.component_size(bld
.dispatch_width())));
4660 for (unsigned i
= 0; i
< components
; i
++) {
4661 const fs_reg component_i
= offset(src
, bld
, i
);
4662 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4663 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4668 setup_imm_df(const fs_builder
&bld
, double v
)
4670 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4671 assert(devinfo
->gen
>= 7);
4673 if (devinfo
->gen
>= 8)
4674 return brw_imm_df(v
);
4676 /* gen7.5 does not support DF immediates straighforward but the DIM
4677 * instruction allows to set the 64-bit immediate value.
4679 if (devinfo
->is_haswell
) {
4680 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4681 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4682 ubld
.DIM(dst
, brw_imm_df(v
));
4683 return component(dst
, 0);
4686 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4687 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4688 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4690 * Alternatively, we could also produce a normal VGRF (without stride 0)
4691 * by writing to all the channels in the VGRF, however, that would hit the
4692 * gen7 bug where we have to split writes that span more than 1 register
4693 * into instructions with a width of 4 (otherwise the write to the second
4694 * register written runs into an execmask hardware bug) which isn't very
4707 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4708 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4709 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4710 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4712 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);