2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (var
->data
.index
> 0) {
134 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
135 assert(var
->data
.index
== 1);
136 this->dual_src_output
= reg
;
137 this->do_dual_src
= true;
138 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
139 /* Writing gl_FragColor outputs to all color regions. */
140 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
141 this->outputs
[i
] = reg
;
142 this->output_components
[i
] = 4;
144 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
145 this->frag_depth
= reg
;
146 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
147 this->frag_stencil
= reg
;
148 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
149 this->sample_mask
= reg
;
151 int vector_elements
= var
->type
->without_array()->vector_elements
;
153 /* gl_FragData or a user-defined FS output */
154 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
155 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
157 /* General color output. */
158 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
159 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
160 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
161 this->output_components
[output
] = vector_elements
;
166 unreachable("unhandled shader stage");
172 fs_visitor::nir_setup_uniforms()
174 if (dispatch_width
!= 8)
177 uniforms
= nir
->num_uniforms
/ 4;
181 emit_system_values_block(nir_block
*block
, void *void_visitor
)
183 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
186 nir_foreach_instr(block
, instr
) {
187 if (instr
->type
!= nir_instr_type_intrinsic
)
190 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
191 switch (intrin
->intrinsic
) {
192 case nir_intrinsic_load_vertex_id
:
193 unreachable("should be lowered by lower_vertex_id().");
195 case nir_intrinsic_load_vertex_id_zero_base
:
196 assert(v
->stage
== MESA_SHADER_VERTEX
);
197 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
198 if (reg
->file
== BAD_FILE
)
199 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
202 case nir_intrinsic_load_base_vertex
:
203 assert(v
->stage
== MESA_SHADER_VERTEX
);
204 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
205 if (reg
->file
== BAD_FILE
)
206 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
209 case nir_intrinsic_load_instance_id
:
210 assert(v
->stage
== MESA_SHADER_VERTEX
);
211 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
212 if (reg
->file
== BAD_FILE
)
213 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
216 case nir_intrinsic_load_base_instance
:
217 assert(v
->stage
== MESA_SHADER_VERTEX
);
218 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
219 if (reg
->file
== BAD_FILE
)
220 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
223 case nir_intrinsic_load_draw_id
:
224 assert(v
->stage
== MESA_SHADER_VERTEX
);
225 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
226 if (reg
->file
== BAD_FILE
)
227 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
230 case nir_intrinsic_load_invocation_id
:
231 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
232 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
233 if (reg
->file
== BAD_FILE
) {
234 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
235 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
236 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
237 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
242 case nir_intrinsic_load_sample_pos
:
243 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
244 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
245 if (reg
->file
== BAD_FILE
)
246 *reg
= *v
->emit_samplepos_setup();
249 case nir_intrinsic_load_sample_id
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
252 if (reg
->file
== BAD_FILE
)
253 *reg
= *v
->emit_sampleid_setup();
256 case nir_intrinsic_load_sample_mask_in
:
257 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
258 assert(v
->devinfo
->gen
>= 7);
259 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
260 if (reg
->file
== BAD_FILE
)
261 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
262 BRW_REGISTER_TYPE_D
));
265 case nir_intrinsic_load_local_invocation_id
:
266 assert(v
->stage
== MESA_SHADER_COMPUTE
);
267 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
268 if (reg
->file
== BAD_FILE
)
269 *reg
= *v
->emit_cs_local_invocation_id_setup();
272 case nir_intrinsic_load_work_group_id
:
273 assert(v
->stage
== MESA_SHADER_COMPUTE
);
274 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
275 if (reg
->file
== BAD_FILE
)
276 *reg
= *v
->emit_cs_work_group_id_setup();
279 case nir_intrinsic_load_helper_invocation
:
280 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
281 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
282 if (reg
->file
== BAD_FILE
) {
283 const fs_builder abld
=
284 v
->bld
.annotate("gl_HelperInvocation", NULL
);
286 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
287 * pixel mask is in g1.7 of the thread payload.
289 * We move the per-channel pixel enable bit to the low bit of each
290 * channel by shifting the byte containing the pixel mask by the
291 * vector immediate 0x76543210UV.
293 * The region of <1,8,0> reads only 1 byte (the pixel masks for
294 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
295 * masks for 2 and 3) in SIMD16.
297 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
299 stride(byte_offset(retype(brw_vec1_grf(1, 0),
300 BRW_REGISTER_TYPE_UB
), 28),
302 brw_imm_uv(0x76543210));
304 /* A set bit in the pixel mask means the channel is enabled, but
305 * that is the opposite of gl_HelperInvocation so we need to invert
308 * The negate source-modifier bit of logical instructions on Gen8+
309 * performs 1's complement negation, so we can use that instead of
312 fs_reg inverted
= negate(shifted
);
313 if (v
->devinfo
->gen
< 8) {
314 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
315 abld
.NOT(inverted
, shifted
);
318 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
319 * with 1 and negating.
321 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
322 abld
.AND(anded
, inverted
, brw_imm_uw(1));
324 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
325 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
339 fs_visitor::nir_emit_system_values()
341 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
342 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
343 nir_system_values
[i
] = fs_reg();
346 nir_foreach_function(nir
, function
) {
347 assert(strcmp(function
->name
, "main") == 0);
348 assert(function
->impl
);
349 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
354 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
356 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
357 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
358 nir_locals
[i
] = fs_reg();
361 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
362 unsigned array_elems
=
363 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
364 unsigned size
= array_elems
* reg
->num_components
;
365 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
368 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
371 nir_emit_cf_list(&impl
->body
);
375 fs_visitor::nir_emit_cf_list(exec_list
*list
)
377 exec_list_validate(list
);
378 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
379 switch (node
->type
) {
381 nir_emit_if(nir_cf_node_as_if(node
));
384 case nir_cf_node_loop
:
385 nir_emit_loop(nir_cf_node_as_loop(node
));
388 case nir_cf_node_block
:
389 nir_emit_block(nir_cf_node_as_block(node
));
393 unreachable("Invalid CFG node block");
399 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
401 /* first, put the condition into f0 */
402 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
403 retype(get_nir_src(if_stmt
->condition
),
404 BRW_REGISTER_TYPE_D
));
405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
407 bld
.IF(BRW_PREDICATE_NORMAL
);
409 nir_emit_cf_list(&if_stmt
->then_list
);
411 /* note: if the else is empty, dead CF elimination will remove it */
412 bld
.emit(BRW_OPCODE_ELSE
);
414 nir_emit_cf_list(&if_stmt
->else_list
);
416 bld
.emit(BRW_OPCODE_ENDIF
);
420 fs_visitor::nir_emit_loop(nir_loop
*loop
)
422 bld
.emit(BRW_OPCODE_DO
);
424 nir_emit_cf_list(&loop
->body
);
426 bld
.emit(BRW_OPCODE_WHILE
);
430 fs_visitor::nir_emit_block(nir_block
*block
)
432 nir_foreach_instr(block
, instr
) {
433 nir_emit_instr(instr
);
438 fs_visitor::nir_emit_instr(nir_instr
*instr
)
440 const fs_builder abld
= bld
.annotate(NULL
, instr
);
442 switch (instr
->type
) {
443 case nir_instr_type_alu
:
444 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
447 case nir_instr_type_intrinsic
:
449 case MESA_SHADER_VERTEX
:
450 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_TESS_EVAL
:
453 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
455 case MESA_SHADER_GEOMETRY
:
456 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
458 case MESA_SHADER_FRAGMENT
:
459 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_COMPUTE
:
462 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 unreachable("unsupported shader stage");
469 case nir_instr_type_tex
:
470 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
473 case nir_instr_type_load_const
:
474 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
477 case nir_instr_type_ssa_undef
:
478 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
481 case nir_instr_type_jump
:
482 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
486 unreachable("unknown instruction type");
491 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
492 const fs_reg
&result
)
494 if (!instr
->src
[0].src
.is_ssa
||
495 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
498 nir_intrinsic_instr
*src0
=
499 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
501 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
504 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
505 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
508 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
509 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
512 fs_reg tmp
= vgrf(glsl_type::int_type
);
514 if (devinfo
->gen
>= 6) {
515 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
516 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
518 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
520 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
521 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
523 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
525 * This negation looks like it's safe in practice, because bits 0:4 will
526 * surely be TRIANGLES
529 if (value1
->f
[0] == -1.0f
) {
533 tmp
.type
= BRW_REGISTER_TYPE_W
;
534 tmp
.subreg_offset
= 2;
537 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
539 tmp
.type
= BRW_REGISTER_TYPE_D
;
540 tmp
.subreg_offset
= 0;
543 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
544 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
546 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
548 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
549 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
551 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
553 * This negation looks like it's safe in practice, because bits 0:4 will
554 * surely be TRIANGLES
557 if (value1
->f
[0] == -1.0f
) {
561 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
563 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
569 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
571 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
574 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
575 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
578 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
579 op
[i
] = get_nir_src(instr
->src
[i
].src
);
580 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
581 op
[i
].abs
= instr
->src
[i
].abs
;
582 op
[i
].negate
= instr
->src
[i
].negate
;
585 /* We get a bunch of mov's out of the from_ssa pass and they may still
586 * be vectorized. We'll handle them as a special-case. We'll also
587 * handle vecN here because it's basically the same thing.
595 fs_reg temp
= result
;
596 bool need_extra_copy
= false;
597 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
598 if (!instr
->src
[i
].src
.is_ssa
&&
599 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
600 need_extra_copy
= true;
601 temp
= bld
.vgrf(result
.type
, 4);
606 for (unsigned i
= 0; i
< 4; i
++) {
607 if (!(instr
->dest
.write_mask
& (1 << i
)))
610 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
611 inst
= bld
.MOV(offset(temp
, bld
, i
),
612 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
614 inst
= bld
.MOV(offset(temp
, bld
, i
),
615 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
617 inst
->saturate
= instr
->dest
.saturate
;
620 /* In this case the source and destination registers were the same,
621 * so we need to insert an extra set of moves in order to deal with
624 if (need_extra_copy
) {
625 for (unsigned i
= 0; i
< 4; i
++) {
626 if (!(instr
->dest
.write_mask
& (1 << i
)))
629 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
638 /* At this point, we have dealt with any instruction that operates on
639 * more than a single channel. Therefore, we can just adjust the source
640 * and destination registers for that channel and emit the instruction.
642 unsigned channel
= 0;
643 if (nir_op_infos
[instr
->op
].output_size
== 0) {
644 /* Since NIR is doing the scalarizing for us, we should only ever see
645 * vectorized operations with a single channel.
647 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
648 channel
= ffs(instr
->dest
.write_mask
) - 1;
650 result
= offset(result
, bld
, channel
);
653 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
654 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
655 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
661 inst
= bld
.MOV(result
, op
[0]);
662 inst
->saturate
= instr
->dest
.saturate
;
667 bld
.MOV(result
, op
[0]);
671 /* AND(val, 0x80000000) gives the sign bit.
673 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
676 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
678 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
679 op
[0].type
= BRW_REGISTER_TYPE_UD
;
680 result
.type
= BRW_REGISTER_TYPE_UD
;
681 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
683 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
684 inst
->predicate
= BRW_PREDICATE_NORMAL
;
685 if (instr
->dest
.saturate
) {
686 inst
= bld
.MOV(result
, result
);
687 inst
->saturate
= true;
693 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
694 * -> non-negative val generates 0x00000000.
695 * Predicated OR sets 1 if val is positive.
697 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
698 bld
.ASR(result
, op
[0], brw_imm_d(31));
699 inst
= bld
.OR(result
, result
, brw_imm_d(1));
700 inst
->predicate
= BRW_PREDICATE_NORMAL
;
704 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
705 inst
->saturate
= instr
->dest
.saturate
;
709 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
710 inst
->saturate
= instr
->dest
.saturate
;
714 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
715 inst
->saturate
= instr
->dest
.saturate
;
719 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
720 inst
->saturate
= instr
->dest
.saturate
;
724 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
725 inst
->saturate
= instr
->dest
.saturate
;
729 if (fs_key
->high_quality_derivatives
) {
730 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
732 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
734 inst
->saturate
= instr
->dest
.saturate
;
736 case nir_op_fddx_fine
:
737 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
740 case nir_op_fddx_coarse
:
741 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
742 inst
->saturate
= instr
->dest
.saturate
;
745 if (fs_key
->high_quality_derivatives
) {
746 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
747 brw_imm_d(fs_key
->render_to_fbo
));
749 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
750 brw_imm_d(fs_key
->render_to_fbo
));
752 inst
->saturate
= instr
->dest
.saturate
;
754 case nir_op_fddy_fine
:
755 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
756 brw_imm_d(fs_key
->render_to_fbo
));
757 inst
->saturate
= instr
->dest
.saturate
;
759 case nir_op_fddy_coarse
:
760 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
761 brw_imm_d(fs_key
->render_to_fbo
));
762 inst
->saturate
= instr
->dest
.saturate
;
767 inst
= bld
.ADD(result
, op
[0], op
[1]);
768 inst
->saturate
= instr
->dest
.saturate
;
772 inst
= bld
.MUL(result
, op
[0], op
[1]);
773 inst
->saturate
= instr
->dest
.saturate
;
777 bld
.MUL(result
, op
[0], op
[1]);
780 case nir_op_imul_high
:
781 case nir_op_umul_high
:
782 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
787 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
790 case nir_op_uadd_carry
:
791 unreachable("Should have been lowered by carry_to_arith().");
793 case nir_op_usub_borrow
:
794 unreachable("Should have been lowered by borrow_to_arith().");
798 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
799 * appears that our hardware just does the right thing for signed
802 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
806 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
807 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
809 /* Math instructions don't support conditional mod */
810 inst
= bld
.MOV(bld
.null_reg_d(), result
);
811 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
813 /* Now, we need to determine if signs of the sources are different.
814 * When we XOR the sources, the top bit is 0 if they are the same and 1
815 * if they are different. We can then use a conditional modifier to
816 * turn that into a predicate. This leads us to an XOR.l instruction.
818 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
819 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
820 inst
->predicate
= BRW_PREDICATE_NORMAL
;
821 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
823 /* If the result of the initial remainder operation is non-zero and the
824 * two sources have different signs, add in a copy of op[1] to get the
825 * final integer modulus value.
827 inst
= bld
.ADD(result
, result
, op
[1]);
828 inst
->predicate
= BRW_PREDICATE_NORMAL
;
835 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
841 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
846 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
851 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
855 if (devinfo
->gen
>= 8) {
856 op
[0] = resolve_source_modifiers(op
[0]);
858 bld
.NOT(result
, op
[0]);
861 if (devinfo
->gen
>= 8) {
862 op
[0] = resolve_source_modifiers(op
[0]);
863 op
[1] = resolve_source_modifiers(op
[1]);
865 bld
.XOR(result
, op
[0], op
[1]);
868 if (devinfo
->gen
>= 8) {
869 op
[0] = resolve_source_modifiers(op
[0]);
870 op
[1] = resolve_source_modifiers(op
[1]);
872 bld
.OR(result
, op
[0], op
[1]);
875 if (devinfo
->gen
>= 8) {
876 op
[0] = resolve_source_modifiers(op
[0]);
877 op
[1] = resolve_source_modifiers(op
[1]);
879 bld
.AND(result
, op
[0], op
[1]);
885 case nir_op_ball_fequal2
:
886 case nir_op_ball_iequal2
:
887 case nir_op_ball_fequal3
:
888 case nir_op_ball_iequal3
:
889 case nir_op_ball_fequal4
:
890 case nir_op_ball_iequal4
:
891 case nir_op_bany_fnequal2
:
892 case nir_op_bany_inequal2
:
893 case nir_op_bany_fnequal3
:
894 case nir_op_bany_inequal3
:
895 case nir_op_bany_fnequal4
:
896 case nir_op_bany_inequal4
:
897 unreachable("Lowered by nir_lower_alu_reductions");
899 case nir_op_fnoise1_1
:
900 case nir_op_fnoise1_2
:
901 case nir_op_fnoise1_3
:
902 case nir_op_fnoise1_4
:
903 case nir_op_fnoise2_1
:
904 case nir_op_fnoise2_2
:
905 case nir_op_fnoise2_3
:
906 case nir_op_fnoise2_4
:
907 case nir_op_fnoise3_1
:
908 case nir_op_fnoise3_2
:
909 case nir_op_fnoise3_3
:
910 case nir_op_fnoise3_4
:
911 case nir_op_fnoise4_1
:
912 case nir_op_fnoise4_2
:
913 case nir_op_fnoise4_3
:
914 case nir_op_fnoise4_4
:
915 unreachable("not reached: should be handled by lower_noise");
918 unreachable("not reached: should be handled by ldexp_to_arith()");
921 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
922 inst
->saturate
= instr
->dest
.saturate
;
926 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
927 inst
->saturate
= instr
->dest
.saturate
;
932 bld
.MOV(result
, negate(op
[0]));
936 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
939 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
943 inst
= bld
.RNDZ(result
, op
[0]);
944 inst
->saturate
= instr
->dest
.saturate
;
948 op
[0].negate
= !op
[0].negate
;
949 fs_reg temp
= vgrf(glsl_type::float_type
);
950 bld
.RNDD(temp
, op
[0]);
952 inst
= bld
.MOV(result
, temp
);
953 inst
->saturate
= instr
->dest
.saturate
;
957 inst
= bld
.RNDD(result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
961 inst
= bld
.FRC(result
, op
[0]);
962 inst
->saturate
= instr
->dest
.saturate
;
964 case nir_op_fround_even
:
965 inst
= bld
.RNDE(result
, op
[0]);
966 inst
->saturate
= instr
->dest
.saturate
;
969 case nir_op_fquantize2f16
: {
970 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
971 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
972 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
974 /* The destination stride must be at least as big as the source stride. */
975 tmp16
.type
= BRW_REGISTER_TYPE_W
;
978 /* Check for denormal */
979 fs_reg abs_src0
= op
[0];
981 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
983 /* Get the appropriately signed zero */
984 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
985 retype(op
[0], BRW_REGISTER_TYPE_UD
),
986 brw_imm_ud(0x80000000));
987 /* Do the actual F32 -> F16 -> F32 conversion */
988 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
989 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
990 /* Select that or zero based on normal status */
991 inst
= bld
.SEL(result
, zero
, tmp32
);
992 inst
->predicate
= BRW_PREDICATE_NORMAL
;
993 inst
->saturate
= instr
->dest
.saturate
;
1000 if (devinfo
->gen
>= 6) {
1001 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1002 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1004 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
1005 inst
= bld
.SEL(result
, op
[0], op
[1]);
1006 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1008 inst
->saturate
= instr
->dest
.saturate
;
1014 if (devinfo
->gen
>= 6) {
1015 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1016 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1018 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1019 inst
= bld
.SEL(result
, op
[0], op
[1]);
1020 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1022 inst
->saturate
= instr
->dest
.saturate
;
1025 case nir_op_pack_snorm_2x16
:
1026 case nir_op_pack_snorm_4x8
:
1027 case nir_op_pack_unorm_2x16
:
1028 case nir_op_pack_unorm_4x8
:
1029 case nir_op_unpack_snorm_2x16
:
1030 case nir_op_unpack_snorm_4x8
:
1031 case nir_op_unpack_unorm_2x16
:
1032 case nir_op_unpack_unorm_4x8
:
1033 case nir_op_unpack_half_2x16
:
1034 case nir_op_pack_half_2x16
:
1035 unreachable("not reached: should be handled by lower_packing_builtins");
1037 case nir_op_unpack_half_2x16_split_x
:
1038 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1039 inst
->saturate
= instr
->dest
.saturate
;
1041 case nir_op_unpack_half_2x16_split_y
:
1042 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1043 inst
->saturate
= instr
->dest
.saturate
;
1047 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1048 inst
->saturate
= instr
->dest
.saturate
;
1051 case nir_op_bitfield_reverse
:
1052 bld
.BFREV(result
, op
[0]);
1055 case nir_op_bit_count
:
1056 bld
.CBIT(result
, op
[0]);
1059 case nir_op_ufind_msb
:
1060 case nir_op_ifind_msb
: {
1061 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1063 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1064 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1065 * subtract the result from 31 to convert the MSB count into an LSB count.
1067 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1069 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1070 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1071 inst
->src
[0].negate
= true;
1075 case nir_op_find_lsb
:
1076 bld
.FBL(result
, op
[0]);
1079 case nir_op_ubitfield_extract
:
1080 case nir_op_ibitfield_extract
:
1081 unreachable("should have been lowered");
1084 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1087 bld
.BFI1(result
, op
[0], op
[1]);
1090 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1093 case nir_op_bitfield_insert
:
1094 unreachable("not reached: should have been lowered");
1097 bld
.SHL(result
, op
[0], op
[1]);
1100 bld
.ASR(result
, op
[0], op
[1]);
1103 bld
.SHR(result
, op
[0], op
[1]);
1106 case nir_op_pack_half_2x16_split
:
1107 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1111 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1112 inst
->saturate
= instr
->dest
.saturate
;
1116 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1117 inst
->saturate
= instr
->dest
.saturate
;
1121 if (optimize_frontfacing_ternary(instr
, result
))
1124 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1125 inst
= bld
.SEL(result
, op
[1], op
[2]);
1126 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1129 case nir_op_extract_ubyte
:
1130 case nir_op_extract_ibyte
: {
1131 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1132 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1133 result
, op
[0], brw_imm_ud(byte
->u
[0]));
1137 case nir_op_extract_uword
:
1138 case nir_op_extract_iword
: {
1139 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1140 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1141 result
, op
[0], brw_imm_ud(word
->u
[0]));
1146 unreachable("unhandled instruction");
1149 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1150 * to sign extend the low bit to 0/~0
1152 if (devinfo
->gen
<= 5 &&
1153 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1154 fs_reg masked
= vgrf(glsl_type::int_type
);
1155 bld
.AND(masked
, result
, brw_imm_d(1));
1156 masked
.negate
= true;
1157 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1162 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1163 nir_load_const_instr
*instr
)
1165 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1167 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1168 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1170 nir_ssa_values
[instr
->def
.index
] = reg
;
1174 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1176 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1177 instr
->def
.num_components
);
1181 fs_visitor::get_nir_src(nir_src src
)
1185 reg
= nir_ssa_values
[src
.ssa
->index
];
1187 /* We don't handle indirects on locals */
1188 assert(src
.reg
.indirect
== NULL
);
1189 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1190 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1193 /* to avoid floating-point denorm flushing problems, set the type by
1194 * default to D - instructions that need floating point semantics will set
1195 * this to F if they need to
1197 return retype(reg
, BRW_REGISTER_TYPE_D
);
1201 fs_visitor::get_nir_dest(nir_dest dest
)
1204 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1205 dest
.ssa
.num_components
);
1206 return nir_ssa_values
[dest
.ssa
.index
];
1208 /* We don't handle indirects on locals */
1209 assert(dest
.reg
.indirect
== NULL
);
1210 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1211 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1216 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1218 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1219 BRW_REGISTER_TYPE_UD
);
1221 unsigned indirect_max
= 0;
1223 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1224 tail
= tail
->child
) {
1225 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1226 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1227 const unsigned size
= glsl_get_length(tail
->type
);
1228 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1229 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1230 image
= offset(image
, bld
, base
* element_size
);
1232 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1233 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1235 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1236 /* IVB hangs when trying to access an invalid surface index with
1237 * the dataport. According to the spec "if the index used to
1238 * select an individual element is negative or greater than or
1239 * equal to the size of the array, the results of the operation
1240 * are undefined but may not lead to termination" -- which is one
1241 * of the possible outcomes of the hang. Clamp the index to
1242 * prevent access outside of the array bounds.
1244 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1245 BRW_REGISTER_TYPE_UD
),
1246 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1248 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1251 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1253 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1254 if (indirect
.file
== BAD_FILE
) {
1257 bld
.ADD(indirect
, indirect
, tmp
);
1262 if (indirect
.file
== BAD_FILE
) {
1265 /* Emit a pile of MOVs to load the uniform into a temporary. The
1266 * dead-code elimination pass will get rid of what we don't use.
1268 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1269 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1270 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1271 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1272 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1279 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1282 for (unsigned i
= 0; i
< 4; i
++) {
1283 if (!((wr_mask
>> i
) & 1))
1286 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1287 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1288 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1289 if (new_inst
->src
[j
].file
== VGRF
)
1290 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1297 * Get the matching channel register datatype for an image intrinsic of the
1298 * specified GLSL image type.
1301 get_image_base_type(const glsl_type
*type
)
1303 switch ((glsl_base_type
)type
->sampler_type
) {
1304 case GLSL_TYPE_UINT
:
1305 return BRW_REGISTER_TYPE_UD
;
1307 return BRW_REGISTER_TYPE_D
;
1308 case GLSL_TYPE_FLOAT
:
1309 return BRW_REGISTER_TYPE_F
;
1311 unreachable("Not reached.");
1316 * Get the appropriate atomic op for an image atomic intrinsic.
1319 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1322 case nir_intrinsic_image_atomic_add
:
1324 case nir_intrinsic_image_atomic_min
:
1325 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1326 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1327 case nir_intrinsic_image_atomic_max
:
1328 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1329 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1330 case nir_intrinsic_image_atomic_and
:
1332 case nir_intrinsic_image_atomic_or
:
1334 case nir_intrinsic_image_atomic_xor
:
1336 case nir_intrinsic_image_atomic_exchange
:
1338 case nir_intrinsic_image_atomic_comp_swap
:
1339 return BRW_AOP_CMPWR
;
1341 unreachable("Not reachable.");
1346 emit_pixel_interpolater_send(const fs_builder
&bld
,
1351 glsl_interp_qualifier interpolation
)
1357 if (src
.file
== BAD_FILE
) {
1359 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1363 mlen
= 2 * bld
.dispatch_width() / 8;
1366 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1368 /* 2 floats per slot returned */
1369 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1370 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1376 * Computes 1 << x, given a D/UD register containing some value x.
1379 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1381 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1383 fs_reg result
= bld
.vgrf(x
.type
, 1);
1384 fs_reg one
= bld
.vgrf(x
.type
, 1);
1386 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1387 bld
.SHL(result
, one
, x
);
1392 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1394 assert(stage
== MESA_SHADER_GEOMETRY
);
1396 struct brw_gs_prog_data
*gs_prog_data
=
1397 (struct brw_gs_prog_data
*) prog_data
;
1399 /* We can only do EndPrimitive() functionality when the control data
1400 * consists of cut bits. Fortunately, the only time it isn't is when the
1401 * output type is points, in which case EndPrimitive() is a no-op.
1403 if (gs_prog_data
->control_data_format
!=
1404 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1408 /* Cut bits use one bit per vertex. */
1409 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1411 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1412 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1414 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1415 * vertex n, 0 otherwise. So all we need to do here is mark bit
1416 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1417 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1418 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1420 * Note that if EndPrimitive() is called before emitting any vertices, this
1421 * will cause us to set bit 31 of the control_data_bits register to 1.
1422 * That's fine because:
1424 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1425 * output, so the hardware will ignore cut bit 31.
1427 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1428 * last vertex, so setting cut bit 31 has no effect (since the primitive
1429 * is automatically ended when the GS terminates).
1431 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1432 * control_data_bits register to 0 when the first vertex is emitted.
1435 const fs_builder abld
= bld
.annotate("end primitive");
1437 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1438 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1439 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1440 fs_reg mask
= intexp2(abld
, prev_count
);
1441 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1442 * attention to the lower 5 bits of its second source argument, so on this
1443 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1444 * ((vertex_count - 1) % 32).
1446 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1450 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1452 assert(stage
== MESA_SHADER_GEOMETRY
);
1453 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1455 struct brw_gs_prog_data
*gs_prog_data
=
1456 (struct brw_gs_prog_data
*) prog_data
;
1458 const fs_builder abld
= bld
.annotate("emit control data bits");
1459 const fs_builder fwa_bld
= bld
.exec_all();
1461 /* We use a single UD register to accumulate control data bits (32 bits
1462 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1465 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1466 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1467 * use the Channel Mask phase to enable/disable which DWord within that
1468 * group to write. (Remember, different SIMD8 channels may have emitted
1469 * different numbers of vertices, so we may need per-slot offsets.)
1471 * Channel masking presents an annoying problem: we may have to replicate
1472 * the data up to 4 times:
1474 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1476 * To avoid penalizing shaders that emit a small number of vertices, we
1477 * can avoid these sometimes: if the size of the control data header is
1478 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1479 * land in the same 128-bit group, so we can skip per-slot offsets.
1481 * Similarly, if the control data header is <= 32 bits, there is only one
1482 * DWord, so we can skip channel masks.
1484 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1486 fs_reg channel_mask
, per_slot_offset
;
1488 if (gs_compile
->control_data_header_size_bits
> 32) {
1489 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1490 channel_mask
= vgrf(glsl_type::uint_type
);
1493 if (gs_compile
->control_data_header_size_bits
> 128) {
1494 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1495 per_slot_offset
= vgrf(glsl_type::uint_type
);
1498 /* Figure out which DWord we're trying to write to using the formula:
1500 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1502 * Since bits_per_vertex is a power of two, and is known at compile
1503 * time, this can be optimized to:
1505 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1507 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1508 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1509 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1510 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1511 unsigned log2_bits_per_vertex
=
1512 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1513 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1515 if (per_slot_offset
.file
!= BAD_FILE
) {
1516 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1517 * the appropriate OWord within the control data header.
1519 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1522 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1523 * write to the appropriate DWORD within the OWORD.
1525 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1526 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1527 channel_mask
= intexp2(fwa_bld
, channel
);
1528 /* Then the channel masks need to be in bits 23:16. */
1529 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1532 /* Store the control data bits in the message payload and send it. */
1534 if (channel_mask
.file
!= BAD_FILE
)
1535 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1536 if (per_slot_offset
.file
!= BAD_FILE
)
1539 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1540 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1542 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1543 if (per_slot_offset
.file
!= BAD_FILE
)
1544 sources
[i
++] = per_slot_offset
;
1545 if (channel_mask
.file
!= BAD_FILE
)
1546 sources
[i
++] = channel_mask
;
1548 sources
[i
++] = this->control_data_bits
;
1551 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1552 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1554 /* We need to increment Global Offset by 256-bits to make room for
1555 * Broadwell's extra "Vertex Count" payload at the beginning of the
1556 * URB entry. Since this is an OWord message, Global Offset is counted
1557 * in 128-bit units, so we must set it to 2.
1559 if (gs_prog_data
->static_vertex_count
== -1)
1564 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1567 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1569 /* Note: we are calling this *before* increasing vertex_count, so
1570 * this->vertex_count == vertex_count - 1 in the formula above.
1573 /* Stream mode uses 2 bits per vertex */
1574 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1576 /* Must be a valid stream */
1577 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1579 /* Control data bits are initialized to 0 so we don't have to set any
1580 * bits when sending vertices to stream 0.
1585 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1587 /* reg::sid = stream_id */
1588 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1589 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1591 /* reg:shift_count = 2 * (vertex_count - 1) */
1592 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1593 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1595 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1596 * attention to the lower 5 bits of its second source argument, so on this
1597 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1598 * stream_id << ((2 * (vertex_count - 1)) % 32).
1600 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1601 abld
.SHL(mask
, sid
, shift_count
);
1602 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1606 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1609 assert(stage
== MESA_SHADER_GEOMETRY
);
1611 struct brw_gs_prog_data
*gs_prog_data
=
1612 (struct brw_gs_prog_data
*) prog_data
;
1614 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1615 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1617 /* Haswell and later hardware ignores the "Render Stream Select" bits
1618 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1619 * and instead sends all primitives down the pipeline for rasterization.
1620 * If the SOL stage is enabled, "Render Stream Select" is honored and
1621 * primitives bound to non-zero streams are discarded after stream output.
1623 * Since the only purpose of primives sent to non-zero streams is to
1624 * be recorded by transform feedback, we can simply discard all geometry
1625 * bound to these streams when transform feedback is disabled.
1627 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1630 /* If we're outputting 32 control data bits or less, then we can wait
1631 * until the shader is over to output them all. Otherwise we need to
1632 * output them as we go. Now is the time to do it, since we're about to
1633 * output the vertex_count'th vertex, so it's guaranteed that the
1634 * control data bits associated with the (vertex_count - 1)th vertex are
1637 if (gs_compile
->control_data_header_size_bits
> 32) {
1638 const fs_builder abld
=
1639 bld
.annotate("emit vertex: emit control data bits");
1641 /* Only emit control data bits if we've finished accumulating a batch
1642 * of 32 bits. This is the case when:
1644 * (vertex_count * bits_per_vertex) % 32 == 0
1646 * (in other words, when the last 5 bits of vertex_count *
1647 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1648 * integer n (which is always the case, since bits_per_vertex is
1649 * always 1 or 2), this is equivalent to requiring that the last 5-n
1650 * bits of vertex_count are 0:
1652 * vertex_count & (2^(5-n) - 1) == 0
1654 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1657 * vertex_count & (32 / bits_per_vertex - 1) == 0
1659 * TODO: If vertex_count is an immediate, we could do some of this math
1660 * at compile time...
1663 abld
.AND(bld
.null_reg_d(), vertex_count
,
1664 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1665 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1667 abld
.IF(BRW_PREDICATE_NORMAL
);
1668 /* If vertex_count is 0, then no control data bits have been
1669 * accumulated yet, so we can skip emitting them.
1671 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1672 BRW_CONDITIONAL_NEQ
);
1673 abld
.IF(BRW_PREDICATE_NORMAL
);
1674 emit_gs_control_data_bits(vertex_count
);
1675 abld
.emit(BRW_OPCODE_ENDIF
);
1677 /* Reset control_data_bits to 0 so we can start accumulating a new
1680 * Note: in the case where vertex_count == 0, this neutralizes the
1681 * effect of any call to EndPrimitive() that the shader may have
1682 * made before outputting its first vertex.
1684 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1685 inst
->force_writemask_all
= true;
1686 abld
.emit(BRW_OPCODE_ENDIF
);
1689 emit_urb_writes(vertex_count
);
1691 /* In stream mode we have to set control data bits for all vertices
1692 * unless we have disabled control data bits completely (which we do
1693 * do for GL_POINTS outputs that don't use streams).
1695 if (gs_compile
->control_data_header_size_bits
> 0 &&
1696 gs_prog_data
->control_data_format
==
1697 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1698 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1703 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1704 const nir_src
&vertex_src
,
1705 unsigned base_offset
,
1706 const nir_src
&offset_src
,
1707 unsigned num_components
)
1709 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1711 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1712 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1713 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1715 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1716 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1717 * gl_PointSize is available as a GS input, however, so it must be that.
1719 const bool is_point_size
= (base_offset
== 0);
1721 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1722 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1723 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1724 vertex_const
->u
[0] * push_reg_count
;
1725 /* This input was pushed into registers. */
1726 if (is_point_size
) {
1727 /* gl_PointSize comes in .w */
1728 assert(imm_offset
== 0);
1729 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1731 for (unsigned i
= 0; i
< num_components
; i
++) {
1732 bld
.MOV(offset(dst
, bld
, i
),
1733 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1737 /* Resort to the pull model. Ensure the VUE handles are provided. */
1738 gs_prog_data
->base
.include_vue_handles
= true;
1740 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1744 /* The vertex index is constant; just select the proper URB handle. */
1746 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1747 BRW_REGISTER_TYPE_UD
);
1749 /* The vertex index is non-constant. We need to use indirect
1750 * addressing to fetch the proper URB handle.
1752 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1753 * indicating that channel <n> should read the handle from
1754 * DWord <n>. We convert that to bytes by multiplying by 4.
1756 * Next, we convert the vertex index to bytes by multiplying
1757 * by 32 (shifting by 5), and add the two together. This is
1758 * the final indirect byte offset.
1760 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1761 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1762 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1763 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1764 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1766 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1767 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1768 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1769 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1770 /* Convert vertex_index to bytes (multiply by 32) */
1771 bld
.SHL(vertex_offset_bytes
,
1772 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1774 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1776 /* Use first_icp_handle as the base offset. There is one register
1777 * of URB handles per vertex, so inform the register allocator that
1778 * we might read up to nir->info.gs.vertices_in registers.
1780 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1781 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1782 fs_reg(icp_offset_bytes
),
1783 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1788 /* Constant indexing - use global offset. */
1789 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1790 inst
->offset
= base_offset
+ offset_const
->u
[0];
1791 inst
->base_mrf
= -1;
1793 inst
->regs_written
= num_components
;
1795 /* Indirect indexing - use per-slot offsets as well. */
1796 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1797 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1798 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1800 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1801 inst
->offset
= base_offset
;
1802 inst
->base_mrf
= -1;
1804 inst
->regs_written
= num_components
;
1807 if (is_point_size
) {
1808 /* Read the whole VUE header (because of alignment) and read .w. */
1809 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1811 inst
->regs_written
= 4;
1812 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1818 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1820 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1821 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1824 /* The only constant offset we should find is 0. brw_nir.c's
1825 * add_const_offset_to_base() will fold other constant offsets
1826 * into instr->const_index[0].
1828 assert(const_value
->u
[0] == 0);
1832 return get_nir_src(*offset_src
);
1836 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1837 nir_intrinsic_instr
*instr
)
1839 assert(stage
== MESA_SHADER_VERTEX
);
1842 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1843 dest
= get_nir_dest(instr
->dest
);
1845 switch (instr
->intrinsic
) {
1846 case nir_intrinsic_load_vertex_id
:
1847 unreachable("should be lowered by lower_vertex_id()");
1849 case nir_intrinsic_load_vertex_id_zero_base
:
1850 case nir_intrinsic_load_base_vertex
:
1851 case nir_intrinsic_load_instance_id
:
1852 case nir_intrinsic_load_base_instance
:
1853 case nir_intrinsic_load_draw_id
: {
1854 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1855 fs_reg val
= nir_system_values
[sv
];
1856 assert(val
.file
!= BAD_FILE
);
1857 dest
.type
= val
.type
;
1863 nir_emit_intrinsic(bld
, instr
);
1869 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1870 nir_intrinsic_instr
*instr
)
1872 assert(stage
== MESA_SHADER_TESS_EVAL
);
1873 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1876 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1877 dest
= get_nir_dest(instr
->dest
);
1879 switch (instr
->intrinsic
) {
1880 case nir_intrinsic_load_primitive_id
:
1881 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1883 case nir_intrinsic_load_tess_coord
:
1884 /* gl_TessCoord is part of the payload in g1-3 */
1885 for (unsigned i
= 0; i
< 3; i
++) {
1886 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1890 case nir_intrinsic_load_tess_level_outer
:
1891 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1892 * appears as a push-model input. So, we can simply use the ATTR file
1893 * rather than issuing URB read messages. The data is stored in the
1894 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1897 switch (tes_prog_data
->domain
) {
1898 case BRW_TESS_DOMAIN_QUAD
:
1899 for (unsigned i
= 0; i
< 4; i
++)
1900 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1902 case BRW_TESS_DOMAIN_TRI
:
1903 for (unsigned i
= 0; i
< 3; i
++)
1904 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1906 case BRW_TESS_DOMAIN_ISOLINE
:
1907 for (unsigned i
= 0; i
< 2; i
++)
1908 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1913 case nir_intrinsic_load_tess_level_inner
:
1914 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1915 * appears as a push-model input. So, we can simply use the ATTR file
1916 * rather than issuing URB read messages.
1918 switch (tes_prog_data
->domain
) {
1919 case BRW_TESS_DOMAIN_QUAD
:
1920 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1921 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1923 case BRW_TESS_DOMAIN_TRI
:
1924 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1926 case BRW_TESS_DOMAIN_ISOLINE
:
1927 /* ignore - value is undefined */
1932 case nir_intrinsic_load_input
:
1933 case nir_intrinsic_load_per_vertex_input
: {
1934 fs_reg indirect_offset
= get_indirect_offset(instr
);
1935 unsigned imm_offset
= instr
->const_index
[0];
1938 if (indirect_offset
.file
== BAD_FILE
) {
1939 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1940 * which is 16 registers (since each holds 2 vec4 slots).
1942 const unsigned max_push_slots
= 32;
1943 if (imm_offset
< max_push_slots
) {
1944 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1945 for (int i
= 0; i
< instr
->num_components
; i
++) {
1946 bld
.MOV(offset(dest
, bld
, i
),
1947 component(src
, 4 * (imm_offset
% 2) + i
));
1949 tes_prog_data
->base
.urb_read_length
=
1950 MAX2(tes_prog_data
->base
.urb_read_length
,
1951 DIV_ROUND_UP(imm_offset
+ 1, 2));
1953 /* Replicate the patch handle to all enabled channels */
1954 const fs_reg srcs
[] = {
1955 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1957 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1958 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1960 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1962 inst
->offset
= imm_offset
;
1963 inst
->base_mrf
= -1;
1964 inst
->regs_written
= instr
->num_components
;
1967 /* Indirect indexing - use per-slot offsets as well. */
1968 const fs_reg srcs
[] = {
1969 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1972 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1973 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1975 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1977 inst
->offset
= imm_offset
;
1978 inst
->base_mrf
= -1;
1979 inst
->regs_written
= instr
->num_components
;
1984 nir_emit_intrinsic(bld
, instr
);
1990 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1991 nir_intrinsic_instr
*instr
)
1993 assert(stage
== MESA_SHADER_GEOMETRY
);
1994 fs_reg indirect_offset
;
1997 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1998 dest
= get_nir_dest(instr
->dest
);
2000 switch (instr
->intrinsic
) {
2001 case nir_intrinsic_load_primitive_id
:
2002 assert(stage
== MESA_SHADER_GEOMETRY
);
2003 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2004 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2005 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2008 case nir_intrinsic_load_input
:
2009 unreachable("load_input intrinsics are invalid for the GS stage");
2011 case nir_intrinsic_load_per_vertex_input
:
2012 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2013 instr
->src
[1], instr
->num_components
);
2016 case nir_intrinsic_emit_vertex_with_counter
:
2017 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2020 case nir_intrinsic_end_primitive_with_counter
:
2021 emit_gs_end_primitive(instr
->src
[0]);
2024 case nir_intrinsic_set_vertex_count
:
2025 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2028 case nir_intrinsic_load_invocation_id
: {
2029 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2030 assert(val
.file
!= BAD_FILE
);
2031 dest
.type
= val
.type
;
2037 nir_emit_intrinsic(bld
, instr
);
2043 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2044 nir_intrinsic_instr
*instr
)
2046 assert(stage
== MESA_SHADER_FRAGMENT
);
2047 struct brw_wm_prog_data
*wm_prog_data
=
2048 (struct brw_wm_prog_data
*) prog_data
;
2051 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2052 dest
= get_nir_dest(instr
->dest
);
2054 switch (instr
->intrinsic
) {
2055 case nir_intrinsic_load_front_face
:
2056 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2057 *emit_frontfacing_interpolation());
2060 case nir_intrinsic_load_sample_pos
: {
2061 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2062 assert(sample_pos
.file
!= BAD_FILE
);
2063 dest
.type
= sample_pos
.type
;
2064 bld
.MOV(dest
, sample_pos
);
2065 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2069 case nir_intrinsic_load_helper_invocation
:
2070 case nir_intrinsic_load_sample_mask_in
:
2071 case nir_intrinsic_load_sample_id
: {
2072 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2073 fs_reg val
= nir_system_values
[sv
];
2074 assert(val
.file
!= BAD_FILE
);
2075 dest
.type
= val
.type
;
2080 case nir_intrinsic_discard
:
2081 case nir_intrinsic_discard_if
: {
2082 /* We track our discarded pixels in f0.1. By predicating on it, we can
2083 * update just the flag bits that aren't yet discarded. If there's no
2084 * condition, we emit a CMP of g0 != g0, so all currently executing
2085 * channels will get turned off.
2088 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2089 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2090 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2092 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2093 BRW_REGISTER_TYPE_UW
));
2094 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2096 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2097 cmp
->flag_subreg
= 1;
2099 if (devinfo
->gen
>= 6) {
2100 emit_discard_jump();
2105 case nir_intrinsic_interp_var_at_centroid
:
2106 case nir_intrinsic_interp_var_at_sample
:
2107 case nir_intrinsic_interp_var_at_offset
: {
2108 /* Handle ARB_gpu_shader5 interpolation intrinsics
2110 * It's worth a quick word of explanation as to why we handle the full
2111 * variable-based interpolation intrinsic rather than a lowered version
2112 * with like we do for other inputs. We have to do that because the way
2113 * we set up inputs doesn't allow us to use the already setup inputs for
2114 * interpolation. At the beginning of the shader, we go through all of
2115 * the input variables and do the initial interpolation and put it in
2116 * the nir_inputs array based on its location as determined in
2117 * nir_lower_io. If the input isn't used, dead code cleans up and
2118 * everything works fine. However, when we get to the ARB_gpu_shader5
2119 * interpolation intrinsics, we need to reinterpolate the input
2120 * differently. If we used an intrinsic that just had an index it would
2121 * only give us the offset into the nir_inputs array. However, this is
2122 * useless because that value is post-interpolation and we need
2123 * pre-interpolation. In order to get the actual location of the bits
2124 * we get from the vertex fetching hardware, we need the variable.
2126 wm_prog_data
->pulls_bary
= true;
2128 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2129 const glsl_interp_qualifier interpolation
=
2130 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2132 switch (instr
->intrinsic
) {
2133 case nir_intrinsic_interp_var_at_centroid
:
2134 emit_pixel_interpolater_send(bld
,
2135 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2142 case nir_intrinsic_interp_var_at_sample
: {
2143 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2146 unsigned msg_data
= const_sample
->i
[0] << 4;
2148 emit_pixel_interpolater_send(bld
,
2149 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2152 brw_imm_ud(msg_data
),
2155 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2156 BRW_REGISTER_TYPE_UD
);
2158 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2159 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2160 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2161 bld
.exec_all().group(1, 0)
2162 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2163 emit_pixel_interpolater_send(bld
,
2164 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2170 /* Make a loop that sends a message to the pixel interpolater
2171 * for the sample number in each live channel. If there are
2172 * multiple channels with the same sample number then these
2173 * will be handled simultaneously with a single interation of
2176 bld
.emit(BRW_OPCODE_DO
);
2178 /* Get the next live sample number into sample_id_reg */
2179 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2181 /* Set the flag register so that we can perform the send
2182 * message on all channels that have the same sample number
2184 bld
.CMP(bld
.null_reg_ud(),
2185 sample_src
, sample_id
,
2186 BRW_CONDITIONAL_EQ
);
2187 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2188 bld
.exec_all().group(1, 0)
2189 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2191 emit_pixel_interpolater_send(bld
,
2192 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2197 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2199 /* Continue the loop if there are any live channels left */
2200 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2202 bld
.emit(BRW_OPCODE_WHILE
));
2209 case nir_intrinsic_interp_var_at_offset
: {
2210 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2213 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2214 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2216 emit_pixel_interpolater_send(bld
,
2217 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2220 brw_imm_ud(off_x
| (off_y
<< 4)),
2223 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2224 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2225 BRW_REGISTER_TYPE_F
);
2226 for (int i
= 0; i
< 2; i
++) {
2227 fs_reg temp
= vgrf(glsl_type::float_type
);
2228 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2229 fs_reg itemp
= vgrf(glsl_type::int_type
);
2230 bld
.MOV(itemp
, temp
); /* float to int */
2232 /* Clamp the upper end of the range to +7/16.
2233 * ARB_gpu_shader5 requires that we support a maximum offset
2234 * of +0.5, which isn't representable in a S0.4 value -- if
2235 * we didn't clamp it, we'd end up with -8/16, which is the
2236 * opposite of what the shader author wanted.
2238 * This is legal due to ARB_gpu_shader5's quantization
2241 * "Not all values of <offset> may be supported; x and y
2242 * offsets may be rounded to fixed-point values with the
2243 * number of fraction bits given by the
2244 * implementation-dependent constant
2245 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2247 set_condmod(BRW_CONDITIONAL_L
,
2248 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2251 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2252 emit_pixel_interpolater_send(bld
,
2263 unreachable("Invalid intrinsic");
2266 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2267 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2268 src
.type
= dest
.type
;
2270 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2271 dest
= offset(dest
, bld
, 1);
2276 nir_emit_intrinsic(bld
, instr
);
2282 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2283 nir_intrinsic_instr
*instr
)
2285 assert(stage
== MESA_SHADER_COMPUTE
);
2286 struct brw_cs_prog_data
*cs_prog_data
=
2287 (struct brw_cs_prog_data
*) prog_data
;
2290 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2291 dest
= get_nir_dest(instr
->dest
);
2293 switch (instr
->intrinsic
) {
2294 case nir_intrinsic_barrier
:
2296 cs_prog_data
->uses_barrier
= true;
2299 case nir_intrinsic_load_local_invocation_id
:
2300 case nir_intrinsic_load_work_group_id
: {
2301 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2302 fs_reg val
= nir_system_values
[sv
];
2303 assert(val
.file
!= BAD_FILE
);
2304 dest
.type
= val
.type
;
2305 for (unsigned i
= 0; i
< 3; i
++)
2306 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2310 case nir_intrinsic_load_num_work_groups
: {
2311 const unsigned surface
=
2312 cs_prog_data
->binding_table
.work_groups_start
;
2314 cs_prog_data
->uses_num_work_groups
= true;
2316 fs_reg surf_index
= brw_imm_ud(surface
);
2317 brw_mark_surface_used(prog_data
, surface
);
2319 /* Read the 3 GLuint components of gl_NumWorkGroups */
2320 for (unsigned i
= 0; i
< 3; i
++) {
2321 fs_reg read_result
=
2322 emit_untyped_read(bld
, surf_index
,
2324 1 /* dims */, 1 /* size */,
2325 BRW_PREDICATE_NONE
);
2326 read_result
.type
= dest
.type
;
2327 bld
.MOV(dest
, read_result
);
2328 dest
= offset(dest
, bld
, 1);
2333 case nir_intrinsic_shared_atomic_add
:
2334 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2336 case nir_intrinsic_shared_atomic_imin
:
2337 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2339 case nir_intrinsic_shared_atomic_umin
:
2340 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2342 case nir_intrinsic_shared_atomic_imax
:
2343 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2345 case nir_intrinsic_shared_atomic_umax
:
2346 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2348 case nir_intrinsic_shared_atomic_and
:
2349 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2351 case nir_intrinsic_shared_atomic_or
:
2352 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2354 case nir_intrinsic_shared_atomic_xor
:
2355 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2357 case nir_intrinsic_shared_atomic_exchange
:
2358 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2360 case nir_intrinsic_shared_atomic_comp_swap
:
2361 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2364 case nir_intrinsic_load_shared
: {
2365 assert(devinfo
->gen
>= 7);
2367 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2369 /* Get the offset to read from */
2371 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2373 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2375 offset_reg
= vgrf(glsl_type::uint_type
);
2377 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2378 brw_imm_ud(instr
->const_index
[0]));
2381 /* Read the vector */
2382 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2384 instr
->num_components
,
2385 BRW_PREDICATE_NONE
);
2386 read_result
.type
= dest
.type
;
2387 for (int i
= 0; i
< instr
->num_components
; i
++)
2388 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2393 case nir_intrinsic_store_shared
: {
2394 assert(devinfo
->gen
>= 7);
2397 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2400 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2403 unsigned writemask
= instr
->const_index
[1];
2405 /* Combine groups of consecutive enabled channels in one write
2406 * message. We use ffs to find the first enabled channel and then ffs on
2407 * the bit-inverse, down-shifted writemask to determine the length of
2408 * the block of enabled bits.
2411 unsigned first_component
= ffs(writemask
) - 1;
2412 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2415 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2417 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2418 4 * first_component
);
2420 offset_reg
= vgrf(glsl_type::uint_type
);
2422 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2423 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2426 emit_untyped_write(bld
, surf_index
, offset_reg
,
2427 offset(val_reg
, bld
, first_component
),
2428 1 /* dims */, length
,
2429 BRW_PREDICATE_NONE
);
2431 /* Clear the bits in the writemask that we just wrote, then try
2432 * again to see if more channels are left.
2434 writemask
&= (15 << (first_component
+ length
));
2441 nir_emit_intrinsic(bld
, instr
);
2447 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2450 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2451 dest
= get_nir_dest(instr
->dest
);
2453 switch (instr
->intrinsic
) {
2454 case nir_intrinsic_atomic_counter_inc
:
2455 case nir_intrinsic_atomic_counter_dec
:
2456 case nir_intrinsic_atomic_counter_read
: {
2457 using namespace surface_access
;
2459 /* Get the arguments of the atomic intrinsic. */
2460 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2461 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2462 instr
->const_index
[0]);
2465 /* Emit a surface read or atomic op. */
2466 switch (instr
->intrinsic
) {
2467 case nir_intrinsic_atomic_counter_read
:
2468 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2471 case nir_intrinsic_atomic_counter_inc
:
2472 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2473 fs_reg(), 1, 1, BRW_AOP_INC
);
2476 case nir_intrinsic_atomic_counter_dec
:
2477 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2478 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2482 unreachable("Unreachable");
2485 /* Assign the result. */
2486 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2488 /* Mark the surface as used. */
2489 brw_mark_surface_used(stage_prog_data
, surface
);
2493 case nir_intrinsic_image_load
:
2494 case nir_intrinsic_image_store
:
2495 case nir_intrinsic_image_atomic_add
:
2496 case nir_intrinsic_image_atomic_min
:
2497 case nir_intrinsic_image_atomic_max
:
2498 case nir_intrinsic_image_atomic_and
:
2499 case nir_intrinsic_image_atomic_or
:
2500 case nir_intrinsic_image_atomic_xor
:
2501 case nir_intrinsic_image_atomic_exchange
:
2502 case nir_intrinsic_image_atomic_comp_swap
: {
2503 using namespace image_access
;
2505 /* Get the referenced image variable and type. */
2506 const nir_variable
*var
= instr
->variables
[0]->var
;
2507 const glsl_type
*type
= var
->type
->without_array();
2508 const brw_reg_type base_type
= get_image_base_type(type
);
2510 /* Get some metadata from the image intrinsic. */
2511 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2512 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2513 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2514 const mesa_format format
=
2515 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2516 _mesa_get_shader_image_format(var
->data
.image
.format
));
2518 /* Get the arguments of the image intrinsic. */
2519 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2520 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2521 BRW_REGISTER_TYPE_UD
);
2522 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2523 retype(get_nir_src(instr
->src
[2]), base_type
) :
2525 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2526 retype(get_nir_src(instr
->src
[3]), base_type
) :
2530 /* Emit an image load, store or atomic op. */
2531 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2532 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2534 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2535 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2538 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2539 surf_dims
, arr_dims
, info
->dest_components
,
2540 get_image_atomic_op(instr
->intrinsic
, type
));
2542 /* Assign the result. */
2543 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2544 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2545 offset(tmp
, bld
, c
));
2549 case nir_intrinsic_memory_barrier_atomic_counter
:
2550 case nir_intrinsic_memory_barrier_buffer
:
2551 case nir_intrinsic_memory_barrier_image
:
2552 case nir_intrinsic_memory_barrier
: {
2553 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2554 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2559 case nir_intrinsic_group_memory_barrier
:
2560 case nir_intrinsic_memory_barrier_shared
:
2561 /* We treat these workgroup-level barriers as no-ops. This should be
2562 * safe at present and as long as:
2564 * - Memory access instructions are not subsequently reordered by the
2565 * compiler back-end.
2567 * - All threads from a given compute shader workgroup fit within a
2568 * single subslice and therefore talk to the same HDC shared unit
2569 * what supposedly guarantees ordering and coherency between threads
2570 * from the same workgroup. This may change in the future when we
2571 * start splitting workgroups across multiple subslices.
2573 * - The context is not in fault-and-stream mode, which could cause
2574 * memory transactions (including to SLM) prior to the barrier to be
2575 * replayed after the barrier if a pagefault occurs. This shouldn't
2576 * be a problem up to and including SKL because fault-and-stream is
2577 * not usable due to hardware issues, but that's likely to change in
2582 case nir_intrinsic_shader_clock
: {
2583 /* We cannot do anything if there is an event, so ignore it for now */
2584 fs_reg shader_clock
= get_timestamp(bld
);
2585 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2587 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2591 case nir_intrinsic_image_size
: {
2592 /* Get the referenced image variable and type. */
2593 const nir_variable
*var
= instr
->variables
[0]->var
;
2594 const glsl_type
*type
= var
->type
->without_array();
2596 /* Get the size of the image. */
2597 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2598 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2600 /* For 1DArray image types, the array index is stored in the Z component.
2601 * Fix this by swizzling the Z component to the Y component.
2603 const bool is_1d_array_image
=
2604 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2605 type
->sampler_array
;
2607 /* For CubeArray images, we should count the number of cubes instead
2608 * of the number of faces. Fix it by dividing the (Z component) by 6.
2610 const bool is_cube_array_image
=
2611 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2612 type
->sampler_array
;
2614 /* Copy all the components. */
2615 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2616 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2617 if ((int)c
>= type
->coordinate_components()) {
2618 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2620 } else if (c
== 1 && is_1d_array_image
) {
2621 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2622 offset(size
, bld
, 2));
2623 } else if (c
== 2 && is_cube_array_image
) {
2624 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2625 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2626 offset(size
, bld
, c
), brw_imm_d(6));
2628 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2629 offset(size
, bld
, c
));
2636 case nir_intrinsic_image_samples
:
2637 /* The driver does not support multi-sampled images. */
2638 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2641 case nir_intrinsic_load_uniform
: {
2642 /* Offsets are in bytes but they should always be multiples of 4 */
2643 assert(instr
->const_index
[0] % 4 == 0);
2645 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2647 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2649 /* Offsets are in bytes but they should always be multiples of 4 */
2650 assert(const_offset
->u
[0] % 4 == 0);
2651 src
.reg_offset
= const_offset
->u
[0] / 4;
2653 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2654 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2657 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
2658 BRW_REGISTER_TYPE_UD
);
2660 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
2661 * go past the end of the uniform. In order to keep the n'th
2662 * component from running past, we subtract off the size of all but
2663 * one component of the vector.
2665 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
2666 unsigned read_size
= instr
->const_index
[1] -
2667 (instr
->num_components
- 1) * 4;
2669 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2670 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
2671 offset(dest
, bld
, j
), offset(src
, bld
, j
),
2672 indirect
, brw_imm_ud(read_size
));
2678 case nir_intrinsic_load_ubo
: {
2679 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2683 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2685 surf_index
= brw_imm_ud(index
);
2686 brw_mark_surface_used(prog_data
, index
);
2688 /* The block index is not a constant. Evaluate the index expression
2689 * per-channel and add the base UBO index; we have to select a value
2690 * from any live channel.
2692 surf_index
= vgrf(glsl_type::uint_type
);
2693 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2694 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2695 surf_index
= bld
.emit_uniformize(surf_index
);
2697 /* Assume this may touch any UBO. It would be nice to provide
2698 * a tighter bound, but the array information is already lowered away.
2700 brw_mark_surface_used(prog_data
,
2701 stage_prog_data
->binding_table
.ubo_start
+
2702 nir
->info
.num_ubos
- 1);
2705 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2706 if (const_offset
== NULL
) {
2707 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2708 BRW_REGISTER_TYPE_D
);
2710 for (int i
= 0; i
< instr
->num_components
; i
++)
2711 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2712 base_offset
, i
* 4);
2714 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2715 packed_consts
.type
= dest
.type
;
2717 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2718 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2719 surf_index
, const_offset_reg
);
2721 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2722 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2724 /* The std140 packing rules don't allow vectors to cross 16-byte
2725 * boundaries, and a reg is 32 bytes.
2727 assert(packed_consts
.subreg_offset
< 32);
2729 bld
.MOV(dest
, packed_consts
);
2730 dest
= offset(dest
, bld
, 1);
2736 case nir_intrinsic_load_ssbo
: {
2737 assert(devinfo
->gen
>= 7);
2739 nir_const_value
*const_uniform_block
=
2740 nir_src_as_const_value(instr
->src
[0]);
2743 if (const_uniform_block
) {
2744 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2745 const_uniform_block
->u
[0];
2746 surf_index
= brw_imm_ud(index
);
2747 brw_mark_surface_used(prog_data
, index
);
2749 surf_index
= vgrf(glsl_type::uint_type
);
2750 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2751 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2753 /* Assume this may touch any UBO. It would be nice to provide
2754 * a tighter bound, but the array information is already lowered away.
2756 brw_mark_surface_used(prog_data
,
2757 stage_prog_data
->binding_table
.ssbo_start
+
2758 nir
->info
.num_ssbos
- 1);
2762 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2764 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2766 offset_reg
= get_nir_src(instr
->src
[1]);
2769 /* Read the vector */
2770 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2772 instr
->num_components
,
2773 BRW_PREDICATE_NONE
);
2774 read_result
.type
= dest
.type
;
2775 for (int i
= 0; i
< instr
->num_components
; i
++)
2776 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2781 case nir_intrinsic_load_input
: {
2783 if (stage
== MESA_SHADER_VERTEX
) {
2784 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2786 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2787 instr
->const_index
[0]);
2790 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2791 assert(const_offset
&& "Indirect input loads not allowed");
2792 src
= offset(src
, bld
, const_offset
->u
[0]);
2794 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2795 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2800 case nir_intrinsic_store_ssbo
: {
2801 assert(devinfo
->gen
>= 7);
2805 nir_const_value
*const_uniform_block
=
2806 nir_src_as_const_value(instr
->src
[1]);
2807 if (const_uniform_block
) {
2808 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2809 const_uniform_block
->u
[0];
2810 surf_index
= brw_imm_ud(index
);
2811 brw_mark_surface_used(prog_data
, index
);
2813 surf_index
= vgrf(glsl_type::uint_type
);
2814 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2815 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2817 brw_mark_surface_used(prog_data
,
2818 stage_prog_data
->binding_table
.ssbo_start
+
2819 nir
->info
.num_ssbos
- 1);
2823 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2826 unsigned writemask
= instr
->const_index
[0];
2828 /* Combine groups of consecutive enabled channels in one write
2829 * message. We use ffs to find the first enabled channel and then ffs on
2830 * the bit-inverse, down-shifted writemask to determine the length of
2831 * the block of enabled bits.
2834 unsigned first_component
= ffs(writemask
) - 1;
2835 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2838 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2840 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2842 offset_reg
= vgrf(glsl_type::uint_type
);
2844 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2845 brw_imm_ud(4 * first_component
));
2848 emit_untyped_write(bld
, surf_index
, offset_reg
,
2849 offset(val_reg
, bld
, first_component
),
2850 1 /* dims */, length
,
2851 BRW_PREDICATE_NONE
);
2853 /* Clear the bits in the writemask that we just wrote, then try
2854 * again to see if more channels are left.
2856 writemask
&= (15 << (first_component
+ length
));
2861 case nir_intrinsic_store_output
: {
2862 fs_reg src
= get_nir_src(instr
->src
[0]);
2863 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2864 instr
->const_index
[0]);
2866 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2867 assert(const_offset
&& "Indirect output stores not allowed");
2868 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2870 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2871 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2876 case nir_intrinsic_ssbo_atomic_add
:
2877 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2879 case nir_intrinsic_ssbo_atomic_imin
:
2880 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2882 case nir_intrinsic_ssbo_atomic_umin
:
2883 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2885 case nir_intrinsic_ssbo_atomic_imax
:
2886 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2888 case nir_intrinsic_ssbo_atomic_umax
:
2889 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2891 case nir_intrinsic_ssbo_atomic_and
:
2892 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2894 case nir_intrinsic_ssbo_atomic_or
:
2895 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2897 case nir_intrinsic_ssbo_atomic_xor
:
2898 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2900 case nir_intrinsic_ssbo_atomic_exchange
:
2901 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2903 case nir_intrinsic_ssbo_atomic_comp_swap
:
2904 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2907 case nir_intrinsic_get_buffer_size
: {
2908 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2909 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2910 int reg_width
= dispatch_width
/ 8;
2913 fs_reg source
= brw_imm_d(0);
2915 int mlen
= 1 * reg_width
;
2917 /* A resinfo's sampler message is used to get the buffer size.
2918 * The SIMD8's writeback message consists of four registers and
2919 * SIMD16's writeback message consists of 8 destination registers
2920 * (two per each component), although we are only interested on the
2921 * first component, where resinfo returns the buffer size for
2924 int regs_written
= 4 * mlen
;
2925 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2926 BRW_REGISTER_TYPE_UD
);
2927 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2928 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2929 BRW_REGISTER_TYPE_UD
);
2930 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2931 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2932 src_payload
, brw_imm_ud(index
));
2933 inst
->header_size
= 0;
2935 inst
->regs_written
= regs_written
;
2937 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2939 brw_mark_surface_used(prog_data
, index
);
2944 unreachable("unknown intrinsic");
2949 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2950 int op
, nir_intrinsic_instr
*instr
)
2953 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2954 dest
= get_nir_dest(instr
->dest
);
2957 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2958 if (const_surface
) {
2959 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2960 const_surface
->u
[0];
2961 surface
= brw_imm_ud(surf_index
);
2962 brw_mark_surface_used(prog_data
, surf_index
);
2964 surface
= vgrf(glsl_type::uint_type
);
2965 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2966 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2968 /* Assume this may touch any SSBO. This is the same we do for other
2969 * UBO/SSBO accesses with non-constant surface.
2971 brw_mark_surface_used(prog_data
,
2972 stage_prog_data
->binding_table
.ssbo_start
+
2973 nir
->info
.num_ssbos
- 1);
2976 fs_reg offset
= get_nir_src(instr
->src
[1]);
2977 fs_reg data1
= get_nir_src(instr
->src
[2]);
2979 if (op
== BRW_AOP_CMPWR
)
2980 data2
= get_nir_src(instr
->src
[3]);
2982 /* Emit the actual atomic operation operation */
2984 fs_reg atomic_result
=
2985 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2987 1 /* dims */, 1 /* rsize */,
2989 BRW_PREDICATE_NONE
);
2990 dest
.type
= atomic_result
.type
;
2991 bld
.MOV(dest
, atomic_result
);
2995 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2996 int op
, nir_intrinsic_instr
*instr
)
2999 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3000 dest
= get_nir_dest(instr
->dest
);
3002 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3003 fs_reg offset
= get_nir_src(instr
->src
[0]);
3004 fs_reg data1
= get_nir_src(instr
->src
[1]);
3006 if (op
== BRW_AOP_CMPWR
)
3007 data2
= get_nir_src(instr
->src
[2]);
3009 /* Emit the actual atomic operation operation */
3011 fs_reg atomic_result
=
3012 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
3014 1 /* dims */, 1 /* rsize */,
3016 BRW_PREDICATE_NONE
);
3017 dest
.type
= atomic_result
.type
;
3018 bld
.MOV(dest
, atomic_result
);
3022 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3024 unsigned texture
= instr
->texture_index
;
3025 unsigned sampler
= instr
->sampler_index
;
3026 fs_reg
texture_reg(brw_imm_ud(texture
));
3027 fs_reg
sampler_reg(brw_imm_ud(sampler
));
3029 int gather_component
= instr
->component
;
3031 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3034 int lod_components
= 0;
3035 int UNUSED offset_components
= 0;
3037 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
3039 /* Our hardware requires a LOD for buffer textures */
3040 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3043 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3044 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3045 switch (instr
->src
[i
].src_type
) {
3046 case nir_tex_src_bias
:
3047 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3049 case nir_tex_src_comparitor
:
3050 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
3052 case nir_tex_src_coord
:
3053 switch (instr
->op
) {
3055 case nir_texop_txf_ms
:
3056 case nir_texop_samples_identical
:
3057 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
3060 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
3064 case nir_tex_src_ddx
:
3065 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3066 lod_components
= nir_tex_instr_src_size(instr
, i
);
3068 case nir_tex_src_ddy
:
3069 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
3071 case nir_tex_src_lod
:
3072 switch (instr
->op
) {
3074 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
3077 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
3080 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
3084 case nir_tex_src_ms_index
:
3085 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
3087 case nir_tex_src_offset
:
3088 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
3089 if (instr
->is_array
)
3090 offset_components
= instr
->coord_components
- 1;
3092 offset_components
= instr
->coord_components
;
3094 case nir_tex_src_projector
:
3095 unreachable("should be lowered");
3097 case nir_tex_src_texture_offset
: {
3098 /* Figure out the highest possible texture index and mark it as used */
3099 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3100 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3101 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3103 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3105 brw_mark_surface_used(prog_data
, max_used
);
3107 /* Emit code to evaluate the actual indexing expression */
3108 texture_reg
= vgrf(glsl_type::uint_type
);
3109 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3110 texture_reg
= bld
.emit_uniformize(texture_reg
);
3114 case nir_tex_src_sampler_offset
: {
3115 /* Emit code to evaluate the actual indexing expression */
3116 sampler_reg
= vgrf(glsl_type::uint_type
);
3117 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3118 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3123 unreachable("unknown texture source");
3127 if (instr
->op
== nir_texop_txf_ms
||
3128 instr
->op
== nir_texop_samples_identical
) {
3129 if (devinfo
->gen
>= 7 &&
3130 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3131 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3133 mcs
= brw_imm_ud(0u);
3137 for (unsigned i
= 0; i
< 3; i
++) {
3138 if (instr
->const_offset
[i
] != 0) {
3139 assert(offset_components
== 0);
3140 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
3145 enum glsl_base_type dest_base_type
=
3146 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3148 const glsl_type
*dest_type
=
3149 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3152 ir_texture_opcode op
;
3153 switch (instr
->op
) {
3154 case nir_texop_lod
: op
= ir_lod
; break;
3155 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3156 case nir_texop_tex
: op
= ir_tex
; break;
3157 case nir_texop_tg4
: op
= ir_tg4
; break;
3158 case nir_texop_txb
: op
= ir_txb
; break;
3159 case nir_texop_txd
: op
= ir_txd
; break;
3160 case nir_texop_txf
: op
= ir_txf
; break;
3161 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3162 case nir_texop_txl
: op
= ir_txl
; break;
3163 case nir_texop_txs
: op
= ir_txs
; break;
3164 case nir_texop_texture_samples
: {
3165 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3166 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3167 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3168 texture_reg
, texture_reg
);
3170 inst
->header_size
= 1;
3171 inst
->base_mrf
= -1;
3174 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3176 unreachable("unknown texture opcode");
3179 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3180 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3181 tex_offset
, mcs
, gather_component
,
3182 is_cube_array
, texture
, texture_reg
, sampler
, sampler_reg
);
3184 fs_reg dest
= get_nir_dest(instr
->dest
);
3185 dest
.type
= this->result
.type
;
3186 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3187 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3188 dest
, this->result
),
3189 (1 << num_components
) - 1);
3193 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3195 switch (instr
->type
) {
3196 case nir_jump_break
:
3197 bld
.emit(BRW_OPCODE_BREAK
);
3199 case nir_jump_continue
:
3200 bld
.emit(BRW_OPCODE_CONTINUE
);
3202 case nir_jump_return
:
3204 unreachable("unknown jump");