2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
66 var
->data
.origin_upper_left
);
67 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
69 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
70 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
71 reg
.type
= BRW_REGISTER_TYPE_D
;
72 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
73 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
74 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
75 reg
.type
= BRW_REGISTER_TYPE_D
;
76 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
78 int location
= var
->data
.location
;
79 emit_general_interpolation(&input
, var
->name
, var
->type
,
80 (glsl_interp_qualifier
) var
->data
.interpolation
,
81 &location
, var
->data
.centroid
,
88 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
89 const glsl_type
*type
,
92 if (type
->is_array() || type
->is_matrix()) {
93 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
94 const unsigned length
= glsl_get_length(type
);
96 for (unsigned i
= 0; i
< length
; i
++) {
97 nir_setup_single_output_varying(reg
, elem_type
, location
);
99 } else if (type
->is_record()) {
100 for (unsigned i
= 0; i
< type
->length
; i
++) {
101 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
102 nir_setup_single_output_varying(reg
, field_type
, location
);
105 assert(type
->is_scalar() || type
->is_vector());
106 this->outputs
[*location
] = *reg
;
107 this->output_components
[*location
] = type
->vector_elements
;
108 *reg
= offset(*reg
, bld
, 4);
114 fs_visitor::nir_setup_outputs()
116 if (stage
== MESA_SHADER_TESS_CTRL
)
119 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
121 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
123 nir_foreach_variable(var
, &nir
->outputs
) {
124 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
127 case MESA_SHADER_VERTEX
:
128 case MESA_SHADER_TESS_EVAL
:
129 case MESA_SHADER_GEOMETRY
: {
130 unsigned location
= var
->data
.location
;
131 nir_setup_single_output_varying(®
, var
->type
, &location
);
134 case MESA_SHADER_FRAGMENT
:
135 if (key
->force_dual_color_blend
&&
136 var
->data
.location
== FRAG_RESULT_DATA1
) {
137 this->dual_src_output
= reg
;
138 this->do_dual_src
= true;
139 } else if (var
->data
.index
> 0) {
140 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
141 assert(var
->data
.index
== 1);
142 this->dual_src_output
= reg
;
143 this->do_dual_src
= true;
144 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
145 /* Writing gl_FragColor outputs to all color regions. */
146 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
147 this->outputs
[i
] = reg
;
148 this->output_components
[i
] = 4;
150 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
151 this->frag_depth
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
153 this->frag_stencil
= reg
;
154 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
155 this->sample_mask
= reg
;
157 int vector_elements
= var
->type
->without_array()->vector_elements
;
159 /* gl_FragData or a user-defined FS output */
160 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
161 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
163 /* General color output. */
164 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
165 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
166 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
167 this->output_components
[output
] = vector_elements
;
172 unreachable("unhandled shader stage");
178 fs_visitor::nir_setup_uniforms()
180 if (dispatch_width
!= 8)
183 uniforms
= nir
->num_uniforms
/ 4;
187 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
191 nir_foreach_instr(instr
, block
) {
192 if (instr
->type
!= nir_instr_type_intrinsic
)
195 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
196 switch (intrin
->intrinsic
) {
197 case nir_intrinsic_load_vertex_id
:
198 unreachable("should be lowered by lower_vertex_id().");
200 case nir_intrinsic_load_vertex_id_zero_base
:
201 assert(v
->stage
== MESA_SHADER_VERTEX
);
202 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
203 if (reg
->file
== BAD_FILE
)
204 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
207 case nir_intrinsic_load_base_vertex
:
208 assert(v
->stage
== MESA_SHADER_VERTEX
);
209 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
210 if (reg
->file
== BAD_FILE
)
211 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
214 case nir_intrinsic_load_instance_id
:
215 assert(v
->stage
== MESA_SHADER_VERTEX
);
216 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
217 if (reg
->file
== BAD_FILE
)
218 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
221 case nir_intrinsic_load_base_instance
:
222 assert(v
->stage
== MESA_SHADER_VERTEX
);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
228 case nir_intrinsic_load_draw_id
:
229 assert(v
->stage
== MESA_SHADER_VERTEX
);
230 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
231 if (reg
->file
== BAD_FILE
)
232 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
235 case nir_intrinsic_load_invocation_id
:
236 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
238 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
240 if (reg
->file
== BAD_FILE
) {
241 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
242 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
243 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
244 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
249 case nir_intrinsic_load_sample_pos
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
252 if (reg
->file
== BAD_FILE
)
253 *reg
= *v
->emit_samplepos_setup();
256 case nir_intrinsic_load_sample_id
:
257 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
258 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
259 if (reg
->file
== BAD_FILE
)
260 *reg
= *v
->emit_sampleid_setup();
263 case nir_intrinsic_load_sample_mask_in
:
264 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
265 assert(v
->devinfo
->gen
>= 7);
266 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
267 if (reg
->file
== BAD_FILE
)
268 *reg
= *v
->emit_samplemaskin_setup();
271 case nir_intrinsic_load_local_invocation_id
:
272 assert(v
->stage
== MESA_SHADER_COMPUTE
);
273 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
274 if (reg
->file
== BAD_FILE
)
275 *reg
= *v
->emit_cs_local_invocation_id_setup();
278 case nir_intrinsic_load_work_group_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_work_group_id_setup();
285 case nir_intrinsic_load_helper_invocation
:
286 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
288 if (reg
->file
== BAD_FILE
) {
289 const fs_builder abld
=
290 v
->bld
.annotate("gl_HelperInvocation", NULL
);
292 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
293 * pixel mask is in g1.7 of the thread payload.
295 * We move the per-channel pixel enable bit to the low bit of each
296 * channel by shifting the byte containing the pixel mask by the
297 * vector immediate 0x76543210UV.
299 * The region of <1,8,0> reads only 1 byte (the pixel masks for
300 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
301 * masks for 2 and 3) in SIMD16.
303 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
305 stride(byte_offset(retype(brw_vec1_grf(1, 0),
306 BRW_REGISTER_TYPE_UB
), 28),
308 brw_imm_uv(0x76543210));
310 /* A set bit in the pixel mask means the channel is enabled, but
311 * that is the opposite of gl_HelperInvocation so we need to invert
314 * The negate source-modifier bit of logical instructions on Gen8+
315 * performs 1's complement negation, so we can use that instead of
318 fs_reg inverted
= negate(shifted
);
319 if (v
->devinfo
->gen
< 8) {
320 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
321 abld
.NOT(inverted
, shifted
);
324 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
325 * with 1 and negating.
327 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
328 abld
.AND(anded
, inverted
, brw_imm_uw(1));
330 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
331 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
345 fs_visitor::nir_emit_system_values()
347 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
348 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
349 nir_system_values
[i
] = fs_reg();
352 nir_foreach_function(function
, nir
) {
353 assert(strcmp(function
->name
, "main") == 0);
354 assert(function
->impl
);
355 nir_foreach_block(block
, function
->impl
) {
356 emit_system_values_block(block
, this);
362 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
364 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
365 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
366 nir_locals
[i
] = fs_reg();
369 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
370 unsigned array_elems
=
371 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
372 unsigned size
= array_elems
* reg
->num_components
;
373 const brw_reg_type reg_type
=
374 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
375 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
378 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
381 nir_emit_cf_list(&impl
->body
);
385 fs_visitor::nir_emit_cf_list(exec_list
*list
)
387 exec_list_validate(list
);
388 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
389 switch (node
->type
) {
391 nir_emit_if(nir_cf_node_as_if(node
));
394 case nir_cf_node_loop
:
395 nir_emit_loop(nir_cf_node_as_loop(node
));
398 case nir_cf_node_block
:
399 nir_emit_block(nir_cf_node_as_block(node
));
403 unreachable("Invalid CFG node block");
409 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
411 /* first, put the condition into f0 */
412 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
413 retype(get_nir_src(if_stmt
->condition
),
414 BRW_REGISTER_TYPE_D
));
415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
417 bld
.IF(BRW_PREDICATE_NORMAL
);
419 nir_emit_cf_list(&if_stmt
->then_list
);
421 /* note: if the else is empty, dead CF elimination will remove it */
422 bld
.emit(BRW_OPCODE_ELSE
);
424 nir_emit_cf_list(&if_stmt
->else_list
);
426 bld
.emit(BRW_OPCODE_ENDIF
);
430 fs_visitor::nir_emit_loop(nir_loop
*loop
)
432 bld
.emit(BRW_OPCODE_DO
);
434 nir_emit_cf_list(&loop
->body
);
436 bld
.emit(BRW_OPCODE_WHILE
);
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(instr
, block
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
457 case nir_instr_type_intrinsic
:
459 case MESA_SHADER_VERTEX
:
460 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
462 case MESA_SHADER_TESS_CTRL
:
463 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_EVAL
:
466 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_GEOMETRY
:
469 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_FRAGMENT
:
472 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_COMPUTE
:
475 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 unreachable("unsupported shader stage");
482 case nir_instr_type_tex
:
483 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
486 case nir_instr_type_load_const
:
487 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
490 case nir_instr_type_ssa_undef
:
491 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
494 case nir_instr_type_jump
:
495 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
499 unreachable("unknown instruction type");
504 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
508 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
509 const fs_reg
&result
)
511 if (!instr
->src
[0].src
.is_ssa
||
512 !instr
->src
[0].src
.ssa
->parent_instr
)
515 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
518 nir_alu_instr
*src0
=
519 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
521 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
522 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
525 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
526 assert(element
!= NULL
);
528 enum opcode extract_op
;
529 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
530 assert(element
->u32
[0] <= 1);
531 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
533 assert(element
->u32
[0] <= 3);
534 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
537 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
538 op0
.type
= brw_type_for_nir_type(
539 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
540 nir_src_bit_size(src0
->src
[0].src
)));
541 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
543 set_saturate(instr
->dest
.saturate
,
544 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
549 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
550 const fs_reg
&result
)
552 if (!instr
->src
[0].src
.is_ssa
||
553 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
556 nir_intrinsic_instr
*src0
=
557 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
559 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
562 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
563 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
566 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
567 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
570 fs_reg tmp
= vgrf(glsl_type::int_type
);
572 if (devinfo
->gen
>= 6) {
573 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
574 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
576 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
578 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
579 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
581 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
583 * This negation looks like it's safe in practice, because bits 0:4 will
584 * surely be TRIANGLES
587 if (value1
->f32
[0] == -1.0f
) {
591 tmp
.type
= BRW_REGISTER_TYPE_W
;
592 tmp
.subreg_offset
= 2;
595 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
597 tmp
.type
= BRW_REGISTER_TYPE_D
;
598 tmp
.subreg_offset
= 0;
601 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
602 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
604 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
606 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
607 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
609 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
611 * This negation looks like it's safe in practice, because bits 0:4 will
612 * surely be TRIANGLES
615 if (value1
->f32
[0] == -1.0f
) {
619 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
621 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
627 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
629 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
632 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
633 result
.type
= brw_type_for_nir_type(
634 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
635 nir_dest_bit_size(instr
->dest
.dest
)));
638 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
639 op
[i
] = get_nir_src(instr
->src
[i
].src
);
640 op
[i
].type
= brw_type_for_nir_type(
641 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
642 nir_src_bit_size(instr
->src
[i
].src
)));
643 op
[i
].abs
= instr
->src
[i
].abs
;
644 op
[i
].negate
= instr
->src
[i
].negate
;
647 /* We get a bunch of mov's out of the from_ssa pass and they may still
648 * be vectorized. We'll handle them as a special-case. We'll also
649 * handle vecN here because it's basically the same thing.
657 fs_reg temp
= result
;
658 bool need_extra_copy
= false;
659 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
660 if (!instr
->src
[i
].src
.is_ssa
&&
661 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
662 need_extra_copy
= true;
663 temp
= bld
.vgrf(result
.type
, 4);
668 for (unsigned i
= 0; i
< 4; i
++) {
669 if (!(instr
->dest
.write_mask
& (1 << i
)))
672 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
673 inst
= bld
.MOV(offset(temp
, bld
, i
),
674 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
676 inst
= bld
.MOV(offset(temp
, bld
, i
),
677 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
679 inst
->saturate
= instr
->dest
.saturate
;
682 /* In this case the source and destination registers were the same,
683 * so we need to insert an extra set of moves in order to deal with
686 if (need_extra_copy
) {
687 for (unsigned i
= 0; i
< 4; i
++) {
688 if (!(instr
->dest
.write_mask
& (1 << i
)))
691 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
700 /* At this point, we have dealt with any instruction that operates on
701 * more than a single channel. Therefore, we can just adjust the source
702 * and destination registers for that channel and emit the instruction.
704 unsigned channel
= 0;
705 if (nir_op_infos
[instr
->op
].output_size
== 0) {
706 /* Since NIR is doing the scalarizing for us, we should only ever see
707 * vectorized operations with a single channel.
709 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
710 channel
= ffs(instr
->dest
.write_mask
) - 1;
712 result
= offset(result
, bld
, channel
);
715 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
716 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
717 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
723 if (optimize_extract_to_float(instr
, result
))
726 inst
= bld
.MOV(result
, op
[0]);
727 inst
->saturate
= instr
->dest
.saturate
;
732 bld
.MOV(result
, op
[0]);
736 /* AND(val, 0x80000000) gives the sign bit.
738 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
741 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
743 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
744 op
[0].type
= BRW_REGISTER_TYPE_UD
;
745 result
.type
= BRW_REGISTER_TYPE_UD
;
746 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
748 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
749 inst
->predicate
= BRW_PREDICATE_NORMAL
;
750 if (instr
->dest
.saturate
) {
751 inst
= bld
.MOV(result
, result
);
752 inst
->saturate
= true;
758 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
759 * -> non-negative val generates 0x00000000.
760 * Predicated OR sets 1 if val is positive.
762 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
763 bld
.ASR(result
, op
[0], brw_imm_d(31));
764 inst
= bld
.OR(result
, result
, brw_imm_d(1));
765 inst
->predicate
= BRW_PREDICATE_NORMAL
;
769 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
770 inst
->saturate
= instr
->dest
.saturate
;
774 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
775 inst
->saturate
= instr
->dest
.saturate
;
779 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
780 inst
->saturate
= instr
->dest
.saturate
;
784 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
785 inst
->saturate
= instr
->dest
.saturate
;
789 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
790 inst
->saturate
= instr
->dest
.saturate
;
794 if (fs_key
->high_quality_derivatives
) {
795 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
797 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
799 inst
->saturate
= instr
->dest
.saturate
;
801 case nir_op_fddx_fine
:
802 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
803 inst
->saturate
= instr
->dest
.saturate
;
805 case nir_op_fddx_coarse
:
806 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
807 inst
->saturate
= instr
->dest
.saturate
;
810 if (fs_key
->high_quality_derivatives
) {
811 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
812 brw_imm_d(fs_key
->render_to_fbo
));
814 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
815 brw_imm_d(fs_key
->render_to_fbo
));
817 inst
->saturate
= instr
->dest
.saturate
;
819 case nir_op_fddy_fine
:
820 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
821 brw_imm_d(fs_key
->render_to_fbo
));
822 inst
->saturate
= instr
->dest
.saturate
;
824 case nir_op_fddy_coarse
:
825 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
826 brw_imm_d(fs_key
->render_to_fbo
));
827 inst
->saturate
= instr
->dest
.saturate
;
832 inst
= bld
.ADD(result
, op
[0], op
[1]);
833 inst
->saturate
= instr
->dest
.saturate
;
837 inst
= bld
.MUL(result
, op
[0], op
[1]);
838 inst
->saturate
= instr
->dest
.saturate
;
842 bld
.MUL(result
, op
[0], op
[1]);
845 case nir_op_imul_high
:
846 case nir_op_umul_high
:
847 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
852 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
855 case nir_op_uadd_carry
:
856 unreachable("Should have been lowered by carry_to_arith().");
858 case nir_op_usub_borrow
:
859 unreachable("Should have been lowered by borrow_to_arith().");
863 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
864 * appears that our hardware just does the right thing for signed
867 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
871 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
872 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
874 /* Math instructions don't support conditional mod */
875 inst
= bld
.MOV(bld
.null_reg_d(), result
);
876 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
878 /* Now, we need to determine if signs of the sources are different.
879 * When we XOR the sources, the top bit is 0 if they are the same and 1
880 * if they are different. We can then use a conditional modifier to
881 * turn that into a predicate. This leads us to an XOR.l instruction.
883 * Technically, according to the PRM, you're not allowed to use .l on a
884 * XOR instruction. However, emperical experiments and Curro's reading
885 * of the simulator source both indicate that it's safe.
887 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
888 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
889 inst
->predicate
= BRW_PREDICATE_NORMAL
;
890 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
892 /* If the result of the initial remainder operation is non-zero and the
893 * two sources have different signs, add in a copy of op[1] to get the
894 * final integer modulus value.
896 inst
= bld
.ADD(result
, result
, op
[1]);
897 inst
->predicate
= BRW_PREDICATE_NORMAL
;
905 fs_reg dest
= result
;
906 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
907 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
909 brw_conditional_mod cond
;
912 cond
= BRW_CONDITIONAL_L
;
915 cond
= BRW_CONDITIONAL_GE
;
918 cond
= BRW_CONDITIONAL_Z
;
921 cond
= BRW_CONDITIONAL_NZ
;
924 unreachable("bad opcode");
926 bld
.CMP(dest
, op
[0], op
[1], cond
);
927 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
928 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
935 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
940 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
944 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
948 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
952 if (devinfo
->gen
>= 8) {
953 op
[0] = resolve_source_modifiers(op
[0]);
955 bld
.NOT(result
, op
[0]);
958 if (devinfo
->gen
>= 8) {
959 op
[0] = resolve_source_modifiers(op
[0]);
960 op
[1] = resolve_source_modifiers(op
[1]);
962 bld
.XOR(result
, op
[0], op
[1]);
965 if (devinfo
->gen
>= 8) {
966 op
[0] = resolve_source_modifiers(op
[0]);
967 op
[1] = resolve_source_modifiers(op
[1]);
969 bld
.OR(result
, op
[0], op
[1]);
972 if (devinfo
->gen
>= 8) {
973 op
[0] = resolve_source_modifiers(op
[0]);
974 op
[1] = resolve_source_modifiers(op
[1]);
976 bld
.AND(result
, op
[0], op
[1]);
982 case nir_op_ball_fequal2
:
983 case nir_op_ball_iequal2
:
984 case nir_op_ball_fequal3
:
985 case nir_op_ball_iequal3
:
986 case nir_op_ball_fequal4
:
987 case nir_op_ball_iequal4
:
988 case nir_op_bany_fnequal2
:
989 case nir_op_bany_inequal2
:
990 case nir_op_bany_fnequal3
:
991 case nir_op_bany_inequal3
:
992 case nir_op_bany_fnequal4
:
993 case nir_op_bany_inequal4
:
994 unreachable("Lowered by nir_lower_alu_reductions");
996 case nir_op_fnoise1_1
:
997 case nir_op_fnoise1_2
:
998 case nir_op_fnoise1_3
:
999 case nir_op_fnoise1_4
:
1000 case nir_op_fnoise2_1
:
1001 case nir_op_fnoise2_2
:
1002 case nir_op_fnoise2_3
:
1003 case nir_op_fnoise2_4
:
1004 case nir_op_fnoise3_1
:
1005 case nir_op_fnoise3_2
:
1006 case nir_op_fnoise3_3
:
1007 case nir_op_fnoise3_4
:
1008 case nir_op_fnoise4_1
:
1009 case nir_op_fnoise4_2
:
1010 case nir_op_fnoise4_3
:
1011 case nir_op_fnoise4_4
:
1012 unreachable("not reached: should be handled by lower_noise");
1015 unreachable("not reached: should be handled by ldexp_to_arith()");
1018 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1019 inst
->saturate
= instr
->dest
.saturate
;
1023 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1024 inst
->saturate
= instr
->dest
.saturate
;
1029 bld
.MOV(result
, negate(op
[0]));
1033 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1036 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1040 inst
= bld
.RNDZ(result
, op
[0]);
1041 inst
->saturate
= instr
->dest
.saturate
;
1044 case nir_op_fceil
: {
1045 op
[0].negate
= !op
[0].negate
;
1046 fs_reg temp
= vgrf(glsl_type::float_type
);
1047 bld
.RNDD(temp
, op
[0]);
1049 inst
= bld
.MOV(result
, temp
);
1050 inst
->saturate
= instr
->dest
.saturate
;
1054 inst
= bld
.RNDD(result
, op
[0]);
1055 inst
->saturate
= instr
->dest
.saturate
;
1058 inst
= bld
.FRC(result
, op
[0]);
1059 inst
->saturate
= instr
->dest
.saturate
;
1061 case nir_op_fround_even
:
1062 inst
= bld
.RNDE(result
, op
[0]);
1063 inst
->saturate
= instr
->dest
.saturate
;
1066 case nir_op_fquantize2f16
: {
1067 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1068 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1069 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1071 /* The destination stride must be at least as big as the source stride. */
1072 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1075 /* Check for denormal */
1076 fs_reg abs_src0
= op
[0];
1077 abs_src0
.abs
= true;
1078 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1080 /* Get the appropriately signed zero */
1081 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1082 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1083 brw_imm_ud(0x80000000));
1084 /* Do the actual F32 -> F16 -> F32 conversion */
1085 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1086 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1087 /* Select that or zero based on normal status */
1088 inst
= bld
.SEL(result
, zero
, tmp32
);
1089 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1090 inst
->saturate
= instr
->dest
.saturate
;
1097 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1098 inst
->saturate
= instr
->dest
.saturate
;
1104 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1105 inst
->saturate
= instr
->dest
.saturate
;
1108 case nir_op_pack_snorm_2x16
:
1109 case nir_op_pack_snorm_4x8
:
1110 case nir_op_pack_unorm_2x16
:
1111 case nir_op_pack_unorm_4x8
:
1112 case nir_op_unpack_snorm_2x16
:
1113 case nir_op_unpack_snorm_4x8
:
1114 case nir_op_unpack_unorm_2x16
:
1115 case nir_op_unpack_unorm_4x8
:
1116 case nir_op_unpack_half_2x16
:
1117 case nir_op_pack_half_2x16
:
1118 unreachable("not reached: should be handled by lower_packing_builtins");
1120 case nir_op_unpack_half_2x16_split_x
:
1121 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1122 inst
->saturate
= instr
->dest
.saturate
;
1124 case nir_op_unpack_half_2x16_split_y
:
1125 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1126 inst
->saturate
= instr
->dest
.saturate
;
1129 case nir_op_pack_double_2x32_split
:
1130 /* Optimize the common case where we are re-packing a double with
1131 * the result of a previous double unpack. In this case we can take the
1132 * 32-bit value to use in the re-pack from the original double and bypass
1133 * the unpack operation.
1135 for (int i
= 0; i
< 2; i
++) {
1136 if (instr
->src
[i
].src
.is_ssa
)
1139 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1140 if (parent_instr
->type
== nir_instr_type_alu
)
1143 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1144 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1145 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1148 if (!alu_parent
->src
[0].src
.is_ssa
)
1151 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1152 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1153 alu_parent
->src
[0].swizzle
[channel
]);
1154 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1155 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1157 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1159 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1162 case nir_op_unpack_double_2x32_split_x
:
1163 case nir_op_unpack_double_2x32_split_y
: {
1164 /* Optimize the common case where we are unpacking from a double we have
1165 * previously packed. In this case we can just bypass the pack operation
1166 * and source directly from its arguments.
1168 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1169 if (instr
->src
[0].src
.is_ssa
) {
1170 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1171 if (parent_instr
->type
== nir_instr_type_alu
) {
1172 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1173 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1174 alu_parent
->src
[index
].src
.is_ssa
) {
1175 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1176 BRW_REGISTER_TYPE_UD
);
1178 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1179 bld
.MOV(result
, op
[0]);
1185 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1186 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1188 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1193 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1194 inst
->saturate
= instr
->dest
.saturate
;
1197 case nir_op_bitfield_reverse
:
1198 bld
.BFREV(result
, op
[0]);
1201 case nir_op_bit_count
:
1202 bld
.CBIT(result
, op
[0]);
1205 case nir_op_ufind_msb
:
1206 case nir_op_ifind_msb
: {
1207 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1209 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1210 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1211 * subtract the result from 31 to convert the MSB count into an LSB count.
1213 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1215 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1216 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1217 inst
->src
[0].negate
= true;
1221 case nir_op_find_lsb
:
1222 bld
.FBL(result
, op
[0]);
1225 case nir_op_ubitfield_extract
:
1226 case nir_op_ibitfield_extract
:
1227 unreachable("should have been lowered");
1230 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1233 bld
.BFI1(result
, op
[0], op
[1]);
1236 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1239 case nir_op_bitfield_insert
:
1240 unreachable("not reached: should have been lowered");
1243 bld
.SHL(result
, op
[0], op
[1]);
1246 bld
.ASR(result
, op
[0], op
[1]);
1249 bld
.SHR(result
, op
[0], op
[1]);
1252 case nir_op_pack_half_2x16_split
:
1253 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1257 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1258 inst
->saturate
= instr
->dest
.saturate
;
1262 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1263 inst
->saturate
= instr
->dest
.saturate
;
1267 if (optimize_frontfacing_ternary(instr
, result
))
1270 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1271 inst
= bld
.SEL(result
, op
[1], op
[2]);
1272 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1275 case nir_op_extract_u8
:
1276 case nir_op_extract_i8
: {
1277 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1278 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1279 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1283 case nir_op_extract_u16
:
1284 case nir_op_extract_i16
: {
1285 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1286 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1287 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1292 unreachable("unhandled instruction");
1295 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1296 * to sign extend the low bit to 0/~0
1298 if (devinfo
->gen
<= 5 &&
1299 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1300 fs_reg masked
= vgrf(glsl_type::int_type
);
1301 bld
.AND(masked
, result
, brw_imm_d(1));
1302 masked
.negate
= true;
1303 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1308 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1309 nir_load_const_instr
*instr
)
1311 const brw_reg_type reg_type
=
1312 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1313 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1315 switch (instr
->def
.bit_size
) {
1317 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1318 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1322 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1323 bld
.MOV(offset(reg
, bld
, i
), brw_imm_df(instr
->value
.f64
[i
]));
1327 unreachable("Invalid bit size");
1330 nir_ssa_values
[instr
->def
.index
] = reg
;
1334 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1336 const brw_reg_type reg_type
=
1337 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1338 nir_ssa_values
[instr
->def
.index
] =
1339 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1343 fs_visitor::get_nir_src(nir_src src
)
1347 reg
= nir_ssa_values
[src
.ssa
->index
];
1349 /* We don't handle indirects on locals */
1350 assert(src
.reg
.indirect
== NULL
);
1351 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1352 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1355 /* to avoid floating-point denorm flushing problems, set the type by
1356 * default to D - instructions that need floating point semantics will set
1357 * this to F if they need to
1359 return retype(reg
, BRW_REGISTER_TYPE_D
);
1363 fs_visitor::get_nir_dest(nir_dest dest
)
1366 const brw_reg_type reg_type
=
1367 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1368 nir_ssa_values
[dest
.ssa
.index
] =
1369 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1370 return nir_ssa_values
[dest
.ssa
.index
];
1372 /* We don't handle indirects on locals */
1373 assert(dest
.reg
.indirect
== NULL
);
1374 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1375 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1380 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1382 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1383 BRW_REGISTER_TYPE_UD
);
1385 unsigned indirect_max
= 0;
1387 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1388 tail
= tail
->child
) {
1389 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1390 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1391 const unsigned size
= glsl_get_length(tail
->type
);
1392 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1393 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1394 image
= offset(image
, bld
, base
* element_size
);
1396 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1397 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1399 /* Accessing an invalid surface index with the dataport can result
1400 * in a hang. According to the spec "if the index used to
1401 * select an individual element is negative or greater than or
1402 * equal to the size of the array, the results of the operation
1403 * are undefined but may not lead to termination" -- which is one
1404 * of the possible outcomes of the hang. Clamp the index to
1405 * prevent access outside of the array bounds.
1407 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1408 BRW_REGISTER_TYPE_UD
),
1409 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1411 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1413 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1414 if (indirect
.file
== BAD_FILE
) {
1417 bld
.ADD(indirect
, indirect
, tmp
);
1422 if (indirect
.file
== BAD_FILE
) {
1425 /* Emit a pile of MOVs to load the uniform into a temporary. The
1426 * dead-code elimination pass will get rid of what we don't use.
1428 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1429 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1430 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1431 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1432 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1439 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1442 for (unsigned i
= 0; i
< 4; i
++) {
1443 if (!((wr_mask
>> i
) & 1))
1446 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1447 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1448 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1449 if (new_inst
->src
[j
].file
== VGRF
)
1450 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1457 * Get the matching channel register datatype for an image intrinsic of the
1458 * specified GLSL image type.
1461 get_image_base_type(const glsl_type
*type
)
1463 switch ((glsl_base_type
)type
->sampled_type
) {
1464 case GLSL_TYPE_UINT
:
1465 return BRW_REGISTER_TYPE_UD
;
1467 return BRW_REGISTER_TYPE_D
;
1468 case GLSL_TYPE_FLOAT
:
1469 return BRW_REGISTER_TYPE_F
;
1471 unreachable("Not reached.");
1476 * Get the appropriate atomic op for an image atomic intrinsic.
1479 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1482 case nir_intrinsic_image_atomic_add
:
1484 case nir_intrinsic_image_atomic_min
:
1485 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1486 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1487 case nir_intrinsic_image_atomic_max
:
1488 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1489 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1490 case nir_intrinsic_image_atomic_and
:
1492 case nir_intrinsic_image_atomic_or
:
1494 case nir_intrinsic_image_atomic_xor
:
1496 case nir_intrinsic_image_atomic_exchange
:
1498 case nir_intrinsic_image_atomic_comp_swap
:
1499 return BRW_AOP_CMPWR
;
1501 unreachable("Not reachable.");
1506 emit_pixel_interpolater_send(const fs_builder
&bld
,
1511 glsl_interp_qualifier interpolation
)
1517 if (src
.file
== BAD_FILE
) {
1519 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1523 mlen
= 2 * bld
.dispatch_width() / 8;
1526 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1528 /* 2 floats per slot returned */
1529 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1530 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1536 * Computes 1 << x, given a D/UD register containing some value x.
1539 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1541 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1543 fs_reg result
= bld
.vgrf(x
.type
, 1);
1544 fs_reg one
= bld
.vgrf(x
.type
, 1);
1546 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1547 bld
.SHL(result
, one
, x
);
1552 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1554 assert(stage
== MESA_SHADER_GEOMETRY
);
1556 struct brw_gs_prog_data
*gs_prog_data
=
1557 (struct brw_gs_prog_data
*) prog_data
;
1559 /* We can only do EndPrimitive() functionality when the control data
1560 * consists of cut bits. Fortunately, the only time it isn't is when the
1561 * output type is points, in which case EndPrimitive() is a no-op.
1563 if (gs_prog_data
->control_data_format
!=
1564 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1568 /* Cut bits use one bit per vertex. */
1569 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1571 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1572 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1574 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1575 * vertex n, 0 otherwise. So all we need to do here is mark bit
1576 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1577 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1578 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1580 * Note that if EndPrimitive() is called before emitting any vertices, this
1581 * will cause us to set bit 31 of the control_data_bits register to 1.
1582 * That's fine because:
1584 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1585 * output, so the hardware will ignore cut bit 31.
1587 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1588 * last vertex, so setting cut bit 31 has no effect (since the primitive
1589 * is automatically ended when the GS terminates).
1591 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1592 * control_data_bits register to 0 when the first vertex is emitted.
1595 const fs_builder abld
= bld
.annotate("end primitive");
1597 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1598 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1599 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1600 fs_reg mask
= intexp2(abld
, prev_count
);
1601 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1602 * attention to the lower 5 bits of its second source argument, so on this
1603 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1604 * ((vertex_count - 1) % 32).
1606 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1610 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1612 assert(stage
== MESA_SHADER_GEOMETRY
);
1613 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1615 struct brw_gs_prog_data
*gs_prog_data
=
1616 (struct brw_gs_prog_data
*) prog_data
;
1618 const fs_builder abld
= bld
.annotate("emit control data bits");
1619 const fs_builder fwa_bld
= bld
.exec_all();
1621 /* We use a single UD register to accumulate control data bits (32 bits
1622 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1625 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1626 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1627 * use the Channel Mask phase to enable/disable which DWord within that
1628 * group to write. (Remember, different SIMD8 channels may have emitted
1629 * different numbers of vertices, so we may need per-slot offsets.)
1631 * Channel masking presents an annoying problem: we may have to replicate
1632 * the data up to 4 times:
1634 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1636 * To avoid penalizing shaders that emit a small number of vertices, we
1637 * can avoid these sometimes: if the size of the control data header is
1638 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1639 * land in the same 128-bit group, so we can skip per-slot offsets.
1641 * Similarly, if the control data header is <= 32 bits, there is only one
1642 * DWord, so we can skip channel masks.
1644 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1646 fs_reg channel_mask
, per_slot_offset
;
1648 if (gs_compile
->control_data_header_size_bits
> 32) {
1649 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1650 channel_mask
= vgrf(glsl_type::uint_type
);
1653 if (gs_compile
->control_data_header_size_bits
> 128) {
1654 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1655 per_slot_offset
= vgrf(glsl_type::uint_type
);
1658 /* Figure out which DWord we're trying to write to using the formula:
1660 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1662 * Since bits_per_vertex is a power of two, and is known at compile
1663 * time, this can be optimized to:
1665 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1667 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1668 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1669 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1670 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1671 unsigned log2_bits_per_vertex
=
1672 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1673 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1675 if (per_slot_offset
.file
!= BAD_FILE
) {
1676 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1677 * the appropriate OWord within the control data header.
1679 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1682 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1683 * write to the appropriate DWORD within the OWORD.
1685 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1686 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1687 channel_mask
= intexp2(fwa_bld
, channel
);
1688 /* Then the channel masks need to be in bits 23:16. */
1689 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1692 /* Store the control data bits in the message payload and send it. */
1694 if (channel_mask
.file
!= BAD_FILE
)
1695 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1696 if (per_slot_offset
.file
!= BAD_FILE
)
1699 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1700 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1702 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1703 if (per_slot_offset
.file
!= BAD_FILE
)
1704 sources
[i
++] = per_slot_offset
;
1705 if (channel_mask
.file
!= BAD_FILE
)
1706 sources
[i
++] = channel_mask
;
1708 sources
[i
++] = this->control_data_bits
;
1711 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1712 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1714 /* We need to increment Global Offset by 256-bits to make room for
1715 * Broadwell's extra "Vertex Count" payload at the beginning of the
1716 * URB entry. Since this is an OWord message, Global Offset is counted
1717 * in 128-bit units, so we must set it to 2.
1719 if (gs_prog_data
->static_vertex_count
== -1)
1724 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1727 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1729 /* Note: we are calling this *before* increasing vertex_count, so
1730 * this->vertex_count == vertex_count - 1 in the formula above.
1733 /* Stream mode uses 2 bits per vertex */
1734 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1736 /* Must be a valid stream */
1737 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1739 /* Control data bits are initialized to 0 so we don't have to set any
1740 * bits when sending vertices to stream 0.
1745 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1747 /* reg::sid = stream_id */
1748 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1749 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1751 /* reg:shift_count = 2 * (vertex_count - 1) */
1752 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1753 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1755 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1756 * attention to the lower 5 bits of its second source argument, so on this
1757 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1758 * stream_id << ((2 * (vertex_count - 1)) % 32).
1760 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1761 abld
.SHL(mask
, sid
, shift_count
);
1762 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1766 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1769 assert(stage
== MESA_SHADER_GEOMETRY
);
1771 struct brw_gs_prog_data
*gs_prog_data
=
1772 (struct brw_gs_prog_data
*) prog_data
;
1774 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1775 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1777 /* Haswell and later hardware ignores the "Render Stream Select" bits
1778 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1779 * and instead sends all primitives down the pipeline for rasterization.
1780 * If the SOL stage is enabled, "Render Stream Select" is honored and
1781 * primitives bound to non-zero streams are discarded after stream output.
1783 * Since the only purpose of primives sent to non-zero streams is to
1784 * be recorded by transform feedback, we can simply discard all geometry
1785 * bound to these streams when transform feedback is disabled.
1787 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1790 /* If we're outputting 32 control data bits or less, then we can wait
1791 * until the shader is over to output them all. Otherwise we need to
1792 * output them as we go. Now is the time to do it, since we're about to
1793 * output the vertex_count'th vertex, so it's guaranteed that the
1794 * control data bits associated with the (vertex_count - 1)th vertex are
1797 if (gs_compile
->control_data_header_size_bits
> 32) {
1798 const fs_builder abld
=
1799 bld
.annotate("emit vertex: emit control data bits");
1801 /* Only emit control data bits if we've finished accumulating a batch
1802 * of 32 bits. This is the case when:
1804 * (vertex_count * bits_per_vertex) % 32 == 0
1806 * (in other words, when the last 5 bits of vertex_count *
1807 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1808 * integer n (which is always the case, since bits_per_vertex is
1809 * always 1 or 2), this is equivalent to requiring that the last 5-n
1810 * bits of vertex_count are 0:
1812 * vertex_count & (2^(5-n) - 1) == 0
1814 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1817 * vertex_count & (32 / bits_per_vertex - 1) == 0
1819 * TODO: If vertex_count is an immediate, we could do some of this math
1820 * at compile time...
1823 abld
.AND(bld
.null_reg_d(), vertex_count
,
1824 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1825 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1827 abld
.IF(BRW_PREDICATE_NORMAL
);
1828 /* If vertex_count is 0, then no control data bits have been
1829 * accumulated yet, so we can skip emitting them.
1831 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1832 BRW_CONDITIONAL_NEQ
);
1833 abld
.IF(BRW_PREDICATE_NORMAL
);
1834 emit_gs_control_data_bits(vertex_count
);
1835 abld
.emit(BRW_OPCODE_ENDIF
);
1837 /* Reset control_data_bits to 0 so we can start accumulating a new
1840 * Note: in the case where vertex_count == 0, this neutralizes the
1841 * effect of any call to EndPrimitive() that the shader may have
1842 * made before outputting its first vertex.
1844 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1845 inst
->force_writemask_all
= true;
1846 abld
.emit(BRW_OPCODE_ENDIF
);
1849 emit_urb_writes(vertex_count
);
1851 /* In stream mode we have to set control data bits for all vertices
1852 * unless we have disabled control data bits completely (which we do
1853 * do for GL_POINTS outputs that don't use streams).
1855 if (gs_compile
->control_data_header_size_bits
> 0 &&
1856 gs_prog_data
->control_data_format
==
1857 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1858 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1863 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1864 const nir_src
&vertex_src
,
1865 unsigned base_offset
,
1866 const nir_src
&offset_src
,
1867 unsigned num_components
)
1869 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1871 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1872 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1873 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1875 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1876 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1877 * gl_PointSize is available as a GS input, however, so it must be that.
1879 const bool is_point_size
= (base_offset
== 0);
1881 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1882 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1883 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1884 vertex_const
->u32
[0] * push_reg_count
;
1885 /* This input was pushed into registers. */
1886 if (is_point_size
) {
1887 /* gl_PointSize comes in .w */
1888 assert(imm_offset
== 0);
1889 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1891 for (unsigned i
= 0; i
< num_components
; i
++) {
1892 bld
.MOV(offset(dst
, bld
, i
),
1893 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1897 /* Resort to the pull model. Ensure the VUE handles are provided. */
1898 gs_prog_data
->base
.include_vue_handles
= true;
1900 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1904 /* The vertex index is constant; just select the proper URB handle. */
1906 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
1907 BRW_REGISTER_TYPE_UD
);
1909 /* The vertex index is non-constant. We need to use indirect
1910 * addressing to fetch the proper URB handle.
1912 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1913 * indicating that channel <n> should read the handle from
1914 * DWord <n>. We convert that to bytes by multiplying by 4.
1916 * Next, we convert the vertex index to bytes by multiplying
1917 * by 32 (shifting by 5), and add the two together. This is
1918 * the final indirect byte offset.
1920 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1921 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1922 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1923 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1924 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1926 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1927 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1928 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1929 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1930 /* Convert vertex_index to bytes (multiply by 32) */
1931 bld
.SHL(vertex_offset_bytes
,
1932 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1934 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1936 /* Use first_icp_handle as the base offset. There is one register
1937 * of URB handles per vertex, so inform the register allocator that
1938 * we might read up to nir->info.gs.vertices_in registers.
1940 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1941 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1942 fs_reg(icp_offset_bytes
),
1943 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1948 /* Constant indexing - use global offset. */
1949 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1950 inst
->offset
= base_offset
+ offset_const
->u32
[0];
1951 inst
->base_mrf
= -1;
1953 inst
->regs_written
= num_components
;
1955 /* Indirect indexing - use per-slot offsets as well. */
1956 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1957 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1958 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1960 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1961 inst
->offset
= base_offset
;
1962 inst
->base_mrf
= -1;
1964 inst
->regs_written
= num_components
;
1967 if (is_point_size
) {
1968 /* Read the whole VUE header (because of alignment) and read .w. */
1969 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1971 inst
->regs_written
= 4;
1972 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1978 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1980 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1981 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1984 /* The only constant offset we should find is 0. brw_nir.c's
1985 * add_const_offset_to_base() will fold other constant offsets
1986 * into instr->const_index[0].
1988 assert(const_value
->u32
[0] == 0);
1992 return get_nir_src(*offset_src
);
1996 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1997 nir_intrinsic_instr
*instr
)
1999 assert(stage
== MESA_SHADER_VERTEX
);
2002 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2003 dest
= get_nir_dest(instr
->dest
);
2005 switch (instr
->intrinsic
) {
2006 case nir_intrinsic_load_vertex_id
:
2007 unreachable("should be lowered by lower_vertex_id()");
2009 case nir_intrinsic_load_vertex_id_zero_base
:
2010 case nir_intrinsic_load_base_vertex
:
2011 case nir_intrinsic_load_instance_id
:
2012 case nir_intrinsic_load_base_instance
:
2013 case nir_intrinsic_load_draw_id
: {
2014 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2015 fs_reg val
= nir_system_values
[sv
];
2016 assert(val
.file
!= BAD_FILE
);
2017 dest
.type
= val
.type
;
2023 nir_emit_intrinsic(bld
, instr
);
2029 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2030 nir_intrinsic_instr
*instr
)
2032 assert(stage
== MESA_SHADER_TESS_CTRL
);
2033 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2034 struct brw_tcs_prog_data
*tcs_prog_data
=
2035 (struct brw_tcs_prog_data
*) prog_data
;
2038 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2039 dst
= get_nir_dest(instr
->dest
);
2041 switch (instr
->intrinsic
) {
2042 case nir_intrinsic_load_primitive_id
:
2043 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2045 case nir_intrinsic_load_invocation_id
:
2046 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2048 case nir_intrinsic_load_patch_vertices_in
:
2049 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2050 brw_imm_d(tcs_key
->input_vertices
));
2053 case nir_intrinsic_barrier
: {
2054 if (tcs_prog_data
->instances
== 1)
2057 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2058 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2060 const fs_builder fwa_bld
= bld
.exec_all();
2062 /* Zero the message header */
2063 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2065 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2066 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2067 brw_imm_ud(INTEL_MASK(16, 13)));
2069 /* Shift it up to bits 27:24. */
2070 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2072 /* Set the Barrier Count and the enable bit */
2073 fwa_bld
.OR(m0_2
, m0_2
,
2074 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2076 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2080 case nir_intrinsic_load_input
:
2081 unreachable("nir_lower_io should never give us these.");
2084 case nir_intrinsic_load_per_vertex_input
: {
2085 fs_reg indirect_offset
= get_indirect_offset(instr
);
2086 unsigned imm_offset
= instr
->const_index
[0];
2088 const nir_src
&vertex_src
= instr
->src
[0];
2089 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2096 /* Emit a MOV to resolve <0,1,0> regioning. */
2097 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2099 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2100 vertex_const
->i32
[0] & 7),
2101 BRW_REGISTER_TYPE_UD
));
2102 } else if (tcs_prog_data
->instances
== 1 &&
2103 vertex_src
.is_ssa
&&
2104 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2105 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2106 /* For the common case of only 1 instance, an array index of
2107 * gl_InvocationID means reading g1. Skip all the indirect work.
2109 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2111 /* The vertex index is non-constant. We need to use indirect
2112 * addressing to fetch the proper URB handle.
2114 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2116 /* Each ICP handle is a single DWord (4 bytes) */
2117 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2118 bld
.SHL(vertex_offset_bytes
,
2119 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2122 /* Start at g1. We might read up to 4 registers. */
2123 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2124 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2125 brw_imm_ud(4 * REG_SIZE
));
2128 if (indirect_offset
.file
== BAD_FILE
) {
2129 /* Constant indexing - use global offset. */
2130 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2131 inst
->offset
= imm_offset
;
2133 inst
->base_mrf
= -1;
2134 inst
->regs_written
= instr
->num_components
;
2136 /* Indirect indexing - use per-slot offsets as well. */
2137 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2138 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2139 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2141 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2142 inst
->offset
= imm_offset
;
2143 inst
->base_mrf
= -1;
2145 inst
->regs_written
= instr
->num_components
;
2148 /* Copy the temporary to the destination to deal with writemasking.
2150 * Also attempt to deal with gl_PointSize being in the .w component.
2152 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2153 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2154 inst
->regs_written
= 4;
2155 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2160 case nir_intrinsic_load_output
:
2161 case nir_intrinsic_load_per_vertex_output
: {
2162 fs_reg indirect_offset
= get_indirect_offset(instr
);
2163 unsigned imm_offset
= instr
->const_index
[0];
2166 if (indirect_offset
.file
== BAD_FILE
) {
2167 /* Replicate the patch handle to all enabled channels */
2168 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2169 bld
.MOV(patch_handle
,
2170 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2172 if (imm_offset
== 0) {
2173 /* This is a read of gl_TessLevelInner[], which lives in the
2174 * Patch URB header. The layout depends on the domain.
2176 dst
.type
= BRW_REGISTER_TYPE_F
;
2177 switch (tcs_key
->tes_primitive_mode
) {
2179 /* DWords 3-2 (reversed) */
2180 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2182 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2185 inst
->base_mrf
= -1;
2186 inst
->regs_written
= 4;
2188 /* dst.xy = tmp.wz */
2189 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2190 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2194 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2195 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2198 inst
->base_mrf
= -1;
2199 inst
->regs_written
= 1;
2202 /* All channels are undefined. */
2205 unreachable("Bogus tessellation domain");
2207 } else if (imm_offset
== 1) {
2208 /* This is a read of gl_TessLevelOuter[], which lives in the
2209 * Patch URB header. The layout depends on the domain.
2211 dst
.type
= BRW_REGISTER_TYPE_F
;
2213 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2214 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2217 inst
->base_mrf
= -1;
2218 inst
->regs_written
= 4;
2220 /* Reswizzle: WZYX */
2222 offset(tmp
, bld
, 3),
2223 offset(tmp
, bld
, 2),
2224 offset(tmp
, bld
, 1),
2225 offset(tmp
, bld
, 0),
2228 unsigned num_components
;
2229 switch (tcs_key
->tes_primitive_mode
) {
2237 /* Isolines are not reversed; swizzle .zw -> .xy */
2238 srcs
[0] = offset(tmp
, bld
, 2);
2239 srcs
[1] = offset(tmp
, bld
, 3);
2243 unreachable("Bogus tessellation domain");
2245 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2247 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2248 inst
->offset
= imm_offset
;
2250 inst
->base_mrf
= -1;
2251 inst
->regs_written
= instr
->num_components
;
2254 /* Indirect indexing - use per-slot offsets as well. */
2255 const fs_reg srcs
[] = {
2256 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2259 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2260 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2262 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2263 inst
->offset
= imm_offset
;
2265 inst
->base_mrf
= -1;
2266 inst
->regs_written
= instr
->num_components
;
2271 case nir_intrinsic_store_output
:
2272 case nir_intrinsic_store_per_vertex_output
: {
2273 fs_reg value
= get_nir_src(instr
->src
[0]);
2274 fs_reg indirect_offset
= get_indirect_offset(instr
);
2275 unsigned imm_offset
= instr
->const_index
[0];
2276 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2277 unsigned mask
= instr
->const_index
[1];
2278 unsigned header_regs
= 0;
2280 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2282 if (indirect_offset
.file
!= BAD_FILE
) {
2283 srcs
[header_regs
++] = indirect_offset
;
2284 } else if (!is_passthrough_shader
) {
2285 if (imm_offset
== 0) {
2286 value
.type
= BRW_REGISTER_TYPE_F
;
2288 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2290 /* This is a write to gl_TessLevelInner[], which lives in the
2291 * Patch URB header. The layout depends on the domain.
2293 switch (tcs_key
->tes_primitive_mode
) {
2295 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2296 * We use an XXYX swizzle to reverse put .xy in the .wz
2297 * channels, and use a .zw writemask.
2299 mask
= writemask_for_backwards_vector(mask
);
2300 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2303 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2304 * writemask to X and bump the URB offset by 1.
2309 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2312 unreachable("Bogus tessellation domain");
2314 } else if (imm_offset
== 1) {
2315 /* This is a write to gl_TessLevelOuter[] which lives in the
2316 * Patch URB Header at DWords 4-7. However, it's reversed, so
2317 * instead of .xyzw we have .wzyx.
2319 value
.type
= BRW_REGISTER_TYPE_F
;
2321 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2323 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2324 /* Isolines .xy should be stored in .zw, in order. */
2325 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2328 /* Other domains are reversed; store .wzyx instead of .xyzw */
2329 swiz
= BRW_SWIZZLE_WZYX
;
2330 mask
= writemask_for_backwards_vector(mask
);
2338 unsigned num_components
= _mesa_fls(mask
);
2341 if (mask
!= WRITEMASK_XYZW
) {
2342 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2343 opcode
= indirect_offset
.file
!= BAD_FILE
?
2344 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2345 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2347 opcode
= indirect_offset
.file
!= BAD_FILE
?
2348 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2349 SHADER_OPCODE_URB_WRITE_SIMD8
;
2352 for (unsigned i
= 0; i
< num_components
; i
++) {
2353 if (mask
& (1 << i
))
2354 srcs
[header_regs
+ i
] = offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2357 unsigned mlen
= header_regs
+ num_components
;
2360 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2361 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2363 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2364 inst
->offset
= imm_offset
;
2366 inst
->base_mrf
= -1;
2371 nir_emit_intrinsic(bld
, instr
);
2377 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2378 nir_intrinsic_instr
*instr
)
2380 assert(stage
== MESA_SHADER_TESS_EVAL
);
2381 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2384 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2385 dest
= get_nir_dest(instr
->dest
);
2387 switch (instr
->intrinsic
) {
2388 case nir_intrinsic_load_primitive_id
:
2389 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2391 case nir_intrinsic_load_tess_coord
:
2392 /* gl_TessCoord is part of the payload in g1-3 */
2393 for (unsigned i
= 0; i
< 3; i
++) {
2394 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2398 case nir_intrinsic_load_tess_level_outer
:
2399 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2400 * appears as a push-model input. So, we can simply use the ATTR file
2401 * rather than issuing URB read messages. The data is stored in the
2402 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2405 switch (tes_prog_data
->domain
) {
2406 case BRW_TESS_DOMAIN_QUAD
:
2407 for (unsigned i
= 0; i
< 4; i
++)
2408 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2410 case BRW_TESS_DOMAIN_TRI
:
2411 for (unsigned i
= 0; i
< 3; i
++)
2412 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2414 case BRW_TESS_DOMAIN_ISOLINE
:
2415 for (unsigned i
= 0; i
< 2; i
++)
2416 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2421 case nir_intrinsic_load_tess_level_inner
:
2422 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2423 * appears as a push-model input. So, we can simply use the ATTR file
2424 * rather than issuing URB read messages.
2426 switch (tes_prog_data
->domain
) {
2427 case BRW_TESS_DOMAIN_QUAD
:
2428 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2429 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2431 case BRW_TESS_DOMAIN_TRI
:
2432 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2434 case BRW_TESS_DOMAIN_ISOLINE
:
2435 /* ignore - value is undefined */
2440 case nir_intrinsic_load_input
:
2441 case nir_intrinsic_load_per_vertex_input
: {
2442 fs_reg indirect_offset
= get_indirect_offset(instr
);
2443 unsigned imm_offset
= instr
->const_index
[0];
2446 if (indirect_offset
.file
== BAD_FILE
) {
2447 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2448 * which is 16 registers (since each holds 2 vec4 slots).
2450 const unsigned max_push_slots
= 32;
2451 if (imm_offset
< max_push_slots
) {
2452 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2453 for (int i
= 0; i
< instr
->num_components
; i
++) {
2454 bld
.MOV(offset(dest
, bld
, i
),
2455 component(src
, 4 * (imm_offset
% 2) + i
));
2457 tes_prog_data
->base
.urb_read_length
=
2458 MAX2(tes_prog_data
->base
.urb_read_length
,
2459 DIV_ROUND_UP(imm_offset
+ 1, 2));
2461 /* Replicate the patch handle to all enabled channels */
2462 const fs_reg srcs
[] = {
2463 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2465 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2466 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2468 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2470 inst
->offset
= imm_offset
;
2471 inst
->base_mrf
= -1;
2472 inst
->regs_written
= instr
->num_components
;
2475 /* Indirect indexing - use per-slot offsets as well. */
2476 const fs_reg srcs
[] = {
2477 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2480 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2481 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2483 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2485 inst
->offset
= imm_offset
;
2486 inst
->base_mrf
= -1;
2487 inst
->regs_written
= instr
->num_components
;
2492 nir_emit_intrinsic(bld
, instr
);
2498 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2499 nir_intrinsic_instr
*instr
)
2501 assert(stage
== MESA_SHADER_GEOMETRY
);
2502 fs_reg indirect_offset
;
2505 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2506 dest
= get_nir_dest(instr
->dest
);
2508 switch (instr
->intrinsic
) {
2509 case nir_intrinsic_load_primitive_id
:
2510 assert(stage
== MESA_SHADER_GEOMETRY
);
2511 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2512 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2513 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2516 case nir_intrinsic_load_input
:
2517 unreachable("load_input intrinsics are invalid for the GS stage");
2519 case nir_intrinsic_load_per_vertex_input
:
2520 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2521 instr
->src
[1], instr
->num_components
);
2524 case nir_intrinsic_emit_vertex_with_counter
:
2525 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2528 case nir_intrinsic_end_primitive_with_counter
:
2529 emit_gs_end_primitive(instr
->src
[0]);
2532 case nir_intrinsic_set_vertex_count
:
2533 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2536 case nir_intrinsic_load_invocation_id
: {
2537 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2538 assert(val
.file
!= BAD_FILE
);
2539 dest
.type
= val
.type
;
2545 nir_emit_intrinsic(bld
, instr
);
2551 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2552 nir_intrinsic_instr
*instr
)
2554 assert(stage
== MESA_SHADER_FRAGMENT
);
2555 struct brw_wm_prog_data
*wm_prog_data
=
2556 (struct brw_wm_prog_data
*) prog_data
;
2557 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
2560 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2561 dest
= get_nir_dest(instr
->dest
);
2563 switch (instr
->intrinsic
) {
2564 case nir_intrinsic_load_front_face
:
2565 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2566 *emit_frontfacing_interpolation());
2569 case nir_intrinsic_load_sample_pos
: {
2570 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2571 assert(sample_pos
.file
!= BAD_FILE
);
2572 dest
.type
= sample_pos
.type
;
2573 bld
.MOV(dest
, sample_pos
);
2574 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2578 case nir_intrinsic_load_helper_invocation
:
2579 case nir_intrinsic_load_sample_mask_in
:
2580 case nir_intrinsic_load_sample_id
: {
2581 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2582 fs_reg val
= nir_system_values
[sv
];
2583 assert(val
.file
!= BAD_FILE
);
2584 dest
.type
= val
.type
;
2589 case nir_intrinsic_discard
:
2590 case nir_intrinsic_discard_if
: {
2591 /* We track our discarded pixels in f0.1. By predicating on it, we can
2592 * update just the flag bits that aren't yet discarded. If there's no
2593 * condition, we emit a CMP of g0 != g0, so all currently executing
2594 * channels will get turned off.
2597 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2598 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2599 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2601 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2602 BRW_REGISTER_TYPE_UW
));
2603 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2605 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2606 cmp
->flag_subreg
= 1;
2608 if (devinfo
->gen
>= 6) {
2609 emit_discard_jump();
2614 case nir_intrinsic_interp_var_at_centroid
:
2615 case nir_intrinsic_interp_var_at_sample
:
2616 case nir_intrinsic_interp_var_at_offset
: {
2617 /* Handle ARB_gpu_shader5 interpolation intrinsics
2619 * It's worth a quick word of explanation as to why we handle the full
2620 * variable-based interpolation intrinsic rather than a lowered version
2621 * with like we do for other inputs. We have to do that because the way
2622 * we set up inputs doesn't allow us to use the already setup inputs for
2623 * interpolation. At the beginning of the shader, we go through all of
2624 * the input variables and do the initial interpolation and put it in
2625 * the nir_inputs array based on its location as determined in
2626 * nir_lower_io. If the input isn't used, dead code cleans up and
2627 * everything works fine. However, when we get to the ARB_gpu_shader5
2628 * interpolation intrinsics, we need to reinterpolate the input
2629 * differently. If we used an intrinsic that just had an index it would
2630 * only give us the offset into the nir_inputs array. However, this is
2631 * useless because that value is post-interpolation and we need
2632 * pre-interpolation. In order to get the actual location of the bits
2633 * we get from the vertex fetching hardware, we need the variable.
2635 wm_prog_data
->pulls_bary
= true;
2637 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2638 const glsl_interp_qualifier interpolation
=
2639 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2641 switch (instr
->intrinsic
) {
2642 case nir_intrinsic_interp_var_at_centroid
:
2643 emit_pixel_interpolater_send(bld
,
2644 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2651 case nir_intrinsic_interp_var_at_sample
: {
2652 if (!wm_key
->multisample_fbo
) {
2653 /* From the ARB_gpu_shader5 specification:
2654 * "If multisample buffers are not available, the input varying
2655 * will be evaluated at the center of the pixel."
2657 emit_pixel_interpolater_send(bld
,
2658 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2666 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2669 unsigned msg_data
= const_sample
->i32
[0] << 4;
2671 emit_pixel_interpolater_send(bld
,
2672 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2675 brw_imm_ud(msg_data
),
2678 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2679 BRW_REGISTER_TYPE_UD
);
2681 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2682 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2683 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2684 bld
.exec_all().group(1, 0)
2685 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2686 emit_pixel_interpolater_send(bld
,
2687 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2693 /* Make a loop that sends a message to the pixel interpolater
2694 * for the sample number in each live channel. If there are
2695 * multiple channels with the same sample number then these
2696 * will be handled simultaneously with a single interation of
2699 bld
.emit(BRW_OPCODE_DO
);
2701 /* Get the next live sample number into sample_id_reg */
2702 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2704 /* Set the flag register so that we can perform the send
2705 * message on all channels that have the same sample number
2707 bld
.CMP(bld
.null_reg_ud(),
2708 sample_src
, sample_id
,
2709 BRW_CONDITIONAL_EQ
);
2710 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2711 bld
.exec_all().group(1, 0)
2712 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2714 emit_pixel_interpolater_send(bld
,
2715 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2720 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2722 /* Continue the loop if there are any live channels left */
2723 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2725 bld
.emit(BRW_OPCODE_WHILE
));
2732 case nir_intrinsic_interp_var_at_offset
: {
2733 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2736 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
2737 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
2739 emit_pixel_interpolater_send(bld
,
2740 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2743 brw_imm_ud(off_x
| (off_y
<< 4)),
2746 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2747 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2748 BRW_REGISTER_TYPE_F
);
2749 for (int i
= 0; i
< 2; i
++) {
2750 fs_reg temp
= vgrf(glsl_type::float_type
);
2751 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2752 fs_reg itemp
= vgrf(glsl_type::int_type
);
2753 bld
.MOV(itemp
, temp
); /* float to int */
2755 /* Clamp the upper end of the range to +7/16.
2756 * ARB_gpu_shader5 requires that we support a maximum offset
2757 * of +0.5, which isn't representable in a S0.4 value -- if
2758 * we didn't clamp it, we'd end up with -8/16, which is the
2759 * opposite of what the shader author wanted.
2761 * This is legal due to ARB_gpu_shader5's quantization
2764 * "Not all values of <offset> may be supported; x and y
2765 * offsets may be rounded to fixed-point values with the
2766 * number of fraction bits given by the
2767 * implementation-dependent constant
2768 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2770 set_condmod(BRW_CONDITIONAL_L
,
2771 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2774 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2775 emit_pixel_interpolater_send(bld
,
2786 unreachable("Invalid intrinsic");
2789 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2790 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2791 src
.type
= dest
.type
;
2793 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2794 dest
= offset(dest
, bld
, 1);
2799 nir_emit_intrinsic(bld
, instr
);
2805 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2806 nir_intrinsic_instr
*instr
)
2808 assert(stage
== MESA_SHADER_COMPUTE
);
2809 struct brw_cs_prog_data
*cs_prog_data
=
2810 (struct brw_cs_prog_data
*) prog_data
;
2813 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2814 dest
= get_nir_dest(instr
->dest
);
2816 switch (instr
->intrinsic
) {
2817 case nir_intrinsic_barrier
:
2819 cs_prog_data
->uses_barrier
= true;
2822 case nir_intrinsic_load_local_invocation_id
:
2823 case nir_intrinsic_load_work_group_id
: {
2824 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2825 fs_reg val
= nir_system_values
[sv
];
2826 assert(val
.file
!= BAD_FILE
);
2827 dest
.type
= val
.type
;
2828 for (unsigned i
= 0; i
< 3; i
++)
2829 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2833 case nir_intrinsic_load_num_work_groups
: {
2834 const unsigned surface
=
2835 cs_prog_data
->binding_table
.work_groups_start
;
2837 cs_prog_data
->uses_num_work_groups
= true;
2839 fs_reg surf_index
= brw_imm_ud(surface
);
2840 brw_mark_surface_used(prog_data
, surface
);
2842 /* Read the 3 GLuint components of gl_NumWorkGroups */
2843 for (unsigned i
= 0; i
< 3; i
++) {
2844 fs_reg read_result
=
2845 emit_untyped_read(bld
, surf_index
,
2847 1 /* dims */, 1 /* size */,
2848 BRW_PREDICATE_NONE
);
2849 read_result
.type
= dest
.type
;
2850 bld
.MOV(dest
, read_result
);
2851 dest
= offset(dest
, bld
, 1);
2856 case nir_intrinsic_shared_atomic_add
:
2857 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2859 case nir_intrinsic_shared_atomic_imin
:
2860 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2862 case nir_intrinsic_shared_atomic_umin
:
2863 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2865 case nir_intrinsic_shared_atomic_imax
:
2866 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2868 case nir_intrinsic_shared_atomic_umax
:
2869 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2871 case nir_intrinsic_shared_atomic_and
:
2872 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2874 case nir_intrinsic_shared_atomic_or
:
2875 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2877 case nir_intrinsic_shared_atomic_xor
:
2878 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2880 case nir_intrinsic_shared_atomic_exchange
:
2881 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2883 case nir_intrinsic_shared_atomic_comp_swap
:
2884 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2887 case nir_intrinsic_load_shared
: {
2888 assert(devinfo
->gen
>= 7);
2890 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2892 /* Get the offset to read from */
2894 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2896 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
2898 offset_reg
= vgrf(glsl_type::uint_type
);
2900 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2901 brw_imm_ud(instr
->const_index
[0]));
2904 /* Read the vector */
2905 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2907 instr
->num_components
,
2908 BRW_PREDICATE_NONE
);
2909 read_result
.type
= dest
.type
;
2910 for (int i
= 0; i
< instr
->num_components
; i
++)
2911 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2916 case nir_intrinsic_store_shared
: {
2917 assert(devinfo
->gen
>= 7);
2920 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2923 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2926 unsigned writemask
= instr
->const_index
[1];
2928 /* Combine groups of consecutive enabled channels in one write
2929 * message. We use ffs to find the first enabled channel and then ffs on
2930 * the bit-inverse, down-shifted writemask to determine the length of
2931 * the block of enabled bits.
2934 unsigned first_component
= ffs(writemask
) - 1;
2935 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2938 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2940 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
2941 4 * first_component
);
2943 offset_reg
= vgrf(glsl_type::uint_type
);
2945 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2946 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2949 emit_untyped_write(bld
, surf_index
, offset_reg
,
2950 offset(val_reg
, bld
, first_component
),
2951 1 /* dims */, length
,
2952 BRW_PREDICATE_NONE
);
2954 /* Clear the bits in the writemask that we just wrote, then try
2955 * again to see if more channels are left.
2957 writemask
&= (15 << (first_component
+ length
));
2964 nir_emit_intrinsic(bld
, instr
);
2970 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2973 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2974 dest
= get_nir_dest(instr
->dest
);
2976 switch (instr
->intrinsic
) {
2977 case nir_intrinsic_atomic_counter_inc
:
2978 case nir_intrinsic_atomic_counter_dec
:
2979 case nir_intrinsic_atomic_counter_read
: {
2980 /* Get the arguments of the atomic intrinsic. */
2981 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2982 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2983 instr
->const_index
[0]);
2986 /* Emit a surface read or atomic op. */
2987 switch (instr
->intrinsic
) {
2988 case nir_intrinsic_atomic_counter_read
:
2989 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2992 case nir_intrinsic_atomic_counter_inc
:
2993 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2994 fs_reg(), 1, 1, BRW_AOP_INC
);
2997 case nir_intrinsic_atomic_counter_dec
:
2998 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2999 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3003 unreachable("Unreachable");
3006 /* Assign the result. */
3007 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3009 /* Mark the surface as used. */
3010 brw_mark_surface_used(stage_prog_data
, surface
);
3014 case nir_intrinsic_image_load
:
3015 case nir_intrinsic_image_store
:
3016 case nir_intrinsic_image_atomic_add
:
3017 case nir_intrinsic_image_atomic_min
:
3018 case nir_intrinsic_image_atomic_max
:
3019 case nir_intrinsic_image_atomic_and
:
3020 case nir_intrinsic_image_atomic_or
:
3021 case nir_intrinsic_image_atomic_xor
:
3022 case nir_intrinsic_image_atomic_exchange
:
3023 case nir_intrinsic_image_atomic_comp_swap
: {
3024 using namespace image_access
;
3026 /* Get the referenced image variable and type. */
3027 const nir_variable
*var
= instr
->variables
[0]->var
;
3028 const glsl_type
*type
= var
->type
->without_array();
3029 const brw_reg_type base_type
= get_image_base_type(type
);
3031 /* Get some metadata from the image intrinsic. */
3032 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3033 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3034 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3035 const unsigned format
= var
->data
.image
.format
;
3037 /* Get the arguments of the image intrinsic. */
3038 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3039 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3040 BRW_REGISTER_TYPE_UD
);
3041 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3042 retype(get_nir_src(instr
->src
[2]), base_type
) :
3044 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3045 retype(get_nir_src(instr
->src
[3]), base_type
) :
3049 /* Emit an image load, store or atomic op. */
3050 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3051 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3053 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3054 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3055 var
->data
.image
.write_only
? GL_NONE
: format
);
3058 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3059 surf_dims
, arr_dims
, info
->dest_components
,
3060 get_image_atomic_op(instr
->intrinsic
, type
));
3062 /* Assign the result. */
3063 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3064 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3065 offset(tmp
, bld
, c
));
3069 case nir_intrinsic_memory_barrier_atomic_counter
:
3070 case nir_intrinsic_memory_barrier_buffer
:
3071 case nir_intrinsic_memory_barrier_image
:
3072 case nir_intrinsic_memory_barrier
: {
3073 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
3074 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3079 case nir_intrinsic_group_memory_barrier
:
3080 case nir_intrinsic_memory_barrier_shared
:
3081 /* We treat these workgroup-level barriers as no-ops. This should be
3082 * safe at present and as long as:
3084 * - Memory access instructions are not subsequently reordered by the
3085 * compiler back-end.
3087 * - All threads from a given compute shader workgroup fit within a
3088 * single subslice and therefore talk to the same HDC shared unit
3089 * what supposedly guarantees ordering and coherency between threads
3090 * from the same workgroup. This may change in the future when we
3091 * start splitting workgroups across multiple subslices.
3093 * - The context is not in fault-and-stream mode, which could cause
3094 * memory transactions (including to SLM) prior to the barrier to be
3095 * replayed after the barrier if a pagefault occurs. This shouldn't
3096 * be a problem up to and including SKL because fault-and-stream is
3097 * not usable due to hardware issues, but that's likely to change in
3102 case nir_intrinsic_shader_clock
: {
3103 /* We cannot do anything if there is an event, so ignore it for now */
3104 fs_reg shader_clock
= get_timestamp(bld
);
3105 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3107 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3111 case nir_intrinsic_image_size
: {
3112 /* Get the referenced image variable and type. */
3113 const nir_variable
*var
= instr
->variables
[0]->var
;
3114 const glsl_type
*type
= var
->type
->without_array();
3116 /* Get the size of the image. */
3117 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3118 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3120 /* For 1DArray image types, the array index is stored in the Z component.
3121 * Fix this by swizzling the Z component to the Y component.
3123 const bool is_1d_array_image
=
3124 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3125 type
->sampler_array
;
3127 /* For CubeArray images, we should count the number of cubes instead
3128 * of the number of faces. Fix it by dividing the (Z component) by 6.
3130 const bool is_cube_array_image
=
3131 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3132 type
->sampler_array
;
3134 /* Copy all the components. */
3135 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3136 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3137 if ((int)c
>= type
->coordinate_components()) {
3138 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3140 } else if (c
== 1 && is_1d_array_image
) {
3141 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3142 offset(size
, bld
, 2));
3143 } else if (c
== 2 && is_cube_array_image
) {
3144 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3145 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3146 offset(size
, bld
, c
), brw_imm_d(6));
3148 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3149 offset(size
, bld
, c
));
3156 case nir_intrinsic_image_samples
:
3157 /* The driver does not support multi-sampled images. */
3158 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3161 case nir_intrinsic_load_uniform
: {
3162 /* Offsets are in bytes but they should always be multiples of 4 */
3163 assert(instr
->const_index
[0] % 4 == 0);
3165 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3167 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3169 /* Offsets are in bytes but they should always be multiples of 4 */
3170 assert(const_offset
->u32
[0] % 4 == 0);
3171 src
.reg_offset
= const_offset
->u32
[0] / 4;
3173 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3174 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3177 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3178 BRW_REGISTER_TYPE_UD
);
3180 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3181 * go past the end of the uniform. In order to keep the n'th
3182 * component from running past, we subtract off the size of all but
3183 * one component of the vector.
3185 assert(instr
->const_index
[1] >= instr
->num_components
* 4);
3186 unsigned read_size
= instr
->const_index
[1] -
3187 (instr
->num_components
- 1) * 4;
3189 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3190 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3191 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3192 indirect
, brw_imm_ud(read_size
));
3198 case nir_intrinsic_load_ubo
: {
3199 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3203 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3204 const_index
->u32
[0];
3205 surf_index
= brw_imm_ud(index
);
3206 brw_mark_surface_used(prog_data
, index
);
3208 /* The block index is not a constant. Evaluate the index expression
3209 * per-channel and add the base UBO index; we have to select a value
3210 * from any live channel.
3212 surf_index
= vgrf(glsl_type::uint_type
);
3213 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3214 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3215 surf_index
= bld
.emit_uniformize(surf_index
);
3217 /* Assume this may touch any UBO. It would be nice to provide
3218 * a tighter bound, but the array information is already lowered away.
3220 brw_mark_surface_used(prog_data
,
3221 stage_prog_data
->binding_table
.ubo_start
+
3222 nir
->info
.num_ubos
- 1);
3225 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3226 if (const_offset
== NULL
) {
3227 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3228 BRW_REGISTER_TYPE_UD
);
3230 for (int i
= 0; i
< instr
->num_components
; i
++)
3231 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3232 base_offset
, i
* 4);
3234 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
3235 packed_consts
.type
= dest
.type
;
3237 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u32
[0] & ~15);
3238 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
3239 surf_index
, const_offset_reg
);
3241 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
3242 packed_consts
.set_smear(const_offset
->u32
[0] % 16 / 4 + i
);
3244 /* The std140 packing rules don't allow vectors to cross 16-byte
3245 * boundaries, and a reg is 32 bytes.
3247 assert(packed_consts
.subreg_offset
< 32);
3249 bld
.MOV(dest
, packed_consts
);
3250 dest
= offset(dest
, bld
, 1);
3256 case nir_intrinsic_load_ssbo
: {
3257 assert(devinfo
->gen
>= 7);
3259 nir_const_value
*const_uniform_block
=
3260 nir_src_as_const_value(instr
->src
[0]);
3263 if (const_uniform_block
) {
3264 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3265 const_uniform_block
->u32
[0];
3266 surf_index
= brw_imm_ud(index
);
3267 brw_mark_surface_used(prog_data
, index
);
3269 surf_index
= vgrf(glsl_type::uint_type
);
3270 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3271 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3273 /* Assume this may touch any UBO. It would be nice to provide
3274 * a tighter bound, but the array information is already lowered away.
3276 brw_mark_surface_used(prog_data
,
3277 stage_prog_data
->binding_table
.ssbo_start
+
3278 nir
->info
.num_ssbos
- 1);
3282 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3284 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3286 offset_reg
= get_nir_src(instr
->src
[1]);
3289 /* Read the vector */
3290 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
3292 instr
->num_components
,
3293 BRW_PREDICATE_NONE
);
3294 read_result
.type
= dest
.type
;
3295 for (int i
= 0; i
< instr
->num_components
; i
++)
3296 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
3301 case nir_intrinsic_load_input
: {
3303 if (stage
== MESA_SHADER_VERTEX
) {
3304 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3306 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3307 instr
->const_index
[0]);
3310 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3311 assert(const_offset
&& "Indirect input loads not allowed");
3312 src
= offset(src
, bld
, const_offset
->u32
[0]);
3314 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3315 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3320 case nir_intrinsic_store_ssbo
: {
3321 assert(devinfo
->gen
>= 7);
3325 nir_const_value
*const_uniform_block
=
3326 nir_src_as_const_value(instr
->src
[1]);
3327 if (const_uniform_block
) {
3328 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3329 const_uniform_block
->u32
[0];
3330 surf_index
= brw_imm_ud(index
);
3331 brw_mark_surface_used(prog_data
, index
);
3333 surf_index
= vgrf(glsl_type::uint_type
);
3334 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3335 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3337 brw_mark_surface_used(prog_data
,
3338 stage_prog_data
->binding_table
.ssbo_start
+
3339 nir
->info
.num_ssbos
- 1);
3343 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3346 unsigned writemask
= instr
->const_index
[0];
3348 /* Combine groups of consecutive enabled channels in one write
3349 * message. We use ffs to find the first enabled channel and then ffs on
3350 * the bit-inverse, down-shifted writemask to determine the length of
3351 * the block of enabled bits.
3354 unsigned first_component
= ffs(writemask
) - 1;
3355 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3358 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3360 offset_reg
= brw_imm_ud(const_offset
->u32
[0] + 4 * first_component
);
3362 offset_reg
= vgrf(glsl_type::uint_type
);
3364 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3365 brw_imm_ud(4 * first_component
));
3368 emit_untyped_write(bld
, surf_index
, offset_reg
,
3369 offset(val_reg
, bld
, first_component
),
3370 1 /* dims */, length
,
3371 BRW_PREDICATE_NONE
);
3373 /* Clear the bits in the writemask that we just wrote, then try
3374 * again to see if more channels are left.
3376 writemask
&= (15 << (first_component
+ length
));
3381 case nir_intrinsic_store_output
: {
3382 fs_reg src
= get_nir_src(instr
->src
[0]);
3383 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3384 instr
->const_index
[0]);
3386 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3387 assert(const_offset
&& "Indirect output stores not allowed");
3388 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3390 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3391 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
3396 case nir_intrinsic_ssbo_atomic_add
:
3397 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
3399 case nir_intrinsic_ssbo_atomic_imin
:
3400 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
3402 case nir_intrinsic_ssbo_atomic_umin
:
3403 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
3405 case nir_intrinsic_ssbo_atomic_imax
:
3406 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
3408 case nir_intrinsic_ssbo_atomic_umax
:
3409 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
3411 case nir_intrinsic_ssbo_atomic_and
:
3412 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
3414 case nir_intrinsic_ssbo_atomic_or
:
3415 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
3417 case nir_intrinsic_ssbo_atomic_xor
:
3418 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
3420 case nir_intrinsic_ssbo_atomic_exchange
:
3421 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
3423 case nir_intrinsic_ssbo_atomic_comp_swap
:
3424 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3427 case nir_intrinsic_get_buffer_size
: {
3428 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
3429 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
3430 int reg_width
= dispatch_width
/ 8;
3433 fs_reg source
= brw_imm_d(0);
3435 int mlen
= 1 * reg_width
;
3437 /* A resinfo's sampler message is used to get the buffer size.
3438 * The SIMD8's writeback message consists of four registers and
3439 * SIMD16's writeback message consists of 8 destination registers
3440 * (two per each component), although we are only interested on the
3441 * first component, where resinfo returns the buffer size for
3444 int regs_written
= 4 * mlen
;
3445 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
3446 BRW_REGISTER_TYPE_UD
);
3447 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
3448 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
3449 BRW_REGISTER_TYPE_UD
);
3450 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
3451 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
3452 src_payload
, brw_imm_ud(index
));
3453 inst
->header_size
= 0;
3455 inst
->regs_written
= regs_written
;
3457 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
3459 brw_mark_surface_used(prog_data
, index
);
3464 unreachable("unknown intrinsic");
3469 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
3470 int op
, nir_intrinsic_instr
*instr
)
3473 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3474 dest
= get_nir_dest(instr
->dest
);
3477 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3478 if (const_surface
) {
3479 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3480 const_surface
->u32
[0];
3481 surface
= brw_imm_ud(surf_index
);
3482 brw_mark_surface_used(prog_data
, surf_index
);
3484 surface
= vgrf(glsl_type::uint_type
);
3485 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3486 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3488 /* Assume this may touch any SSBO. This is the same we do for other
3489 * UBO/SSBO accesses with non-constant surface.
3491 brw_mark_surface_used(prog_data
,
3492 stage_prog_data
->binding_table
.ssbo_start
+
3493 nir
->info
.num_ssbos
- 1);
3496 fs_reg offset
= get_nir_src(instr
->src
[1]);
3497 fs_reg data1
= get_nir_src(instr
->src
[2]);
3499 if (op
== BRW_AOP_CMPWR
)
3500 data2
= get_nir_src(instr
->src
[3]);
3502 /* Emit the actual atomic operation operation */
3504 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3506 1 /* dims */, 1 /* rsize */,
3508 BRW_PREDICATE_NONE
);
3509 dest
.type
= atomic_result
.type
;
3510 bld
.MOV(dest
, atomic_result
);
3514 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3515 int op
, nir_intrinsic_instr
*instr
)
3518 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3519 dest
= get_nir_dest(instr
->dest
);
3521 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3522 fs_reg offset
= get_nir_src(instr
->src
[0]);
3523 fs_reg data1
= get_nir_src(instr
->src
[1]);
3525 if (op
== BRW_AOP_CMPWR
)
3526 data2
= get_nir_src(instr
->src
[2]);
3528 /* Emit the actual atomic operation operation */
3530 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3532 1 /* dims */, 1 /* rsize */,
3534 BRW_PREDICATE_NONE
);
3535 dest
.type
= atomic_result
.type
;
3536 bld
.MOV(dest
, atomic_result
);
3540 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3542 unsigned texture
= instr
->texture_index
;
3543 unsigned sampler
= instr
->sampler_index
;
3545 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3547 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
3548 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
3550 int lod_components
= 0;
3552 /* The hardware requires a LOD for buffer textures */
3553 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
3554 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
3556 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
3557 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
3558 switch (instr
->src
[i
].src_type
) {
3559 case nir_tex_src_bias
:
3560 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3562 case nir_tex_src_comparitor
:
3563 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
3565 case nir_tex_src_coord
:
3566 switch (instr
->op
) {
3568 case nir_texop_txf_ms
:
3569 case nir_texop_samples_identical
:
3570 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
3573 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
3577 case nir_tex_src_ddx
:
3578 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3579 lod_components
= nir_tex_instr_src_size(instr
, i
);
3581 case nir_tex_src_ddy
:
3582 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
3584 case nir_tex_src_lod
:
3585 switch (instr
->op
) {
3587 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3590 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_D
);
3593 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
3597 case nir_tex_src_ms_index
:
3598 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
3601 case nir_tex_src_offset
: {
3602 nir_const_value
*const_offset
=
3603 nir_src_as_const_value(instr
->src
[i
].src
);
3605 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
3606 if (header_bits
!= 0)
3607 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
3609 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
3610 retype(src
, BRW_REGISTER_TYPE_D
);
3615 case nir_tex_src_projector
:
3616 unreachable("should be lowered");
3618 case nir_tex_src_texture_offset
: {
3619 /* Figure out the highest possible texture index and mark it as used */
3620 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3621 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3622 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3624 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3626 brw_mark_surface_used(prog_data
, max_used
);
3628 /* Emit code to evaluate the actual indexing expression */
3629 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3630 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
3631 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
3635 case nir_tex_src_sampler_offset
: {
3636 /* Emit code to evaluate the actual indexing expression */
3637 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3638 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
3639 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
3644 unreachable("unknown texture source");
3648 if (instr
->op
== nir_texop_txf_ms
||
3649 instr
->op
== nir_texop_samples_identical
) {
3650 if (devinfo
->gen
>= 7 &&
3651 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3652 srcs
[TEX_LOGICAL_SRC_MCS
] =
3653 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
3654 instr
->coord_components
,
3655 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3657 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
3661 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
3662 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
3664 if (instr
->op
== nir_texop_query_levels
) {
3665 /* textureQueryLevels() is implemented in terms of TXS so we need to
3666 * pass a valid LOD argument.
3668 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
3669 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
3673 switch (instr
->op
) {
3675 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
3678 opcode
= FS_OPCODE_TXB_LOGICAL
;
3681 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
3684 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
3687 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
3689 case nir_texop_txf_ms
:
3690 if ((key_tex
->msaa_16
& (1 << sampler
)))
3691 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
3693 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
3695 case nir_texop_query_levels
:
3697 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
3700 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
3703 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
3704 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
3705 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
3707 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
3709 case nir_texop_texture_samples
: {
3710 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3712 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 4);
3713 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, tmp
,
3714 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3715 srcs
[TEX_LOGICAL_SRC_SURFACE
],
3716 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
3718 inst
->header_size
= 1;
3719 inst
->base_mrf
= -1;
3720 inst
->regs_written
= 4 * (dispatch_width
/ 8);
3722 /* Pick off the one component we care about */
3726 case nir_texop_samples_identical
: {
3727 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3729 /* If mcs is an immediate value, it means there is no MCS. In that case
3730 * just return false.
3732 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
3733 bld
.MOV(dst
, brw_imm_ud(0u));
3734 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
3735 fs_reg tmp
= vgrf(glsl_type::uint_type
);
3736 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
3737 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
3738 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
3740 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
3741 BRW_CONDITIONAL_EQ
);
3746 unreachable("unknown texture opcode");
3749 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
3750 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
3752 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
3753 if (devinfo
->gen
>= 9 &&
3754 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
3755 unsigned write_mask
= instr
->dest
.is_ssa
?
3756 nir_ssa_def_components_read(&instr
->dest
.ssa
):
3757 (1 << dest_size
) - 1;
3758 assert(write_mask
!= 0); /* dead code should have been eliminated */
3759 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
3761 inst
->regs_written
= 4 * dispatch_width
/ 8;
3764 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
3765 inst
->shadow_compare
= true;
3767 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
3768 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
3770 if (instr
->op
== nir_texop_tg4
) {
3771 if (instr
->component
== 1 &&
3772 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
3773 /* gather4 sampler is broken for green channel on RG32F --
3774 * we must ask for blue instead.
3776 inst
->offset
|= 2 << 16;
3778 inst
->offset
|= instr
->component
<< 16;
3781 if (devinfo
->gen
== 6)
3782 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
3786 for (unsigned i
= 0; i
< dest_size
; i
++)
3787 nir_dest
[i
] = offset(dst
, bld
, i
);
3789 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
3792 if (instr
->op
== nir_texop_query_levels
) {
3793 /* # levels is in .w */
3794 nir_dest
[0] = offset(dst
, bld
, 3);
3795 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
3796 (devinfo
->gen
< 7 || is_cube_array
)) {
3797 fs_reg depth
= offset(dst
, bld
, 2);
3798 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
3800 if (is_cube_array
) {
3801 /* fixup #layers for cube map arrays */
3802 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
3803 } else if (devinfo
->gen
< 7) {
3804 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
3805 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
3808 nir_dest
[2] = fixed_depth
;
3811 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
3815 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3817 switch (instr
->type
) {
3818 case nir_jump_break
:
3819 bld
.emit(BRW_OPCODE_BREAK
);
3821 case nir_jump_continue
:
3822 bld
.emit(BRW_OPCODE_CONTINUE
);
3824 case nir_jump_return
:
3826 unreachable("unknown jump");