2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (key
->force_dual_color_blend
&&
134 var
->data
.location
== FRAG_RESULT_DATA1
) {
135 this->dual_src_output
= reg
;
136 this->do_dual_src
= true;
137 } else if (var
->data
.index
> 0) {
138 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
139 assert(var
->data
.index
== 1);
140 this->dual_src_output
= reg
;
141 this->do_dual_src
= true;
142 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
143 /* Writing gl_FragColor outputs to all color regions. */
144 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
145 this->outputs
[i
] = reg
;
146 this->output_components
[i
] = 4;
148 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
149 this->frag_depth
= reg
;
150 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
151 this->frag_stencil
= reg
;
152 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
153 this->sample_mask
= reg
;
155 int vector_elements
= var
->type
->without_array()->vector_elements
;
157 /* gl_FragData or a user-defined FS output */
158 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
159 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
161 /* General color output. */
162 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
163 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
164 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
165 this->output_components
[output
] = vector_elements
;
170 unreachable("unhandled shader stage");
176 fs_visitor::nir_setup_uniforms()
178 if (dispatch_width
!= 8)
181 uniforms
= nir
->num_uniforms
/ 4;
183 nir_foreach_variable(var
, &nir
->uniforms
) {
184 /* UBO's and atomics don't take up space in the uniform file */
185 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
188 if (type_size_scalar(var
->type
) > 0)
189 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
194 emit_system_values_block(nir_block
*block
, void *void_visitor
)
196 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
199 nir_foreach_instr(block
, instr
) {
200 if (instr
->type
!= nir_instr_type_intrinsic
)
203 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
204 switch (intrin
->intrinsic
) {
205 case nir_intrinsic_load_vertex_id
:
206 unreachable("should be lowered by lower_vertex_id().");
208 case nir_intrinsic_load_vertex_id_zero_base
:
209 assert(v
->stage
== MESA_SHADER_VERTEX
);
210 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
211 if (reg
->file
== BAD_FILE
)
212 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
215 case nir_intrinsic_load_base_vertex
:
216 assert(v
->stage
== MESA_SHADER_VERTEX
);
217 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
218 if (reg
->file
== BAD_FILE
)
219 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
222 case nir_intrinsic_load_instance_id
:
223 assert(v
->stage
== MESA_SHADER_VERTEX
);
224 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
225 if (reg
->file
== BAD_FILE
)
226 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
229 case nir_intrinsic_load_base_instance
:
230 assert(v
->stage
== MESA_SHADER_VERTEX
);
231 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
232 if (reg
->file
== BAD_FILE
)
233 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
236 case nir_intrinsic_load_draw_id
:
237 assert(v
->stage
== MESA_SHADER_VERTEX
);
238 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
239 if (reg
->file
== BAD_FILE
)
240 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
243 case nir_intrinsic_load_invocation_id
:
244 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
245 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
246 if (reg
->file
== BAD_FILE
) {
247 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
248 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
249 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
250 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
255 case nir_intrinsic_load_sample_pos
:
256 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
257 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
258 if (reg
->file
== BAD_FILE
)
259 *reg
= *v
->emit_samplepos_setup();
262 case nir_intrinsic_load_sample_id
:
263 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
264 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
265 if (reg
->file
== BAD_FILE
)
266 *reg
= *v
->emit_sampleid_setup();
269 case nir_intrinsic_load_sample_mask_in
:
270 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
271 assert(v
->devinfo
->gen
>= 7);
272 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
273 if (reg
->file
== BAD_FILE
)
274 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
275 BRW_REGISTER_TYPE_D
));
278 case nir_intrinsic_load_local_invocation_id
:
279 assert(v
->stage
== MESA_SHADER_COMPUTE
);
280 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
281 if (reg
->file
== BAD_FILE
)
282 *reg
= *v
->emit_cs_local_invocation_id_setup();
285 case nir_intrinsic_load_work_group_id
:
286 assert(v
->stage
== MESA_SHADER_COMPUTE
);
287 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
288 if (reg
->file
== BAD_FILE
)
289 *reg
= *v
->emit_cs_work_group_id_setup();
292 case nir_intrinsic_load_helper_invocation
:
293 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
294 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
295 if (reg
->file
== BAD_FILE
) {
296 const fs_builder abld
=
297 v
->bld
.annotate("gl_HelperInvocation", NULL
);
299 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
300 * pixel mask is in g1.7 of the thread payload.
302 * We move the per-channel pixel enable bit to the low bit of each
303 * channel by shifting the byte containing the pixel mask by the
304 * vector immediate 0x76543210UV.
306 * The region of <1,8,0> reads only 1 byte (the pixel masks for
307 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
308 * masks for 2 and 3) in SIMD16.
310 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
312 stride(byte_offset(retype(brw_vec1_grf(1, 0),
313 BRW_REGISTER_TYPE_UB
), 28),
315 brw_imm_uv(0x76543210));
317 /* A set bit in the pixel mask means the channel is enabled, but
318 * that is the opposite of gl_HelperInvocation so we need to invert
321 * The negate source-modifier bit of logical instructions on Gen8+
322 * performs 1's complement negation, so we can use that instead of
325 fs_reg inverted
= negate(shifted
);
326 if (v
->devinfo
->gen
< 8) {
327 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
328 abld
.NOT(inverted
, shifted
);
331 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
332 * with 1 and negating.
334 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
335 abld
.AND(anded
, inverted
, brw_imm_uw(1));
337 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
338 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
352 fs_visitor::nir_emit_system_values()
354 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
355 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
356 nir_system_values
[i
] = fs_reg();
359 nir_foreach_function(nir
, function
) {
360 assert(strcmp(function
->name
, "main") == 0);
361 assert(function
->impl
);
362 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
367 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
369 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
370 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
371 nir_locals
[i
] = fs_reg();
374 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
375 unsigned array_elems
=
376 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
377 unsigned size
= array_elems
* reg
->num_components
;
378 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
381 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
384 nir_emit_cf_list(&impl
->body
);
388 fs_visitor::nir_emit_cf_list(exec_list
*list
)
390 exec_list_validate(list
);
391 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
392 switch (node
->type
) {
394 nir_emit_if(nir_cf_node_as_if(node
));
397 case nir_cf_node_loop
:
398 nir_emit_loop(nir_cf_node_as_loop(node
));
401 case nir_cf_node_block
:
402 nir_emit_block(nir_cf_node_as_block(node
));
406 unreachable("Invalid CFG node block");
412 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
414 /* first, put the condition into f0 */
415 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
416 retype(get_nir_src(if_stmt
->condition
),
417 BRW_REGISTER_TYPE_D
));
418 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
420 bld
.IF(BRW_PREDICATE_NORMAL
);
422 nir_emit_cf_list(&if_stmt
->then_list
);
424 /* note: if the else is empty, dead CF elimination will remove it */
425 bld
.emit(BRW_OPCODE_ELSE
);
427 nir_emit_cf_list(&if_stmt
->else_list
);
429 bld
.emit(BRW_OPCODE_ENDIF
);
433 fs_visitor::nir_emit_loop(nir_loop
*loop
)
435 bld
.emit(BRW_OPCODE_DO
);
437 nir_emit_cf_list(&loop
->body
);
439 bld
.emit(BRW_OPCODE_WHILE
);
443 fs_visitor::nir_emit_block(nir_block
*block
)
445 nir_foreach_instr(block
, instr
) {
446 nir_emit_instr(instr
);
451 fs_visitor::nir_emit_instr(nir_instr
*instr
)
453 const fs_builder abld
= bld
.annotate(NULL
, instr
);
455 switch (instr
->type
) {
456 case nir_instr_type_alu
:
457 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
460 case nir_instr_type_intrinsic
:
462 case MESA_SHADER_VERTEX
:
463 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
465 case MESA_SHADER_TESS_EVAL
:
466 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
468 case MESA_SHADER_GEOMETRY
:
469 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
471 case MESA_SHADER_FRAGMENT
:
472 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 case MESA_SHADER_COMPUTE
:
475 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
478 unreachable("unsupported shader stage");
482 case nir_instr_type_tex
:
483 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
486 case nir_instr_type_load_const
:
487 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
490 case nir_instr_type_ssa_undef
:
491 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
494 case nir_instr_type_jump
:
495 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
499 unreachable("unknown instruction type");
504 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
505 const fs_reg
&result
)
507 if (!instr
->src
[0].src
.is_ssa
||
508 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
511 nir_intrinsic_instr
*src0
=
512 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
514 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
517 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
518 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
521 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
522 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
525 fs_reg tmp
= vgrf(glsl_type::int_type
);
527 if (devinfo
->gen
>= 6) {
528 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
529 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
531 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
533 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
534 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
536 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
538 * This negation looks like it's safe in practice, because bits 0:4 will
539 * surely be TRIANGLES
542 if (value1
->f
[0] == -1.0f
) {
546 tmp
.type
= BRW_REGISTER_TYPE_W
;
547 tmp
.subreg_offset
= 2;
550 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
552 tmp
.type
= BRW_REGISTER_TYPE_D
;
553 tmp
.subreg_offset
= 0;
556 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
557 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
559 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
561 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
562 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
564 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
566 * This negation looks like it's safe in practice, because bits 0:4 will
567 * surely be TRIANGLES
570 if (value1
->f
[0] == -1.0f
) {
574 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
576 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
582 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
584 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
587 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
588 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
591 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
592 op
[i
] = get_nir_src(instr
->src
[i
].src
);
593 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
594 op
[i
].abs
= instr
->src
[i
].abs
;
595 op
[i
].negate
= instr
->src
[i
].negate
;
598 /* We get a bunch of mov's out of the from_ssa pass and they may still
599 * be vectorized. We'll handle them as a special-case. We'll also
600 * handle vecN here because it's basically the same thing.
608 fs_reg temp
= result
;
609 bool need_extra_copy
= false;
610 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
611 if (!instr
->src
[i
].src
.is_ssa
&&
612 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
613 need_extra_copy
= true;
614 temp
= bld
.vgrf(result
.type
, 4);
619 for (unsigned i
= 0; i
< 4; i
++) {
620 if (!(instr
->dest
.write_mask
& (1 << i
)))
623 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
624 inst
= bld
.MOV(offset(temp
, bld
, i
),
625 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
627 inst
= bld
.MOV(offset(temp
, bld
, i
),
628 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
630 inst
->saturate
= instr
->dest
.saturate
;
633 /* In this case the source and destination registers were the same,
634 * so we need to insert an extra set of moves in order to deal with
637 if (need_extra_copy
) {
638 for (unsigned i
= 0; i
< 4; i
++) {
639 if (!(instr
->dest
.write_mask
& (1 << i
)))
642 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
651 /* At this point, we have dealt with any instruction that operates on
652 * more than a single channel. Therefore, we can just adjust the source
653 * and destination registers for that channel and emit the instruction.
655 unsigned channel
= 0;
656 if (nir_op_infos
[instr
->op
].output_size
== 0) {
657 /* Since NIR is doing the scalarizing for us, we should only ever see
658 * vectorized operations with a single channel.
660 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
661 channel
= ffs(instr
->dest
.write_mask
) - 1;
663 result
= offset(result
, bld
, channel
);
666 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
667 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
668 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
674 inst
= bld
.MOV(result
, op
[0]);
675 inst
->saturate
= instr
->dest
.saturate
;
680 bld
.MOV(result
, op
[0]);
684 /* AND(val, 0x80000000) gives the sign bit.
686 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
689 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
691 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
692 op
[0].type
= BRW_REGISTER_TYPE_UD
;
693 result
.type
= BRW_REGISTER_TYPE_UD
;
694 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
696 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
697 inst
->predicate
= BRW_PREDICATE_NORMAL
;
698 if (instr
->dest
.saturate
) {
699 inst
= bld
.MOV(result
, result
);
700 inst
->saturate
= true;
706 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
707 * -> non-negative val generates 0x00000000.
708 * Predicated OR sets 1 if val is positive.
710 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
711 bld
.ASR(result
, op
[0], brw_imm_d(31));
712 inst
= bld
.OR(result
, result
, brw_imm_d(1));
713 inst
->predicate
= BRW_PREDICATE_NORMAL
;
717 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
718 inst
->saturate
= instr
->dest
.saturate
;
722 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
723 inst
->saturate
= instr
->dest
.saturate
;
727 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
728 inst
->saturate
= instr
->dest
.saturate
;
732 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
737 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
742 if (fs_key
->high_quality_derivatives
) {
743 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
745 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
749 case nir_op_fddx_fine
:
750 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
751 inst
->saturate
= instr
->dest
.saturate
;
753 case nir_op_fddx_coarse
:
754 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
755 inst
->saturate
= instr
->dest
.saturate
;
758 if (fs_key
->high_quality_derivatives
) {
759 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
760 brw_imm_d(fs_key
->render_to_fbo
));
762 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
763 brw_imm_d(fs_key
->render_to_fbo
));
765 inst
->saturate
= instr
->dest
.saturate
;
767 case nir_op_fddy_fine
:
768 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
769 brw_imm_d(fs_key
->render_to_fbo
));
770 inst
->saturate
= instr
->dest
.saturate
;
772 case nir_op_fddy_coarse
:
773 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
774 brw_imm_d(fs_key
->render_to_fbo
));
775 inst
->saturate
= instr
->dest
.saturate
;
780 inst
= bld
.ADD(result
, op
[0], op
[1]);
781 inst
->saturate
= instr
->dest
.saturate
;
785 inst
= bld
.MUL(result
, op
[0], op
[1]);
786 inst
->saturate
= instr
->dest
.saturate
;
790 bld
.MUL(result
, op
[0], op
[1]);
793 case nir_op_imul_high
:
794 case nir_op_umul_high
:
795 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
800 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
803 case nir_op_uadd_carry
:
804 unreachable("Should have been lowered by carry_to_arith().");
806 case nir_op_usub_borrow
:
807 unreachable("Should have been lowered by borrow_to_arith().");
810 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
816 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
822 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
827 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
832 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
836 if (devinfo
->gen
>= 8) {
837 op
[0] = resolve_source_modifiers(op
[0]);
839 bld
.NOT(result
, op
[0]);
842 if (devinfo
->gen
>= 8) {
843 op
[0] = resolve_source_modifiers(op
[0]);
844 op
[1] = resolve_source_modifiers(op
[1]);
846 bld
.XOR(result
, op
[0], op
[1]);
849 if (devinfo
->gen
>= 8) {
850 op
[0] = resolve_source_modifiers(op
[0]);
851 op
[1] = resolve_source_modifiers(op
[1]);
853 bld
.OR(result
, op
[0], op
[1]);
856 if (devinfo
->gen
>= 8) {
857 op
[0] = resolve_source_modifiers(op
[0]);
858 op
[1] = resolve_source_modifiers(op
[1]);
860 bld
.AND(result
, op
[0], op
[1]);
866 case nir_op_ball_fequal2
:
867 case nir_op_ball_iequal2
:
868 case nir_op_ball_fequal3
:
869 case nir_op_ball_iequal3
:
870 case nir_op_ball_fequal4
:
871 case nir_op_ball_iequal4
:
872 case nir_op_bany_fnequal2
:
873 case nir_op_bany_inequal2
:
874 case nir_op_bany_fnequal3
:
875 case nir_op_bany_inequal3
:
876 case nir_op_bany_fnequal4
:
877 case nir_op_bany_inequal4
:
878 unreachable("Lowered by nir_lower_alu_reductions");
880 case nir_op_fnoise1_1
:
881 case nir_op_fnoise1_2
:
882 case nir_op_fnoise1_3
:
883 case nir_op_fnoise1_4
:
884 case nir_op_fnoise2_1
:
885 case nir_op_fnoise2_2
:
886 case nir_op_fnoise2_3
:
887 case nir_op_fnoise2_4
:
888 case nir_op_fnoise3_1
:
889 case nir_op_fnoise3_2
:
890 case nir_op_fnoise3_3
:
891 case nir_op_fnoise3_4
:
892 case nir_op_fnoise4_1
:
893 case nir_op_fnoise4_2
:
894 case nir_op_fnoise4_3
:
895 case nir_op_fnoise4_4
:
896 unreachable("not reached: should be handled by lower_noise");
899 unreachable("not reached: should be handled by ldexp_to_arith()");
902 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
907 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
908 inst
->saturate
= instr
->dest
.saturate
;
913 bld
.MOV(result
, negate(op
[0]));
917 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
920 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
924 inst
= bld
.RNDZ(result
, op
[0]);
925 inst
->saturate
= instr
->dest
.saturate
;
929 op
[0].negate
= !op
[0].negate
;
930 fs_reg temp
= vgrf(glsl_type::float_type
);
931 bld
.RNDD(temp
, op
[0]);
933 inst
= bld
.MOV(result
, temp
);
934 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.RNDD(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
942 inst
= bld
.FRC(result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
945 case nir_op_fround_even
:
946 inst
= bld
.RNDE(result
, op
[0]);
947 inst
->saturate
= instr
->dest
.saturate
;
953 if (devinfo
->gen
>= 6) {
954 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
955 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
957 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
958 inst
= bld
.SEL(result
, op
[0], op
[1]);
959 inst
->predicate
= BRW_PREDICATE_NORMAL
;
961 inst
->saturate
= instr
->dest
.saturate
;
967 if (devinfo
->gen
>= 6) {
968 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
969 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
971 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
972 inst
= bld
.SEL(result
, op
[0], op
[1]);
973 inst
->predicate
= BRW_PREDICATE_NORMAL
;
975 inst
->saturate
= instr
->dest
.saturate
;
978 case nir_op_pack_snorm_2x16
:
979 case nir_op_pack_snorm_4x8
:
980 case nir_op_pack_unorm_2x16
:
981 case nir_op_pack_unorm_4x8
:
982 case nir_op_unpack_snorm_2x16
:
983 case nir_op_unpack_snorm_4x8
:
984 case nir_op_unpack_unorm_2x16
:
985 case nir_op_unpack_unorm_4x8
:
986 case nir_op_unpack_half_2x16
:
987 case nir_op_pack_half_2x16
:
988 unreachable("not reached: should be handled by lower_packing_builtins");
990 case nir_op_unpack_half_2x16_split_x
:
991 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
992 inst
->saturate
= instr
->dest
.saturate
;
994 case nir_op_unpack_half_2x16_split_y
:
995 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
996 inst
->saturate
= instr
->dest
.saturate
;
1000 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1004 case nir_op_bitfield_reverse
:
1005 bld
.BFREV(result
, op
[0]);
1008 case nir_op_bit_count
:
1009 bld
.CBIT(result
, op
[0]);
1012 case nir_op_ufind_msb
:
1013 case nir_op_ifind_msb
: {
1014 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1016 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1017 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1018 * subtract the result from 31 to convert the MSB count into an LSB count.
1020 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1022 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1023 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1024 inst
->src
[0].negate
= true;
1028 case nir_op_find_lsb
:
1029 bld
.FBL(result
, op
[0]);
1032 case nir_op_ubitfield_extract
:
1033 case nir_op_ibitfield_extract
:
1034 unreachable("should have been lowered");
1037 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1040 bld
.BFI1(result
, op
[0], op
[1]);
1043 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1046 case nir_op_bitfield_insert
:
1047 unreachable("not reached: should have been lowered");
1050 bld
.SHL(result
, op
[0], op
[1]);
1053 bld
.ASR(result
, op
[0], op
[1]);
1056 bld
.SHR(result
, op
[0], op
[1]);
1059 case nir_op_pack_half_2x16_split
:
1060 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1064 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1065 inst
->saturate
= instr
->dest
.saturate
;
1069 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1070 inst
->saturate
= instr
->dest
.saturate
;
1074 if (optimize_frontfacing_ternary(instr
, result
))
1077 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1078 inst
= bld
.SEL(result
, op
[1], op
[2]);
1079 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1082 case nir_op_extract_u8
:
1083 case nir_op_extract_i8
: {
1084 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1085 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1086 result
, op
[0], brw_imm_ud(byte
->u
[0]));
1090 case nir_op_extract_u16
:
1091 case nir_op_extract_i16
: {
1092 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1093 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1094 result
, op
[0], brw_imm_ud(word
->u
[0]));
1099 unreachable("unhandled instruction");
1102 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1103 * to sign extend the low bit to 0/~0
1105 if (devinfo
->gen
<= 5 &&
1106 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1107 fs_reg masked
= vgrf(glsl_type::int_type
);
1108 bld
.AND(masked
, result
, brw_imm_d(1));
1109 masked
.negate
= true;
1110 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1115 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1116 nir_load_const_instr
*instr
)
1118 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1120 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1121 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1123 nir_ssa_values
[instr
->def
.index
] = reg
;
1127 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1129 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1130 instr
->def
.num_components
);
1134 fs_visitor::get_nir_src(nir_src src
)
1138 reg
= nir_ssa_values
[src
.ssa
->index
];
1140 /* We don't handle indirects on locals */
1141 assert(src
.reg
.indirect
== NULL
);
1142 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1143 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1146 /* to avoid floating-point denorm flushing problems, set the type by
1147 * default to D - instructions that need floating point semantics will set
1148 * this to F if they need to
1150 return retype(reg
, BRW_REGISTER_TYPE_D
);
1154 fs_visitor::get_nir_dest(nir_dest dest
)
1157 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1158 dest
.ssa
.num_components
);
1159 return nir_ssa_values
[dest
.ssa
.index
];
1161 /* We don't handle indirects on locals */
1162 assert(dest
.reg
.indirect
== NULL
);
1163 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1164 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1169 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1171 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1172 BRW_REGISTER_TYPE_UD
);
1174 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1175 tail
= tail
->child
) {
1176 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1177 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1178 const unsigned size
= glsl_get_length(tail
->type
);
1179 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1180 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1181 image
= offset(image
, bld
, base
* element_size
);
1183 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1184 fs_reg tmp
= vgrf(glsl_type::int_type
);
1186 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1187 /* IVB hangs when trying to access an invalid surface index with
1188 * the dataport. According to the spec "if the index used to
1189 * select an individual element is negative or greater than or
1190 * equal to the size of the array, the results of the operation
1191 * are undefined but may not lead to termination" -- which is one
1192 * of the possible outcomes of the hang. Clamp the index to
1193 * prevent access outside of the array bounds.
1195 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1196 BRW_REGISTER_TYPE_UD
),
1197 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1199 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1202 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1204 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1206 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1214 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1217 for (unsigned i
= 0; i
< 4; i
++) {
1218 if (!((wr_mask
>> i
) & 1))
1221 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1222 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1223 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1224 if (new_inst
->src
[j
].file
== VGRF
)
1225 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1232 * Get the matching channel register datatype for an image intrinsic of the
1233 * specified GLSL image type.
1236 get_image_base_type(const glsl_type
*type
)
1238 switch ((glsl_base_type
)type
->sampler_type
) {
1239 case GLSL_TYPE_UINT
:
1240 return BRW_REGISTER_TYPE_UD
;
1242 return BRW_REGISTER_TYPE_D
;
1243 case GLSL_TYPE_FLOAT
:
1244 return BRW_REGISTER_TYPE_F
;
1246 unreachable("Not reached.");
1251 * Get the appropriate atomic op for an image atomic intrinsic.
1254 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1257 case nir_intrinsic_image_atomic_add
:
1259 case nir_intrinsic_image_atomic_min
:
1260 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1261 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1262 case nir_intrinsic_image_atomic_max
:
1263 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1264 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1265 case nir_intrinsic_image_atomic_and
:
1267 case nir_intrinsic_image_atomic_or
:
1269 case nir_intrinsic_image_atomic_xor
:
1271 case nir_intrinsic_image_atomic_exchange
:
1273 case nir_intrinsic_image_atomic_comp_swap
:
1274 return BRW_AOP_CMPWR
;
1276 unreachable("Not reachable.");
1281 emit_pixel_interpolater_send(const fs_builder
&bld
,
1286 glsl_interp_qualifier interpolation
)
1292 if (src
.file
== BAD_FILE
) {
1294 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1298 mlen
= 2 * bld
.dispatch_width() / 8;
1301 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1303 /* 2 floats per slot returned */
1304 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1305 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1311 * Computes 1 << x, given a D/UD register containing some value x.
1314 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1316 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1318 fs_reg result
= bld
.vgrf(x
.type
, 1);
1319 fs_reg one
= bld
.vgrf(x
.type
, 1);
1321 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1322 bld
.SHL(result
, one
, x
);
1327 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1329 assert(stage
== MESA_SHADER_GEOMETRY
);
1331 struct brw_gs_prog_data
*gs_prog_data
=
1332 (struct brw_gs_prog_data
*) prog_data
;
1334 /* We can only do EndPrimitive() functionality when the control data
1335 * consists of cut bits. Fortunately, the only time it isn't is when the
1336 * output type is points, in which case EndPrimitive() is a no-op.
1338 if (gs_prog_data
->control_data_format
!=
1339 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1343 /* Cut bits use one bit per vertex. */
1344 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1346 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1347 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1349 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1350 * vertex n, 0 otherwise. So all we need to do here is mark bit
1351 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1352 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1353 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1355 * Note that if EndPrimitive() is called before emitting any vertices, this
1356 * will cause us to set bit 31 of the control_data_bits register to 1.
1357 * That's fine because:
1359 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1360 * output, so the hardware will ignore cut bit 31.
1362 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1363 * last vertex, so setting cut bit 31 has no effect (since the primitive
1364 * is automatically ended when the GS terminates).
1366 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1367 * control_data_bits register to 0 when the first vertex is emitted.
1370 const fs_builder abld
= bld
.annotate("end primitive");
1372 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1373 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1374 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1375 fs_reg mask
= intexp2(abld
, prev_count
);
1376 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1377 * attention to the lower 5 bits of its second source argument, so on this
1378 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1379 * ((vertex_count - 1) % 32).
1381 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1385 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1387 assert(stage
== MESA_SHADER_GEOMETRY
);
1388 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1390 struct brw_gs_prog_data
*gs_prog_data
=
1391 (struct brw_gs_prog_data
*) prog_data
;
1393 const fs_builder abld
= bld
.annotate("emit control data bits");
1394 const fs_builder fwa_bld
= bld
.exec_all();
1396 /* We use a single UD register to accumulate control data bits (32 bits
1397 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1400 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1401 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1402 * use the Channel Mask phase to enable/disable which DWord within that
1403 * group to write. (Remember, different SIMD8 channels may have emitted
1404 * different numbers of vertices, so we may need per-slot offsets.)
1406 * Channel masking presents an annoying problem: we may have to replicate
1407 * the data up to 4 times:
1409 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1411 * To avoid penalizing shaders that emit a small number of vertices, we
1412 * can avoid these sometimes: if the size of the control data header is
1413 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1414 * land in the same 128-bit group, so we can skip per-slot offsets.
1416 * Similarly, if the control data header is <= 32 bits, there is only one
1417 * DWord, so we can skip channel masks.
1419 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1421 fs_reg channel_mask
, per_slot_offset
;
1423 if (gs_compile
->control_data_header_size_bits
> 32) {
1424 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1425 channel_mask
= vgrf(glsl_type::uint_type
);
1428 if (gs_compile
->control_data_header_size_bits
> 128) {
1429 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1430 per_slot_offset
= vgrf(glsl_type::uint_type
);
1433 /* Figure out which DWord we're trying to write to using the formula:
1435 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1437 * Since bits_per_vertex is a power of two, and is known at compile
1438 * time, this can be optimized to:
1440 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1442 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1443 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1444 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1445 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1446 unsigned log2_bits_per_vertex
=
1447 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1448 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1450 if (per_slot_offset
.file
!= BAD_FILE
) {
1451 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1452 * the appropriate OWord within the control data header.
1454 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1457 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1458 * write to the appropriate DWORD within the OWORD.
1460 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1461 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1462 channel_mask
= intexp2(fwa_bld
, channel
);
1463 /* Then the channel masks need to be in bits 23:16. */
1464 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1467 /* Store the control data bits in the message payload and send it. */
1469 if (channel_mask
.file
!= BAD_FILE
)
1470 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1471 if (per_slot_offset
.file
!= BAD_FILE
)
1474 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1475 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1477 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1478 if (per_slot_offset
.file
!= BAD_FILE
)
1479 sources
[i
++] = per_slot_offset
;
1480 if (channel_mask
.file
!= BAD_FILE
)
1481 sources
[i
++] = channel_mask
;
1483 sources
[i
++] = this->control_data_bits
;
1486 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1487 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1489 /* We need to increment Global Offset by 256-bits to make room for
1490 * Broadwell's extra "Vertex Count" payload at the beginning of the
1491 * URB entry. Since this is an OWord message, Global Offset is counted
1492 * in 128-bit units, so we must set it to 2.
1494 if (gs_prog_data
->static_vertex_count
== -1)
1499 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1502 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1504 /* Note: we are calling this *before* increasing vertex_count, so
1505 * this->vertex_count == vertex_count - 1 in the formula above.
1508 /* Stream mode uses 2 bits per vertex */
1509 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1511 /* Must be a valid stream */
1512 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1514 /* Control data bits are initialized to 0 so we don't have to set any
1515 * bits when sending vertices to stream 0.
1520 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1522 /* reg::sid = stream_id */
1523 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1524 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1526 /* reg:shift_count = 2 * (vertex_count - 1) */
1527 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1528 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1530 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1531 * attention to the lower 5 bits of its second source argument, so on this
1532 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1533 * stream_id << ((2 * (vertex_count - 1)) % 32).
1535 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1536 abld
.SHL(mask
, sid
, shift_count
);
1537 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1541 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1544 assert(stage
== MESA_SHADER_GEOMETRY
);
1546 struct brw_gs_prog_data
*gs_prog_data
=
1547 (struct brw_gs_prog_data
*) prog_data
;
1549 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1550 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1552 /* Haswell and later hardware ignores the "Render Stream Select" bits
1553 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1554 * and instead sends all primitives down the pipeline for rasterization.
1555 * If the SOL stage is enabled, "Render Stream Select" is honored and
1556 * primitives bound to non-zero streams are discarded after stream output.
1558 * Since the only purpose of primives sent to non-zero streams is to
1559 * be recorded by transform feedback, we can simply discard all geometry
1560 * bound to these streams when transform feedback is disabled.
1562 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1565 /* If we're outputting 32 control data bits or less, then we can wait
1566 * until the shader is over to output them all. Otherwise we need to
1567 * output them as we go. Now is the time to do it, since we're about to
1568 * output the vertex_count'th vertex, so it's guaranteed that the
1569 * control data bits associated with the (vertex_count - 1)th vertex are
1572 if (gs_compile
->control_data_header_size_bits
> 32) {
1573 const fs_builder abld
=
1574 bld
.annotate("emit vertex: emit control data bits");
1576 /* Only emit control data bits if we've finished accumulating a batch
1577 * of 32 bits. This is the case when:
1579 * (vertex_count * bits_per_vertex) % 32 == 0
1581 * (in other words, when the last 5 bits of vertex_count *
1582 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1583 * integer n (which is always the case, since bits_per_vertex is
1584 * always 1 or 2), this is equivalent to requiring that the last 5-n
1585 * bits of vertex_count are 0:
1587 * vertex_count & (2^(5-n) - 1) == 0
1589 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1592 * vertex_count & (32 / bits_per_vertex - 1) == 0
1594 * TODO: If vertex_count is an immediate, we could do some of this math
1595 * at compile time...
1598 abld
.AND(bld
.null_reg_d(), vertex_count
,
1599 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1600 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1602 abld
.IF(BRW_PREDICATE_NORMAL
);
1603 /* If vertex_count is 0, then no control data bits have been
1604 * accumulated yet, so we can skip emitting them.
1606 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1607 BRW_CONDITIONAL_NEQ
);
1608 abld
.IF(BRW_PREDICATE_NORMAL
);
1609 emit_gs_control_data_bits(vertex_count
);
1610 abld
.emit(BRW_OPCODE_ENDIF
);
1612 /* Reset control_data_bits to 0 so we can start accumulating a new
1615 * Note: in the case where vertex_count == 0, this neutralizes the
1616 * effect of any call to EndPrimitive() that the shader may have
1617 * made before outputting its first vertex.
1619 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1620 inst
->force_writemask_all
= true;
1621 abld
.emit(BRW_OPCODE_ENDIF
);
1624 emit_urb_writes(vertex_count
);
1626 /* In stream mode we have to set control data bits for all vertices
1627 * unless we have disabled control data bits completely (which we do
1628 * do for GL_POINTS outputs that don't use streams).
1630 if (gs_compile
->control_data_header_size_bits
> 0 &&
1631 gs_prog_data
->control_data_format
==
1632 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1633 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1638 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1639 const nir_src
&vertex_src
,
1640 unsigned base_offset
,
1641 const nir_src
&offset_src
,
1642 unsigned num_components
)
1644 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1646 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1647 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1648 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1650 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1651 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1652 * gl_PointSize is available as a GS input, however, so it must be that.
1654 const bool is_point_size
= (base_offset
== 0);
1656 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1657 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1658 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1659 vertex_const
->u
[0] * push_reg_count
;
1660 /* This input was pushed into registers. */
1661 if (is_point_size
) {
1662 /* gl_PointSize comes in .w */
1663 assert(imm_offset
== 0);
1664 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1666 for (unsigned i
= 0; i
< num_components
; i
++) {
1667 bld
.MOV(offset(dst
, bld
, i
),
1668 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1672 /* Resort to the pull model. Ensure the VUE handles are provided. */
1673 gs_prog_data
->base
.include_vue_handles
= true;
1675 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1679 /* The vertex index is constant; just select the proper URB handle. */
1681 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1682 BRW_REGISTER_TYPE_UD
);
1684 /* The vertex index is non-constant. We need to use indirect
1685 * addressing to fetch the proper URB handle.
1687 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1688 * indicating that channel <n> should read the handle from
1689 * DWord <n>. We convert that to bytes by multiplying by 4.
1691 * Next, we convert the vertex index to bytes by multiplying
1692 * by 32 (shifting by 5), and add the two together. This is
1693 * the final indirect byte offset.
1695 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1696 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1697 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1698 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1699 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1701 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1702 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1703 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1704 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1705 /* Convert vertex_index to bytes (multiply by 32) */
1706 bld
.SHL(vertex_offset_bytes
,
1707 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1709 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1711 /* Use first_icp_handle as the base offset. There is one register
1712 * of URB handles per vertex, so inform the register allocator that
1713 * we might read up to nir->info.gs.vertices_in registers.
1715 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1716 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1717 fs_reg(icp_offset_bytes
),
1718 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1723 /* Constant indexing - use global offset. */
1724 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1725 inst
->offset
= base_offset
+ offset_const
->u
[0];
1726 inst
->base_mrf
= -1;
1728 inst
->regs_written
= num_components
;
1730 /* Indirect indexing - use per-slot offsets as well. */
1731 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1732 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1733 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1735 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1736 inst
->offset
= base_offset
;
1737 inst
->base_mrf
= -1;
1739 inst
->regs_written
= num_components
;
1742 if (is_point_size
) {
1743 /* Read the whole VUE header (because of alignment) and read .w. */
1744 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1746 inst
->regs_written
= 4;
1747 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1753 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1755 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1756 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1759 /* The only constant offset we should find is 0. brw_nir.c's
1760 * add_const_offset_to_base() will fold other constant offsets
1761 * into instr->const_index[0].
1763 assert(const_value
->u
[0] == 0);
1767 return get_nir_src(*offset_src
);
1771 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1772 nir_intrinsic_instr
*instr
)
1774 assert(stage
== MESA_SHADER_VERTEX
);
1777 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1778 dest
= get_nir_dest(instr
->dest
);
1780 switch (instr
->intrinsic
) {
1781 case nir_intrinsic_load_vertex_id
:
1782 unreachable("should be lowered by lower_vertex_id()");
1784 case nir_intrinsic_load_vertex_id_zero_base
:
1785 case nir_intrinsic_load_base_vertex
:
1786 case nir_intrinsic_load_instance_id
:
1787 case nir_intrinsic_load_base_instance
:
1788 case nir_intrinsic_load_draw_id
: {
1789 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1790 fs_reg val
= nir_system_values
[sv
];
1791 assert(val
.file
!= BAD_FILE
);
1792 dest
.type
= val
.type
;
1798 nir_emit_intrinsic(bld
, instr
);
1804 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1805 nir_intrinsic_instr
*instr
)
1807 assert(stage
== MESA_SHADER_TESS_EVAL
);
1808 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1811 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1812 dest
= get_nir_dest(instr
->dest
);
1814 switch (instr
->intrinsic
) {
1815 case nir_intrinsic_load_primitive_id
:
1816 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1818 case nir_intrinsic_load_tess_coord
:
1819 /* gl_TessCoord is part of the payload in g1-3 */
1820 for (unsigned i
= 0; i
< 3; i
++) {
1821 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1825 case nir_intrinsic_load_tess_level_outer
:
1826 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1827 * appears as a push-model input. So, we can simply use the ATTR file
1828 * rather than issuing URB read messages. The data is stored in the
1829 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1832 switch (tes_prog_data
->domain
) {
1833 case BRW_TESS_DOMAIN_QUAD
:
1834 for (unsigned i
= 0; i
< 4; i
++)
1835 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1837 case BRW_TESS_DOMAIN_TRI
:
1838 for (unsigned i
= 0; i
< 3; i
++)
1839 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1841 case BRW_TESS_DOMAIN_ISOLINE
:
1842 for (unsigned i
= 0; i
< 2; i
++)
1843 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1848 case nir_intrinsic_load_tess_level_inner
:
1849 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1850 * appears as a push-model input. So, we can simply use the ATTR file
1851 * rather than issuing URB read messages.
1853 switch (tes_prog_data
->domain
) {
1854 case BRW_TESS_DOMAIN_QUAD
:
1855 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1856 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1858 case BRW_TESS_DOMAIN_TRI
:
1859 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1861 case BRW_TESS_DOMAIN_ISOLINE
:
1862 /* ignore - value is undefined */
1867 case nir_intrinsic_load_input
:
1868 case nir_intrinsic_load_per_vertex_input
: {
1869 fs_reg indirect_offset
= get_indirect_offset(instr
);
1870 unsigned imm_offset
= instr
->const_index
[0];
1873 if (indirect_offset
.file
== BAD_FILE
) {
1874 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1875 * which is 16 registers (since each holds 2 vec4 slots).
1877 const unsigned max_push_slots
= 32;
1878 if (imm_offset
< max_push_slots
) {
1879 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1880 for (int i
= 0; i
< instr
->num_components
; i
++) {
1881 bld
.MOV(offset(dest
, bld
, i
),
1882 component(src
, 4 * (imm_offset
% 2) + i
));
1884 tes_prog_data
->base
.urb_read_length
=
1885 MAX2(tes_prog_data
->base
.urb_read_length
,
1886 DIV_ROUND_UP(imm_offset
+ 1, 2));
1888 /* Replicate the patch handle to all enabled channels */
1889 const fs_reg srcs
[] = {
1890 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1892 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1893 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1895 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1897 inst
->offset
= imm_offset
;
1898 inst
->base_mrf
= -1;
1899 inst
->regs_written
= instr
->num_components
;
1902 /* Indirect indexing - use per-slot offsets as well. */
1903 const fs_reg srcs
[] = {
1904 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1907 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1908 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1910 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1912 inst
->offset
= imm_offset
;
1913 inst
->base_mrf
= -1;
1914 inst
->regs_written
= instr
->num_components
;
1919 nir_emit_intrinsic(bld
, instr
);
1925 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1926 nir_intrinsic_instr
*instr
)
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1929 fs_reg indirect_offset
;
1932 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1933 dest
= get_nir_dest(instr
->dest
);
1935 switch (instr
->intrinsic
) {
1936 case nir_intrinsic_load_primitive_id
:
1937 assert(stage
== MESA_SHADER_GEOMETRY
);
1938 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1939 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1940 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1943 case nir_intrinsic_load_input
:
1944 unreachable("load_input intrinsics are invalid for the GS stage");
1946 case nir_intrinsic_load_per_vertex_input
:
1947 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1948 instr
->src
[1], instr
->num_components
);
1951 case nir_intrinsic_emit_vertex_with_counter
:
1952 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1955 case nir_intrinsic_end_primitive_with_counter
:
1956 emit_gs_end_primitive(instr
->src
[0]);
1959 case nir_intrinsic_set_vertex_count
:
1960 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1963 case nir_intrinsic_load_invocation_id
: {
1964 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1965 assert(val
.file
!= BAD_FILE
);
1966 dest
.type
= val
.type
;
1972 nir_emit_intrinsic(bld
, instr
);
1978 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1979 nir_intrinsic_instr
*instr
)
1981 assert(stage
== MESA_SHADER_FRAGMENT
);
1982 struct brw_wm_prog_data
*wm_prog_data
=
1983 (struct brw_wm_prog_data
*) prog_data
;
1986 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1987 dest
= get_nir_dest(instr
->dest
);
1989 switch (instr
->intrinsic
) {
1990 case nir_intrinsic_load_front_face
:
1991 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1992 *emit_frontfacing_interpolation());
1995 case nir_intrinsic_load_sample_pos
: {
1996 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1997 assert(sample_pos
.file
!= BAD_FILE
);
1998 dest
.type
= sample_pos
.type
;
1999 bld
.MOV(dest
, sample_pos
);
2000 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2004 case nir_intrinsic_load_helper_invocation
:
2005 case nir_intrinsic_load_sample_mask_in
:
2006 case nir_intrinsic_load_sample_id
: {
2007 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2008 fs_reg val
= nir_system_values
[sv
];
2009 assert(val
.file
!= BAD_FILE
);
2010 dest
.type
= val
.type
;
2015 case nir_intrinsic_discard
:
2016 case nir_intrinsic_discard_if
: {
2017 /* We track our discarded pixels in f0.1. By predicating on it, we can
2018 * update just the flag bits that aren't yet discarded. If there's no
2019 * condition, we emit a CMP of g0 != g0, so all currently executing
2020 * channels will get turned off.
2023 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2024 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2025 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2027 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2028 BRW_REGISTER_TYPE_UW
));
2029 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2031 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2032 cmp
->flag_subreg
= 1;
2034 if (devinfo
->gen
>= 6) {
2035 emit_discard_jump();
2040 case nir_intrinsic_interp_var_at_centroid
:
2041 case nir_intrinsic_interp_var_at_sample
:
2042 case nir_intrinsic_interp_var_at_offset
: {
2043 /* Handle ARB_gpu_shader5 interpolation intrinsics
2045 * It's worth a quick word of explanation as to why we handle the full
2046 * variable-based interpolation intrinsic rather than a lowered version
2047 * with like we do for other inputs. We have to do that because the way
2048 * we set up inputs doesn't allow us to use the already setup inputs for
2049 * interpolation. At the beginning of the shader, we go through all of
2050 * the input variables and do the initial interpolation and put it in
2051 * the nir_inputs array based on its location as determined in
2052 * nir_lower_io. If the input isn't used, dead code cleans up and
2053 * everything works fine. However, when we get to the ARB_gpu_shader5
2054 * interpolation intrinsics, we need to reinterpolate the input
2055 * differently. If we used an intrinsic that just had an index it would
2056 * only give us the offset into the nir_inputs array. However, this is
2057 * useless because that value is post-interpolation and we need
2058 * pre-interpolation. In order to get the actual location of the bits
2059 * we get from the vertex fetching hardware, we need the variable.
2061 wm_prog_data
->pulls_bary
= true;
2063 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2064 const glsl_interp_qualifier interpolation
=
2065 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2067 switch (instr
->intrinsic
) {
2068 case nir_intrinsic_interp_var_at_centroid
:
2069 emit_pixel_interpolater_send(bld
,
2070 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2077 case nir_intrinsic_interp_var_at_sample
: {
2078 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2081 unsigned msg_data
= const_sample
->i
[0] << 4;
2083 emit_pixel_interpolater_send(bld
,
2084 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2087 brw_imm_ud(msg_data
),
2090 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2091 BRW_REGISTER_TYPE_UD
);
2093 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2094 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2095 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2096 bld
.exec_all().group(1, 0)
2097 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2098 emit_pixel_interpolater_send(bld
,
2099 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2105 /* Make a loop that sends a message to the pixel interpolater
2106 * for the sample number in each live channel. If there are
2107 * multiple channels with the same sample number then these
2108 * will be handled simultaneously with a single interation of
2111 bld
.emit(BRW_OPCODE_DO
);
2113 /* Get the next live sample number into sample_id_reg */
2114 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2116 /* Set the flag register so that we can perform the send
2117 * message on all channels that have the same sample number
2119 bld
.CMP(bld
.null_reg_ud(),
2120 sample_src
, sample_id
,
2121 BRW_CONDITIONAL_EQ
);
2122 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2123 bld
.exec_all().group(1, 0)
2124 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2126 emit_pixel_interpolater_send(bld
,
2127 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2132 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2134 /* Continue the loop if there are any live channels left */
2135 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2137 bld
.emit(BRW_OPCODE_WHILE
));
2144 case nir_intrinsic_interp_var_at_offset
: {
2145 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2148 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2149 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2151 emit_pixel_interpolater_send(bld
,
2152 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2155 brw_imm_ud(off_x
| (off_y
<< 4)),
2158 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2159 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2160 BRW_REGISTER_TYPE_F
);
2161 for (int i
= 0; i
< 2; i
++) {
2162 fs_reg temp
= vgrf(glsl_type::float_type
);
2163 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2164 fs_reg itemp
= vgrf(glsl_type::int_type
);
2165 bld
.MOV(itemp
, temp
); /* float to int */
2167 /* Clamp the upper end of the range to +7/16.
2168 * ARB_gpu_shader5 requires that we support a maximum offset
2169 * of +0.5, which isn't representable in a S0.4 value -- if
2170 * we didn't clamp it, we'd end up with -8/16, which is the
2171 * opposite of what the shader author wanted.
2173 * This is legal due to ARB_gpu_shader5's quantization
2176 * "Not all values of <offset> may be supported; x and y
2177 * offsets may be rounded to fixed-point values with the
2178 * number of fraction bits given by the
2179 * implementation-dependent constant
2180 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2182 set_condmod(BRW_CONDITIONAL_L
,
2183 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2186 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2187 emit_pixel_interpolater_send(bld
,
2198 unreachable("Invalid intrinsic");
2201 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2202 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2203 src
.type
= dest
.type
;
2205 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2206 dest
= offset(dest
, bld
, 1);
2211 nir_emit_intrinsic(bld
, instr
);
2217 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2218 nir_intrinsic_instr
*instr
)
2220 assert(stage
== MESA_SHADER_COMPUTE
);
2221 struct brw_cs_prog_data
*cs_prog_data
=
2222 (struct brw_cs_prog_data
*) prog_data
;
2225 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2226 dest
= get_nir_dest(instr
->dest
);
2228 switch (instr
->intrinsic
) {
2229 case nir_intrinsic_barrier
:
2231 cs_prog_data
->uses_barrier
= true;
2234 case nir_intrinsic_load_local_invocation_id
:
2235 case nir_intrinsic_load_work_group_id
: {
2236 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2237 fs_reg val
= nir_system_values
[sv
];
2238 assert(val
.file
!= BAD_FILE
);
2239 dest
.type
= val
.type
;
2240 for (unsigned i
= 0; i
< 3; i
++)
2241 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2245 case nir_intrinsic_load_num_work_groups
: {
2246 const unsigned surface
=
2247 cs_prog_data
->binding_table
.work_groups_start
;
2249 cs_prog_data
->uses_num_work_groups
= true;
2251 fs_reg surf_index
= brw_imm_ud(surface
);
2252 brw_mark_surface_used(prog_data
, surface
);
2254 /* Read the 3 GLuint components of gl_NumWorkGroups */
2255 for (unsigned i
= 0; i
< 3; i
++) {
2256 fs_reg read_result
=
2257 emit_untyped_read(bld
, surf_index
,
2259 1 /* dims */, 1 /* size */,
2260 BRW_PREDICATE_NONE
);
2261 read_result
.type
= dest
.type
;
2262 bld
.MOV(dest
, read_result
);
2263 dest
= offset(dest
, bld
, 1);
2268 case nir_intrinsic_shared_atomic_add
:
2269 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2271 case nir_intrinsic_shared_atomic_imin
:
2272 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2274 case nir_intrinsic_shared_atomic_umin
:
2275 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2277 case nir_intrinsic_shared_atomic_imax
:
2278 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2280 case nir_intrinsic_shared_atomic_umax
:
2281 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2283 case nir_intrinsic_shared_atomic_and
:
2284 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2286 case nir_intrinsic_shared_atomic_or
:
2287 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2289 case nir_intrinsic_shared_atomic_xor
:
2290 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2292 case nir_intrinsic_shared_atomic_exchange
:
2293 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2295 case nir_intrinsic_shared_atomic_comp_swap
:
2296 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2300 nir_emit_intrinsic(bld
, instr
);
2306 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2309 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2310 dest
= get_nir_dest(instr
->dest
);
2312 switch (instr
->intrinsic
) {
2313 case nir_intrinsic_atomic_counter_inc
:
2314 case nir_intrinsic_atomic_counter_dec
:
2315 case nir_intrinsic_atomic_counter_read
: {
2316 using namespace surface_access
;
2318 /* Get the arguments of the atomic intrinsic. */
2319 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2320 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2321 instr
->const_index
[0]);
2324 /* Emit a surface read or atomic op. */
2325 switch (instr
->intrinsic
) {
2326 case nir_intrinsic_atomic_counter_read
:
2327 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2330 case nir_intrinsic_atomic_counter_inc
:
2331 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2332 fs_reg(), 1, 1, BRW_AOP_INC
);
2335 case nir_intrinsic_atomic_counter_dec
:
2336 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2337 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2341 unreachable("Unreachable");
2344 /* Assign the result. */
2345 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2347 /* Mark the surface as used. */
2348 brw_mark_surface_used(stage_prog_data
, surface
);
2352 case nir_intrinsic_image_load
:
2353 case nir_intrinsic_image_store
:
2354 case nir_intrinsic_image_atomic_add
:
2355 case nir_intrinsic_image_atomic_min
:
2356 case nir_intrinsic_image_atomic_max
:
2357 case nir_intrinsic_image_atomic_and
:
2358 case nir_intrinsic_image_atomic_or
:
2359 case nir_intrinsic_image_atomic_xor
:
2360 case nir_intrinsic_image_atomic_exchange
:
2361 case nir_intrinsic_image_atomic_comp_swap
: {
2362 using namespace image_access
;
2364 /* Get the referenced image variable and type. */
2365 const nir_variable
*var
= instr
->variables
[0]->var
;
2366 const glsl_type
*type
= var
->type
->without_array();
2367 const brw_reg_type base_type
= get_image_base_type(type
);
2369 /* Get some metadata from the image intrinsic. */
2370 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2371 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2372 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2373 const mesa_format format
=
2374 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2375 _mesa_get_shader_image_format(var
->data
.image
.format
));
2377 /* Get the arguments of the image intrinsic. */
2378 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2379 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2380 BRW_REGISTER_TYPE_UD
);
2381 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2382 retype(get_nir_src(instr
->src
[2]), base_type
) :
2384 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2385 retype(get_nir_src(instr
->src
[3]), base_type
) :
2389 /* Emit an image load, store or atomic op. */
2390 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2391 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2393 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2394 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2397 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2398 surf_dims
, arr_dims
, info
->dest_components
,
2399 get_image_atomic_op(instr
->intrinsic
, type
));
2401 /* Assign the result. */
2402 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2403 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2404 offset(tmp
, bld
, c
));
2408 case nir_intrinsic_memory_barrier_atomic_counter
:
2409 case nir_intrinsic_memory_barrier_buffer
:
2410 case nir_intrinsic_memory_barrier_image
:
2411 case nir_intrinsic_memory_barrier
: {
2412 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2413 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2418 case nir_intrinsic_group_memory_barrier
:
2419 case nir_intrinsic_memory_barrier_shared
:
2420 /* We treat these workgroup-level barriers as no-ops. This should be
2421 * safe at present and as long as:
2423 * - Memory access instructions are not subsequently reordered by the
2424 * compiler back-end.
2426 * - All threads from a given compute shader workgroup fit within a
2427 * single subslice and therefore talk to the same HDC shared unit
2428 * what supposedly guarantees ordering and coherency between threads
2429 * from the same workgroup. This may change in the future when we
2430 * start splitting workgroups across multiple subslices.
2432 * - The context is not in fault-and-stream mode, which could cause
2433 * memory transactions (including to SLM) prior to the barrier to be
2434 * replayed after the barrier if a pagefault occurs. This shouldn't
2435 * be a problem up to and including SKL because fault-and-stream is
2436 * not usable due to hardware issues, but that's likely to change in
2441 case nir_intrinsic_shader_clock
: {
2442 /* We cannot do anything if there is an event, so ignore it for now */
2443 fs_reg shader_clock
= get_timestamp(bld
);
2444 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2446 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2450 case nir_intrinsic_image_size
: {
2451 /* Get the referenced image variable and type. */
2452 const nir_variable
*var
= instr
->variables
[0]->var
;
2453 const glsl_type
*type
= var
->type
->without_array();
2455 /* Get the size of the image. */
2456 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2457 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2459 /* For 1DArray image types, the array index is stored in the Z component.
2460 * Fix this by swizzling the Z component to the Y component.
2462 const bool is_1d_array_image
=
2463 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2464 type
->sampler_array
;
2466 /* For CubeArray images, we should count the number of cubes instead
2467 * of the number of faces. Fix it by dividing the (Z component) by 6.
2469 const bool is_cube_array_image
=
2470 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2471 type
->sampler_array
;
2473 /* Copy all the components. */
2474 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2475 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2476 if ((int)c
>= type
->coordinate_components()) {
2477 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2479 } else if (c
== 1 && is_1d_array_image
) {
2480 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2481 offset(size
, bld
, 2));
2482 } else if (c
== 2 && is_cube_array_image
) {
2483 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2484 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2485 offset(size
, bld
, c
), brw_imm_d(6));
2487 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2488 offset(size
, bld
, c
));
2495 case nir_intrinsic_image_samples
:
2496 /* The driver does not support multi-sampled images. */
2497 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2500 case nir_intrinsic_load_uniform
: {
2501 /* Offsets are in bytes but they should always be multiples of 4 */
2502 assert(instr
->const_index
[0] % 4 == 0);
2504 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2506 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2508 /* Offsets are in bytes but they should always be multiples of 4 */
2509 assert(const_offset
->u
[0] % 4 == 0);
2510 src
.reg_offset
= const_offset
->u
[0] / 4;
2512 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2515 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2516 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2521 case nir_intrinsic_load_ubo
: {
2522 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2526 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2528 surf_index
= brw_imm_ud(index
);
2529 brw_mark_surface_used(prog_data
, index
);
2531 /* The block index is not a constant. Evaluate the index expression
2532 * per-channel and add the base UBO index; we have to select a value
2533 * from any live channel.
2535 surf_index
= vgrf(glsl_type::uint_type
);
2536 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2537 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2538 surf_index
= bld
.emit_uniformize(surf_index
);
2540 /* Assume this may touch any UBO. It would be nice to provide
2541 * a tighter bound, but the array information is already lowered away.
2543 brw_mark_surface_used(prog_data
,
2544 stage_prog_data
->binding_table
.ubo_start
+
2545 nir
->info
.num_ubos
- 1);
2548 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2549 if (const_offset
== NULL
) {
2550 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2551 BRW_REGISTER_TYPE_D
);
2553 for (int i
= 0; i
< instr
->num_components
; i
++)
2554 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2555 base_offset
, i
* 4);
2557 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2558 packed_consts
.type
= dest
.type
;
2560 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2561 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2562 surf_index
, const_offset_reg
);
2564 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2565 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2567 /* The std140 packing rules don't allow vectors to cross 16-byte
2568 * boundaries, and a reg is 32 bytes.
2570 assert(packed_consts
.subreg_offset
< 32);
2572 bld
.MOV(dest
, packed_consts
);
2573 dest
= offset(dest
, bld
, 1);
2579 case nir_intrinsic_load_ssbo
: {
2580 assert(devinfo
->gen
>= 7);
2582 nir_const_value
*const_uniform_block
=
2583 nir_src_as_const_value(instr
->src
[0]);
2586 if (const_uniform_block
) {
2587 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2588 const_uniform_block
->u
[0];
2589 surf_index
= brw_imm_ud(index
);
2590 brw_mark_surface_used(prog_data
, index
);
2592 surf_index
= vgrf(glsl_type::uint_type
);
2593 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2594 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2596 /* Assume this may touch any UBO. It would be nice to provide
2597 * a tighter bound, but the array information is already lowered away.
2599 brw_mark_surface_used(prog_data
,
2600 stage_prog_data
->binding_table
.ssbo_start
+
2601 nir
->info
.num_ssbos
- 1);
2605 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2607 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2609 offset_reg
= get_nir_src(instr
->src
[1]);
2612 /* Read the vector */
2613 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2615 instr
->num_components
,
2616 BRW_PREDICATE_NONE
);
2617 read_result
.type
= dest
.type
;
2618 for (int i
= 0; i
< instr
->num_components
; i
++)
2619 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2624 case nir_intrinsic_load_shared
: {
2625 assert(devinfo
->gen
>= 7);
2627 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2629 /* Get the offset to read from */
2631 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2633 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2635 offset_reg
= vgrf(glsl_type::uint_type
);
2637 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2638 brw_imm_ud(instr
->const_index
[0]));
2641 /* Read the vector */
2642 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2644 instr
->num_components
,
2645 BRW_PREDICATE_NONE
);
2646 read_result
.type
= dest
.type
;
2647 for (int i
= 0; i
< instr
->num_components
; i
++)
2648 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2653 case nir_intrinsic_store_shared
: {
2654 assert(devinfo
->gen
>= 7);
2657 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2660 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2663 unsigned writemask
= instr
->const_index
[1];
2665 /* Combine groups of consecutive enabled channels in one write
2666 * message. We use ffs to find the first enabled channel and then ffs on
2667 * the bit-inverse, down-shifted writemask to determine the length of
2668 * the block of enabled bits.
2671 unsigned first_component
= ffs(writemask
) - 1;
2672 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2675 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2677 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2678 4 * first_component
);
2680 offset_reg
= vgrf(glsl_type::uint_type
);
2682 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2683 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2686 emit_untyped_write(bld
, surf_index
, offset_reg
,
2687 offset(val_reg
, bld
, first_component
),
2688 1 /* dims */, length
,
2689 BRW_PREDICATE_NONE
);
2691 /* Clear the bits in the writemask that we just wrote, then try
2692 * again to see if more channels are left.
2694 writemask
&= (15 << (first_component
+ length
));
2700 case nir_intrinsic_load_input
: {
2702 if (stage
== MESA_SHADER_VERTEX
) {
2703 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2705 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2706 instr
->const_index
[0]);
2709 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2710 assert(const_offset
&& "Indirect input loads not allowed");
2711 src
= offset(src
, bld
, const_offset
->u
[0]);
2713 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2714 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2719 case nir_intrinsic_store_ssbo
: {
2720 assert(devinfo
->gen
>= 7);
2724 nir_const_value
*const_uniform_block
=
2725 nir_src_as_const_value(instr
->src
[1]);
2726 if (const_uniform_block
) {
2727 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2728 const_uniform_block
->u
[0];
2729 surf_index
= brw_imm_ud(index
);
2730 brw_mark_surface_used(prog_data
, index
);
2732 surf_index
= vgrf(glsl_type::uint_type
);
2733 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2734 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2736 brw_mark_surface_used(prog_data
,
2737 stage_prog_data
->binding_table
.ssbo_start
+
2738 nir
->info
.num_ssbos
- 1);
2742 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2745 unsigned writemask
= instr
->const_index
[0];
2747 /* Combine groups of consecutive enabled channels in one write
2748 * message. We use ffs to find the first enabled channel and then ffs on
2749 * the bit-inverse, down-shifted writemask to determine the length of
2750 * the block of enabled bits.
2753 unsigned first_component
= ffs(writemask
) - 1;
2754 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2757 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2759 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2761 offset_reg
= vgrf(glsl_type::uint_type
);
2763 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2764 brw_imm_ud(4 * first_component
));
2767 emit_untyped_write(bld
, surf_index
, offset_reg
,
2768 offset(val_reg
, bld
, first_component
),
2769 1 /* dims */, length
,
2770 BRW_PREDICATE_NONE
);
2772 /* Clear the bits in the writemask that we just wrote, then try
2773 * again to see if more channels are left.
2775 writemask
&= (15 << (first_component
+ length
));
2780 case nir_intrinsic_store_output
: {
2781 fs_reg src
= get_nir_src(instr
->src
[0]);
2782 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2783 instr
->const_index
[0]);
2785 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2786 assert(const_offset
&& "Indirect output stores not allowed");
2787 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2789 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2790 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2795 case nir_intrinsic_ssbo_atomic_add
:
2796 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2798 case nir_intrinsic_ssbo_atomic_imin
:
2799 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2801 case nir_intrinsic_ssbo_atomic_umin
:
2802 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2804 case nir_intrinsic_ssbo_atomic_imax
:
2805 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2807 case nir_intrinsic_ssbo_atomic_umax
:
2808 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2810 case nir_intrinsic_ssbo_atomic_and
:
2811 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2813 case nir_intrinsic_ssbo_atomic_or
:
2814 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2816 case nir_intrinsic_ssbo_atomic_xor
:
2817 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2819 case nir_intrinsic_ssbo_atomic_exchange
:
2820 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2822 case nir_intrinsic_ssbo_atomic_comp_swap
:
2823 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2826 case nir_intrinsic_get_buffer_size
: {
2827 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2828 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2829 int reg_width
= dispatch_width
/ 8;
2832 fs_reg source
= brw_imm_d(0);
2834 int mlen
= 1 * reg_width
;
2836 /* A resinfo's sampler message is used to get the buffer size.
2837 * The SIMD8's writeback message consists of four registers and
2838 * SIMD16's writeback message consists of 8 destination registers
2839 * (two per each component), although we are only interested on the
2840 * first component, where resinfo returns the buffer size for
2843 int regs_written
= 4 * mlen
;
2844 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2845 BRW_REGISTER_TYPE_UD
);
2846 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2847 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2848 BRW_REGISTER_TYPE_UD
);
2849 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2850 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2851 src_payload
, brw_imm_ud(index
));
2852 inst
->header_size
= 0;
2854 inst
->regs_written
= regs_written
;
2856 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2858 brw_mark_surface_used(prog_data
, index
);
2863 unreachable("unknown intrinsic");
2868 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2869 int op
, nir_intrinsic_instr
*instr
)
2872 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2873 dest
= get_nir_dest(instr
->dest
);
2876 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2877 if (const_surface
) {
2878 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2879 const_surface
->u
[0];
2880 surface
= brw_imm_ud(surf_index
);
2881 brw_mark_surface_used(prog_data
, surf_index
);
2883 surface
= vgrf(glsl_type::uint_type
);
2884 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2885 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2887 /* Assume this may touch any SSBO. This is the same we do for other
2888 * UBO/SSBO accesses with non-constant surface.
2890 brw_mark_surface_used(prog_data
,
2891 stage_prog_data
->binding_table
.ssbo_start
+
2892 nir
->info
.num_ssbos
- 1);
2895 fs_reg offset
= get_nir_src(instr
->src
[1]);
2896 fs_reg data1
= get_nir_src(instr
->src
[2]);
2898 if (op
== BRW_AOP_CMPWR
)
2899 data2
= get_nir_src(instr
->src
[3]);
2901 /* Emit the actual atomic operation operation */
2903 fs_reg atomic_result
=
2904 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2906 1 /* dims */, 1 /* rsize */,
2908 BRW_PREDICATE_NONE
);
2909 dest
.type
= atomic_result
.type
;
2910 bld
.MOV(dest
, atomic_result
);
2914 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2915 int op
, nir_intrinsic_instr
*instr
)
2918 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2919 dest
= get_nir_dest(instr
->dest
);
2921 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2922 fs_reg offset
= get_nir_src(instr
->src
[0]);
2923 fs_reg data1
= get_nir_src(instr
->src
[1]);
2925 if (op
== BRW_AOP_CMPWR
)
2926 data2
= get_nir_src(instr
->src
[2]);
2928 /* Emit the actual atomic operation operation */
2930 fs_reg atomic_result
=
2931 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2933 1 /* dims */, 1 /* rsize */,
2935 BRW_PREDICATE_NONE
);
2936 dest
.type
= atomic_result
.type
;
2937 bld
.MOV(dest
, atomic_result
);
2941 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2943 unsigned texture
= instr
->texture_index
;
2944 fs_reg
texture_reg(brw_imm_ud(texture
));
2946 int gather_component
= instr
->component
;
2948 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2951 int lod_components
= 0;
2952 int UNUSED offset_components
= 0;
2954 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2956 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2957 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2958 switch (instr
->src
[i
].src_type
) {
2959 case nir_tex_src_bias
:
2960 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2962 case nir_tex_src_comparitor
:
2963 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2965 case nir_tex_src_coord
:
2966 switch (instr
->op
) {
2968 case nir_texop_txf_ms
:
2969 case nir_texop_samples_identical
:
2970 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2973 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2977 case nir_tex_src_ddx
:
2978 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2979 lod_components
= nir_tex_instr_src_size(instr
, i
);
2981 case nir_tex_src_ddy
:
2982 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2984 case nir_tex_src_lod
:
2985 switch (instr
->op
) {
2987 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2990 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2993 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2997 case nir_tex_src_ms_index
:
2998 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
3000 case nir_tex_src_offset
:
3001 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
3002 if (instr
->is_array
)
3003 offset_components
= instr
->coord_components
- 1;
3005 offset_components
= instr
->coord_components
;
3007 case nir_tex_src_projector
:
3008 unreachable("should be lowered");
3010 case nir_tex_src_texture_offset
: {
3011 /* Figure out the highest possible texture index and mark it as used */
3012 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3013 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3014 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3016 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3018 brw_mark_surface_used(prog_data
, max_used
);
3020 /* Emit code to evaluate the actual indexing expression */
3021 texture_reg
= vgrf(glsl_type::uint_type
);
3022 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3023 texture_reg
= bld
.emit_uniformize(texture_reg
);
3028 unreachable("unknown texture source");
3032 if (instr
->op
== nir_texop_txf_ms
||
3033 instr
->op
== nir_texop_samples_identical
) {
3034 if (devinfo
->gen
>= 7 &&
3035 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3036 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3038 mcs
= brw_imm_ud(0u);
3042 for (unsigned i
= 0; i
< 3; i
++) {
3043 if (instr
->const_offset
[i
] != 0) {
3044 assert(offset_components
== 0);
3045 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
3050 enum glsl_base_type dest_base_type
=
3051 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3053 const glsl_type
*dest_type
=
3054 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3057 ir_texture_opcode op
;
3058 switch (instr
->op
) {
3059 case nir_texop_lod
: op
= ir_lod
; break;
3060 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3061 case nir_texop_tex
: op
= ir_tex
; break;
3062 case nir_texop_tg4
: op
= ir_tg4
; break;
3063 case nir_texop_txb
: op
= ir_txb
; break;
3064 case nir_texop_txd
: op
= ir_txd
; break;
3065 case nir_texop_txf
: op
= ir_txf
; break;
3066 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3067 case nir_texop_txl
: op
= ir_txl
; break;
3068 case nir_texop_txs
: op
= ir_txs
; break;
3069 case nir_texop_texture_samples
: {
3070 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3071 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3072 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3075 inst
->header_size
= 1;
3076 inst
->base_mrf
= -1;
3079 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3081 unreachable("unknown texture opcode");
3084 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3085 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3086 tex_offset
, mcs
, gather_component
,
3087 is_cube_array
, texture
, texture_reg
);
3089 fs_reg dest
= get_nir_dest(instr
->dest
);
3090 dest
.type
= this->result
.type
;
3091 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3092 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3093 dest
, this->result
),
3094 (1 << num_components
) - 1);
3098 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3100 switch (instr
->type
) {
3101 case nir_jump_break
:
3102 bld
.emit(BRW_OPCODE_BREAK
);
3104 case nir_jump_continue
:
3105 bld
.emit(BRW_OPCODE_CONTINUE
);
3107 case nir_jump_return
:
3109 unreachable("unknown jump");