2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
34 fs_visitor::emit_nir_code()
36 nir_shader
*nir
= prog
->nir
;
38 /* emit the arrays used for inputs and outputs - load/store intrinsics will
39 * be converted to reads/writes of these arrays
42 if (nir
->num_inputs
> 0) {
43 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
44 nir_setup_inputs(nir
);
47 if (nir
->num_outputs
> 0) {
48 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
49 nir_setup_outputs(nir
);
52 if (nir
->num_uniforms
> 0) {
53 nir_setup_uniforms(nir
);
56 nir_emit_system_values(nir
);
58 /* get the main function and emit it */
59 nir_foreach_overload(nir
, overload
) {
60 assert(strcmp(overload
->function
->name
, "main") == 0);
61 assert(overload
->impl
);
62 nir_emit_impl(overload
->impl
);
67 fs_visitor::nir_setup_inputs(nir_shader
*shader
)
69 foreach_list_typed(nir_variable
, var
, node
, &shader
->inputs
) {
70 enum brw_reg_type type
= brw_type_for_base_type(var
->type
);
71 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
75 case MESA_SHADER_VERTEX
: {
76 /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
77 * stored in nir_variable::location.
79 * However, NIR's load_input intrinsics use a different index - an
80 * offset into a single contiguous array containing all inputs.
81 * This index corresponds to the nir_variable::driver_location field.
83 * So, we need to copy from fs_reg(ATTR, var->location) to
84 * offset(nir_inputs, var->data.driver_location).
86 const glsl_type
*const t
= var
->type
->without_array();
87 const unsigned components
= t
->components();
88 const unsigned cols
= t
->matrix_columns
;
89 const unsigned elts
= t
->vector_elements
;
90 unsigned array_length
= var
->type
->is_array() ? var
->type
->length
: 1;
91 for (unsigned i
= 0; i
< array_length
; i
++) {
92 for (unsigned j
= 0; j
< cols
; j
++) {
93 for (unsigned k
= 0; k
< elts
; k
++) {
94 bld
.MOV(offset(retype(input
, type
), bld
,
95 components
* i
+ elts
* j
+ k
),
96 offset(fs_reg(ATTR
, var
->data
.location
+ i
, type
),
103 case MESA_SHADER_GEOMETRY
:
104 case MESA_SHADER_COMPUTE
:
105 unreachable("fs_visitor not used for these stages yet.");
107 case MESA_SHADER_FRAGMENT
:
108 if (var
->data
.location
== VARYING_SLOT_POS
) {
109 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
110 var
->data
.origin_upper_left
);
111 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
114 emit_general_interpolation(input
, var
->name
, var
->type
,
115 (glsl_interp_qualifier
) var
->data
.interpolation
,
116 var
->data
.location
, var
->data
.centroid
,
125 fs_visitor::nir_setup_outputs(nir_shader
*shader
)
127 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
129 foreach_list_typed(nir_variable
, var
, node
, &shader
->outputs
) {
130 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
132 int vector_elements
=
133 var
->type
->is_array() ? var
->type
->fields
.array
->vector_elements
134 : var
->type
->vector_elements
;
137 case MESA_SHADER_VERTEX
:
138 for (int i
= 0; i
< ALIGN(type_size(var
->type
), 4) / 4; i
++) {
139 int output
= var
->data
.location
+ i
;
140 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
141 this->output_components
[output
] = vector_elements
;
144 case MESA_SHADER_FRAGMENT
:
145 if (var
->data
.index
> 0) {
146 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
147 assert(var
->data
.index
== 1);
148 this->dual_src_output
= reg
;
149 this->do_dual_src
= true;
150 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
151 /* Writing gl_FragColor outputs to all color regions. */
152 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
153 this->outputs
[i
] = reg
;
154 this->output_components
[i
] = 4;
156 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
157 this->frag_depth
= reg
;
158 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
159 this->sample_mask
= reg
;
161 /* gl_FragData or a user-defined FS output */
162 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
163 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
165 /* General color output. */
166 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
167 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
168 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
169 this->output_components
[output
] = vector_elements
;
174 unreachable("unhandled shader stage");
180 fs_visitor::nir_setup_uniforms(nir_shader
*shader
)
182 uniforms
= shader
->num_uniforms
;
183 num_direct_uniforms
= shader
->num_direct_uniforms
;
185 /* We split the uniform register file in half. The first half is
186 * entirely direct uniforms. The second half is indirect.
188 param_size
[0] = num_direct_uniforms
;
189 if (shader
->num_uniforms
> num_direct_uniforms
)
190 param_size
[num_direct_uniforms
] = shader
->num_uniforms
- num_direct_uniforms
;
192 if (dispatch_width
!= 8)
196 foreach_list_typed(nir_variable
, var
, node
, &shader
->uniforms
) {
197 /* UBO's and atomics don't take up space in the uniform file */
198 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
201 if (strncmp(var
->name
, "gl_", 3) == 0)
202 nir_setup_builtin_uniform(var
);
204 nir_setup_uniform(var
);
207 /* prog_to_nir doesn't create uniform variables; set param up directly. */
208 for (unsigned p
= 0; p
< prog
->Parameters
->NumParameters
; p
++) {
209 for (unsigned int i
= 0; i
< 4; i
++) {
210 stage_prog_data
->param
[4 * p
+ i
] =
211 &prog
->Parameters
->ParameterValues
[p
][i
];
218 fs_visitor::nir_setup_uniform(nir_variable
*var
)
220 int namelen
= strlen(var
->name
);
222 /* The data for our (non-builtin) uniforms is stored in a series of
223 * gl_uniform_driver_storage structs for each subcomponent that
224 * glGetUniformLocation() could name. We know it's been set up in the
225 * same order we'd walk the type, so walk the list of storage and find
226 * anything with our name, or the prefix of a component that starts with
229 unsigned index
= var
->data
.driver_location
;
230 for (unsigned u
= 0; u
< shader_prog
->NumUniformStorage
; u
++) {
231 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
233 if (storage
->builtin
)
236 if (strncmp(var
->name
, storage
->name
, namelen
) != 0 ||
237 (storage
->name
[namelen
] != 0 &&
238 storage
->name
[namelen
] != '.' &&
239 storage
->name
[namelen
] != '[')) {
243 unsigned slots
= storage
->type
->component_slots();
244 if (storage
->array_elements
)
245 slots
*= storage
->array_elements
;
247 for (unsigned i
= 0; i
< slots
; i
++) {
248 stage_prog_data
->param
[index
++] = &storage
->storage
[i
];
252 /* Make sure we actually initialized the right amount of stuff here. */
253 assert(var
->data
.driver_location
+ var
->type
->component_slots() == index
);
257 fs_visitor::nir_setup_builtin_uniform(nir_variable
*var
)
259 const nir_state_slot
*const slots
= var
->state_slots
;
260 assert(var
->state_slots
!= NULL
);
262 unsigned uniform_index
= var
->data
.driver_location
;
263 for (unsigned int i
= 0; i
< var
->num_state_slots
; i
++) {
264 /* This state reference has already been setup by ir_to_mesa, but we'll
265 * get the same index back here.
267 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
268 (gl_state_index
*)slots
[i
].tokens
);
270 /* Add each of the unique swizzles of the element as a parameter.
271 * This'll end up matching the expected layout of the
272 * array/matrix/structure we're trying to fill in.
275 for (unsigned int j
= 0; j
< 4; j
++) {
276 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
277 if (swiz
== last_swiz
)
281 stage_prog_data
->param
[uniform_index
++] =
282 &prog
->Parameters
->ParameterValues
[index
][swiz
];
288 emit_system_values_block(nir_block
*block
, void *void_visitor
)
290 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
293 nir_foreach_instr(block
, instr
) {
294 if (instr
->type
!= nir_instr_type_intrinsic
)
297 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
298 switch (intrin
->intrinsic
) {
299 case nir_intrinsic_load_vertex_id
:
300 unreachable("should be lowered by lower_vertex_id().");
302 case nir_intrinsic_load_vertex_id_zero_base
:
303 assert(v
->stage
== MESA_SHADER_VERTEX
);
304 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
305 if (reg
->file
== BAD_FILE
)
306 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
309 case nir_intrinsic_load_base_vertex
:
310 assert(v
->stage
== MESA_SHADER_VERTEX
);
311 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
312 if (reg
->file
== BAD_FILE
)
313 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
316 case nir_intrinsic_load_instance_id
:
317 assert(v
->stage
== MESA_SHADER_VERTEX
);
318 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
319 if (reg
->file
== BAD_FILE
)
320 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
323 case nir_intrinsic_load_sample_pos
:
324 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
325 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
326 if (reg
->file
== BAD_FILE
)
327 *reg
= *v
->emit_samplepos_setup();
330 case nir_intrinsic_load_sample_id
:
331 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
332 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
333 if (reg
->file
== BAD_FILE
)
334 *reg
= *v
->emit_sampleid_setup();
337 case nir_intrinsic_load_sample_mask_in
:
338 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
339 assert(v
->devinfo
->gen
>= 7);
340 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
341 if (reg
->file
== BAD_FILE
)
342 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
343 BRW_REGISTER_TYPE_D
));
355 fs_visitor::nir_emit_system_values(nir_shader
*shader
)
357 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
358 nir_foreach_overload(shader
, overload
) {
359 assert(strcmp(overload
->function
->name
, "main") == 0);
360 assert(overload
->impl
);
361 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
366 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
368 nir_locals
= reralloc(mem_ctx
, nir_locals
, fs_reg
, impl
->reg_alloc
);
369 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
370 unsigned array_elems
=
371 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
372 unsigned size
= array_elems
* reg
->num_components
;
373 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
376 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
379 nir_emit_cf_list(&impl
->body
);
383 fs_visitor::nir_emit_cf_list(exec_list
*list
)
385 exec_list_validate(list
);
386 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
387 switch (node
->type
) {
389 nir_emit_if(nir_cf_node_as_if(node
));
392 case nir_cf_node_loop
:
393 nir_emit_loop(nir_cf_node_as_loop(node
));
396 case nir_cf_node_block
:
397 nir_emit_block(nir_cf_node_as_block(node
));
401 unreachable("Invalid CFG node block");
407 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
409 /* first, put the condition into f0 */
410 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
411 retype(get_nir_src(if_stmt
->condition
),
412 BRW_REGISTER_TYPE_D
));
413 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
415 bld
.IF(BRW_PREDICATE_NORMAL
);
417 nir_emit_cf_list(&if_stmt
->then_list
);
419 /* note: if the else is empty, dead CF elimination will remove it */
420 bld
.emit(BRW_OPCODE_ELSE
);
422 nir_emit_cf_list(&if_stmt
->else_list
);
424 bld
.emit(BRW_OPCODE_ENDIF
);
426 try_replace_with_sel();
430 fs_visitor::nir_emit_loop(nir_loop
*loop
)
432 bld
.emit(BRW_OPCODE_DO
);
434 nir_emit_cf_list(&loop
->body
);
436 bld
.emit(BRW_OPCODE_WHILE
);
440 fs_visitor::nir_emit_block(nir_block
*block
)
442 nir_foreach_instr(block
, instr
) {
443 nir_emit_instr(instr
);
448 fs_visitor::nir_emit_instr(nir_instr
*instr
)
450 const fs_builder abld
= bld
.annotate(NULL
, instr
);
452 switch (instr
->type
) {
453 case nir_instr_type_alu
:
454 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
457 case nir_instr_type_intrinsic
:
458 nir_emit_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case nir_instr_type_tex
:
462 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
465 case nir_instr_type_load_const
:
466 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
469 case nir_instr_type_ssa_undef
:
470 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
473 case nir_instr_type_jump
:
474 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
478 unreachable("unknown instruction type");
483 brw_type_for_nir_type(nir_alu_type type
)
486 case nir_type_unsigned
:
487 return BRW_REGISTER_TYPE_UD
;
490 return BRW_REGISTER_TYPE_D
;
492 return BRW_REGISTER_TYPE_F
;
494 unreachable("unknown type");
497 return BRW_REGISTER_TYPE_F
;
501 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
502 const fs_reg
&result
)
504 if (!instr
->src
[0].src
.is_ssa
||
505 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
508 nir_intrinsic_instr
*src0
=
509 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
511 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
514 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
515 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
518 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
519 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
522 fs_reg tmp
= vgrf(glsl_type::int_type
);
524 if (devinfo
->gen
>= 6) {
525 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
526 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
528 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
530 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
531 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
533 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
535 * This negation looks like it's safe in practice, because bits 0:4 will
536 * surely be TRIANGLES
539 if (value1
->f
[0] == -1.0f
) {
543 tmp
.type
= BRW_REGISTER_TYPE_W
;
544 tmp
.subreg_offset
= 2;
547 fs_inst
*or_inst
= bld
.OR(tmp
, g0
, fs_reg(0x3f80));
548 or_inst
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
550 tmp
.type
= BRW_REGISTER_TYPE_D
;
551 tmp
.subreg_offset
= 0;
554 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
555 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
557 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
559 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
560 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
562 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
564 * This negation looks like it's safe in practice, because bits 0:4 will
565 * surely be TRIANGLES
568 if (value1
->f
[0] == -1.0f
) {
572 bld
.OR(tmp
, g1_6
, fs_reg(0x3f800000));
574 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, fs_reg(0xbf800000));
580 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
582 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
585 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
586 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
589 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
590 op
[i
] = get_nir_src(instr
->src
[i
].src
);
591 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
592 op
[i
].abs
= instr
->src
[i
].abs
;
593 op
[i
].negate
= instr
->src
[i
].negate
;
596 /* We get a bunch of mov's out of the from_ssa pass and they may still
597 * be vectorized. We'll handle them as a special-case. We'll also
598 * handle vecN here because it's basically the same thing.
606 fs_reg temp
= result
;
607 bool need_extra_copy
= false;
608 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
609 if (!instr
->src
[i
].src
.is_ssa
&&
610 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
611 need_extra_copy
= true;
612 temp
= bld
.vgrf(result
.type
, 4);
617 for (unsigned i
= 0; i
< 4; i
++) {
618 if (!(instr
->dest
.write_mask
& (1 << i
)))
621 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
622 inst
= bld
.MOV(offset(temp
, bld
, i
),
623 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
625 inst
= bld
.MOV(offset(temp
, bld
, i
),
626 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
628 inst
->saturate
= instr
->dest
.saturate
;
631 /* In this case the source and destination registers were the same,
632 * so we need to insert an extra set of moves in order to deal with
635 if (need_extra_copy
) {
636 for (unsigned i
= 0; i
< 4; i
++) {
637 if (!(instr
->dest
.write_mask
& (1 << i
)))
640 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
649 /* At this point, we have dealt with any instruction that operates on
650 * more than a single channel. Therefore, we can just adjust the source
651 * and destination registers for that channel and emit the instruction.
653 unsigned channel
= 0;
654 if (nir_op_infos
[instr
->op
].output_size
== 0) {
655 /* Since NIR is doing the scalarizing for us, we should only ever see
656 * vectorized operations with a single channel.
658 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
659 channel
= ffs(instr
->dest
.write_mask
) - 1;
661 result
= offset(result
, bld
, channel
);
664 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
665 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
666 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
672 inst
= bld
.MOV(result
, op
[0]);
673 inst
->saturate
= instr
->dest
.saturate
;
678 bld
.MOV(result
, op
[0]);
682 /* AND(val, 0x80000000) gives the sign bit.
684 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
687 bld
.CMP(bld
.null_reg_f(), op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
689 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
690 op
[0].type
= BRW_REGISTER_TYPE_UD
;
691 result
.type
= BRW_REGISTER_TYPE_UD
;
692 bld
.AND(result_int
, op
[0], fs_reg(0x80000000u
));
694 inst
= bld
.OR(result_int
, result_int
, fs_reg(0x3f800000u
));
695 inst
->predicate
= BRW_PREDICATE_NORMAL
;
696 if (instr
->dest
.saturate
) {
697 inst
= bld
.MOV(result
, result
);
698 inst
->saturate
= true;
704 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
705 * -> non-negative val generates 0x00000000.
706 * Predicated OR sets 1 if val is positive.
708 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_G
);
709 bld
.ASR(result
, op
[0], fs_reg(31));
710 inst
= bld
.OR(result
, result
, fs_reg(1));
711 inst
->predicate
= BRW_PREDICATE_NORMAL
;
715 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
716 inst
->saturate
= instr
->dest
.saturate
;
720 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
721 inst
->saturate
= instr
->dest
.saturate
;
725 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
726 inst
->saturate
= instr
->dest
.saturate
;
730 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
731 inst
->saturate
= instr
->dest
.saturate
;
735 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
736 inst
->saturate
= instr
->dest
.saturate
;
740 if (fs_key
->high_quality_derivatives
) {
741 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
743 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
745 inst
->saturate
= instr
->dest
.saturate
;
747 case nir_op_fddx_fine
:
748 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
749 inst
->saturate
= instr
->dest
.saturate
;
751 case nir_op_fddx_coarse
:
752 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
753 inst
->saturate
= instr
->dest
.saturate
;
756 if (fs_key
->high_quality_derivatives
) {
757 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
758 fs_reg(fs_key
->render_to_fbo
));
760 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
761 fs_reg(fs_key
->render_to_fbo
));
763 inst
->saturate
= instr
->dest
.saturate
;
765 case nir_op_fddy_fine
:
766 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
767 fs_reg(fs_key
->render_to_fbo
));
768 inst
->saturate
= instr
->dest
.saturate
;
770 case nir_op_fddy_coarse
:
771 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
772 fs_reg(fs_key
->render_to_fbo
));
773 inst
->saturate
= instr
->dest
.saturate
;
778 inst
= bld
.ADD(result
, op
[0], op
[1]);
779 inst
->saturate
= instr
->dest
.saturate
;
783 inst
= bld
.MUL(result
, op
[0], op
[1]);
784 inst
->saturate
= instr
->dest
.saturate
;
788 bld
.MUL(result
, op
[0], op
[1]);
791 case nir_op_imul_high
:
792 case nir_op_umul_high
: {
793 if (devinfo
->gen
>= 7)
794 no16("SIMD16 explicit accumulator operands unsupported\n");
796 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
), result
.type
);
798 fs_inst
*mul
= bld
.MUL(acc
, op
[0], op
[1]);
799 bld
.MACH(result
, op
[0], op
[1]);
801 /* Until Gen8, integer multiplies read 32-bits from one source, and
802 * 16-bits from the other, and relying on the MACH instruction to
803 * generate the high bits of the result.
805 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
806 * but in order to do a 64x64-bit multiply we have to simulate the
807 * previous behavior and then use a MACH instruction.
809 * FINISHME: Don't use source modifiers on src1.
811 if (devinfo
->gen
>= 8) {
812 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
813 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
814 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
815 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
816 mul
->src
[1].stride
= 2;
818 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
819 mul
->src
[1].stride
= 2;
827 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
830 case nir_op_uadd_carry
:
831 unreachable("Should have been lowered by carry_to_arith().");
833 case nir_op_usub_borrow
:
834 unreachable("Should have been lowered by borrow_to_arith().");
837 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
843 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
849 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
854 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
859 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
863 if (devinfo
->gen
>= 8) {
864 resolve_source_modifiers(&op
[0]);
866 bld
.NOT(result
, op
[0]);
869 if (devinfo
->gen
>= 8) {
870 resolve_source_modifiers(&op
[0]);
871 resolve_source_modifiers(&op
[1]);
873 bld
.XOR(result
, op
[0], op
[1]);
876 if (devinfo
->gen
>= 8) {
877 resolve_source_modifiers(&op
[0]);
878 resolve_source_modifiers(&op
[1]);
880 bld
.OR(result
, op
[0], op
[1]);
883 if (devinfo
->gen
>= 8) {
884 resolve_source_modifiers(&op
[0]);
885 resolve_source_modifiers(&op
[1]);
887 bld
.AND(result
, op
[0], op
[1]);
899 case nir_op_ball_fequal2
:
900 case nir_op_ball_iequal2
:
901 case nir_op_ball_fequal3
:
902 case nir_op_ball_iequal3
:
903 case nir_op_ball_fequal4
:
904 case nir_op_ball_iequal4
:
905 case nir_op_bany_fnequal2
:
906 case nir_op_bany_inequal2
:
907 case nir_op_bany_fnequal3
:
908 case nir_op_bany_inequal3
:
909 case nir_op_bany_fnequal4
:
910 case nir_op_bany_inequal4
:
911 unreachable("Lowered by nir_lower_alu_reductions");
913 case nir_op_fnoise1_1
:
914 case nir_op_fnoise1_2
:
915 case nir_op_fnoise1_3
:
916 case nir_op_fnoise1_4
:
917 case nir_op_fnoise2_1
:
918 case nir_op_fnoise2_2
:
919 case nir_op_fnoise2_3
:
920 case nir_op_fnoise2_4
:
921 case nir_op_fnoise3_1
:
922 case nir_op_fnoise3_2
:
923 case nir_op_fnoise3_3
:
924 case nir_op_fnoise3_4
:
925 case nir_op_fnoise4_1
:
926 case nir_op_fnoise4_2
:
927 case nir_op_fnoise4_3
:
928 case nir_op_fnoise4_4
:
929 unreachable("not reached: should be handled by lower_noise");
932 unreachable("not reached: should be handled by ldexp_to_arith()");
935 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
936 inst
->saturate
= instr
->dest
.saturate
;
940 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
941 inst
->saturate
= instr
->dest
.saturate
;
946 bld
.MOV(result
, negate(op
[0]));
950 bld
.CMP(result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
);
953 bld
.CMP(result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
957 inst
= bld
.RNDZ(result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
962 op
[0].negate
= !op
[0].negate
;
963 fs_reg temp
= vgrf(glsl_type::float_type
);
964 bld
.RNDD(temp
, op
[0]);
966 inst
= bld
.MOV(result
, temp
);
967 inst
->saturate
= instr
->dest
.saturate
;
971 inst
= bld
.RNDD(result
, op
[0]);
972 inst
->saturate
= instr
->dest
.saturate
;
975 inst
= bld
.FRC(result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
978 case nir_op_fround_even
:
979 inst
= bld
.RNDE(result
, op
[0]);
980 inst
->saturate
= instr
->dest
.saturate
;
986 if (devinfo
->gen
>= 6) {
987 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
988 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
990 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
991 inst
= bld
.SEL(result
, op
[0], op
[1]);
992 inst
->predicate
= BRW_PREDICATE_NORMAL
;
994 inst
->saturate
= instr
->dest
.saturate
;
1000 if (devinfo
->gen
>= 6) {
1001 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
1002 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1004 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
1005 inst
= bld
.SEL(result
, op
[0], op
[1]);
1006 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1008 inst
->saturate
= instr
->dest
.saturate
;
1011 case nir_op_pack_snorm_2x16
:
1012 case nir_op_pack_snorm_4x8
:
1013 case nir_op_pack_unorm_2x16
:
1014 case nir_op_pack_unorm_4x8
:
1015 case nir_op_unpack_snorm_2x16
:
1016 case nir_op_unpack_snorm_4x8
:
1017 case nir_op_unpack_unorm_2x16
:
1018 case nir_op_unpack_unorm_4x8
:
1019 case nir_op_unpack_half_2x16
:
1020 case nir_op_pack_half_2x16
:
1021 unreachable("not reached: should be handled by lower_packing_builtins");
1023 case nir_op_unpack_half_2x16_split_x
:
1024 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1025 inst
->saturate
= instr
->dest
.saturate
;
1027 case nir_op_unpack_half_2x16_split_y
:
1028 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1029 inst
->saturate
= instr
->dest
.saturate
;
1033 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1034 inst
->saturate
= instr
->dest
.saturate
;
1037 case nir_op_bitfield_reverse
:
1038 bld
.BFREV(result
, op
[0]);
1041 case nir_op_bit_count
:
1042 bld
.CBIT(result
, op
[0]);
1045 case nir_op_ufind_msb
:
1046 case nir_op_ifind_msb
: {
1047 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1049 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1050 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1051 * subtract the result from 31 to convert the MSB count into an LSB count.
1054 bld
.CMP(bld
.null_reg_d(), result
, fs_reg(-1), BRW_CONDITIONAL_NZ
);
1055 fs_reg
neg_result(result
);
1056 neg_result
.negate
= true;
1057 inst
= bld
.ADD(result
, neg_result
, fs_reg(31));
1058 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1062 case nir_op_find_lsb
:
1063 bld
.FBL(result
, op
[0]);
1066 case nir_op_ubitfield_extract
:
1067 case nir_op_ibitfield_extract
:
1068 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1071 bld
.BFI1(result
, op
[0], op
[1]);
1074 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1077 case nir_op_bitfield_insert
:
1078 unreachable("not reached: should be handled by "
1079 "lower_instructions::bitfield_insert_to_bfm_bfi");
1082 bld
.SHL(result
, op
[0], op
[1]);
1085 bld
.ASR(result
, op
[0], op
[1]);
1088 bld
.SHR(result
, op
[0], op
[1]);
1091 case nir_op_pack_half_2x16_split
:
1092 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1096 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1097 inst
->saturate
= instr
->dest
.saturate
;
1101 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1102 inst
->saturate
= instr
->dest
.saturate
;
1106 if (optimize_frontfacing_ternary(instr
, result
))
1109 bld
.CMP(bld
.null_reg_d(), op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
);
1110 inst
= bld
.SEL(result
, op
[1], op
[2]);
1111 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1115 unreachable("unhandled instruction");
1118 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1119 * to sign extend the low bit to 0/~0
1121 if (devinfo
->gen
<= 5 &&
1122 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1123 fs_reg masked
= vgrf(glsl_type::int_type
);
1124 bld
.AND(masked
, result
, fs_reg(1));
1125 masked
.negate
= true;
1126 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1131 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1132 nir_load_const_instr
*instr
)
1134 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1136 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1137 bld
.MOV(offset(reg
, bld
, i
), fs_reg(instr
->value
.i
[i
]));
1139 nir_ssa_values
[instr
->def
.index
] = reg
;
1143 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1145 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1146 instr
->def
.num_components
);
1150 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1151 unsigned base_offset
, nir_src
*indirect
)
1155 assert(!nir_reg
->is_global
);
1157 reg
= v
->nir_locals
[nir_reg
->index
];
1159 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1161 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1163 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1164 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1165 fs_reg(multiplier
));
1172 fs_visitor::get_nir_src(nir_src src
)
1176 reg
= nir_ssa_values
[src
.ssa
->index
];
1178 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1182 /* to avoid floating-point denorm flushing problems, set the type by
1183 * default to D - instructions that need floating point semantics will set
1184 * this to F if they need to
1186 return retype(reg
, BRW_REGISTER_TYPE_D
);
1190 fs_visitor::get_nir_dest(nir_dest dest
)
1193 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1194 dest
.ssa
.num_components
);
1195 return nir_ssa_values
[dest
.ssa
.index
];
1198 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1203 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1206 for (unsigned i
= 0; i
< 4; i
++) {
1207 if (!((wr_mask
>> i
) & 1))
1210 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1211 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1212 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1213 if (new_inst
->src
[j
].file
== GRF
)
1214 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1221 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
1224 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1225 dest
= get_nir_dest(instr
->dest
);
1227 bool has_indirect
= false;
1229 switch (instr
->intrinsic
) {
1230 case nir_intrinsic_discard
:
1231 case nir_intrinsic_discard_if
: {
1232 /* We track our discarded pixels in f0.1. By predicating on it, we can
1233 * update just the flag bits that aren't yet discarded. If there's no
1234 * condition, we emit a CMP of g0 != g0, so all currently executing
1235 * channels will get turned off.
1238 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1239 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1240 fs_reg(0), BRW_CONDITIONAL_Z
);
1242 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1243 BRW_REGISTER_TYPE_UW
));
1244 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1246 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1247 cmp
->flag_subreg
= 1;
1249 if (devinfo
->gen
>= 6) {
1250 emit_discard_jump();
1255 case nir_intrinsic_atomic_counter_inc
:
1256 case nir_intrinsic_atomic_counter_dec
:
1257 case nir_intrinsic_atomic_counter_read
: {
1258 unsigned surf_index
= prog_data
->binding_table
.abo_start
+
1259 (unsigned) instr
->const_index
[0];
1260 fs_reg offset
= fs_reg(get_nir_src(instr
->src
[0]));
1262 switch (instr
->intrinsic
) {
1263 case nir_intrinsic_atomic_counter_inc
:
1264 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dest
, offset
,
1265 fs_reg(), fs_reg());
1267 case nir_intrinsic_atomic_counter_dec
:
1268 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dest
, offset
,
1269 fs_reg(), fs_reg());
1271 case nir_intrinsic_atomic_counter_read
:
1272 emit_untyped_surface_read(surf_index
, dest
, offset
);
1275 unreachable("Unreachable");
1280 case nir_intrinsic_load_front_face
:
1281 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1282 *emit_frontfacing_interpolation());
1285 case nir_intrinsic_load_vertex_id
:
1286 unreachable("should be lowered by lower_vertex_id()");
1288 case nir_intrinsic_load_vertex_id_zero_base
: {
1289 fs_reg vertex_id
= nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
1290 assert(vertex_id
.file
!= BAD_FILE
);
1291 dest
.type
= vertex_id
.type
;
1292 bld
.MOV(dest
, vertex_id
);
1296 case nir_intrinsic_load_base_vertex
: {
1297 fs_reg base_vertex
= nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
1298 assert(base_vertex
.file
!= BAD_FILE
);
1299 dest
.type
= base_vertex
.type
;
1300 bld
.MOV(dest
, base_vertex
);
1304 case nir_intrinsic_load_instance_id
: {
1305 fs_reg instance_id
= nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
1306 assert(instance_id
.file
!= BAD_FILE
);
1307 dest
.type
= instance_id
.type
;
1308 bld
.MOV(dest
, instance_id
);
1312 case nir_intrinsic_load_sample_mask_in
: {
1313 fs_reg sample_mask_in
= nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
1314 assert(sample_mask_in
.file
!= BAD_FILE
);
1315 dest
.type
= sample_mask_in
.type
;
1316 bld
.MOV(dest
, sample_mask_in
);
1320 case nir_intrinsic_load_sample_pos
: {
1321 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1322 assert(sample_pos
.file
!= BAD_FILE
);
1323 dest
.type
= sample_pos
.type
;
1324 bld
.MOV(dest
, sample_pos
);
1325 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1329 case nir_intrinsic_load_sample_id
: {
1330 fs_reg sample_id
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
1331 assert(sample_id
.file
!= BAD_FILE
);
1332 dest
.type
= sample_id
.type
;
1333 bld
.MOV(dest
, sample_id
);
1337 case nir_intrinsic_load_uniform_indirect
:
1338 has_indirect
= true;
1340 case nir_intrinsic_load_uniform
: {
1341 unsigned index
= instr
->const_index
[0];
1344 if (index
< num_direct_uniforms
) {
1345 uniform_reg
= fs_reg(UNIFORM
, 0);
1347 uniform_reg
= fs_reg(UNIFORM
, num_direct_uniforms
);
1348 index
-= num_direct_uniforms
;
1351 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1352 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, index
);
1354 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1358 dest
= offset(dest
, bld
, 1);
1363 case nir_intrinsic_load_ubo_indirect
:
1364 has_indirect
= true;
1366 case nir_intrinsic_load_ubo
: {
1367 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
1371 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
1374 /* The block index is not a constant. Evaluate the index expression
1375 * per-channel and add the base UBO index; we have to select a value
1376 * from any live channel.
1378 surf_index
= vgrf(glsl_type::uint_type
);
1379 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
1380 fs_reg(stage_prog_data
->binding_table
.ubo_start
));
1381 surf_index
= bld
.emit_uniformize(surf_index
);
1383 /* Assume this may touch any UBO. It would be nice to provide
1384 * a tighter bound, but the array information is already lowered away.
1386 brw_mark_surface_used(prog_data
,
1387 stage_prog_data
->binding_table
.ubo_start
+
1388 shader_prog
->NumUniformBlocks
- 1);
1392 /* Turn the byte offset into a dword offset. */
1393 fs_reg base_offset
= vgrf(glsl_type::int_type
);
1394 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
1395 BRW_REGISTER_TYPE_D
),
1398 unsigned vec4_offset
= instr
->const_index
[0] / 4;
1399 for (int i
= 0; i
< instr
->num_components
; i
++)
1400 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
1401 base_offset
, vec4_offset
+ i
);
1403 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
1404 packed_consts
.type
= dest
.type
;
1406 fs_reg
const_offset_reg((unsigned) instr
->const_index
[0] & ~15);
1407 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
1408 surf_index
, const_offset_reg
);
1410 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
1411 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
1413 /* The std140 packing rules don't allow vectors to cross 16-byte
1414 * boundaries, and a reg is 32 bytes.
1416 assert(packed_consts
.subreg_offset
< 32);
1418 bld
.MOV(dest
, packed_consts
);
1419 dest
= offset(dest
, bld
, 1);
1425 case nir_intrinsic_load_input_indirect
:
1426 has_indirect
= true;
1428 case nir_intrinsic_load_input
: {
1430 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1431 fs_reg src
= offset(retype(nir_inputs
, dest
.type
), bld
,
1432 instr
->const_index
[0] + index
);
1434 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
1438 dest
= offset(dest
, bld
, 1);
1443 /* Handle ARB_gpu_shader5 interpolation intrinsics
1445 * It's worth a quick word of explanation as to why we handle the full
1446 * variable-based interpolation intrinsic rather than a lowered version
1447 * with like we do for other inputs. We have to do that because the way
1448 * we set up inputs doesn't allow us to use the already setup inputs for
1449 * interpolation. At the beginning of the shader, we go through all of
1450 * the input variables and do the initial interpolation and put it in
1451 * the nir_inputs array based on its location as determined in
1452 * nir_lower_io. If the input isn't used, dead code cleans up and
1453 * everything works fine. However, when we get to the ARB_gpu_shader5
1454 * interpolation intrinsics, we need to reinterpolate the input
1455 * differently. If we used an intrinsic that just had an index it would
1456 * only give us the offset into the nir_inputs array. However, this is
1457 * useless because that value is post-interpolation and we need
1458 * pre-interpolation. In order to get the actual location of the bits
1459 * we get from the vertex fetching hardware, we need the variable.
1461 case nir_intrinsic_interp_var_at_centroid
:
1462 case nir_intrinsic_interp_var_at_sample
:
1463 case nir_intrinsic_interp_var_at_offset
: {
1464 assert(stage
== MESA_SHADER_FRAGMENT
);
1466 ((struct brw_wm_prog_data
*) prog_data
)->pulls_bary
= true;
1468 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1470 /* For most messages, we need one reg of ignored data; the hardware
1471 * requires mlen==1 even when there is no payload. in the per-slot
1472 * offset case, we'll replace this with the proper source data.
1474 fs_reg src
= vgrf(glsl_type::float_type
);
1475 int mlen
= 1; /* one reg unless overriden */
1478 switch (instr
->intrinsic
) {
1479 case nir_intrinsic_interp_var_at_centroid
:
1480 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1481 dst_xy
, src
, fs_reg(0u));
1484 case nir_intrinsic_interp_var_at_sample
: {
1485 /* XXX: We should probably handle non-constant sample id's */
1486 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1487 assert(const_sample
);
1488 unsigned msg_data
= const_sample
? const_sample
->i
[0] << 4 : 0;
1489 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_xy
, src
,
1494 case nir_intrinsic_interp_var_at_offset
: {
1495 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1498 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1499 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1501 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_xy
, src
,
1502 fs_reg(off_x
| (off_y
<< 4)));
1504 src
= vgrf(glsl_type::ivec2_type
);
1505 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1506 BRW_REGISTER_TYPE_F
);
1507 for (int i
= 0; i
< 2; i
++) {
1508 fs_reg temp
= vgrf(glsl_type::float_type
);
1509 bld
.MUL(temp
, offset(offset_src
, bld
, i
), fs_reg(16.0f
));
1510 fs_reg itemp
= vgrf(glsl_type::int_type
);
1511 bld
.MOV(itemp
, temp
); /* float to int */
1513 /* Clamp the upper end of the range to +7/16.
1514 * ARB_gpu_shader5 requires that we support a maximum offset
1515 * of +0.5, which isn't representable in a S0.4 value -- if
1516 * we didn't clamp it, we'd end up with -8/16, which is the
1517 * opposite of what the shader author wanted.
1519 * This is legal due to ARB_gpu_shader5's quantization
1522 * "Not all values of <offset> may be supported; x and y
1523 * offsets may be rounded to fixed-point values with the
1524 * number of fraction bits given by the
1525 * implementation-dependent constant
1526 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
1528 set_condmod(BRW_CONDITIONAL_L
,
1529 bld
.SEL(offset(src
, bld
, i
), itemp
, fs_reg(7)));
1532 mlen
= 2 * dispatch_width
/ 8;
1533 inst
= bld
.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_xy
, src
,
1540 unreachable("Invalid intrinsic");
1544 /* 2 floats per slot returned */
1545 inst
->regs_written
= 2 * dispatch_width
/ 8;
1546 inst
->pi_noperspective
= instr
->variables
[0]->var
->data
.interpolation
==
1547 INTERP_QUALIFIER_NOPERSPECTIVE
;
1549 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1550 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
1551 src
.type
= dest
.type
;
1553 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
1554 dest
= offset(dest
, bld
, 1);
1559 case nir_intrinsic_store_output_indirect
:
1560 has_indirect
= true;
1562 case nir_intrinsic_store_output
: {
1563 fs_reg src
= get_nir_src(instr
->src
[0]);
1565 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
1566 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
1567 instr
->const_index
[0] + index
);
1569 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
1571 bld
.MOV(new_dest
, src
);
1572 src
= offset(src
, bld
, 1);
1577 case nir_intrinsic_barrier
:
1582 unreachable("unknown intrinsic");
1587 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
1589 unsigned sampler
= instr
->sampler_index
;
1590 fs_reg
sampler_reg(sampler
);
1592 /* FINISHME: We're failing to recompile our programs when the sampler is
1593 * updated. This only matters for the texture rectangle scale parameters
1594 * (pre-gen6, or gen6+ with GL_CLAMP).
1596 int texunit
= prog
->SamplerUnits
[sampler
];
1598 int gather_component
= instr
->component
;
1600 bool is_rect
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
;
1602 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
1605 int lod_components
= 0;
1606 int UNUSED offset_components
= 0;
1608 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
1610 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
1611 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
1612 switch (instr
->src
[i
].src_type
) {
1613 case nir_tex_src_bias
:
1614 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1616 case nir_tex_src_comparitor
:
1617 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
1619 case nir_tex_src_coord
:
1620 switch (instr
->op
) {
1622 case nir_texop_txf_ms
:
1623 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
1626 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
1630 case nir_tex_src_ddx
:
1631 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1632 lod_components
= nir_tex_instr_src_size(instr
, i
);
1634 case nir_tex_src_ddy
:
1635 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
1637 case nir_tex_src_lod
:
1638 switch (instr
->op
) {
1640 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
1643 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
1646 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
1650 case nir_tex_src_ms_index
:
1651 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
1653 case nir_tex_src_offset
:
1654 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
1655 if (instr
->is_array
)
1656 offset_components
= instr
->coord_components
- 1;
1658 offset_components
= instr
->coord_components
;
1660 case nir_tex_src_projector
:
1661 unreachable("should be lowered");
1663 case nir_tex_src_sampler_offset
: {
1664 /* Figure out the highest possible sampler index and mark it as used */
1665 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
1666 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
1667 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1669 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1671 brw_mark_surface_used(prog_data
, max_used
);
1673 /* Emit code to evaluate the actual indexing expression */
1674 sampler_reg
= vgrf(glsl_type::uint_type
);
1675 bld
.ADD(sampler_reg
, src
, fs_reg(sampler
));
1676 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
1681 unreachable("unknown texture source");
1685 if (instr
->op
== nir_texop_txf_ms
) {
1686 if (devinfo
->gen
>= 7 &&
1687 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
1688 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
1694 for (unsigned i
= 0; i
< 3; i
++) {
1695 if (instr
->const_offset
[i
] != 0) {
1696 assert(offset_components
== 0);
1697 tex_offset
= fs_reg(brw_texture_offset(instr
->const_offset
, 3));
1702 enum glsl_base_type dest_base_type
;
1703 switch (instr
->dest_type
) {
1704 case nir_type_float
:
1705 dest_base_type
= GLSL_TYPE_FLOAT
;
1708 dest_base_type
= GLSL_TYPE_INT
;
1710 case nir_type_unsigned
:
1711 dest_base_type
= GLSL_TYPE_UINT
;
1714 unreachable("bad type");
1717 const glsl_type
*dest_type
=
1718 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
1721 ir_texture_opcode op
;
1722 switch (instr
->op
) {
1723 case nir_texop_lod
: op
= ir_lod
; break;
1724 case nir_texop_query_levels
: op
= ir_query_levels
; break;
1725 case nir_texop_tex
: op
= ir_tex
; break;
1726 case nir_texop_tg4
: op
= ir_tg4
; break;
1727 case nir_texop_txb
: op
= ir_txb
; break;
1728 case nir_texop_txd
: op
= ir_txd
; break;
1729 case nir_texop_txf
: op
= ir_txf
; break;
1730 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
1731 case nir_texop_txl
: op
= ir_txl
; break;
1732 case nir_texop_txs
: op
= ir_txs
; break;
1734 unreachable("unknown texture opcode");
1737 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
1738 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
1739 tex_offset
, mcs
, gather_component
,
1740 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
1742 fs_reg dest
= get_nir_dest(instr
->dest
);
1743 dest
.type
= this->result
.type
;
1744 unsigned num_components
= nir_tex_instr_dest_size(instr
);
1745 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
1746 dest
, this->result
),
1747 (1 << num_components
) - 1);
1751 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
1753 switch (instr
->type
) {
1754 case nir_jump_break
:
1755 bld
.emit(BRW_OPCODE_BREAK
);
1757 case nir_jump_continue
:
1758 bld
.emit(BRW_OPCODE_CONTINUE
);
1760 case nir_jump_return
:
1762 unreachable("unknown jump");