src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 extern "C" {
  29
  30 #include <sys/types.h>
  31
  32 #include "main/macros.h"
  33 #include "main/shaderobj.h"
  34 #include "main/uniforms.h"
  35 #include "program/prog_parameter.h"
  36 #include "program/prog_print.h"
  37 #include "program/prog_optimize.h"
  38 #include "program/register_allocate.h"
  39 #include "program/sampler.h"
  40 #include "program/hash_table.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_wm.h"
  44 }
  45 #include "brw_fs.h"
  46 #include "../glsl/glsl_types.h"
  47 #include "../glsl/ir_optimization.h"
  48 #include "../glsl/ir_print_visitor.h"
  49
  50 static void
  51 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width)
  52 {
  53    if (reg->file == GRF && reg->reg != 0) {
  54       assert(reg->reg_offset >= 0);
  55       reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset * reg_width;
  56       reg->reg = 0;
  57    }
  58 }
  59
  60 void
  61 fs_visitor::assign_regs_trivial()
  62 {
  63    int last_grf = 0;
  64    int hw_reg_mapping[this->virtual_grf_next];
  65    int i;
  66    int reg_width = c->dispatch_width / 8;
  67
  68    hw_reg_mapping[0] = 0;
  69    /* Note that compressed instructions require alignment to 2 registers. */
  70    hw_reg_mapping[1] = ALIGN(this->first_non_payload_grf, reg_width);
  71    for (i = 2; i < this->virtual_grf_next; i++) {
  72       hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
  73                            this->virtual_grf_sizes[i - 1] * reg_width);
  74    }
  75    last_grf = hw_reg_mapping[i - 1] + (this->virtual_grf_sizes[i - 1] *
  76                                        reg_width);
  77
  78    foreach_iter(exec_list_iterator, iter, this->instructions) {
  79       fs_inst *inst = (fs_inst *)iter.get();
  80
  81       assign_reg(hw_reg_mapping, &inst->dst, reg_width);
  82       assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
  83       assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
  84    }
  85
  86    if (last_grf >= BRW_MAX_GRF) {
  87       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  88            last_grf, BRW_MAX_GRF);
  89    }
  90
  91    this->grf_used = last_grf + reg_width;
  92 }
  93
  94 bool
  95 fs_visitor::assign_regs()
  96 {
  97    /* Most of this allocation was written for a reg_width of 1
  98     * (dispatch_width == 8).  In extending to 16-wide, the code was
  99     * left in place and it was converted to have the hardware
 100     * registers it's allocating be contiguous physical pairs of regs
 101     * for reg_width == 2.
 102     */
 103    int reg_width = c->dispatch_width / 8;
 104    int last_grf = 0;
 105    int hw_reg_mapping[this->virtual_grf_next + 1];
 106    int first_assigned_grf = ALIGN(this->first_non_payload_grf, reg_width);
 107    int base_reg_count = (BRW_MAX_GRF - first_assigned_grf) / reg_width;
 108    int class_sizes[base_reg_count];
 109    int class_count = 0;
 110    int aligned_pair_class = -1;
 111
 112    calculate_live_intervals();
 113
 114    /* Set up the register classes.
 115     *
 116     * The base registers store a scalar value.  For texture samples,
 117     * we get virtual GRFs composed of 4 contiguous hw register.  For
 118     * structures and arrays, we store them as contiguous larger things
 119     * than that, though we should be able to do better most of the
 120     * time.
 121     */
 122    class_sizes[class_count++] = 1;
 123    if (brw->has_pln && intel->gen < 6) {
 124       /* Always set up the (unaligned) pairs for gen5, so we can find
 125        * them for making the aligned pair class.
 126        */
 127       class_sizes[class_count++] = 2;
 128    }
 129    for (int r = 1; r < this->virtual_grf_next; r++) {
 130       int i;
 131
 132       for (i = 0; i < class_count; i++) {
 133          if (class_sizes[i] == this->virtual_grf_sizes[r])
 134             break;
 135       }
 136       if (i == class_count) {
 137          if (this->virtual_grf_sizes[r] >= base_reg_count) {
 138             fail("Object too large to register allocate.\n");
 139          }
 140
 141          class_sizes[class_count++] = this->virtual_grf_sizes[r];
 142       }
 143    }
 144
 145    int ra_reg_count = 0;
 146    int class_base_reg[class_count];
 147    int class_reg_count[class_count];
 148    int classes[class_count + 1];
 149
 150    for (int i = 0; i < class_count; i++) {
 151       class_base_reg[i] = ra_reg_count;
 152       class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
 153       ra_reg_count += class_reg_count[i];
 154    }
 155
 156    struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
 157    for (int i = 0; i < class_count; i++) {
 158       classes[i] = ra_alloc_reg_class(regs);
 159
 160       for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 161          ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
 162       }
 163
 164       /* Add conflicts between our contiguous registers aliasing
 165        * base regs and other register classes' contiguous registers
 166        * that alias base regs, or the base regs themselves for classes[0].
 167        */
 168       for (int c = 0; c <= i; c++) {
 169          for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 170             for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
 171                  c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
 172                  c_r++) {
 173
 174                if (0) {
 175                   printf("%d/%d conflicts %d/%d\n",
 176                          class_sizes[i], first_assigned_grf + i_r,
 177                          class_sizes[c], first_assigned_grf + c_r);
 178                }
 179
 180                ra_add_reg_conflict(regs,
 181                                    class_base_reg[i] + i_r,
 182                                    class_base_reg[c] + c_r);
 183             }
 184          }
 185       }
 186    }
 187
 188    /* Add a special class for aligned pairs, which we'll put delta_x/y
 189     * in on gen5 so that we can do PLN.
 190     */
 191    if (brw->has_pln && reg_width == 1 && intel->gen < 6) {
 192       int reg_count = (base_reg_count - 1) / 2;
 193       int unaligned_pair_class = 1;
 194       assert(class_sizes[unaligned_pair_class] == 2);
 195
 196       aligned_pair_class = class_count;
 197       classes[aligned_pair_class] = ra_alloc_reg_class(regs);
 198       class_sizes[aligned_pair_class] = 2;
 199       class_base_reg[aligned_pair_class] = 0;
 200       class_reg_count[aligned_pair_class] = 0;
 201       int start = (first_assigned_grf & 1) ? 1 : 0;
 202
 203       for (int i = 0; i < reg_count; i++) {
 204          ra_class_add_reg(regs, classes[aligned_pair_class],
 205                           class_base_reg[unaligned_pair_class] + i * 2 + start);
 206       }
 207       class_count++;
 208    }
 209
 210    ra_set_finalize(regs);
 211
 212    struct ra_graph *g = ra_alloc_interference_graph(regs,
 213                                                     this->virtual_grf_next);
 214    /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
 215     * with nodes.
 216     */
 217    ra_set_node_class(g, 0, classes[0]);
 218
 219    for (int i = 1; i < this->virtual_grf_next; i++) {
 220       for (int c = 0; c < class_count; c++) {
 221          if (class_sizes[c] == this->virtual_grf_sizes[i]) {
 222             if (aligned_pair_class >= 0 &&
 223                 this->delta_x.reg == i) {
 224                ra_set_node_class(g, i, classes[aligned_pair_class]);
 225             } else {
 226                ra_set_node_class(g, i, classes[c]);
 227             }
 228             break;
 229          }
 230       }
 231
 232       for (int j = 1; j < i; j++) {
 233          if (virtual_grf_interferes(i, j)) {
 234             ra_add_node_interference(g, i, j);
 235          }
 236       }
 237    }
 238
 239    if (!ra_allocate_no_spills(g)) {
 240       /* Failed to allocate registers.  Spill a reg, and the caller will
 241        * loop back into here to try again.
 242        */
 243       int reg = choose_spill_reg(g);
 244
 245       if (reg == -1) {
 246          fail("no register to spill\n");
 247       } else if (c->dispatch_width == 16) {
 248          fail("no spilling support on 16-wide yet\n");
 249       } else {
 250          spill_reg(reg);
 251       }
 252
 253
 254       ralloc_free(g);
 255       ralloc_free(regs);
 256
 257       return false;
 258    }
 259
 260    /* Get the chosen virtual registers for each node, and map virtual
 261     * regs in the register classes back down to real hardware reg
 262     * numbers.
 263     */
 264    hw_reg_mapping[0] = 0; /* unused */
 265    for (int i = 1; i < this->virtual_grf_next; i++) {
 266       int reg = ra_get_node_reg(g, i);
 267       int hw_reg = -1;
 268
 269       for (int c = 0; c < class_count; c++) {
 270          if (reg >= class_base_reg[c] &&
 271              reg < class_base_reg[c] + class_reg_count[c]) {
 272             hw_reg = reg - class_base_reg[c];
 273             break;
 274          }
 275       }
 276
 277       assert(hw_reg >= 0);
 278       hw_reg_mapping[i] = first_assigned_grf + hw_reg * reg_width;
 279       last_grf = MAX2(last_grf,
 280                       hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
 281    }
 282
 283    foreach_iter(exec_list_iterator, iter, this->instructions) {
 284       fs_inst *inst = (fs_inst *)iter.get();
 285
 286       assign_reg(hw_reg_mapping, &inst->dst, reg_width);
 287       assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
 288       assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
 289    }
 290
 291    this->grf_used = last_grf + reg_width;
 292
 293    ralloc_free(g);
 294    ralloc_free(regs);
 295
 296    return true;
 297 }
 298
 299 void
 300 fs_visitor::emit_unspill(fs_inst *inst, fs_reg dst, uint32_t spill_offset)
 301 {
 302    int size = virtual_grf_sizes[dst.reg];
 303    dst.reg_offset = 0;
 304
 305    for (int chan = 0; chan < size; chan++) {
 306       fs_inst *unspill_inst = new(mem_ctx) fs_inst(FS_OPCODE_UNSPILL,
 307                                                    dst);
 308       dst.reg_offset++;
 309       unspill_inst->offset = spill_offset + chan * REG_SIZE;
 310       unspill_inst->ir = inst->ir;
 311       unspill_inst->annotation = inst->annotation;
 312
 313       /* Choose a MRF that won't conflict with an MRF that's live across the
 314        * spill.  Nothing else will make it up to MRF 14/15.
 315        */
 316       unspill_inst->base_mrf = 14;
 317       unspill_inst->mlen = 1; /* header contains offset */
 318       inst->insert_before(unspill_inst);
 319    }
 320 }
 321
 322 int
 323 fs_visitor::choose_spill_reg(struct ra_graph *g)
 324 {
 325    float loop_scale = 1.0;
 326    float spill_costs[this->virtual_grf_next];
 327    bool no_spill[this->virtual_grf_next];
 328
 329    for (int i = 0; i < this->virtual_grf_next; i++) {
 330       spill_costs[i] = 0.0;
 331       no_spill[i] = false;
 332    }
 333
 334    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 335     * spill/unspill we'll have to do, and guess that the insides of
 336     * loops run 10 times.
 337     */
 338    foreach_iter(exec_list_iterator, iter, this->instructions) {
 339       fs_inst *inst = (fs_inst *)iter.get();
 340
 341       for (unsigned int i = 0; i < 3; i++) {
 342          if (inst->src[i].file == GRF) {
 343             int size = virtual_grf_sizes[inst->src[i].reg];
 344             spill_costs[inst->src[i].reg] += size * loop_scale;
 345          }
 346       }
 347
 348       if (inst->dst.file == GRF) {
 349          int size = virtual_grf_sizes[inst->dst.reg];
 350          spill_costs[inst->dst.reg] += size * loop_scale;
 351       }
 352
 353       switch (inst->opcode) {
 354
 355       case BRW_OPCODE_DO:
 356          loop_scale *= 10;
 357          break;
 358
 359       case BRW_OPCODE_WHILE:
 360          loop_scale /= 10;
 361          break;
 362
 363       case FS_OPCODE_SPILL:
 364          if (inst->src[0].file == GRF)
 365             no_spill[inst->src[0].reg] = true;
 366          break;
 367
 368       case FS_OPCODE_UNSPILL:
 369          if (inst->dst.file == GRF)
 370             no_spill[inst->dst.reg] = true;
 371          break;
 372       }
 373    }
 374
 375    for (int i = 0; i < this->virtual_grf_next; i++) {
 376       if (!no_spill[i])
 377          ra_set_node_spill_cost(g, i, spill_costs[i]);
 378    }
 379
 380    return ra_get_best_spill_node(g);
 381 }
 382
 383 void
 384 fs_visitor::spill_reg(int spill_reg)
 385 {
 386    int size = virtual_grf_sizes[spill_reg];
 387    unsigned int spill_offset = c->last_scratch;
 388    assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */
 389    c->last_scratch += size * REG_SIZE;
 390
 391    /* Generate spill/unspill instructions for the objects being
 392     * spilled.  Right now, we spill or unspill the whole thing to a
 393     * virtual grf of the same size.  For most instructions, though, we
 394     * could just spill/unspill the GRF being accessed.
 395     */
 396    foreach_iter(exec_list_iterator, iter, this->instructions) {
 397       fs_inst *inst = (fs_inst *)iter.get();
 398
 399       for (unsigned int i = 0; i < 3; i++) {
 400          if (inst->src[i].file == GRF &&
 401              inst->src[i].reg == spill_reg) {
 402             inst->src[i].reg = virtual_grf_alloc(size);
 403             emit_unspill(inst, inst->src[i], spill_offset);
 404          }
 405       }
 406
 407       if (inst->dst.file == GRF &&
 408           inst->dst.reg == spill_reg) {
 409          inst->dst.reg = virtual_grf_alloc(size);
 410
 411          /* Since we spill/unspill the whole thing even if we access
 412           * just a component, we may need to unspill before the
 413           * instruction we're spilling for.
 414           */
 415          if (size != 1 || inst->predicated) {
 416             emit_unspill(inst, inst->dst, spill_offset);
 417          }
 418
 419          fs_reg spill_src = inst->dst;
 420          spill_src.reg_offset = 0;
 421          spill_src.abs = false;
 422          spill_src.negate = false;
 423          spill_src.smear = -1;
 424
 425          for (int chan = 0; chan < size; chan++) {
 426             fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,
 427                                                        reg_null_f, spill_src);
 428             spill_src.reg_offset++;
 429             spill_inst->offset = spill_offset + chan * REG_SIZE;
 430             spill_inst->ir = inst->ir;
 431             spill_inst->annotation = inst->annotation;
 432             spill_inst->base_mrf = 14;
 433             spill_inst->mlen = 2; /* header, value */
 434             inst->insert_after(spill_inst);
 435          }
 436       }
 437    }
 438
 439    this->live_intervals_valid = false;
 440 }