src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 extern "C" {
  29
  30 #include <sys/types.h>
  31
  32 #include "main/macros.h"
  33 #include "main/shaderobj.h"
  34 #include "main/uniforms.h"
  35 #include "program/prog_parameter.h"
  36 #include "program/prog_print.h"
  37 #include "program/prog_optimize.h"
  38 #include "program/register_allocate.h"
  39 #include "program/sampler.h"
  40 #include "program/hash_table.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_wm.h"
  44 #include "talloc.h"
  45 }
  46 #include "brw_fs.h"
  47 #include "../glsl/glsl_types.h"
  48 #include "../glsl/ir_optimization.h"
  49 #include "../glsl/ir_print_visitor.h"
  50
  51 static void
  52 assign_reg(int *reg_hw_locations, fs_reg *reg)
  53 {
  54    if (reg->file == GRF && reg->reg != 0) {
  55       assert(reg->reg_offset >= 0);
  56       reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
  57       reg->reg = 0;
  58    }
  59 }
  60
  61 void
  62 fs_visitor::assign_regs_trivial()
  63 {
  64    int last_grf = 0;
  65    int hw_reg_mapping[this->virtual_grf_next];
  66    int i;
  67
  68    hw_reg_mapping[0] = 0;
  69    hw_reg_mapping[1] = this->first_non_payload_grf;
  70    for (i = 2; i < this->virtual_grf_next; i++) {
  71       hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
  72                            this->virtual_grf_sizes[i - 1]);
  73    }
  74    last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
  75
  76    foreach_iter(exec_list_iterator, iter, this->instructions) {
  77       fs_inst *inst = (fs_inst *)iter.get();
  78
  79       assign_reg(hw_reg_mapping, &inst->dst);
  80       assign_reg(hw_reg_mapping, &inst->src[0]);
  81       assign_reg(hw_reg_mapping, &inst->src[1]);
  82    }
  83
  84    this->grf_used = last_grf + 1;
  85 }
  86
  87 void
  88 fs_visitor::assign_regs()
  89 {
  90    int last_grf = 0;
  91    int hw_reg_mapping[this->virtual_grf_next + 1];
  92    int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
  93    int class_sizes[base_reg_count];
  94    int class_count = 0;
  95    int aligned_pair_class = -1;
  96
  97    /* Set up the register classes.
  98     *
  99     * The base registers store a scalar value.  For texture samples,
 100     * we get virtual GRFs composed of 4 contiguous hw register.  For
 101     * structures and arrays, we store them as contiguous larger things
 102     * than that, though we should be able to do better most of the
 103     * time.
 104     */
 105    class_sizes[class_count++] = 1;
 106    if (brw->has_pln && intel->gen < 6) {
 107       /* Always set up the (unaligned) pairs for gen5, so we can find
 108        * them for making the aligned pair class.
 109        */
 110       class_sizes[class_count++] = 2;
 111    }
 112    for (int r = 1; r < this->virtual_grf_next; r++) {
 113       int i;
 114
 115       for (i = 0; i < class_count; i++) {
 116          if (class_sizes[i] == this->virtual_grf_sizes[r])
 117             break;
 118       }
 119       if (i == class_count) {
 120          if (this->virtual_grf_sizes[r] >= base_reg_count) {
 121             fprintf(stderr, "Object too large to register allocate.\n");
 122             this->fail = true;
 123          }
 124
 125          class_sizes[class_count++] = this->virtual_grf_sizes[r];
 126       }
 127    }
 128
 129    int ra_reg_count = 0;
 130    int class_base_reg[class_count];
 131    int class_reg_count[class_count];
 132    int classes[class_count + 1];
 133
 134    for (int i = 0; i < class_count; i++) {
 135       class_base_reg[i] = ra_reg_count;
 136       class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
 137       ra_reg_count += class_reg_count[i];
 138    }
 139
 140    struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
 141    for (int i = 0; i < class_count; i++) {
 142       classes[i] = ra_alloc_reg_class(regs);
 143
 144       for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 145          ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
 146       }
 147
 148       /* Add conflicts between our contiguous registers aliasing
 149        * base regs and other register classes' contiguous registers
 150        * that alias base regs, or the base regs themselves for classes[0].
 151        */
 152       for (int c = 0; c <= i; c++) {
 153          for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 154             for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
 155                  c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
 156                  c_r++) {
 157
 158                if (0) {
 159                   printf("%d/%d conflicts %d/%d\n",
 160                          class_sizes[i], this->first_non_payload_grf + i_r,
 161                          class_sizes[c], this->first_non_payload_grf + c_r);
 162                }
 163
 164                ra_add_reg_conflict(regs,
 165                                    class_base_reg[i] + i_r,
 166                                    class_base_reg[c] + c_r);
 167             }
 168          }
 169       }
 170    }
 171
 172    /* Add a special class for aligned pairs, which we'll put delta_x/y
 173     * in on gen5 so that we can do PLN.
 174     */
 175    if (brw->has_pln && intel->gen < 6) {
 176       int reg_count = (base_reg_count - 1) / 2;
 177       int unaligned_pair_class = 1;
 178       assert(class_sizes[unaligned_pair_class] == 2);
 179
 180       aligned_pair_class = class_count;
 181       classes[aligned_pair_class] = ra_alloc_reg_class(regs);
 182       class_sizes[aligned_pair_class] = 2;
 183       class_base_reg[aligned_pair_class] = 0;
 184       class_reg_count[aligned_pair_class] = 0;
 185       int start = (this->first_non_payload_grf & 1) ? 1 : 0;
 186
 187       for (int i = 0; i < reg_count; i++) {
 188          ra_class_add_reg(regs, classes[aligned_pair_class],
 189                           class_base_reg[unaligned_pair_class] + i * 2 + start);
 190       }
 191       class_count++;
 192    }
 193
 194    ra_set_finalize(regs);
 195
 196    struct ra_graph *g = ra_alloc_interference_graph(regs,
 197                                                     this->virtual_grf_next);
 198    /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
 199     * with nodes.
 200     */
 201    ra_set_node_class(g, 0, classes[0]);
 202
 203    for (int i = 1; i < this->virtual_grf_next; i++) {
 204       for (int c = 0; c < class_count; c++) {
 205          if (class_sizes[c] == this->virtual_grf_sizes[i]) {
 206             if (aligned_pair_class >= 0 &&
 207                 this->delta_x.reg == i) {
 208                ra_set_node_class(g, i, classes[aligned_pair_class]);
 209             } else {
 210                ra_set_node_class(g, i, classes[c]);
 211             }
 212             break;
 213          }
 214       }
 215
 216       for (int j = 1; j < i; j++) {
 217          if (virtual_grf_interferes(i, j)) {
 218             ra_add_node_interference(g, i, j);
 219          }
 220       }
 221    }
 222
 223    /* FINISHME: Handle spilling */
 224    if (!ra_allocate_no_spills(g)) {
 225       fprintf(stderr, "Failed to allocate registers.\n");
 226       this->fail = true;
 227       return;
 228    }
 229
 230    /* Get the chosen virtual registers for each node, and map virtual
 231     * regs in the register classes back down to real hardware reg
 232     * numbers.
 233     */
 234    hw_reg_mapping[0] = 0; /* unused */
 235    for (int i = 1; i < this->virtual_grf_next; i++) {
 236       int reg = ra_get_node_reg(g, i);
 237       int hw_reg = -1;
 238
 239       for (int c = 0; c < class_count; c++) {
 240          if (reg >= class_base_reg[c] &&
 241              reg < class_base_reg[c] + class_reg_count[c]) {
 242             hw_reg = reg - class_base_reg[c];
 243             break;
 244          }
 245       }
 246
 247       assert(hw_reg >= 0);
 248       hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
 249       last_grf = MAX2(last_grf,
 250                       hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
 251    }
 252
 253    foreach_iter(exec_list_iterator, iter, this->instructions) {
 254       fs_inst *inst = (fs_inst *)iter.get();
 255
 256       assign_reg(hw_reg_mapping, &inst->dst);
 257       assign_reg(hw_reg_mapping, &inst->src[0]);
 258       assign_reg(hw_reg_mapping, &inst->src[1]);
 259    }
 260
 261    this->grf_used = last_grf + 1;
 262
 263    talloc_free(g);
 264    talloc_free(regs);
 265 }