2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
34 assign_reg(unsigned *reg_hw_locations
, fs_reg
*reg
)
36 if (reg
->file
== GRF
) {
37 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
43 fs_visitor::assign_regs_trivial()
45 unsigned hw_reg_mapping
[this->alloc
.count
+ 1];
47 int reg_width
= dispatch_width
/ 8;
49 /* Note that compressed instructions require alignment to 2 registers. */
50 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
51 for (i
= 1; i
<= this->alloc
.count
; i
++) {
52 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
53 this->alloc
.sizes
[i
- 1]);
55 this->grf_used
= hw_reg_mapping
[this->alloc
.count
];
57 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
58 assign_reg(hw_reg_mapping
, &inst
->dst
);
59 for (i
= 0; i
< inst
->sources
; i
++) {
60 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
64 if (this->grf_used
>= max_grf
) {
65 fail("Ran out of regs on trivial allocator (%d/%d)\n",
66 this->grf_used
, max_grf
);
68 this->alloc
.count
= this->grf_used
;
74 brw_alloc_reg_set(struct intel_screen
*screen
, int reg_width
)
76 const struct brw_device_info
*devinfo
= screen
->devinfo
;
77 int base_reg_count
= BRW_MAX_GRF
;
78 int index
= reg_width
- 1;
80 /* The registers used to make up almost all values handled in the compiler
81 * are a scalar value occupying a single register (or 2 registers in the
82 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
83 * multiplying allocated register numbers by 2). Things that were
84 * aggregates of scalar values at the GLSL level were split to scalar
85 * values by split_virtual_grfs().
87 * However, texture SEND messages return a series of contiguous registers
88 * to write into. We currently always ask for 4 registers, but we may
89 * convert that to use less some day.
91 * Additionally, on gen5 we need aligned pairs of registers for the PLN
92 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
95 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
96 * and we add in '3' to make indexing the array easier for the common case
97 * (since we'll probably want it for texturing later).
99 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
100 * means that we may need any size up to the sampler message size limit (11
104 int class_sizes
[MAX_VGRF_SIZE
];
106 if (devinfo
->gen
>= 7) {
107 for (class_count
= 0; class_count
< MAX_VGRF_SIZE
; class_count
++)
108 class_sizes
[class_count
] = class_count
+ 1;
110 for (class_count
= 0; class_count
< 4; class_count
++)
111 class_sizes
[class_count
] = class_count
+ 1;
112 class_sizes
[class_count
++] = 8;
115 memset(screen
->wm_reg_sets
[index
].class_to_ra_reg_range
, 0,
116 sizeof(screen
->wm_reg_sets
[index
].class_to_ra_reg_range
));
117 int *class_to_ra_reg_range
= screen
->wm_reg_sets
[index
].class_to_ra_reg_range
;
119 /* Compute the total number of registers across all classes. */
120 int ra_reg_count
= 0;
121 for (int i
= 0; i
< class_count
; i
++) {
122 if (devinfo
->gen
<= 5 && reg_width
== 2) {
125 * In order to reduce the hardware complexity, the following
126 * rules and restrictions apply to the compressed instruction:
128 * * Operand Alignment Rule: With the exceptions listed below, a
129 * source/destination operand in general should be aligned to
130 * even 256-bit physical register with a region size equal to
131 * two 256-bit physical register
133 ra_reg_count
+= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
135 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
137 /* Mark the last register. We'll fill in the beginnings later. */
138 class_to_ra_reg_range
[class_sizes
[i
]] = ra_reg_count
;
141 /* Fill out the rest of the range markers */
142 for (int i
= 1; i
< 17; ++i
) {
143 if (class_to_ra_reg_range
[i
] == 0)
144 class_to_ra_reg_range
[i
] = class_to_ra_reg_range
[i
-1];
147 uint8_t *ra_reg_to_grf
= ralloc_array(screen
, uint8_t, ra_reg_count
);
148 struct ra_regs
*regs
= ra_alloc_reg_set(screen
, ra_reg_count
);
149 if (devinfo
->gen
>= 6)
150 ra_set_allocate_round_robin(regs
);
151 int *classes
= ralloc_array(screen
, int, class_count
);
152 int aligned_pairs_class
= -1;
154 /* Allocate space for q values. We allocate class_count + 1 because we
155 * want to leave room for the aligned pairs class if we have it. */
156 unsigned int **q_values
= ralloc_array(screen
, unsigned int *,
158 for (int i
= 0; i
< class_count
+ 1; ++i
)
159 q_values
[i
] = ralloc_array(q_values
, unsigned int, class_count
+ 1);
161 /* Now, add the registers to their classes, and add the conflicts
162 * between them and the base GRF registers (and also each other).
165 int pairs_base_reg
= 0;
166 int pairs_reg_count
= 0;
167 for (int i
= 0; i
< class_count
; i
++) {
169 if (devinfo
->gen
<= 5 && reg_width
== 2) {
170 class_reg_count
= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
172 /* See comment below. The only difference here is that we are
173 * dealing with pairs of registers instead of single registers.
174 * Registers of odd sizes simply get rounded up. */
175 for (int j
= 0; j
< class_count
; j
++)
176 q_values
[i
][j
] = (class_sizes
[i
] + 1) / 2 +
177 (class_sizes
[j
] + 1) / 2 - 1;
179 class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
181 /* From register_allocate.c:
183 * q(B,C) (indexed by C, B is this register class) in
184 * Runeson/Nyström paper. This is "how many registers of B could
185 * the worst choice register from C conflict with".
187 * If we just let the register allocation algorithm compute these
188 * values, is extremely expensive. However, since all of our
189 * registers are laid out, we can very easily compute them
190 * ourselves. View the register from C as fixed starting at GRF n
191 * somwhere in the middle, and the register from B as sliding back
192 * and forth. Then the first register to conflict from B is the
193 * one starting at n - class_size[B] + 1 and the last register to
194 * conflict will start at n + class_size[B] - 1. Therefore, the
195 * number of conflicts from B is class_size[B] + class_size[C] - 1.
197 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
198 * B | | | | | |n| --> | | | | | | |
199 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
204 for (int j
= 0; j
< class_count
; j
++)
205 q_values
[i
][j
] = class_sizes
[i
] + class_sizes
[j
] - 1;
207 classes
[i
] = ra_alloc_reg_class(regs
);
209 /* Save this off for the aligned pair class at the end. */
210 if (class_sizes
[i
] == 2) {
211 pairs_base_reg
= reg
;
212 pairs_reg_count
= class_reg_count
;
215 if (devinfo
->gen
<= 5 && reg_width
== 2) {
216 for (int j
= 0; j
< class_reg_count
; j
++) {
217 ra_class_add_reg(regs
, classes
[i
], reg
);
219 ra_reg_to_grf
[reg
] = j
* 2;
221 for (int base_reg
= j
;
222 base_reg
< j
+ (class_sizes
[i
] + 1) / 2;
224 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
230 for (int j
= 0; j
< class_reg_count
; j
++) {
231 ra_class_add_reg(regs
, classes
[i
], reg
);
233 ra_reg_to_grf
[reg
] = j
;
235 for (int base_reg
= j
;
236 base_reg
< j
+ class_sizes
[i
];
238 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
245 assert(reg
== ra_reg_count
);
247 /* Add a special class for aligned pairs, which we'll put delta_x/y
248 * in on gen5 so that we can do PLN.
250 if (devinfo
->has_pln
&& reg_width
== 1 && devinfo
->gen
< 6) {
251 aligned_pairs_class
= ra_alloc_reg_class(regs
);
253 for (int i
= 0; i
< pairs_reg_count
; i
++) {
254 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
255 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
259 for (int i
= 0; i
< class_count
; i
++) {
260 /* These are a little counter-intuitive because the pair registers
261 * are required to be aligned while the register they are
262 * potentially interferring with are not. In the case where the
263 * size is even, the worst-case is that the register is
264 * odd-aligned. In the odd-size case, it doesn't matter.
266 q_values
[class_count
][i
] = class_sizes
[i
] / 2 + 1;
267 q_values
[i
][class_count
] = class_sizes
[i
] + 1;
269 q_values
[class_count
][class_count
] = 1;
272 ra_set_finalize(regs
, q_values
);
274 ralloc_free(q_values
);
276 screen
->wm_reg_sets
[index
].regs
= regs
;
277 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->wm_reg_sets
[index
].classes
); i
++)
278 screen
->wm_reg_sets
[index
].classes
[i
] = -1;
279 for (int i
= 0; i
< class_count
; i
++)
280 screen
->wm_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
281 screen
->wm_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
282 screen
->wm_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
286 brw_fs_alloc_reg_sets(struct intel_screen
*screen
)
288 brw_alloc_reg_set(screen
, 1);
289 brw_alloc_reg_set(screen
, 2);
293 count_to_loop_end(const bblock_t
*block
)
295 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
296 return block
->end_ip
;
299 /* Skip the first block, since we don't want to count the do the calling
302 for (block
= block
->next();
304 block
= block
->next()) {
305 if (block
->start()->opcode
== BRW_OPCODE_DO
)
307 if (block
->end()->opcode
== BRW_OPCODE_WHILE
) {
310 return block
->end_ip
;
313 unreachable("not reached");
317 * Sets up interference between thread payload registers and the virtual GRFs
318 * to be allocated for program temporaries.
320 * We want to be able to reallocate the payload for our virtual GRFs, notably
321 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
324 * The layout of the payload registers is:
326 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
327 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
328 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
330 * And we have payload_node_count nodes covering these registers in order
331 * (note that in SIMD16, a node is two registers).
334 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
335 int payload_node_count
,
336 int first_payload_node
)
341 int payload_last_use_ip
[payload_node_count
];
342 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
344 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
345 switch (inst
->opcode
) {
349 /* Since payload regs are deffed only at the start of the shader
350 * execution, any uses of the payload within a loop mean the live
351 * interval extends to the end of the outermost loop. Find the ip of
355 loop_end_ip
= count_to_loop_end(block
);
357 case BRW_OPCODE_WHILE
:
366 use_ip
= loop_end_ip
;
370 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
371 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
372 * the start (see interp_reg()).
374 for (int i
= 0; i
< inst
->sources
; i
++) {
375 if (inst
->src
[i
].file
== HW_REG
&&
376 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
377 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
;
378 if (node_nr
>= payload_node_count
)
381 payload_last_use_ip
[node_nr
] = use_ip
;
385 /* Special case instructions which have extra implied registers used. */
386 switch (inst
->opcode
) {
387 case FS_OPCODE_LINTERP
:
388 /* On gen6+ in SIMD16, there are 4 adjacent registers used by
389 * PLN's sourcing of the deltas, while we list only the first one
390 * in the arguments. Pre-gen6, the deltas are computed in normal
395 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
396 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
397 BRW_GENERAL_REGISTER_FILE
) {
398 for (int i
= 1; i
< 4; ++i
) {
399 int node
= inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
+ i
;
400 assert(node
< payload_node_count
);
401 payload_last_use_ip
[node
] = use_ip
;
409 /* We could omit this for the !inst->header_present case, except
410 * that the simulator apparently incorrectly reads from g0/g1
411 * instead of sideband. It also really freaks out driver
412 * developers to see g0 used in unusual places, so just always
415 payload_last_use_ip
[0] = use_ip
;
416 payload_last_use_ip
[1] = use_ip
;
424 for (int i
= 0; i
< payload_node_count
; i
++) {
425 /* Mark the payload node as interfering with any virtual grf that is
426 * live between the start of the program and our last use of the payload
429 for (unsigned j
= 0; j
< this->alloc
.count
; j
++) {
430 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
431 * in order to not have to worry about the uniform issue described in
432 * calculate_live_intervals().
434 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
435 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
440 for (int i
= 0; i
< payload_node_count
; i
++) {
441 /* Mark each payload node as being allocated to its physical register.
443 * The alternative would be to have per-physical-register classes, which
444 * would just be silly.
446 if (brw
->intelScreen
->devinfo
->gen
<= 5 && dispatch_width
== 16) {
447 /* We have to divide by 2 here because we only have even numbered
448 * registers. Some of the payload registers will be odd, but
449 * that's ok because their physical register numbers have already
450 * been assigned. The only thing this is used for is interference.
452 ra_set_node_reg(g
, first_payload_node
+ i
, i
/ 2);
454 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
460 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
462 * This is used in assign_regs() to decide which of the GRFs that we use as
463 * MRFs on gen7 get normally register allocated, and in register spilling to
464 * see if we can actually use MRFs to do spills without overwriting normal MRF
468 fs_visitor::get_used_mrfs(bool *mrf_used
)
470 int reg_width
= dispatch_width
/ 8;
472 memset(mrf_used
, 0, BRW_MAX_MRF
* sizeof(bool));
474 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
475 if (inst
->dst
.file
== MRF
) {
476 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
477 mrf_used
[reg
] = true;
478 if (reg_width
== 2) {
479 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
480 mrf_used
[reg
+ 4] = true;
482 mrf_used
[reg
+ 1] = true;
487 if (inst
->mlen
> 0) {
488 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
489 mrf_used
[inst
->base_mrf
+ i
] = true;
496 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
497 * messages (treated as MRFs in code generation).
500 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
502 bool mrf_used
[BRW_MAX_MRF
];
503 get_used_mrfs(mrf_used
);
505 for (int i
= 0; i
< BRW_MAX_MRF
; i
++) {
506 /* Mark each MRF reg node as being allocated to its physical register.
508 * The alternative would be to have per-physical-register classes, which
509 * would just be silly.
511 ra_set_node_reg(g
, first_mrf_node
+ i
, GEN7_MRF_HACK_START
+ i
);
513 /* Since we don't have any live/dead analysis on the MRFs, just mark all
514 * that are used as conflicting with all virtual GRFs.
517 for (unsigned j
= 0; j
< this->alloc
.count
; j
++) {
518 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
525 fs_visitor::assign_regs(bool allow_spilling
)
527 struct intel_screen
*screen
= brw
->intelScreen
;
528 /* Most of this allocation was written for a reg_width of 1
529 * (dispatch_width == 8). In extending to SIMD16, the code was
530 * left in place and it was converted to have the hardware
531 * registers it's allocating be contiguous physical pairs of regs
532 * for reg_width == 2.
534 int reg_width
= dispatch_width
/ 8;
535 unsigned hw_reg_mapping
[this->alloc
.count
];
536 int payload_node_count
= ALIGN(this->first_non_payload_grf
, reg_width
);
537 int rsi
= reg_width
- 1; /* Which screen->wm_reg_sets[] to use */
538 calculate_live_intervals();
540 int node_count
= this->alloc
.count
;
541 int first_payload_node
= node_count
;
542 node_count
+= payload_node_count
;
543 int first_mrf_hack_node
= node_count
;
545 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
547 ra_alloc_interference_graph(screen
->wm_reg_sets
[rsi
].regs
, node_count
);
549 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
550 unsigned size
= this->alloc
.sizes
[i
];
553 assert(size
<= ARRAY_SIZE(screen
->wm_reg_sets
[rsi
].classes
) &&
554 "Register allocation relies on split_virtual_grfs()");
555 c
= screen
->wm_reg_sets
[rsi
].classes
[size
- 1];
557 /* Special case: on pre-GEN6 hardware that supports PLN, the
558 * second operand of a PLN instruction needs to be an
559 * even-numbered register, so we have a special register class
560 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
561 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
562 * second operand of a PLN instruction (since it doesn't support
563 * any other interpolation modes). So all we need to do is find
564 * that register and set it to the appropriate class.
566 if (screen
->wm_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
567 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
&&
568 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
569 c
= screen
->wm_reg_sets
[rsi
].aligned_pairs_class
;
572 ra_set_node_class(g
, i
, c
);
574 for (unsigned j
= 0; j
< i
; j
++) {
575 if (virtual_grf_interferes(i
, j
)) {
576 ra_add_node_interference(g
, i
, j
);
581 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
583 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
585 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
586 /* When we do send-from-GRF for FB writes, we need to ensure that
587 * the last write instruction sends from a high register. This is
588 * because the vertex fetcher wants to start filling the low
589 * payload registers while the pixel data port is still working on
590 * writing out the memory. If we don't do this, we get rendering
593 * We could just do "something high". Instead, we just pick the
594 * highest register that works.
597 int size
= alloc
.sizes
[inst
->src
[0].reg
];
598 int reg
= screen
->wm_reg_sets
[rsi
].class_to_ra_reg_range
[size
] - 1;
599 ra_set_node_reg(g
, inst
->src
[0].reg
, reg
);
605 if (dispatch_width
> 8) {
606 /* In 16-wide dispatch we have an issue where a compressed
607 * instruction is actually two instructions executed simultaneiously.
608 * It's actually ok to have the source and destination registers be
609 * the same. In this case, each instruction over-writes its own
610 * source and there's no problem. The real problem here is if the
611 * source and destination registers are off by one. Then you can end
612 * up in a scenario where the first instruction over-writes the
613 * source of the second instruction. Since the compiler doesn't know
614 * about this level of granularity, we simply make the source and
615 * destination interfere.
617 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
618 if (inst
->dst
.file
!= GRF
)
621 for (int i
= 0; i
< inst
->sources
; ++i
) {
622 if (inst
->src
[i
].file
== GRF
) {
623 ra_add_node_interference(g
, inst
->dst
.reg
, inst
->src
[i
].reg
);
629 /* Debug of register spilling: Go spill everything. */
631 int reg
= choose_spill_reg(g
);
640 if (!ra_allocate(g
)) {
641 /* Failed to allocate registers. Spill a reg, and the caller will
642 * loop back into here to try again.
644 int reg
= choose_spill_reg(g
);
647 fail("no register to spill:\n");
648 dump_instructions(NULL
);
649 } else if (allow_spilling
) {
658 /* Get the chosen virtual registers for each node, and map virtual
659 * regs in the register classes back down to real hardware reg
662 this->grf_used
= payload_node_count
;
663 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
664 int reg
= ra_get_node_reg(g
, i
);
666 hw_reg_mapping
[i
] = screen
->wm_reg_sets
[rsi
].ra_reg_to_grf
[reg
];
667 this->grf_used
= MAX2(this->grf_used
,
668 hw_reg_mapping
[i
] + this->alloc
.sizes
[i
]);
671 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
672 assign_reg(hw_reg_mapping
, &inst
->dst
);
673 for (int i
= 0; i
< inst
->sources
; i
++) {
674 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
678 this->alloc
.count
= this->grf_used
;
686 fs_visitor::emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg dst
,
687 uint32_t spill_offset
, int count
)
690 if (dispatch_width
== 16 && count
% 2 == 0) {
695 for (int i
= 0; i
< count
/ reg_size
; i
++) {
696 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
697 bool gen7_read
= brw
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
699 fs_inst
*unspill_inst
=
700 new(mem_ctx
) fs_inst(gen7_read
?
701 SHADER_OPCODE_GEN7_SCRATCH_READ
:
702 SHADER_OPCODE_GEN4_SCRATCH_READ
,
704 unspill_inst
->offset
= spill_offset
;
705 unspill_inst
->ir
= inst
->ir
;
706 unspill_inst
->annotation
= inst
->annotation
;
707 unspill_inst
->regs_written
= reg_size
;
710 unspill_inst
->base_mrf
= 14;
711 unspill_inst
->mlen
= 1; /* header contains offset */
713 inst
->insert_before(block
, unspill_inst
);
715 dst
.reg_offset
+= reg_size
;
716 spill_offset
+= reg_size
* REG_SIZE
;
721 fs_visitor::emit_spill(bblock_t
*block
, fs_inst
*inst
, fs_reg src
,
722 uint32_t spill_offset
, int count
)
725 int spill_base_mrf
= 14;
726 if (dispatch_width
== 16 && count
% 2 == 0) {
731 for (int i
= 0; i
< count
/ reg_size
; i
++) {
732 fs_inst
*spill_inst
=
733 new(mem_ctx
) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
734 reg_size
* 8, reg_null_f
, src
);
735 src
.reg_offset
+= reg_size
;
736 spill_inst
->offset
= spill_offset
+ i
* reg_size
* REG_SIZE
;
737 spill_inst
->ir
= inst
->ir
;
738 spill_inst
->annotation
= inst
->annotation
;
739 spill_inst
->mlen
= 1 + reg_size
; /* header, value */
740 spill_inst
->base_mrf
= spill_base_mrf
;
741 inst
->insert_after(block
, spill_inst
);
746 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
748 float loop_scale
= 1.0;
749 float spill_costs
[this->alloc
.count
];
750 bool no_spill
[this->alloc
.count
];
752 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
753 spill_costs
[i
] = 0.0;
757 /* Calculate costs for spilling nodes. Call it a cost of 1 per
758 * spill/unspill we'll have to do, and guess that the insides of
759 * loops run 10 times.
761 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
762 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
763 if (inst
->src
[i
].file
== GRF
) {
764 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
766 /* Register spilling logic assumes full-width registers; smeared
767 * registers have a width of 1 so if we try to spill them we'll
768 * generate invalid assembly. This shouldn't be a problem because
769 * smeared registers are only used as short-term temporaries when
770 * loading pull constants, so spilling them is unlikely to reduce
771 * register pressure anyhow.
773 if (!inst
->src
[i
].is_contiguous()) {
774 no_spill
[inst
->src
[i
].reg
] = true;
779 if (inst
->dst
.file
== GRF
) {
780 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
782 if (!inst
->dst
.is_contiguous()) {
783 no_spill
[inst
->dst
.reg
] = true;
787 switch (inst
->opcode
) {
793 case BRW_OPCODE_WHILE
:
797 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
798 if (inst
->src
[0].file
== GRF
)
799 no_spill
[inst
->src
[0].reg
] = true;
802 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
803 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
804 if (inst
->dst
.file
== GRF
)
805 no_spill
[inst
->dst
.reg
] = true;
813 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
815 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
818 return ra_get_best_spill_node(g
);
822 fs_visitor::spill_reg(int spill_reg
)
824 int size
= alloc
.sizes
[spill_reg
];
825 unsigned int spill_offset
= last_scratch
;
826 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
827 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
829 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
830 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
831 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
832 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
833 * depth), starting from m1. In summary: We may not be able to spill in
834 * SIMD16 mode, because we'd stomp the FB writes.
836 if (!spilled_any_registers
) {
837 bool mrf_used
[BRW_MAX_MRF
];
838 get_used_mrfs(mrf_used
);
840 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF
; i
++) {
842 fail("Register spilling not supported with m%d used", i
);
847 spilled_any_registers
= true;
850 last_scratch
+= size
* REG_SIZE
;
852 /* Generate spill/unspill instructions for the objects being
853 * spilled. Right now, we spill or unspill the whole thing to a
854 * virtual grf of the same size. For most instructions, though, we
855 * could just spill/unspill the GRF being accessed.
857 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
858 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
859 if (inst
->src
[i
].file
== GRF
&&
860 inst
->src
[i
].reg
== spill_reg
) {
861 int regs_read
= inst
->regs_read(i
);
862 int subset_spill_offset
= (spill_offset
+
863 REG_SIZE
* inst
->src
[i
].reg_offset
);
864 fs_reg
unspill_dst(GRF
, alloc
.allocate(regs_read
));
866 inst
->src
[i
].reg
= unspill_dst
.reg
;
867 inst
->src
[i
].reg_offset
= 0;
869 emit_unspill(block
, inst
, unspill_dst
, subset_spill_offset
,
874 if (inst
->dst
.file
== GRF
&&
875 inst
->dst
.reg
== spill_reg
) {
876 int subset_spill_offset
= (spill_offset
+
877 REG_SIZE
* inst
->dst
.reg_offset
);
878 fs_reg
spill_src(GRF
, alloc
.allocate(inst
->regs_written
));
880 inst
->dst
.reg
= spill_src
.reg
;
881 inst
->dst
.reg_offset
= 0;
883 /* If we're immediately spilling the register, we should not use
884 * destination dependency hints. Doing so will cause the GPU do
885 * try to read and write the register at the same time and may
888 inst
->no_dd_clear
= false;
889 inst
->no_dd_check
= false;
891 /* If our write is going to affect just part of the
892 * inst->regs_written(), then we need to unspill the destination
893 * since we write back out all of the regs_written().
895 if (inst
->is_partial_write())
896 emit_unspill(block
, inst
, spill_src
, subset_spill_offset
,
899 emit_spill(block
, inst
, spill_src
, subset_spill_offset
,
904 invalidate_live_intervals();