2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "glsl/glsl_types.h"
30 #include "glsl/ir_optimization.h"
33 assign_reg(int *reg_hw_locations
, fs_reg
*reg
, int reg_width
)
35 if (reg
->file
== GRF
) {
36 assert(reg
->reg_offset
>= 0);
37 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
* reg_width
;
43 fs_visitor::assign_regs_trivial()
45 int hw_reg_mapping
[this->virtual_grf_count
+ 1];
47 int reg_width
= dispatch_width
/ 8;
49 /* Note that compressed instructions require alignment to 2 registers. */
50 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
51 for (i
= 1; i
<= this->virtual_grf_count
; i
++) {
52 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
53 this->virtual_grf_sizes
[i
- 1] * reg_width
);
55 this->grf_used
= hw_reg_mapping
[this->virtual_grf_count
];
57 foreach_list(node
, &this->instructions
) {
58 fs_inst
*inst
= (fs_inst
*)node
;
60 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
61 assign_reg(hw_reg_mapping
, &inst
->src
[0], reg_width
);
62 assign_reg(hw_reg_mapping
, &inst
->src
[1], reg_width
);
63 assign_reg(hw_reg_mapping
, &inst
->src
[2], reg_width
);
66 if (this->grf_used
>= max_grf
) {
67 fail("Ran out of regs on trivial allocator (%d/%d)\n",
68 this->grf_used
, max_grf
);
74 brw_alloc_reg_set(struct brw_context
*brw
, int reg_width
)
76 struct intel_context
*intel
= &brw
->intel
;
77 int base_reg_count
= BRW_MAX_GRF
/ reg_width
;
78 int index
= reg_width
- 1;
80 /* The registers used to make up almost all values handled in the compiler
81 * are a scalar value occupying a single register (or 2 registers in the
82 * case of 16-wide, which is handled by dividing base_reg_count by 2 and
83 * multiplying allocated register numbers by 2). Things that were
84 * aggregates of scalar values at the GLSL level were split to scalar
85 * values by split_virtual_grfs().
87 * However, texture SEND messages return a series of contiguous registers.
88 * We currently always ask for 4 registers, but we may convert that to use
91 * Additionally, on gen5 we need aligned pairs of registers for the PLN
92 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
95 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
96 * and we add in '3' to make indexing the array easier for the common case
97 * (since we'll probably want it for texturing later).
99 const int class_count
= 5;
100 const int class_sizes
[class_count
] = {1, 2, 3, 4, 8};
102 /* Compute the total number of registers across all classes. */
103 int ra_reg_count
= 0;
104 for (int i
= 0; i
< class_count
; i
++) {
105 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
108 uint8_t *ra_reg_to_grf
= ralloc_array(brw
, uint8_t, ra_reg_count
);
109 struct ra_regs
*regs
= ra_alloc_reg_set(brw
, ra_reg_count
);
111 ra_set_allocate_round_robin(regs
);
112 int *classes
= ralloc_array(brw
, int, class_count
);
113 int aligned_pairs_class
= -1;
115 /* Now, add the registers to their classes, and add the conflicts
116 * between them and the base GRF registers (and also each other).
119 int pairs_base_reg
= 0;
120 int pairs_reg_count
= 0;
121 for (int i
= 0; i
< class_count
; i
++) {
122 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
123 classes
[i
] = ra_alloc_reg_class(regs
);
125 /* Save this off for the aligned pair class at the end. */
126 if (class_sizes
[i
] == 2) {
127 pairs_base_reg
= reg
;
128 pairs_reg_count
= class_reg_count
;
131 for (int j
= 0; j
< class_reg_count
; j
++) {
132 ra_class_add_reg(regs
, classes
[i
], reg
);
134 ra_reg_to_grf
[reg
] = j
;
136 for (int base_reg
= j
;
137 base_reg
< j
+ class_sizes
[i
];
139 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
145 assert(reg
== ra_reg_count
);
147 /* Add a special class for aligned pairs, which we'll put delta_x/y
148 * in on gen5 so that we can do PLN.
150 if (brw
->has_pln
&& reg_width
== 1 && intel
->gen
< 6) {
151 aligned_pairs_class
= ra_alloc_reg_class(regs
);
153 for (int i
= 0; i
< pairs_reg_count
; i
++) {
154 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
155 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
160 ra_set_finalize(regs
, NULL
);
162 brw
->wm
.reg_sets
[index
].regs
= regs
;
163 brw
->wm
.reg_sets
[index
].classes
= classes
;
164 brw
->wm
.reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
165 brw
->wm
.reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
169 brw_fs_alloc_reg_sets(struct brw_context
*brw
)
171 brw_alloc_reg_set(brw
, 1);
172 brw_alloc_reg_set(brw
, 2);
176 count_to_loop_end(fs_inst
*do_inst
)
180 for (fs_inst
*inst
= (fs_inst
*)do_inst
->next
;
182 inst
= (fs_inst
*)inst
->next
) {
183 switch (inst
->opcode
) {
187 case BRW_OPCODE_WHILE
:
199 * Sets up interference between thread payload registers and the virtual GRFs
200 * to be allocated for program temporaries.
202 * We want to be able to reallocate the payload for our virtual GRFs, notably
203 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
206 * The layout of the payload registers is:
208 * 0..nr_payload_regs-1: fixed function setup (including bary coordinates).
209 * nr_payload_regs..nr_payload_regs+curb_read_lengh-1: uniform data
210 * nr_payload_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
212 * And we have payload_node_count nodes covering these registers in order
213 * (note that in 16-wide, a node is two registers).
216 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
217 int payload_node_count
,
218 int first_payload_node
)
220 int reg_width
= dispatch_width
/ 8;
224 int payload_last_use_ip
[payload_node_count
];
225 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
227 foreach_list(node
, &this->instructions
) {
228 fs_inst
*inst
= (fs_inst
*)node
;
230 switch (inst
->opcode
) {
234 /* Since payload regs are deffed only at the start of the shader
235 * execution, any uses of the payload within a loop mean the live
236 * interval extends to the end of the outermost loop. Find the ip of
240 loop_end_ip
= ip
+ count_to_loop_end(inst
);
242 case BRW_OPCODE_WHILE
:
251 use_ip
= loop_end_ip
;
255 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
256 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
257 * the start (see interp_reg()).
259 for (int i
= 0; i
< 3; i
++) {
260 if (inst
->src
[i
].file
== HW_REG
&&
261 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
262 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
/ reg_width
;
263 if (node_nr
>= payload_node_count
)
266 payload_last_use_ip
[node_nr
] = use_ip
;
270 /* Special case instructions which have extra implied registers used. */
271 switch (inst
->opcode
) {
272 case FS_OPCODE_FB_WRITE
:
273 /* We could omit this for the !inst->header_present case, except that
274 * the simulator apparently incorrectly reads from g0/g1 instead of
275 * sideband. It also really freaks out driver developers to see g0
276 * used in unusual places, so just always reserve it.
278 payload_last_use_ip
[0 / reg_width
] = use_ip
;
279 payload_last_use_ip
[1 / reg_width
] = use_ip
;
282 case FS_OPCODE_LINTERP
:
283 /* On gen6+ in 16-wide, there are 4 adjacent registers (so 2 nodes)
284 * used by PLN's sourcing of the deltas, while we list only the first
285 * two in the arguments (1 node). Pre-gen6, the deltas are computed
288 if (intel
->gen
>= 6) {
290 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
291 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
292 BRW_GENERAL_REGISTER_FILE
) {
293 int sechalf_node
= (inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
/
295 assert(sechalf_node
< payload_node_count
);
296 payload_last_use_ip
[sechalf_node
] = use_ip
;
308 for (int i
= 0; i
< payload_node_count
; i
++) {
309 /* Mark the payload node as interfering with any virtual grf that is
310 * live between the start of the program and our last use of the payload
313 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
314 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
315 * in order to not have to worry about the uniform issue described in
316 * calculate_live_intervals().
318 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
319 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
324 for (int i
= 0; i
< payload_node_count
; i
++) {
325 /* Mark each payload node as being allocated to its physical register.
327 * The alternative would be to have per-physical-register classes, which
328 * would just be silly.
330 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
335 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
336 * messages (treated as MRFs in code generation).
339 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
341 int mrf_count
= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
342 int reg_width
= dispatch_width
/ 8;
344 /* Identify all the MRFs used in the program. */
345 bool mrf_used
[mrf_count
];
346 memset(mrf_used
, 0, sizeof(mrf_used
));
347 foreach_list(node
, &this->instructions
) {
348 fs_inst
*inst
= (fs_inst
*)node
;
350 if (inst
->dst
.file
== MRF
) {
351 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
352 mrf_used
[reg
] = true;
353 if (reg_width
== 2) {
354 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
355 mrf_used
[reg
+ 4] = true;
357 mrf_used
[reg
+ 1] = true;
362 if (inst
->mlen
> 0) {
363 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
364 mrf_used
[inst
->base_mrf
+ i
] = true;
369 for (int i
= 0; i
< mrf_count
; i
++) {
370 /* Mark each payload reg node as being allocated to its physical register.
372 * The alternative would be to have per-physical-register classes, which
373 * would just be silly.
375 ra_set_node_reg(g
, first_mrf_node
+ i
,
376 (GEN7_MRF_HACK_START
+ i
) / reg_width
);
378 /* Since we don't have any live/dead analysis on the MRFs, just mark all
379 * that are used as conflicting with all virtual GRFs.
382 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
383 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
390 fs_visitor::assign_regs()
392 /* Most of this allocation was written for a reg_width of 1
393 * (dispatch_width == 8). In extending to 16-wide, the code was
394 * left in place and it was converted to have the hardware
395 * registers it's allocating be contiguous physical pairs of regs
396 * for reg_width == 2.
398 int reg_width
= dispatch_width
/ 8;
399 int hw_reg_mapping
[this->virtual_grf_count
];
400 int payload_node_count
= (ALIGN(this->first_non_payload_grf
, reg_width
) /
402 int rsi
= reg_width
- 1; /* Which brw->wm.reg_sets[] to use */
403 calculate_live_intervals();
405 int node_count
= this->virtual_grf_count
;
406 int first_payload_node
= node_count
;
407 node_count
+= payload_node_count
;
408 int first_mrf_hack_node
= node_count
;
410 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
411 struct ra_graph
*g
= ra_alloc_interference_graph(brw
->wm
.reg_sets
[rsi
].regs
,
414 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
415 int size
= this->virtual_grf_sizes
[i
];
423 "Register allocation relies on split_virtual_grfs()");
424 c
= brw
->wm
.reg_sets
[rsi
].classes
[size
- 1];
427 /* Special case: on pre-GEN6 hardware that supports PLN, the
428 * second operand of a PLN instruction needs to be an
429 * even-numbered register, so we have a special register class
430 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
431 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
432 * second operand of a PLN instruction (since it doesn't support
433 * any other interpolation modes). So all we need to do is find
434 * that register and set it to the appropriate class.
436 if (brw
->wm
.reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
437 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
438 c
= brw
->wm
.reg_sets
[rsi
].aligned_pairs_class
;
441 ra_set_node_class(g
, i
, c
);
443 for (int j
= 0; j
< i
; j
++) {
444 if (virtual_grf_interferes(i
, j
)) {
445 ra_add_node_interference(g
, i
, j
);
450 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
452 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
454 if (!ra_allocate_no_spills(g
)) {
455 /* Failed to allocate registers. Spill a reg, and the caller will
456 * loop back into here to try again.
458 int reg
= choose_spill_reg(g
);
461 fail("no register to spill:\n");
463 } else if (dispatch_width
== 16) {
464 fail("Failure to register allocate. Reduce number of live scalar "
465 "values to avoid this.");
476 /* Get the chosen virtual registers for each node, and map virtual
477 * regs in the register classes back down to real hardware reg
480 this->grf_used
= payload_node_count
* reg_width
;
481 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
482 int reg
= ra_get_node_reg(g
, i
);
484 hw_reg_mapping
[i
] = brw
->wm
.reg_sets
[rsi
].ra_reg_to_grf
[reg
] * reg_width
;
485 this->grf_used
= MAX2(this->grf_used
,
486 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] *
490 foreach_list(node
, &this->instructions
) {
491 fs_inst
*inst
= (fs_inst
*)node
;
493 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
494 assign_reg(hw_reg_mapping
, &inst
->src
[0], reg_width
);
495 assign_reg(hw_reg_mapping
, &inst
->src
[1], reg_width
);
496 assign_reg(hw_reg_mapping
, &inst
->src
[2], reg_width
);
505 fs_visitor::emit_unspill(fs_inst
*inst
, fs_reg dst
, uint32_t spill_offset
)
507 fs_inst
*unspill_inst
= new(mem_ctx
) fs_inst(FS_OPCODE_UNSPILL
, dst
);
508 unspill_inst
->offset
= spill_offset
;
509 unspill_inst
->ir
= inst
->ir
;
510 unspill_inst
->annotation
= inst
->annotation
;
512 /* Choose a MRF that won't conflict with an MRF that's live across the
513 * spill. Nothing else will make it up to MRF 14/15.
515 unspill_inst
->base_mrf
= 14;
516 unspill_inst
->mlen
= 1; /* header contains offset */
517 inst
->insert_before(unspill_inst
);
521 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
523 float loop_scale
= 1.0;
524 float spill_costs
[this->virtual_grf_count
];
525 bool no_spill
[this->virtual_grf_count
];
527 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
528 spill_costs
[i
] = 0.0;
532 /* Calculate costs for spilling nodes. Call it a cost of 1 per
533 * spill/unspill we'll have to do, and guess that the insides of
534 * loops run 10 times.
536 foreach_list(node
, &this->instructions
) {
537 fs_inst
*inst
= (fs_inst
*)node
;
539 for (unsigned int i
= 0; i
< 3; i
++) {
540 if (inst
->src
[i
].file
== GRF
) {
541 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
543 /* Register spilling logic assumes full-width registers; smeared
544 * registers have a width of 1 so if we try to spill them we'll
545 * generate invalid assembly. This shouldn't be a problem because
546 * smeared registers are only used as short-term temporaries when
547 * loading pull constants, so spilling them is unlikely to reduce
548 * register pressure anyhow.
550 if (inst
->src
[i
].smear
>= 0) {
551 no_spill
[inst
->src
[i
].reg
] = true;
556 if (inst
->dst
.file
== GRF
) {
557 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
559 if (inst
->dst
.smear
>= 0) {
560 no_spill
[inst
->dst
.reg
] = true;
564 switch (inst
->opcode
) {
570 case BRW_OPCODE_WHILE
:
574 case FS_OPCODE_SPILL
:
575 if (inst
->src
[0].file
== GRF
)
576 no_spill
[inst
->src
[0].reg
] = true;
579 case FS_OPCODE_UNSPILL
:
580 if (inst
->dst
.file
== GRF
)
581 no_spill
[inst
->dst
.reg
] = true;
589 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
591 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
594 return ra_get_best_spill_node(g
);
598 fs_visitor::spill_reg(int spill_reg
)
600 int size
= virtual_grf_sizes
[spill_reg
];
601 unsigned int spill_offset
= c
->last_scratch
;
602 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
603 c
->last_scratch
+= size
* REG_SIZE
;
605 /* Generate spill/unspill instructions for the objects being
606 * spilled. Right now, we spill or unspill the whole thing to a
607 * virtual grf of the same size. For most instructions, though, we
608 * could just spill/unspill the GRF being accessed.
610 foreach_list(node
, &this->instructions
) {
611 fs_inst
*inst
= (fs_inst
*)node
;
613 for (unsigned int i
= 0; i
< 3; i
++) {
614 if (inst
->src
[i
].file
== GRF
&&
615 inst
->src
[i
].reg
== spill_reg
) {
616 inst
->src
[i
].reg
= virtual_grf_alloc(1);
617 emit_unspill(inst
, inst
->src
[i
],
618 spill_offset
+ REG_SIZE
* inst
->src
[i
].reg_offset
);
622 if (inst
->dst
.file
== GRF
&&
623 inst
->dst
.reg
== spill_reg
) {
624 int subset_spill_offset
= (spill_offset
+
625 REG_SIZE
* inst
->dst
.reg_offset
);
626 inst
->dst
.reg
= virtual_grf_alloc(inst
->regs_written
);
627 inst
->dst
.reg_offset
= 0;
629 /* If our write is going to affect just part of the
630 * inst->regs_written(), then we need to unspill the destination
631 * since we write back out all of the regs_written().
633 if (inst
->predicate
|| inst
->force_uncompressed
|| inst
->force_sechalf
) {
634 fs_reg unspill_reg
= inst
->dst
;
635 for (int chan
= 0; chan
< inst
->regs_written
; chan
++) {
636 emit_unspill(inst
, unspill_reg
,
637 subset_spill_offset
+ REG_SIZE
* chan
);
638 unspill_reg
.reg_offset
++;
642 fs_reg spill_src
= inst
->dst
;
643 spill_src
.reg_offset
= 0;
644 spill_src
.abs
= false;
645 spill_src
.negate
= false;
646 spill_src
.smear
= -1;
648 for (int chan
= 0; chan
< inst
->regs_written
; chan
++) {
649 fs_inst
*spill_inst
= new(mem_ctx
) fs_inst(FS_OPCODE_SPILL
,
650 reg_null_f
, spill_src
);
651 spill_src
.reg_offset
++;
652 spill_inst
->offset
= subset_spill_offset
+ chan
* REG_SIZE
;
653 spill_inst
->ir
= inst
->ir
;
654 spill_inst
->annotation
= inst
->annotation
;
655 spill_inst
->base_mrf
= 14;
656 spill_inst
->mlen
= 2; /* header, value */
657 inst
->insert_after(spill_inst
);
662 this->live_intervals_valid
= false;