2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
33 #define FIRST_SPILL_MRF(gen) (gen == 6 ? 21 : 13)
38 assign_reg(unsigned *reg_hw_locations
, fs_reg
*reg
)
40 if (reg
->file
== GRF
) {
41 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
47 fs_visitor::assign_regs_trivial()
49 unsigned hw_reg_mapping
[this->alloc
.count
+ 1];
51 int reg_width
= dispatch_width
/ 8;
53 /* Note that compressed instructions require alignment to 2 registers. */
54 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
55 for (i
= 1; i
<= this->alloc
.count
; i
++) {
56 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
57 this->alloc
.sizes
[i
- 1]);
59 this->grf_used
= hw_reg_mapping
[this->alloc
.count
];
61 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
62 assign_reg(hw_reg_mapping
, &inst
->dst
);
63 for (i
= 0; i
< inst
->sources
; i
++) {
64 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
68 if (this->grf_used
>= max_grf
) {
69 fail("Ran out of regs on trivial allocator (%d/%d)\n",
70 this->grf_used
, max_grf
);
72 this->alloc
.count
= this->grf_used
;
78 brw_alloc_reg_set(struct brw_compiler
*compiler
, int dispatch_width
)
80 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
81 int base_reg_count
= BRW_MAX_GRF
;
82 int index
= (dispatch_width
/ 8) - 1;
84 if (dispatch_width
> 8 && devinfo
->gen
>= 7) {
85 /* For IVB+, we don't need the PLN hacks or the even-reg alignment in
86 * SIMD16. Therefore, we can use the exact same register sets for
87 * SIMD16 as we do for SIMD8 and we don't need to recalculate them.
89 compiler
->fs_reg_sets
[index
] = compiler
->fs_reg_sets
[0];
93 /* The registers used to make up almost all values handled in the compiler
94 * are a scalar value occupying a single register (or 2 registers in the
95 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
96 * multiplying allocated register numbers by 2). Things that were
97 * aggregates of scalar values at the GLSL level were split to scalar
98 * values by split_virtual_grfs().
100 * However, texture SEND messages return a series of contiguous registers
101 * to write into. We currently always ask for 4 registers, but we may
102 * convert that to use less some day.
104 * Additionally, on gen5 we need aligned pairs of registers for the PLN
105 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
108 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
109 * and we add in '3' to make indexing the array easier for the common case
110 * (since we'll probably want it for texturing later).
112 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
113 * means that we may need any size up to the sampler message size limit (11
117 int class_sizes
[MAX_VGRF_SIZE
];
119 if (devinfo
->gen
>= 7) {
120 for (class_count
= 0; class_count
< MAX_VGRF_SIZE
; class_count
++)
121 class_sizes
[class_count
] = class_count
+ 1;
123 for (class_count
= 0; class_count
< 4; class_count
++)
124 class_sizes
[class_count
] = class_count
+ 1;
125 class_sizes
[class_count
++] = 8;
128 memset(compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
, 0,
129 sizeof(compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
));
130 int *class_to_ra_reg_range
= compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
;
132 /* Compute the total number of registers across all classes. */
133 int ra_reg_count
= 0;
134 for (int i
= 0; i
< class_count
; i
++) {
135 if (devinfo
->gen
<= 5 && dispatch_width
== 16) {
138 * In order to reduce the hardware complexity, the following
139 * rules and restrictions apply to the compressed instruction:
141 * * Operand Alignment Rule: With the exceptions listed below, a
142 * source/destination operand in general should be aligned to
143 * even 256-bit physical register with a region size equal to
144 * two 256-bit physical register
146 ra_reg_count
+= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
148 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
150 /* Mark the last register. We'll fill in the beginnings later. */
151 class_to_ra_reg_range
[class_sizes
[i
]] = ra_reg_count
;
154 /* Fill out the rest of the range markers */
155 for (int i
= 1; i
< 17; ++i
) {
156 if (class_to_ra_reg_range
[i
] == 0)
157 class_to_ra_reg_range
[i
] = class_to_ra_reg_range
[i
-1];
160 uint8_t *ra_reg_to_grf
= ralloc_array(compiler
, uint8_t, ra_reg_count
);
161 struct ra_regs
*regs
= ra_alloc_reg_set(compiler
, ra_reg_count
, false);
162 if (devinfo
->gen
>= 6)
163 ra_set_allocate_round_robin(regs
);
164 int *classes
= ralloc_array(compiler
, int, class_count
);
165 int aligned_pairs_class
= -1;
167 /* Allocate space for q values. We allocate class_count + 1 because we
168 * want to leave room for the aligned pairs class if we have it. */
169 unsigned int **q_values
= ralloc_array(compiler
, unsigned int *,
171 for (int i
= 0; i
< class_count
+ 1; ++i
)
172 q_values
[i
] = ralloc_array(q_values
, unsigned int, class_count
+ 1);
174 /* Now, add the registers to their classes, and add the conflicts
175 * between them and the base GRF registers (and also each other).
178 int pairs_base_reg
= 0;
179 int pairs_reg_count
= 0;
180 for (int i
= 0; i
< class_count
; i
++) {
182 if (devinfo
->gen
<= 5 && dispatch_width
== 16) {
183 class_reg_count
= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
185 /* See comment below. The only difference here is that we are
186 * dealing with pairs of registers instead of single registers.
187 * Registers of odd sizes simply get rounded up. */
188 for (int j
= 0; j
< class_count
; j
++)
189 q_values
[i
][j
] = (class_sizes
[i
] + 1) / 2 +
190 (class_sizes
[j
] + 1) / 2 - 1;
192 class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
194 /* From register_allocate.c:
196 * q(B,C) (indexed by C, B is this register class) in
197 * Runeson/Nyström paper. This is "how many registers of B could
198 * the worst choice register from C conflict with".
200 * If we just let the register allocation algorithm compute these
201 * values, is extremely expensive. However, since all of our
202 * registers are laid out, we can very easily compute them
203 * ourselves. View the register from C as fixed starting at GRF n
204 * somwhere in the middle, and the register from B as sliding back
205 * and forth. Then the first register to conflict from B is the
206 * one starting at n - class_size[B] + 1 and the last register to
207 * conflict will start at n + class_size[B] - 1. Therefore, the
208 * number of conflicts from B is class_size[B] + class_size[C] - 1.
210 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
211 * B | | | | | |n| --> | | | | | | |
212 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
217 for (int j
= 0; j
< class_count
; j
++)
218 q_values
[i
][j
] = class_sizes
[i
] + class_sizes
[j
] - 1;
220 classes
[i
] = ra_alloc_reg_class(regs
);
222 /* Save this off for the aligned pair class at the end. */
223 if (class_sizes
[i
] == 2) {
224 pairs_base_reg
= reg
;
225 pairs_reg_count
= class_reg_count
;
228 if (devinfo
->gen
<= 5 && dispatch_width
== 16) {
229 for (int j
= 0; j
< class_reg_count
; j
++) {
230 ra_class_add_reg(regs
, classes
[i
], reg
);
232 ra_reg_to_grf
[reg
] = j
* 2;
234 for (int base_reg
= j
;
235 base_reg
< j
+ (class_sizes
[i
] + 1) / 2;
237 ra_add_reg_conflict(regs
, base_reg
, reg
);
243 for (int j
= 0; j
< class_reg_count
; j
++) {
244 ra_class_add_reg(regs
, classes
[i
], reg
);
246 ra_reg_to_grf
[reg
] = j
;
248 for (int base_reg
= j
;
249 base_reg
< j
+ class_sizes
[i
];
251 ra_add_reg_conflict(regs
, base_reg
, reg
);
258 assert(reg
== ra_reg_count
);
260 /* Applying transitivity to all of the base registers gives us the
261 * appropreate register conflict relationships everywhere.
263 for (int reg
= 0; reg
< base_reg_count
; reg
++)
264 ra_make_reg_conflicts_transitive(regs
, reg
);
266 /* Add a special class for aligned pairs, which we'll put delta_xy
267 * in on Gen <= 6 so that we can do PLN.
269 if (devinfo
->has_pln
&& dispatch_width
== 8 && devinfo
->gen
<= 6) {
270 aligned_pairs_class
= ra_alloc_reg_class(regs
);
272 for (int i
= 0; i
< pairs_reg_count
; i
++) {
273 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
274 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
278 for (int i
= 0; i
< class_count
; i
++) {
279 /* These are a little counter-intuitive because the pair registers
280 * are required to be aligned while the register they are
281 * potentially interferring with are not. In the case where the
282 * size is even, the worst-case is that the register is
283 * odd-aligned. In the odd-size case, it doesn't matter.
285 q_values
[class_count
][i
] = class_sizes
[i
] / 2 + 1;
286 q_values
[i
][class_count
] = class_sizes
[i
] + 1;
288 q_values
[class_count
][class_count
] = 1;
291 ra_set_finalize(regs
, q_values
);
293 ralloc_free(q_values
);
295 compiler
->fs_reg_sets
[index
].regs
= regs
;
296 for (unsigned i
= 0; i
< ARRAY_SIZE(compiler
->fs_reg_sets
[index
].classes
); i
++)
297 compiler
->fs_reg_sets
[index
].classes
[i
] = -1;
298 for (int i
= 0; i
< class_count
; i
++)
299 compiler
->fs_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
300 compiler
->fs_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
301 compiler
->fs_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
305 brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
)
307 brw_alloc_reg_set(compiler
, 8);
308 brw_alloc_reg_set(compiler
, 16);
312 count_to_loop_end(const bblock_t
*block
)
314 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
315 return block
->end_ip
;
318 /* Skip the first block, since we don't want to count the do the calling
321 for (block
= block
->next();
323 block
= block
->next()) {
324 if (block
->start()->opcode
== BRW_OPCODE_DO
)
326 if (block
->end()->opcode
== BRW_OPCODE_WHILE
) {
329 return block
->end_ip
;
332 unreachable("not reached");
336 * Sets up interference between thread payload registers and the virtual GRFs
337 * to be allocated for program temporaries.
339 * We want to be able to reallocate the payload for our virtual GRFs, notably
340 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
343 * The layout of the payload registers is:
345 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
346 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
347 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
349 * And we have payload_node_count nodes covering these registers in order
350 * (note that in SIMD16, a node is two registers).
353 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
354 int payload_node_count
,
355 int first_payload_node
)
360 int payload_last_use_ip
[payload_node_count
];
361 for (int i
= 0; i
< payload_node_count
; i
++)
362 payload_last_use_ip
[i
] = -1;
365 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
366 switch (inst
->opcode
) {
370 /* Since payload regs are deffed only at the start of the shader
371 * execution, any uses of the payload within a loop mean the live
372 * interval extends to the end of the outermost loop. Find the ip of
376 loop_end_ip
= count_to_loop_end(block
);
378 case BRW_OPCODE_WHILE
:
387 use_ip
= loop_end_ip
;
391 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
392 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
393 * the start (see interp_reg()).
395 for (int i
= 0; i
< inst
->sources
; i
++) {
396 if (inst
->src
[i
].file
== HW_REG
&&
397 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
398 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
;
399 if (node_nr
>= payload_node_count
)
402 for (int j
= 0; j
< inst
->regs_read(i
); j
++) {
403 payload_last_use_ip
[node_nr
+ j
] = use_ip
;
404 assert(node_nr
+ j
< payload_node_count
);
409 /* Special case instructions which have extra implied registers used. */
410 switch (inst
->opcode
) {
411 case CS_OPCODE_CS_TERMINATE
:
412 payload_last_use_ip
[0] = use_ip
;
417 /* We could omit this for the !inst->header_present case, except
418 * that the simulator apparently incorrectly reads from g0/g1
419 * instead of sideband. It also really freaks out driver
420 * developers to see g0 used in unusual places, so just always
423 payload_last_use_ip
[0] = use_ip
;
424 payload_last_use_ip
[1] = use_ip
;
432 for (int i
= 0; i
< payload_node_count
; i
++) {
433 if (payload_last_use_ip
[i
] == -1)
436 /* Mark the payload node as interfering with any virtual grf that is
437 * live between the start of the program and our last use of the payload
440 for (unsigned j
= 0; j
< this->alloc
.count
; j
++) {
441 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
442 * in order to not have to worry about the uniform issue described in
443 * calculate_live_intervals().
445 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
446 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
451 for (int i
= 0; i
< payload_node_count
; i
++) {
452 /* Mark each payload node as being allocated to its physical register.
454 * The alternative would be to have per-physical-register classes, which
455 * would just be silly.
457 if (devinfo
->gen
<= 5 && dispatch_width
== 16) {
458 /* We have to divide by 2 here because we only have even numbered
459 * registers. Some of the payload registers will be odd, but
460 * that's ok because their physical register numbers have already
461 * been assigned. The only thing this is used for is interference.
463 ra_set_node_reg(g
, first_payload_node
+ i
, i
/ 2);
465 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
471 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
473 * This is used in assign_regs() to decide which of the GRFs that we use as
474 * MRFs on gen7 get normally register allocated, and in register spilling to
475 * see if we can actually use MRFs to do spills without overwriting normal MRF
479 get_used_mrfs(fs_visitor
*v
, bool *mrf_used
)
481 int reg_width
= v
->dispatch_width
/ 8;
483 memset(mrf_used
, 0, BRW_MAX_MRF(v
->devinfo
->gen
) * sizeof(bool));
485 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
486 if (inst
->dst
.file
== MRF
) {
487 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
488 mrf_used
[reg
] = true;
489 if (reg_width
== 2) {
490 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
491 mrf_used
[reg
+ 4] = true;
493 mrf_used
[reg
+ 1] = true;
498 if (inst
->mlen
> 0) {
499 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
500 mrf_used
[inst
->base_mrf
+ i
] = true;
507 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
508 * messages (treated as MRFs in code generation).
511 setup_mrf_hack_interference(fs_visitor
*v
, struct ra_graph
*g
,
512 int first_mrf_node
, int *first_used_mrf
)
514 bool mrf_used
[BRW_MAX_MRF(v
->devinfo
->gen
)];
515 get_used_mrfs(v
, mrf_used
);
517 *first_used_mrf
= BRW_MAX_MRF(v
->devinfo
->gen
);
518 for (int i
= 0; i
< BRW_MAX_MRF(v
->devinfo
->gen
); i
++) {
519 /* Mark each MRF reg node as being allocated to its physical register.
521 * The alternative would be to have per-physical-register classes, which
522 * would just be silly.
524 ra_set_node_reg(g
, first_mrf_node
+ i
, GEN7_MRF_HACK_START
+ i
);
526 /* Since we don't have any live/dead analysis on the MRFs, just mark all
527 * that are used as conflicting with all virtual GRFs.
530 if (i
< *first_used_mrf
)
533 for (unsigned j
= 0; j
< v
->alloc
.count
; j
++) {
534 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
541 fs_visitor::assign_regs(bool allow_spilling
)
543 /* Most of this allocation was written for a reg_width of 1
544 * (dispatch_width == 8). In extending to SIMD16, the code was
545 * left in place and it was converted to have the hardware
546 * registers it's allocating be contiguous physical pairs of regs
547 * for reg_width == 2.
549 int reg_width
= dispatch_width
/ 8;
550 unsigned hw_reg_mapping
[this->alloc
.count
];
551 int payload_node_count
= ALIGN(this->first_non_payload_grf
, reg_width
);
552 int rsi
= reg_width
- 1; /* Which compiler->fs_reg_sets[] to use */
553 calculate_live_intervals();
555 int node_count
= this->alloc
.count
;
556 int first_payload_node
= node_count
;
557 node_count
+= payload_node_count
;
558 int first_mrf_hack_node
= node_count
;
559 if (devinfo
->gen
>= 7)
560 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
562 ra_alloc_interference_graph(compiler
->fs_reg_sets
[rsi
].regs
, node_count
);
564 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
565 unsigned size
= this->alloc
.sizes
[i
];
568 assert(size
<= ARRAY_SIZE(compiler
->fs_reg_sets
[rsi
].classes
) &&
569 "Register allocation relies on split_virtual_grfs()");
570 c
= compiler
->fs_reg_sets
[rsi
].classes
[size
- 1];
572 /* Special case: on pre-GEN6 hardware that supports PLN, the
573 * second operand of a PLN instruction needs to be an
574 * even-numbered register, so we have a special register class
575 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
576 * uses this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
577 * second operand of a PLN instruction (since it doesn't support
578 * any other interpolation modes). So all we need to do is find
579 * that register and set it to the appropriate class.
581 if (compiler
->fs_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
582 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
&&
583 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
584 c
= compiler
->fs_reg_sets
[rsi
].aligned_pairs_class
;
587 ra_set_node_class(g
, i
, c
);
589 for (unsigned j
= 0; j
< i
; j
++) {
590 if (virtual_grf_interferes(i
, j
)) {
591 ra_add_node_interference(g
, i
, j
);
596 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
597 if (devinfo
->gen
>= 7) {
598 int first_used_mrf
= BRW_MAX_MRF(devinfo
->gen
);
599 setup_mrf_hack_interference(this, g
, first_mrf_hack_node
,
602 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
603 /* When we do send-from-GRF for FB writes, we need to ensure that
604 * the last write instruction sends from a high register. This is
605 * because the vertex fetcher wants to start filling the low
606 * payload registers while the pixel data port is still working on
607 * writing out the memory. If we don't do this, we get rendering
610 * We could just do "something high". Instead, we just pick the
611 * highest register that works.
614 int size
= alloc
.sizes
[inst
->src
[0].reg
];
615 int reg
= compiler
->fs_reg_sets
[rsi
].class_to_ra_reg_range
[size
] - 1;
617 /* If something happened to spill, we want to push the EOT send
618 * register early enough in the register file that we don't
619 * conflict with any used MRF hack registers.
621 reg
-= BRW_MAX_MRF(devinfo
->gen
) - first_used_mrf
;
623 ra_set_node_reg(g
, inst
->src
[0].reg
, reg
);
629 if (dispatch_width
> 8) {
630 /* In 16-wide dispatch we have an issue where a compressed
631 * instruction is actually two instructions executed simultaneiously.
632 * It's actually ok to have the source and destination registers be
633 * the same. In this case, each instruction over-writes its own
634 * source and there's no problem. The real problem here is if the
635 * source and destination registers are off by one. Then you can end
636 * up in a scenario where the first instruction over-writes the
637 * source of the second instruction. Since the compiler doesn't know
638 * about this level of granularity, we simply make the source and
639 * destination interfere.
641 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
642 if (inst
->dst
.file
!= GRF
)
645 for (int i
= 0; i
< inst
->sources
; ++i
) {
646 if (inst
->src
[i
].file
== GRF
) {
647 ra_add_node_interference(g
, inst
->dst
.reg
, inst
->src
[i
].reg
);
653 /* Debug of register spilling: Go spill everything. */
654 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_FS
)) {
655 int reg
= choose_spill_reg(g
);
664 if (!ra_allocate(g
)) {
665 /* Failed to allocate registers. Spill a reg, and the caller will
666 * loop back into here to try again.
668 int reg
= choose_spill_reg(g
);
671 fail("no register to spill:\n");
672 dump_instructions(NULL
);
673 } else if (allow_spilling
) {
682 /* Get the chosen virtual registers for each node, and map virtual
683 * regs in the register classes back down to real hardware reg
686 this->grf_used
= payload_node_count
;
687 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
688 int reg
= ra_get_node_reg(g
, i
);
690 hw_reg_mapping
[i
] = compiler
->fs_reg_sets
[rsi
].ra_reg_to_grf
[reg
];
691 this->grf_used
= MAX2(this->grf_used
,
692 hw_reg_mapping
[i
] + this->alloc
.sizes
[i
]);
695 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
696 assign_reg(hw_reg_mapping
, &inst
->dst
);
697 for (int i
= 0; i
< inst
->sources
; i
++) {
698 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
702 this->alloc
.count
= this->grf_used
;
710 fs_visitor::emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg dst
,
711 uint32_t spill_offset
, int count
)
714 if (dispatch_width
== 16 && count
% 2 == 0)
717 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
718 .group(reg_size
* 8, 0)
721 for (int i
= 0; i
< count
/ reg_size
; i
++) {
722 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
723 bool gen7_read
= devinfo
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
724 fs_inst
*unspill_inst
= ibld
.emit(gen7_read
?
725 SHADER_OPCODE_GEN7_SCRATCH_READ
:
726 SHADER_OPCODE_GEN4_SCRATCH_READ
,
728 unspill_inst
->offset
= spill_offset
;
729 unspill_inst
->regs_written
= reg_size
;
732 unspill_inst
->base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
) + 1;
733 unspill_inst
->mlen
= 1; /* header contains offset */
736 dst
.reg_offset
+= reg_size
;
737 spill_offset
+= reg_size
* REG_SIZE
;
742 fs_visitor::emit_spill(bblock_t
*block
, fs_inst
*inst
, fs_reg src
,
743 uint32_t spill_offset
, int count
)
746 int spill_base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
) + 1;
747 if (dispatch_width
== 16 && count
% 2 == 0) {
748 spill_base_mrf
= FIRST_SPILL_MRF(devinfo
->gen
);
752 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
753 .group(reg_size
* 8, 0)
754 .at(block
, inst
->next
);
756 for (int i
= 0; i
< count
/ reg_size
; i
++) {
757 fs_inst
*spill_inst
=
758 ibld
.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE
, ibld
.null_reg_f(), src
);
759 src
.reg_offset
+= reg_size
;
760 spill_inst
->offset
= spill_offset
+ i
* reg_size
* REG_SIZE
;
761 spill_inst
->mlen
= 1 + reg_size
; /* header, value */
762 spill_inst
->base_mrf
= spill_base_mrf
;
767 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
769 float loop_scale
= 1.0;
770 float spill_costs
[this->alloc
.count
];
771 bool no_spill
[this->alloc
.count
];
773 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
774 spill_costs
[i
] = 0.0;
778 /* Calculate costs for spilling nodes. Call it a cost of 1 per
779 * spill/unspill we'll have to do, and guess that the insides of
780 * loops run 10 times.
782 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
783 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
784 if (inst
->src
[i
].file
== GRF
) {
785 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
787 /* Register spilling logic assumes full-width registers; smeared
788 * registers have a width of 1 so if we try to spill them we'll
789 * generate invalid assembly. This shouldn't be a problem because
790 * smeared registers are only used as short-term temporaries when
791 * loading pull constants, so spilling them is unlikely to reduce
792 * register pressure anyhow.
794 if (!inst
->src
[i
].is_contiguous()) {
795 no_spill
[inst
->src
[i
].reg
] = true;
800 if (inst
->dst
.file
== GRF
) {
801 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
803 if (!inst
->dst
.is_contiguous()) {
804 no_spill
[inst
->dst
.reg
] = true;
808 switch (inst
->opcode
) {
814 case BRW_OPCODE_WHILE
:
818 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
819 if (inst
->src
[0].file
== GRF
)
820 no_spill
[inst
->src
[0].reg
] = true;
823 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
824 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
825 if (inst
->dst
.file
== GRF
)
826 no_spill
[inst
->dst
.reg
] = true;
834 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
836 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
839 return ra_get_best_spill_node(g
);
843 fs_visitor::spill_reg(int spill_reg
)
845 int size
= alloc
.sizes
[spill_reg
];
846 unsigned int spill_offset
= last_scratch
;
847 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
848 int spill_base_mrf
= dispatch_width
> 8 ? FIRST_SPILL_MRF(devinfo
->gen
) :
849 FIRST_SPILL_MRF(devinfo
->gen
) + 1;
851 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
852 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
853 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
854 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
855 * depth), starting from m1. In summary: We may not be able to spill in
856 * SIMD16 mode, because we'd stomp the FB writes.
858 if (!spilled_any_registers
) {
859 bool mrf_used
[BRW_MAX_MRF(devinfo
->gen
)];
860 get_used_mrfs(this, mrf_used
);
862 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF(devinfo
->gen
); i
++) {
864 fail("Register spilling not supported with m%d used", i
);
869 spilled_any_registers
= true;
872 last_scratch
+= size
* REG_SIZE
;
874 /* Generate spill/unspill instructions for the objects being
875 * spilled. Right now, we spill or unspill the whole thing to a
876 * virtual grf of the same size. For most instructions, though, we
877 * could just spill/unspill the GRF being accessed.
879 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
880 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
881 if (inst
->src
[i
].file
== GRF
&&
882 inst
->src
[i
].reg
== spill_reg
) {
883 int regs_read
= inst
->regs_read(i
);
884 int subset_spill_offset
= (spill_offset
+
885 REG_SIZE
* inst
->src
[i
].reg_offset
);
886 fs_reg
unspill_dst(GRF
, alloc
.allocate(regs_read
));
888 inst
->src
[i
].reg
= unspill_dst
.reg
;
889 inst
->src
[i
].reg_offset
= 0;
891 emit_unspill(block
, inst
, unspill_dst
, subset_spill_offset
,
896 if (inst
->dst
.file
== GRF
&&
897 inst
->dst
.reg
== spill_reg
) {
898 int subset_spill_offset
= (spill_offset
+
899 REG_SIZE
* inst
->dst
.reg_offset
);
900 fs_reg
spill_src(GRF
, alloc
.allocate(inst
->regs_written
));
902 inst
->dst
.reg
= spill_src
.reg
;
903 inst
->dst
.reg_offset
= 0;
905 /* If we're immediately spilling the register, we should not use
906 * destination dependency hints. Doing so will cause the GPU do
907 * try to read and write the register at the same time and may
910 inst
->no_dd_clear
= false;
911 inst
->no_dd_check
= false;
913 /* If our write is going to affect just part of the
914 * inst->regs_written(), then we need to unspill the destination
915 * since we write back out all of the regs_written().
917 if (inst
->is_partial_write())
918 emit_unspill(block
, inst
, spill_src
, subset_spill_offset
,
921 emit_spill(block
, inst
, spill_src
, subset_spill_offset
,
926 invalidate_live_intervals();