8e44a0105769ae787cea5af3cc45422fcf113086
2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 assign_reg(int *reg_hw_locations
, fs_reg
*reg
, int reg_width
)
53 if (reg
->file
== GRF
) {
54 assert(reg
->reg_offset
>= 0);
55 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
* reg_width
;
61 fs_visitor::assign_regs_trivial()
63 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
65 int reg_width
= c
->dispatch_width
/ 8;
67 /* Note that compressed instructions require alignment to 2 registers. */
68 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
69 for (i
= 1; i
<= this->virtual_grf_next
; i
++) {
70 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
71 this->virtual_grf_sizes
[i
- 1] * reg_width
);
73 this->grf_used
= hw_reg_mapping
[this->virtual_grf_next
];
75 foreach_list(node
, &this->instructions
) {
76 fs_inst
*inst
= (fs_inst
*)node
;
78 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
79 assign_reg(hw_reg_mapping
, &inst
->src
[0], reg_width
);
80 assign_reg(hw_reg_mapping
, &inst
->src
[1], reg_width
);
83 if (this->grf_used
>= BRW_MAX_GRF
) {
84 fail("Ran out of regs on trivial allocator (%d/%d)\n",
85 this->grf_used
, BRW_MAX_GRF
);
91 brw_alloc_reg_set_for_classes(struct brw_context
*brw
,
97 struct intel_context
*intel
= &brw
->intel
;
99 /* Compute the total number of registers across all classes. */
100 int ra_reg_count
= 0;
101 for (int i
= 0; i
< class_count
; i
++) {
102 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
105 ralloc_free(brw
->wm
.ra_reg_to_grf
);
106 brw
->wm
.ra_reg_to_grf
= ralloc_array(brw
, uint8_t, ra_reg_count
);
107 ralloc_free(brw
->wm
.regs
);
108 brw
->wm
.regs
= ra_alloc_reg_set(ra_reg_count
);
109 ralloc_free(brw
->wm
.classes
);
110 brw
->wm
.classes
= ralloc_array(brw
, int, class_count
+ 1);
112 brw
->wm
.aligned_pairs_class
= -1;
114 /* Now, add the registers to their classes, and add the conflicts
115 * between them and the base GRF registers (and also each other).
118 int pairs_base_reg
= 0;
119 int pairs_reg_count
= 0;
120 for (int i
= 0; i
< class_count
; i
++) {
121 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
122 brw
->wm
.classes
[i
] = ra_alloc_reg_class(brw
->wm
.regs
);
124 /* Save this off for the aligned pair class at the end. */
125 if (class_sizes
[i
] == 2) {
126 pairs_base_reg
= reg
;
127 pairs_reg_count
= class_reg_count
;
130 for (int j
= 0; j
< class_reg_count
; j
++) {
131 ra_class_add_reg(brw
->wm
.regs
, brw
->wm
.classes
[i
], reg
);
133 brw
->wm
.ra_reg_to_grf
[reg
] = j
;
135 for (int base_reg
= j
;
136 base_reg
< j
+ class_sizes
[i
];
138 ra_add_transitive_reg_conflict(brw
->wm
.regs
, base_reg
, reg
);
144 assert(reg
== ra_reg_count
);
146 /* Add a special class for aligned pairs, which we'll put delta_x/y
147 * in on gen5 so that we can do PLN.
149 if (brw
->has_pln
&& reg_width
== 1 && intel
->gen
< 6) {
150 brw
->wm
.aligned_pairs_class
= ra_alloc_reg_class(brw
->wm
.regs
);
152 for (int i
= 0; i
< pairs_reg_count
; i
++) {
153 if ((brw
->wm
.ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
154 ra_class_add_reg(brw
->wm
.regs
, brw
->wm
.aligned_pairs_class
,
161 ra_set_finalize(brw
->wm
.regs
);
165 fs_visitor::assign_regs()
167 /* Most of this allocation was written for a reg_width of 1
168 * (dispatch_width == 8). In extending to 16-wide, the code was
169 * left in place and it was converted to have the hardware
170 * registers it's allocating be contiguous physical pairs of regs
171 * for reg_width == 2.
173 int reg_width
= c
->dispatch_width
/ 8;
174 int hw_reg_mapping
[this->virtual_grf_next
];
175 int first_assigned_grf
= ALIGN(this->first_non_payload_grf
, reg_width
);
176 int base_reg_count
= (BRW_MAX_GRF
- first_assigned_grf
) / reg_width
;
177 int class_sizes
[base_reg_count
];
180 calculate_live_intervals();
182 /* Set up the register classes.
184 * The base registers store a scalar value. For texture samples,
185 * we get virtual GRFs composed of 4 contiguous hw register. For
186 * structures and arrays, we store them as contiguous larger things
187 * than that, though we should be able to do better most of the
190 class_sizes
[class_count
++] = 1;
191 if (brw
->has_pln
&& intel
->gen
< 6) {
192 /* Always set up the (unaligned) pairs for gen5, so we can find
193 * them for making the aligned pair class.
195 class_sizes
[class_count
++] = 2;
197 for (int r
= 0; r
< this->virtual_grf_next
; r
++) {
200 for (i
= 0; i
< class_count
; i
++) {
201 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
204 if (i
== class_count
) {
205 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
206 fail("Object too large to register allocate.\n");
209 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
213 brw_alloc_reg_set_for_classes(brw
, class_sizes
, class_count
,
214 reg_width
, base_reg_count
);
216 struct ra_graph
*g
= ra_alloc_interference_graph(brw
->wm
.regs
,
217 this->virtual_grf_next
);
219 for (int i
= 0; i
< this->virtual_grf_next
; i
++) {
220 for (int c
= 0; c
< class_count
; c
++) {
221 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
222 if (brw
->wm
.aligned_pairs_class
>= 0 &&
223 this->delta_x
.reg
== i
) {
224 ra_set_node_class(g
, i
, brw
->wm
.aligned_pairs_class
);
226 ra_set_node_class(g
, i
, brw
->wm
.classes
[c
]);
232 for (int j
= 0; j
< i
; j
++) {
233 if (virtual_grf_interferes(i
, j
)) {
234 ra_add_node_interference(g
, i
, j
);
239 if (!ra_allocate_no_spills(g
)) {
240 /* Failed to allocate registers. Spill a reg, and the caller will
241 * loop back into here to try again.
243 int reg
= choose_spill_reg(g
);
246 fail("no register to spill\n");
247 } else if (intel
->gen
>= 7) {
248 fail("no spilling support on gen7 yet\n");
249 } else if (c
->dispatch_width
== 16) {
250 fail("no spilling support on 16-wide yet\n");
261 /* Get the chosen virtual registers for each node, and map virtual
262 * regs in the register classes back down to real hardware reg
265 this->grf_used
= first_assigned_grf
;
266 for (int i
= 0; i
< this->virtual_grf_next
; i
++) {
267 int reg
= ra_get_node_reg(g
, i
);
269 hw_reg_mapping
[i
] = (first_assigned_grf
+
270 brw
->wm
.ra_reg_to_grf
[reg
] * reg_width
);
271 this->grf_used
= MAX2(this->grf_used
,
272 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] *
276 foreach_list(node
, &this->instructions
) {
277 fs_inst
*inst
= (fs_inst
*)node
;
279 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
280 assign_reg(hw_reg_mapping
, &inst
->src
[0], reg_width
);
281 assign_reg(hw_reg_mapping
, &inst
->src
[1], reg_width
);
290 fs_visitor::emit_unspill(fs_inst
*inst
, fs_reg dst
, uint32_t spill_offset
)
292 int size
= virtual_grf_sizes
[dst
.reg
];
295 for (int chan
= 0; chan
< size
; chan
++) {
296 fs_inst
*unspill_inst
= new(mem_ctx
) fs_inst(FS_OPCODE_UNSPILL
,
299 unspill_inst
->offset
= spill_offset
+ chan
* REG_SIZE
;
300 unspill_inst
->ir
= inst
->ir
;
301 unspill_inst
->annotation
= inst
->annotation
;
303 /* Choose a MRF that won't conflict with an MRF that's live across the
304 * spill. Nothing else will make it up to MRF 14/15.
306 unspill_inst
->base_mrf
= 14;
307 unspill_inst
->mlen
= 1; /* header contains offset */
308 inst
->insert_before(unspill_inst
);
313 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
315 float loop_scale
= 1.0;
316 float spill_costs
[this->virtual_grf_next
];
317 bool no_spill
[this->virtual_grf_next
];
319 for (int i
= 0; i
< this->virtual_grf_next
; i
++) {
320 spill_costs
[i
] = 0.0;
324 /* Calculate costs for spilling nodes. Call it a cost of 1 per
325 * spill/unspill we'll have to do, and guess that the insides of
326 * loops run 10 times.
328 foreach_list(node
, &this->instructions
) {
329 fs_inst
*inst
= (fs_inst
*)node
;
331 for (unsigned int i
= 0; i
< 3; i
++) {
332 if (inst
->src
[i
].file
== GRF
) {
333 int size
= virtual_grf_sizes
[inst
->src
[i
].reg
];
334 spill_costs
[inst
->src
[i
].reg
] += size
* loop_scale
;
338 if (inst
->dst
.file
== GRF
) {
339 int size
= virtual_grf_sizes
[inst
->dst
.reg
];
340 spill_costs
[inst
->dst
.reg
] += size
* loop_scale
;
343 switch (inst
->opcode
) {
349 case BRW_OPCODE_WHILE
:
353 case FS_OPCODE_SPILL
:
354 if (inst
->src
[0].file
== GRF
)
355 no_spill
[inst
->src
[0].reg
] = true;
358 case FS_OPCODE_UNSPILL
:
359 if (inst
->dst
.file
== GRF
)
360 no_spill
[inst
->dst
.reg
] = true;
365 for (int i
= 0; i
< this->virtual_grf_next
; i
++) {
367 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
370 return ra_get_best_spill_node(g
);
374 fs_visitor::spill_reg(int spill_reg
)
376 int size
= virtual_grf_sizes
[spill_reg
];
377 unsigned int spill_offset
= c
->last_scratch
;
378 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
379 c
->last_scratch
+= size
* REG_SIZE
;
381 /* Generate spill/unspill instructions for the objects being
382 * spilled. Right now, we spill or unspill the whole thing to a
383 * virtual grf of the same size. For most instructions, though, we
384 * could just spill/unspill the GRF being accessed.
386 foreach_list(node
, &this->instructions
) {
387 fs_inst
*inst
= (fs_inst
*)node
;
389 for (unsigned int i
= 0; i
< 3; i
++) {
390 if (inst
->src
[i
].file
== GRF
&&
391 inst
->src
[i
].reg
== spill_reg
) {
392 inst
->src
[i
].reg
= virtual_grf_alloc(size
);
393 emit_unspill(inst
, inst
->src
[i
], spill_offset
);
397 if (inst
->dst
.file
== GRF
&&
398 inst
->dst
.reg
== spill_reg
) {
399 inst
->dst
.reg
= virtual_grf_alloc(size
);
401 /* Since we spill/unspill the whole thing even if we access
402 * just a component, we may need to unspill before the
403 * instruction we're spilling for.
405 if (size
!= 1 || inst
->predicated
) {
406 emit_unspill(inst
, inst
->dst
, spill_offset
);
409 fs_reg spill_src
= inst
->dst
;
410 spill_src
.reg_offset
= 0;
411 spill_src
.abs
= false;
412 spill_src
.negate
= false;
413 spill_src
.smear
= -1;
415 for (int chan
= 0; chan
< size
; chan
++) {
416 fs_inst
*spill_inst
= new(mem_ctx
) fs_inst(FS_OPCODE_SPILL
,
417 reg_null_f
, spill_src
);
418 spill_src
.reg_offset
++;
419 spill_inst
->offset
= spill_offset
+ chan
* REG_SIZE
;
420 spill_inst
->ir
= inst
->ir
;
421 spill_inst
->annotation
= inst
->annotation
;
422 spill_inst
->base_mrf
= 14;
423 spill_inst
->mlen
= 2; /* header, value */
424 inst
->insert_after(spill_inst
);
429 this->live_intervals_valid
= false;