2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
36 assign_reg(unsigned *reg_hw_locations
, fs_reg
*reg
)
38 if (reg
->file
== GRF
) {
39 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
45 fs_visitor::assign_regs_trivial()
47 unsigned hw_reg_mapping
[this->alloc
.count
+ 1];
49 int reg_width
= dispatch_width
/ 8;
51 /* Note that compressed instructions require alignment to 2 registers. */
52 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
53 for (i
= 1; i
<= this->alloc
.count
; i
++) {
54 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
55 this->alloc
.sizes
[i
- 1]);
57 this->grf_used
= hw_reg_mapping
[this->alloc
.count
];
59 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
60 assign_reg(hw_reg_mapping
, &inst
->dst
);
61 for (i
= 0; i
< inst
->sources
; i
++) {
62 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
66 if (this->grf_used
>= max_grf
) {
67 fail("Ran out of regs on trivial allocator (%d/%d)\n",
68 this->grf_used
, max_grf
);
70 this->alloc
.count
= this->grf_used
;
76 brw_alloc_reg_set(struct brw_compiler
*compiler
, int reg_width
)
78 const struct brw_device_info
*devinfo
= compiler
->devinfo
;
79 int base_reg_count
= BRW_MAX_GRF
;
80 int index
= reg_width
- 1;
82 /* The registers used to make up almost all values handled in the compiler
83 * are a scalar value occupying a single register (or 2 registers in the
84 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
85 * multiplying allocated register numbers by 2). Things that were
86 * aggregates of scalar values at the GLSL level were split to scalar
87 * values by split_virtual_grfs().
89 * However, texture SEND messages return a series of contiguous registers
90 * to write into. We currently always ask for 4 registers, but we may
91 * convert that to use less some day.
93 * Additionally, on gen5 we need aligned pairs of registers for the PLN
94 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
97 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
98 * and we add in '3' to make indexing the array easier for the common case
99 * (since we'll probably want it for texturing later).
101 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
102 * means that we may need any size up to the sampler message size limit (11
106 int class_sizes
[MAX_VGRF_SIZE
];
108 if (devinfo
->gen
>= 7) {
109 for (class_count
= 0; class_count
< MAX_VGRF_SIZE
; class_count
++)
110 class_sizes
[class_count
] = class_count
+ 1;
112 for (class_count
= 0; class_count
< 4; class_count
++)
113 class_sizes
[class_count
] = class_count
+ 1;
114 class_sizes
[class_count
++] = 8;
117 memset(compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
, 0,
118 sizeof(compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
));
119 int *class_to_ra_reg_range
= compiler
->fs_reg_sets
[index
].class_to_ra_reg_range
;
121 /* Compute the total number of registers across all classes. */
122 int ra_reg_count
= 0;
123 for (int i
= 0; i
< class_count
; i
++) {
124 if (devinfo
->gen
<= 5 && reg_width
== 2) {
127 * In order to reduce the hardware complexity, the following
128 * rules and restrictions apply to the compressed instruction:
130 * * Operand Alignment Rule: With the exceptions listed below, a
131 * source/destination operand in general should be aligned to
132 * even 256-bit physical register with a region size equal to
133 * two 256-bit physical register
135 ra_reg_count
+= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
137 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
139 /* Mark the last register. We'll fill in the beginnings later. */
140 class_to_ra_reg_range
[class_sizes
[i
]] = ra_reg_count
;
143 /* Fill out the rest of the range markers */
144 for (int i
= 1; i
< 17; ++i
) {
145 if (class_to_ra_reg_range
[i
] == 0)
146 class_to_ra_reg_range
[i
] = class_to_ra_reg_range
[i
-1];
149 uint8_t *ra_reg_to_grf
= ralloc_array(compiler
, uint8_t, ra_reg_count
);
150 struct ra_regs
*regs
= ra_alloc_reg_set(compiler
, ra_reg_count
);
151 if (devinfo
->gen
>= 6)
152 ra_set_allocate_round_robin(regs
);
153 int *classes
= ralloc_array(compiler
, int, class_count
);
154 int aligned_pairs_class
= -1;
156 /* Allocate space for q values. We allocate class_count + 1 because we
157 * want to leave room for the aligned pairs class if we have it. */
158 unsigned int **q_values
= ralloc_array(compiler
, unsigned int *,
160 for (int i
= 0; i
< class_count
+ 1; ++i
)
161 q_values
[i
] = ralloc_array(q_values
, unsigned int, class_count
+ 1);
163 /* Now, add the registers to their classes, and add the conflicts
164 * between them and the base GRF registers (and also each other).
167 int pairs_base_reg
= 0;
168 int pairs_reg_count
= 0;
169 for (int i
= 0; i
< class_count
; i
++) {
171 if (devinfo
->gen
<= 5 && reg_width
== 2) {
172 class_reg_count
= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
174 /* See comment below. The only difference here is that we are
175 * dealing with pairs of registers instead of single registers.
176 * Registers of odd sizes simply get rounded up. */
177 for (int j
= 0; j
< class_count
; j
++)
178 q_values
[i
][j
] = (class_sizes
[i
] + 1) / 2 +
179 (class_sizes
[j
] + 1) / 2 - 1;
181 class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
183 /* From register_allocate.c:
185 * q(B,C) (indexed by C, B is this register class) in
186 * Runeson/Nyström paper. This is "how many registers of B could
187 * the worst choice register from C conflict with".
189 * If we just let the register allocation algorithm compute these
190 * values, is extremely expensive. However, since all of our
191 * registers are laid out, we can very easily compute them
192 * ourselves. View the register from C as fixed starting at GRF n
193 * somwhere in the middle, and the register from B as sliding back
194 * and forth. Then the first register to conflict from B is the
195 * one starting at n - class_size[B] + 1 and the last register to
196 * conflict will start at n + class_size[B] - 1. Therefore, the
197 * number of conflicts from B is class_size[B] + class_size[C] - 1.
199 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
200 * B | | | | | |n| --> | | | | | | |
201 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
206 for (int j
= 0; j
< class_count
; j
++)
207 q_values
[i
][j
] = class_sizes
[i
] + class_sizes
[j
] - 1;
209 classes
[i
] = ra_alloc_reg_class(regs
);
211 /* Save this off for the aligned pair class at the end. */
212 if (class_sizes
[i
] == 2) {
213 pairs_base_reg
= reg
;
214 pairs_reg_count
= class_reg_count
;
217 if (devinfo
->gen
<= 5 && reg_width
== 2) {
218 for (int j
= 0; j
< class_reg_count
; j
++) {
219 ra_class_add_reg(regs
, classes
[i
], reg
);
221 ra_reg_to_grf
[reg
] = j
* 2;
223 for (int base_reg
= j
;
224 base_reg
< j
+ (class_sizes
[i
] + 1) / 2;
226 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
232 for (int j
= 0; j
< class_reg_count
; j
++) {
233 ra_class_add_reg(regs
, classes
[i
], reg
);
235 ra_reg_to_grf
[reg
] = j
;
237 for (int base_reg
= j
;
238 base_reg
< j
+ class_sizes
[i
];
240 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
247 assert(reg
== ra_reg_count
);
249 /* Add a special class for aligned pairs, which we'll put delta_xy
250 * in on Gen <= 6 so that we can do PLN.
252 if (devinfo
->has_pln
&& reg_width
== 1 && devinfo
->gen
<= 6) {
253 aligned_pairs_class
= ra_alloc_reg_class(regs
);
255 for (int i
= 0; i
< pairs_reg_count
; i
++) {
256 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
257 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
261 for (int i
= 0; i
< class_count
; i
++) {
262 /* These are a little counter-intuitive because the pair registers
263 * are required to be aligned while the register they are
264 * potentially interferring with are not. In the case where the
265 * size is even, the worst-case is that the register is
266 * odd-aligned. In the odd-size case, it doesn't matter.
268 q_values
[class_count
][i
] = class_sizes
[i
] / 2 + 1;
269 q_values
[i
][class_count
] = class_sizes
[i
] + 1;
271 q_values
[class_count
][class_count
] = 1;
274 ra_set_finalize(regs
, q_values
);
276 ralloc_free(q_values
);
278 compiler
->fs_reg_sets
[index
].regs
= regs
;
279 for (unsigned i
= 0; i
< ARRAY_SIZE(compiler
->fs_reg_sets
[index
].classes
); i
++)
280 compiler
->fs_reg_sets
[index
].classes
[i
] = -1;
281 for (int i
= 0; i
< class_count
; i
++)
282 compiler
->fs_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
283 compiler
->fs_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
284 compiler
->fs_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
288 brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
)
290 brw_alloc_reg_set(compiler
, 1);
291 brw_alloc_reg_set(compiler
, 2);
295 count_to_loop_end(const bblock_t
*block
)
297 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
298 return block
->end_ip
;
301 /* Skip the first block, since we don't want to count the do the calling
304 for (block
= block
->next();
306 block
= block
->next()) {
307 if (block
->start()->opcode
== BRW_OPCODE_DO
)
309 if (block
->end()->opcode
== BRW_OPCODE_WHILE
) {
312 return block
->end_ip
;
315 unreachable("not reached");
319 * Sets up interference between thread payload registers and the virtual GRFs
320 * to be allocated for program temporaries.
322 * We want to be able to reallocate the payload for our virtual GRFs, notably
323 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
326 * The layout of the payload registers is:
328 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
329 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
330 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
332 * And we have payload_node_count nodes covering these registers in order
333 * (note that in SIMD16, a node is two registers).
336 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
337 int payload_node_count
,
338 int first_payload_node
)
343 int payload_last_use_ip
[payload_node_count
];
344 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
346 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
347 switch (inst
->opcode
) {
351 /* Since payload regs are deffed only at the start of the shader
352 * execution, any uses of the payload within a loop mean the live
353 * interval extends to the end of the outermost loop. Find the ip of
357 loop_end_ip
= count_to_loop_end(block
);
359 case BRW_OPCODE_WHILE
:
368 use_ip
= loop_end_ip
;
372 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
373 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
374 * the start (see interp_reg()).
376 for (int i
= 0; i
< inst
->sources
; i
++) {
377 if (inst
->src
[i
].file
== HW_REG
&&
378 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
379 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
;
380 if (node_nr
>= payload_node_count
)
383 payload_last_use_ip
[node_nr
] = use_ip
;
387 /* Special case instructions which have extra implied registers used. */
388 switch (inst
->opcode
) {
389 case FS_OPCODE_LINTERP
:
390 /* On gen6+ in SIMD16, there are 4 adjacent registers used by
391 * PLN's sourcing of the deltas, while we list only the first one
392 * in the arguments. Pre-gen6, the deltas are computed in normal
395 if (devinfo
->gen
>= 6) {
397 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
398 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
399 BRW_GENERAL_REGISTER_FILE
) {
400 for (int i
= 1; i
< 4; ++i
) {
401 int node
= inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
+ i
;
402 assert(node
< payload_node_count
);
403 payload_last_use_ip
[node
] = use_ip
;
409 case CS_OPCODE_CS_TERMINATE
:
410 payload_last_use_ip
[0] = use_ip
;
415 /* We could omit this for the !inst->header_present case, except
416 * that the simulator apparently incorrectly reads from g0/g1
417 * instead of sideband. It also really freaks out driver
418 * developers to see g0 used in unusual places, so just always
421 payload_last_use_ip
[0] = use_ip
;
422 payload_last_use_ip
[1] = use_ip
;
430 for (int i
= 0; i
< payload_node_count
; i
++) {
431 /* Mark the payload node as interfering with any virtual grf that is
432 * live between the start of the program and our last use of the payload
435 for (unsigned j
= 0; j
< this->alloc
.count
; j
++) {
436 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
437 * in order to not have to worry about the uniform issue described in
438 * calculate_live_intervals().
440 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
441 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
446 for (int i
= 0; i
< payload_node_count
; i
++) {
447 /* Mark each payload node as being allocated to its physical register.
449 * The alternative would be to have per-physical-register classes, which
450 * would just be silly.
452 if (devinfo
->gen
<= 5 && dispatch_width
== 16) {
453 /* We have to divide by 2 here because we only have even numbered
454 * registers. Some of the payload registers will be odd, but
455 * that's ok because their physical register numbers have already
456 * been assigned. The only thing this is used for is interference.
458 ra_set_node_reg(g
, first_payload_node
+ i
, i
/ 2);
460 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
466 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
468 * This is used in assign_regs() to decide which of the GRFs that we use as
469 * MRFs on gen7 get normally register allocated, and in register spilling to
470 * see if we can actually use MRFs to do spills without overwriting normal MRF
474 get_used_mrfs(fs_visitor
*v
, bool *mrf_used
)
476 int reg_width
= v
->dispatch_width
/ 8;
478 memset(mrf_used
, 0, BRW_MAX_MRF
* sizeof(bool));
480 foreach_block_and_inst(block
, fs_inst
, inst
, v
->cfg
) {
481 if (inst
->dst
.file
== MRF
) {
482 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
483 mrf_used
[reg
] = true;
484 if (reg_width
== 2) {
485 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
486 mrf_used
[reg
+ 4] = true;
488 mrf_used
[reg
+ 1] = true;
493 if (inst
->mlen
> 0) {
494 for (int i
= 0; i
< v
->implied_mrf_writes(inst
); i
++) {
495 mrf_used
[inst
->base_mrf
+ i
] = true;
502 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
503 * messages (treated as MRFs in code generation).
506 setup_mrf_hack_interference(fs_visitor
*v
, struct ra_graph
*g
,
507 int first_mrf_node
, int *first_used_mrf
)
509 bool mrf_used
[BRW_MAX_MRF
];
510 get_used_mrfs(v
, mrf_used
);
512 *first_used_mrf
= BRW_MAX_MRF
;
513 for (int i
= 0; i
< BRW_MAX_MRF
; i
++) {
514 /* Mark each MRF reg node as being allocated to its physical register.
516 * The alternative would be to have per-physical-register classes, which
517 * would just be silly.
519 ra_set_node_reg(g
, first_mrf_node
+ i
, GEN7_MRF_HACK_START
+ i
);
521 /* Since we don't have any live/dead analysis on the MRFs, just mark all
522 * that are used as conflicting with all virtual GRFs.
525 if (i
< *first_used_mrf
)
528 for (unsigned j
= 0; j
< v
->alloc
.count
; j
++) {
529 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
536 fs_visitor::assign_regs(bool allow_spilling
)
538 /* Most of this allocation was written for a reg_width of 1
539 * (dispatch_width == 8). In extending to SIMD16, the code was
540 * left in place and it was converted to have the hardware
541 * registers it's allocating be contiguous physical pairs of regs
542 * for reg_width == 2.
544 int reg_width
= dispatch_width
/ 8;
545 unsigned hw_reg_mapping
[this->alloc
.count
];
546 int payload_node_count
= ALIGN(this->first_non_payload_grf
, reg_width
);
547 int rsi
= reg_width
- 1; /* Which compiler->fs_reg_sets[] to use */
548 calculate_live_intervals();
550 int node_count
= this->alloc
.count
;
551 int first_payload_node
= node_count
;
552 node_count
+= payload_node_count
;
553 int first_mrf_hack_node
= node_count
;
554 if (devinfo
->gen
>= 7)
555 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
557 ra_alloc_interference_graph(compiler
->fs_reg_sets
[rsi
].regs
, node_count
);
559 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
560 unsigned size
= this->alloc
.sizes
[i
];
563 assert(size
<= ARRAY_SIZE(compiler
->fs_reg_sets
[rsi
].classes
) &&
564 "Register allocation relies on split_virtual_grfs()");
565 c
= compiler
->fs_reg_sets
[rsi
].classes
[size
- 1];
567 /* Special case: on pre-GEN6 hardware that supports PLN, the
568 * second operand of a PLN instruction needs to be an
569 * even-numbered register, so we have a special register class
570 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
571 * uses this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
572 * second operand of a PLN instruction (since it doesn't support
573 * any other interpolation modes). So all we need to do is find
574 * that register and set it to the appropriate class.
576 if (compiler
->fs_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
577 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
&&
578 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
579 c
= compiler
->fs_reg_sets
[rsi
].aligned_pairs_class
;
582 ra_set_node_class(g
, i
, c
);
584 for (unsigned j
= 0; j
< i
; j
++) {
585 if (virtual_grf_interferes(i
, j
)) {
586 ra_add_node_interference(g
, i
, j
);
591 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
592 if (devinfo
->gen
>= 7) {
593 int first_used_mrf
= BRW_MAX_MRF
;
594 setup_mrf_hack_interference(this, g
, first_mrf_hack_node
,
597 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
598 /* When we do send-from-GRF for FB writes, we need to ensure that
599 * the last write instruction sends from a high register. This is
600 * because the vertex fetcher wants to start filling the low
601 * payload registers while the pixel data port is still working on
602 * writing out the memory. If we don't do this, we get rendering
605 * We could just do "something high". Instead, we just pick the
606 * highest register that works.
609 int size
= alloc
.sizes
[inst
->src
[0].reg
];
610 int reg
= compiler
->fs_reg_sets
[rsi
].class_to_ra_reg_range
[size
] - 1;
612 /* If something happened to spill, we want to push the EOT send
613 * register early enough in the register file that we don't
614 * conflict with any used MRF hack registers.
616 reg
-= BRW_MAX_MRF
- first_used_mrf
;
618 ra_set_node_reg(g
, inst
->src
[0].reg
, reg
);
624 if (dispatch_width
> 8) {
625 /* In 16-wide dispatch we have an issue where a compressed
626 * instruction is actually two instructions executed simultaneiously.
627 * It's actually ok to have the source and destination registers be
628 * the same. In this case, each instruction over-writes its own
629 * source and there's no problem. The real problem here is if the
630 * source and destination registers are off by one. Then you can end
631 * up in a scenario where the first instruction over-writes the
632 * source of the second instruction. Since the compiler doesn't know
633 * about this level of granularity, we simply make the source and
634 * destination interfere.
636 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
637 if (inst
->dst
.file
!= GRF
)
640 for (int i
= 0; i
< inst
->sources
; ++i
) {
641 if (inst
->src
[i
].file
== GRF
) {
642 ra_add_node_interference(g
, inst
->dst
.reg
, inst
->src
[i
].reg
);
648 /* Debug of register spilling: Go spill everything. */
649 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL
)) {
650 int reg
= choose_spill_reg(g
);
659 if (!ra_allocate(g
)) {
660 /* Failed to allocate registers. Spill a reg, and the caller will
661 * loop back into here to try again.
663 int reg
= choose_spill_reg(g
);
666 fail("no register to spill:\n");
667 dump_instructions(NULL
);
668 } else if (allow_spilling
) {
677 /* Get the chosen virtual registers for each node, and map virtual
678 * regs in the register classes back down to real hardware reg
681 this->grf_used
= payload_node_count
;
682 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
683 int reg
= ra_get_node_reg(g
, i
);
685 hw_reg_mapping
[i
] = compiler
->fs_reg_sets
[rsi
].ra_reg_to_grf
[reg
];
686 this->grf_used
= MAX2(this->grf_used
,
687 hw_reg_mapping
[i
] + this->alloc
.sizes
[i
]);
690 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
691 assign_reg(hw_reg_mapping
, &inst
->dst
);
692 for (int i
= 0; i
< inst
->sources
; i
++) {
693 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
697 this->alloc
.count
= this->grf_used
;
705 fs_visitor::emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg dst
,
706 uint32_t spill_offset
, int count
)
709 if (dispatch_width
== 16 && count
% 2 == 0)
712 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
713 .group(reg_size
* 8, 0)
716 for (int i
= 0; i
< count
/ reg_size
; i
++) {
717 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
718 bool gen7_read
= devinfo
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
719 fs_inst
*unspill_inst
= ibld
.emit(gen7_read
?
720 SHADER_OPCODE_GEN7_SCRATCH_READ
:
721 SHADER_OPCODE_GEN4_SCRATCH_READ
,
723 unspill_inst
->offset
= spill_offset
;
724 unspill_inst
->regs_written
= reg_size
;
727 unspill_inst
->base_mrf
= 14;
728 unspill_inst
->mlen
= 1; /* header contains offset */
731 dst
.reg_offset
+= reg_size
;
732 spill_offset
+= reg_size
* REG_SIZE
;
737 fs_visitor::emit_spill(bblock_t
*block
, fs_inst
*inst
, fs_reg src
,
738 uint32_t spill_offset
, int count
)
741 int spill_base_mrf
= 14;
742 if (dispatch_width
== 16 && count
% 2 == 0) {
747 const fs_builder ibld
= bld
.annotate(inst
->annotation
, inst
->ir
)
748 .group(reg_size
* 8, 0)
749 .at(block
, inst
->next
);
751 for (int i
= 0; i
< count
/ reg_size
; i
++) {
752 fs_inst
*spill_inst
=
753 ibld
.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE
, bld
.null_reg_f(), src
);
754 src
.reg_offset
+= reg_size
;
755 spill_inst
->offset
= spill_offset
+ i
* reg_size
* REG_SIZE
;
756 spill_inst
->mlen
= 1 + reg_size
; /* header, value */
757 spill_inst
->base_mrf
= spill_base_mrf
;
762 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
764 float loop_scale
= 1.0;
765 float spill_costs
[this->alloc
.count
];
766 bool no_spill
[this->alloc
.count
];
768 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
769 spill_costs
[i
] = 0.0;
773 /* Calculate costs for spilling nodes. Call it a cost of 1 per
774 * spill/unspill we'll have to do, and guess that the insides of
775 * loops run 10 times.
777 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
778 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
779 if (inst
->src
[i
].file
== GRF
) {
780 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
782 /* Register spilling logic assumes full-width registers; smeared
783 * registers have a width of 1 so if we try to spill them we'll
784 * generate invalid assembly. This shouldn't be a problem because
785 * smeared registers are only used as short-term temporaries when
786 * loading pull constants, so spilling them is unlikely to reduce
787 * register pressure anyhow.
789 if (!inst
->src
[i
].is_contiguous()) {
790 no_spill
[inst
->src
[i
].reg
] = true;
795 if (inst
->dst
.file
== GRF
) {
796 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
798 if (!inst
->dst
.is_contiguous()) {
799 no_spill
[inst
->dst
.reg
] = true;
803 switch (inst
->opcode
) {
809 case BRW_OPCODE_WHILE
:
813 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
814 if (inst
->src
[0].file
== GRF
)
815 no_spill
[inst
->src
[0].reg
] = true;
818 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
819 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
820 if (inst
->dst
.file
== GRF
)
821 no_spill
[inst
->dst
.reg
] = true;
829 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
831 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
834 return ra_get_best_spill_node(g
);
838 fs_visitor::spill_reg(int spill_reg
)
840 int size
= alloc
.sizes
[spill_reg
];
841 unsigned int spill_offset
= last_scratch
;
842 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
843 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
845 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
846 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
847 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
848 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
849 * depth), starting from m1. In summary: We may not be able to spill in
850 * SIMD16 mode, because we'd stomp the FB writes.
852 if (!spilled_any_registers
) {
853 bool mrf_used
[BRW_MAX_MRF
];
854 get_used_mrfs(this, mrf_used
);
856 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF
; i
++) {
858 fail("Register spilling not supported with m%d used", i
);
863 spilled_any_registers
= true;
866 last_scratch
+= size
* REG_SIZE
;
868 /* Generate spill/unspill instructions for the objects being
869 * spilled. Right now, we spill or unspill the whole thing to a
870 * virtual grf of the same size. For most instructions, though, we
871 * could just spill/unspill the GRF being accessed.
873 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
874 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
875 if (inst
->src
[i
].file
== GRF
&&
876 inst
->src
[i
].reg
== spill_reg
) {
877 int regs_read
= inst
->regs_read(i
);
878 int subset_spill_offset
= (spill_offset
+
879 REG_SIZE
* inst
->src
[i
].reg_offset
);
880 fs_reg
unspill_dst(GRF
, alloc
.allocate(regs_read
));
882 inst
->src
[i
].reg
= unspill_dst
.reg
;
883 inst
->src
[i
].reg_offset
= 0;
885 emit_unspill(block
, inst
, unspill_dst
, subset_spill_offset
,
890 if (inst
->dst
.file
== GRF
&&
891 inst
->dst
.reg
== spill_reg
) {
892 int subset_spill_offset
= (spill_offset
+
893 REG_SIZE
* inst
->dst
.reg_offset
);
894 fs_reg
spill_src(GRF
, alloc
.allocate(inst
->regs_written
));
896 inst
->dst
.reg
= spill_src
.reg
;
897 inst
->dst
.reg_offset
= 0;
899 /* If we're immediately spilling the register, we should not use
900 * destination dependency hints. Doing so will cause the GPU do
901 * try to read and write the register at the same time and may
904 inst
->no_dd_clear
= false;
905 inst
->no_dd_check
= false;
907 /* If our write is going to affect just part of the
908 * inst->regs_written(), then we need to unspill the destination
909 * since we write back out all of the regs_written().
911 if (inst
->is_partial_write())
912 emit_unspill(block
, inst
, spill_src
, subset_spill_offset
,
915 emit_spill(block
, inst
, spill_src
, subset_spill_offset
,
920 invalidate_live_intervals();