src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 extern "C" {
  29
  30 #include <sys/types.h>
  31
  32 #include "main/macros.h"
  33 #include "main/shaderobj.h"
  34 #include "main/uniforms.h"
  35 #include "program/prog_parameter.h"
  36 #include "program/prog_print.h"
  37 #include "program/prog_optimize.h"
  38 #include "program/register_allocate.h"
  39 #include "program/sampler.h"
  40 #include "program/hash_table.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_wm.h"
  44 }
  45 #include "brw_fs.h"
  46 #include "../glsl/glsl_types.h"
  47 #include "../glsl/ir_optimization.h"
  48 #include "../glsl/ir_print_visitor.h"
  49
  50 static void
  51 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width)
  52 {
  53    if (reg->file == GRF && reg->reg != 0) {
  54       assert(reg->reg_offset >= 0);
  55       reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset * reg_width;
  56       reg->reg = 0;
  57    }
  58 }
  59
  60 void
  61 fs_visitor::assign_regs_trivial()
  62 {
  63    int last_grf = 0;
  64    int hw_reg_mapping[this->virtual_grf_next];
  65    int i;
  66    int reg_width = c->dispatch_width / 8;
  67
  68    hw_reg_mapping[0] = 0;
  69    /* Note that compressed instructions require alignment to 2 registers. */
  70    hw_reg_mapping[1] = ALIGN(this->first_non_payload_grf, reg_width);
  71    for (i = 2; i < this->virtual_grf_next; i++) {
  72       hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
  73                            this->virtual_grf_sizes[i - 1] * reg_width);
  74    }
  75    last_grf = hw_reg_mapping[i - 1] + (this->virtual_grf_sizes[i - 1] *
  76                                        reg_width);
  77
  78    foreach_iter(exec_list_iterator, iter, this->instructions) {
  79       fs_inst *inst = (fs_inst *)iter.get();
  80
  81       assign_reg(hw_reg_mapping, &inst->dst, reg_width);
  82       assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
  83       assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
  84    }
  85
  86    if (last_grf >= BRW_MAX_GRF) {
  87       fail("Ran out of regs on trivial allocator (%d/%d)\n",
  88            last_grf, BRW_MAX_GRF);
  89    }
  90
  91    this->grf_used = last_grf + reg_width;
  92 }
  93
  94 bool
  95 fs_visitor::assign_regs()
  96 {
  97    /* Most of this allocation was written for a reg_width of 1
  98     * (dispatch_width == 8).  In extending to 16-wide, the code was
  99     * left in place and it was converted to have the hardware
 100     * registers it's allocating be contiguous physical pairs of regs
 101     * for reg_width == 2.
 102     */
 103    int reg_width = c->dispatch_width / 8;
 104    int hw_reg_mapping[this->virtual_grf_next + 1];
 105    int first_assigned_grf = ALIGN(this->first_non_payload_grf, reg_width);
 106    int base_reg_count = (BRW_MAX_GRF - first_assigned_grf) / reg_width;
 107    int class_sizes[base_reg_count];
 108    int class_count = 0;
 109    int aligned_pair_class = -1;
 110
 111    calculate_live_intervals();
 112
 113    /* Set up the register classes.
 114     *
 115     * The base registers store a scalar value.  For texture samples,
 116     * we get virtual GRFs composed of 4 contiguous hw register.  For
 117     * structures and arrays, we store them as contiguous larger things
 118     * than that, though we should be able to do better most of the
 119     * time.
 120     */
 121    class_sizes[class_count++] = 1;
 122    if (brw->has_pln && intel->gen < 6) {
 123       /* Always set up the (unaligned) pairs for gen5, so we can find
 124        * them for making the aligned pair class.
 125        */
 126       class_sizes[class_count++] = 2;
 127    }
 128    for (int r = 1; r < this->virtual_grf_next; r++) {
 129       int i;
 130
 131       for (i = 0; i < class_count; i++) {
 132          if (class_sizes[i] == this->virtual_grf_sizes[r])
 133             break;
 134       }
 135       if (i == class_count) {
 136          if (this->virtual_grf_sizes[r] >= base_reg_count) {
 137             fail("Object too large to register allocate.\n");
 138          }
 139
 140          class_sizes[class_count++] = this->virtual_grf_sizes[r];
 141       }
 142    }
 143
 144    int ra_reg_count = 0;
 145    int class_base_reg[class_count];
 146    int class_reg_count[class_count];
 147    int classes[class_count + 1];
 148
 149    for (int i = 0; i < class_count; i++) {
 150       class_base_reg[i] = ra_reg_count;
 151       class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
 152       ra_reg_count += class_reg_count[i];
 153    }
 154
 155    struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
 156    for (int i = 0; i < class_count; i++) {
 157       classes[i] = ra_alloc_reg_class(regs);
 158
 159       for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 160          ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
 161       }
 162
 163       /* Add conflicts between our contiguous registers aliasing
 164        * base regs and other register classes' contiguous registers
 165        * that alias base regs, or the base regs themselves for classes[0].
 166        */
 167       for (int c = 0; c <= i; c++) {
 168          for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 169             for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
 170                  c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
 171                  c_r++) {
 172
 173                if (0) {
 174                   printf("%d/%d conflicts %d/%d\n",
 175                          class_sizes[i], first_assigned_grf + i_r,
 176                          class_sizes[c], first_assigned_grf + c_r);
 177                }
 178
 179                ra_add_reg_conflict(regs,
 180                                    class_base_reg[i] + i_r,
 181                                    class_base_reg[c] + c_r);
 182             }
 183          }
 184       }
 185    }
 186
 187    /* Add a special class for aligned pairs, which we'll put delta_x/y
 188     * in on gen5 so that we can do PLN.
 189     */
 190    if (brw->has_pln && reg_width == 1 && intel->gen < 6) {
 191       int reg_count = (base_reg_count - 1) / 2;
 192       int unaligned_pair_class = 1;
 193       assert(class_sizes[unaligned_pair_class] == 2);
 194
 195       aligned_pair_class = class_count;
 196       classes[aligned_pair_class] = ra_alloc_reg_class(regs);
 197       class_sizes[aligned_pair_class] = 2;
 198       class_base_reg[aligned_pair_class] = 0;
 199       class_reg_count[aligned_pair_class] = 0;
 200       int start = (first_assigned_grf & 1) ? 1 : 0;
 201
 202       for (int i = 0; i < reg_count; i++) {
 203          ra_class_add_reg(regs, classes[aligned_pair_class],
 204                           class_base_reg[unaligned_pair_class] + i * 2 + start);
 205       }
 206       class_count++;
 207    }
 208
 209    ra_set_finalize(regs);
 210
 211    struct ra_graph *g = ra_alloc_interference_graph(regs,
 212                                                     this->virtual_grf_next);
 213    /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
 214     * with nodes.
 215     */
 216    ra_set_node_class(g, 0, classes[0]);
 217
 218    for (int i = 1; i < this->virtual_grf_next; i++) {
 219       for (int c = 0; c < class_count; c++) {
 220          if (class_sizes[c] == this->virtual_grf_sizes[i]) {
 221             if (aligned_pair_class >= 0 &&
 222                 this->delta_x.reg == i) {
 223                ra_set_node_class(g, i, classes[aligned_pair_class]);
 224             } else {
 225                ra_set_node_class(g, i, classes[c]);
 226             }
 227             break;
 228          }
 229       }
 230
 231       for (int j = 1; j < i; j++) {
 232          if (virtual_grf_interferes(i, j)) {
 233             ra_add_node_interference(g, i, j);
 234          }
 235       }
 236    }
 237
 238    if (!ra_allocate_no_spills(g)) {
 239       /* Failed to allocate registers.  Spill a reg, and the caller will
 240        * loop back into here to try again.
 241        */
 242       int reg = choose_spill_reg(g);
 243
 244       if (reg == -1) {
 245          fail("no register to spill\n");
 246       } else if (intel->gen >= 7) {
 247          fail("no spilling support on gen7 yet\n");
 248       } else if (c->dispatch_width == 16) {
 249          fail("no spilling support on 16-wide yet\n");
 250       } else {
 251          spill_reg(reg);
 252       }
 253
 254
 255       ralloc_free(g);
 256       ralloc_free(regs);
 257
 258       return false;
 259    }
 260
 261    /* Get the chosen virtual registers for each node, and map virtual
 262     * regs in the register classes back down to real hardware reg
 263     * numbers.
 264     */
 265    this->grf_used = first_assigned_grf;
 266    hw_reg_mapping[0] = 0; /* unused */
 267    for (int i = 1; i < this->virtual_grf_next; i++) {
 268       int reg = ra_get_node_reg(g, i);
 269       int hw_reg = -1;
 270
 271       for (int c = 0; c < class_count; c++) {
 272          if (reg >= class_base_reg[c] &&
 273              reg < class_base_reg[c] + class_reg_count[c]) {
 274             hw_reg = reg - class_base_reg[c];
 275             break;
 276          }
 277       }
 278
 279       assert(hw_reg >= 0);
 280       hw_reg_mapping[i] = first_assigned_grf + hw_reg * reg_width;
 281       this->grf_used = MAX2(this->grf_used,
 282                             hw_reg_mapping[i] + this->virtual_grf_sizes[i] *
 283                             reg_width);
 284    }
 285
 286    foreach_iter(exec_list_iterator, iter, this->instructions) {
 287       fs_inst *inst = (fs_inst *)iter.get();
 288
 289       assign_reg(hw_reg_mapping, &inst->dst, reg_width);
 290       assign_reg(hw_reg_mapping, &inst->src[0], reg_width);
 291       assign_reg(hw_reg_mapping, &inst->src[1], reg_width);
 292    }
 293
 294    ralloc_free(g);
 295    ralloc_free(regs);
 296
 297    return true;
 298 }
 299
 300 void
 301 fs_visitor::emit_unspill(fs_inst *inst, fs_reg dst, uint32_t spill_offset)
 302 {
 303    int size = virtual_grf_sizes[dst.reg];
 304    dst.reg_offset = 0;
 305
 306    for (int chan = 0; chan < size; chan++) {
 307       fs_inst *unspill_inst = new(mem_ctx) fs_inst(FS_OPCODE_UNSPILL,
 308                                                    dst);
 309       dst.reg_offset++;
 310       unspill_inst->offset = spill_offset + chan * REG_SIZE;
 311       unspill_inst->ir = inst->ir;
 312       unspill_inst->annotation = inst->annotation;
 313
 314       /* Choose a MRF that won't conflict with an MRF that's live across the
 315        * spill.  Nothing else will make it up to MRF 14/15.
 316        */
 317       unspill_inst->base_mrf = 14;
 318       unspill_inst->mlen = 1; /* header contains offset */
 319       inst->insert_before(unspill_inst);
 320    }
 321 }
 322
 323 int
 324 fs_visitor::choose_spill_reg(struct ra_graph *g)
 325 {
 326    float loop_scale = 1.0;
 327    float spill_costs[this->virtual_grf_next];
 328    bool no_spill[this->virtual_grf_next];
 329
 330    for (int i = 0; i < this->virtual_grf_next; i++) {
 331       spill_costs[i] = 0.0;
 332       no_spill[i] = false;
 333    }
 334
 335    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 336     * spill/unspill we'll have to do, and guess that the insides of
 337     * loops run 10 times.
 338     */
 339    foreach_iter(exec_list_iterator, iter, this->instructions) {
 340       fs_inst *inst = (fs_inst *)iter.get();
 341
 342       for (unsigned int i = 0; i < 3; i++) {
 343          if (inst->src[i].file == GRF) {
 344             int size = virtual_grf_sizes[inst->src[i].reg];
 345             spill_costs[inst->src[i].reg] += size * loop_scale;
 346          }
 347       }
 348
 349       if (inst->dst.file == GRF) {
 350          int size = virtual_grf_sizes[inst->dst.reg];
 351          spill_costs[inst->dst.reg] += size * loop_scale;
 352       }
 353
 354       switch (inst->opcode) {
 355
 356       case BRW_OPCODE_DO:
 357          loop_scale *= 10;
 358          break;
 359
 360       case BRW_OPCODE_WHILE:
 361          loop_scale /= 10;
 362          break;
 363
 364       case FS_OPCODE_SPILL:
 365          if (inst->src[0].file == GRF)
 366             no_spill[inst->src[0].reg] = true;
 367          break;
 368
 369       case FS_OPCODE_UNSPILL:
 370          if (inst->dst.file == GRF)
 371             no_spill[inst->dst.reg] = true;
 372          break;
 373       }
 374    }
 375
 376    for (int i = 0; i < this->virtual_grf_next; i++) {
 377       if (!no_spill[i])
 378          ra_set_node_spill_cost(g, i, spill_costs[i]);
 379    }
 380
 381    return ra_get_best_spill_node(g);
 382 }
 383
 384 void
 385 fs_visitor::spill_reg(int spill_reg)
 386 {
 387    int size = virtual_grf_sizes[spill_reg];
 388    unsigned int spill_offset = c->last_scratch;
 389    assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */
 390    c->last_scratch += size * REG_SIZE;
 391
 392    /* Generate spill/unspill instructions for the objects being
 393     * spilled.  Right now, we spill or unspill the whole thing to a
 394     * virtual grf of the same size.  For most instructions, though, we
 395     * could just spill/unspill the GRF being accessed.
 396     */
 397    foreach_iter(exec_list_iterator, iter, this->instructions) {
 398       fs_inst *inst = (fs_inst *)iter.get();
 399
 400       for (unsigned int i = 0; i < 3; i++) {
 401          if (inst->src[i].file == GRF &&
 402              inst->src[i].reg == spill_reg) {
 403             inst->src[i].reg = virtual_grf_alloc(size);
 404             emit_unspill(inst, inst->src[i], spill_offset);
 405          }
 406       }
 407
 408       if (inst->dst.file == GRF &&
 409           inst->dst.reg == spill_reg) {
 410          inst->dst.reg = virtual_grf_alloc(size);
 411
 412          /* Since we spill/unspill the whole thing even if we access
 413           * just a component, we may need to unspill before the
 414           * instruction we're spilling for.
 415           */
 416          if (size != 1 || inst->predicated) {
 417             emit_unspill(inst, inst->dst, spill_offset);
 418          }
 419
 420          fs_reg spill_src = inst->dst;
 421          spill_src.reg_offset = 0;
 422          spill_src.abs = false;
 423          spill_src.negate = false;
 424          spill_src.smear = -1;
 425
 426          for (int chan = 0; chan < size; chan++) {
 427             fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,
 428                                                        reg_null_f, spill_src);
 429             spill_src.reg_offset++;
 430             spill_inst->offset = spill_offset + chan * REG_SIZE;
 431             spill_inst->ir = inst->ir;
 432             spill_inst->annotation = inst->annotation;
 433             spill_inst->base_mrf = 14;
 434             spill_inst->mlen = 2; /* header, value */
 435             inst->insert_after(spill_inst);
 436          }
 437       }
 438    }
 439
 440    this->live_intervals_valid = false;
 441 }