2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
34 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
36 if (reg
->file
== GRF
) {
37 assert(reg
->reg_offset
>= 0);
38 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
44 fs_visitor::assign_regs_trivial()
46 int hw_reg_mapping
[this->virtual_grf_count
+ 1];
48 int reg_width
= dispatch_width
/ 8;
50 /* Note that compressed instructions require alignment to 2 registers. */
51 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
52 for (i
= 1; i
<= this->virtual_grf_count
; i
++) {
53 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
54 this->virtual_grf_sizes
[i
- 1]);
56 this->grf_used
= hw_reg_mapping
[this->virtual_grf_count
];
58 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
59 assign_reg(hw_reg_mapping
, &inst
->dst
);
60 for (i
= 0; i
< inst
->sources
; i
++) {
61 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
65 if (this->grf_used
>= max_grf
) {
66 fail("Ran out of regs on trivial allocator (%d/%d)\n",
67 this->grf_used
, max_grf
);
69 this->virtual_grf_count
= this->grf_used
;
75 brw_alloc_reg_set(struct intel_screen
*screen
, int reg_width
)
77 const struct brw_device_info
*devinfo
= screen
->devinfo
;
78 int base_reg_count
= BRW_MAX_GRF
;
79 int index
= reg_width
- 1;
81 /* The registers used to make up almost all values handled in the compiler
82 * are a scalar value occupying a single register (or 2 registers in the
83 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
84 * multiplying allocated register numbers by 2). Things that were
85 * aggregates of scalar values at the GLSL level were split to scalar
86 * values by split_virtual_grfs().
88 * However, texture SEND messages return a series of contiguous registers
89 * to write into. We currently always ask for 4 registers, but we may
90 * convert that to use less some day.
92 * Additionally, on gen5 we need aligned pairs of registers for the PLN
93 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
96 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
97 * and we add in '3' to make indexing the array easier for the common case
98 * (since we'll probably want it for texturing later).
100 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
101 * means that we may need any size up to the sampler message size limit (11
105 int class_sizes
[MAX_VGRF_SIZE
];
107 if (devinfo
->gen
>= 7) {
108 for (class_count
= 0; class_count
< MAX_VGRF_SIZE
; class_count
++)
109 class_sizes
[class_count
] = class_count
+ 1;
111 for (class_count
= 0; class_count
< 4; class_count
++)
112 class_sizes
[class_count
] = class_count
+ 1;
113 class_sizes
[class_count
++] = 8;
116 memset(screen
->wm_reg_sets
[index
].class_to_ra_reg_range
, 0,
117 sizeof(screen
->wm_reg_sets
[index
].class_to_ra_reg_range
));
118 int *class_to_ra_reg_range
= screen
->wm_reg_sets
[index
].class_to_ra_reg_range
;
120 /* Compute the total number of registers across all classes. */
121 int ra_reg_count
= 0;
122 for (int i
= 0; i
< class_count
; i
++) {
123 if (devinfo
->gen
<= 5 && reg_width
== 2) {
126 * In order to reduce the hardware complexity, the following
127 * rules and restrictions apply to the compressed instruction:
129 * * Operand Alignment Rule: With the exceptions listed below, a
130 * source/destination operand in general should be aligned to
131 * even 256-bit physical register with a region size equal to
132 * two 256-bit physical register
134 ra_reg_count
+= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
136 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
138 /* Mark the last register. We'll fill in the beginnings later. */
139 class_to_ra_reg_range
[class_sizes
[i
]] = ra_reg_count
;
142 /* Fill out the rest of the range markers */
143 for (int i
= 1; i
< 17; ++i
) {
144 if (class_to_ra_reg_range
[i
] == 0)
145 class_to_ra_reg_range
[i
] = class_to_ra_reg_range
[i
-1];
148 uint8_t *ra_reg_to_grf
= ralloc_array(screen
, uint8_t, ra_reg_count
);
149 struct ra_regs
*regs
= ra_alloc_reg_set(screen
, ra_reg_count
);
150 if (devinfo
->gen
>= 6)
151 ra_set_allocate_round_robin(regs
);
152 int *classes
= ralloc_array(screen
, int, class_count
);
153 int aligned_pairs_class
= -1;
155 /* Allocate space for q values. We allocate class_count + 1 because we
156 * want to leave room for the aligned pairs class if we have it. */
157 unsigned int **q_values
= ralloc_array(screen
, unsigned int *,
159 for (int i
= 0; i
< class_count
+ 1; ++i
)
160 q_values
[i
] = ralloc_array(q_values
, unsigned int, class_count
+ 1);
162 /* Now, add the registers to their classes, and add the conflicts
163 * between them and the base GRF registers (and also each other).
166 int pairs_base_reg
= 0;
167 int pairs_reg_count
= 0;
168 for (int i
= 0; i
< class_count
; i
++) {
170 if (devinfo
->gen
<= 5 && reg_width
== 2) {
171 class_reg_count
= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
173 /* See comment below. The only difference here is that we are
174 * dealing with pairs of registers instead of single registers.
175 * Registers of odd sizes simply get rounded up. */
176 for (int j
= 0; j
< class_count
; j
++)
177 q_values
[i
][j
] = (class_sizes
[i
] + 1) / 2 +
178 (class_sizes
[j
] + 1) / 2 - 1;
180 class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
182 /* From register_allocate.c:
184 * q(B,C) (indexed by C, B is this register class) in
185 * Runeson/Nyström paper. This is "how many registers of B could
186 * the worst choice register from C conflict with".
188 * If we just let the register allocation algorithm compute these
189 * values, is extremely expensive. However, since all of our
190 * registers are laid out, we can very easily compute them
191 * ourselves. View the register from C as fixed starting at GRF n
192 * somwhere in the middle, and the register from B as sliding back
193 * and forth. Then the first register to conflict from B is the
194 * one starting at n - class_size[B] + 1 and the last register to
195 * conflict will start at n + class_size[B] - 1. Therefore, the
196 * number of conflicts from B is class_size[B] + class_size[C] - 1.
198 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
199 * B | | | | | |n| --> | | | | | | |
200 * +-+-+-+-+-+-+ +-+-+-+-+-+-+
205 for (int j
= 0; j
< class_count
; j
++)
206 q_values
[i
][j
] = class_sizes
[i
] + class_sizes
[j
] - 1;
208 classes
[i
] = ra_alloc_reg_class(regs
);
210 /* Save this off for the aligned pair class at the end. */
211 if (class_sizes
[i
] == 2) {
212 pairs_base_reg
= reg
;
213 pairs_reg_count
= class_reg_count
;
216 if (devinfo
->gen
<= 5 && reg_width
== 2) {
217 for (int j
= 0; j
< class_reg_count
; j
++) {
218 ra_class_add_reg(regs
, classes
[i
], reg
);
220 ra_reg_to_grf
[reg
] = j
* 2;
222 for (int base_reg
= j
;
223 base_reg
< j
+ (class_sizes
[i
] + 1) / 2;
225 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
231 for (int j
= 0; j
< class_reg_count
; j
++) {
232 ra_class_add_reg(regs
, classes
[i
], reg
);
234 ra_reg_to_grf
[reg
] = j
;
236 for (int base_reg
= j
;
237 base_reg
< j
+ class_sizes
[i
];
239 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
246 assert(reg
== ra_reg_count
);
248 /* Add a special class for aligned pairs, which we'll put delta_x/y
249 * in on gen5 so that we can do PLN.
251 if (devinfo
->has_pln
&& reg_width
== 1 && devinfo
->gen
< 6) {
252 aligned_pairs_class
= ra_alloc_reg_class(regs
);
254 for (int i
= 0; i
< pairs_reg_count
; i
++) {
255 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
256 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
260 for (int i
= 0; i
< class_count
; i
++) {
261 /* These are a little counter-intuitive because the pair registers
262 * are required to be aligned while the register they are
263 * potentially interferring with are not. In the case where the
264 * size is even, the worst-case is that the register is
265 * odd-aligned. In the odd-size case, it doesn't matter.
267 q_values
[class_count
][i
] = class_sizes
[i
] / 2 + 1;
268 q_values
[i
][class_count
] = class_sizes
[i
] + 1;
270 q_values
[class_count
][class_count
] = 1;
273 ra_set_finalize(regs
, q_values
);
275 ralloc_free(q_values
);
277 screen
->wm_reg_sets
[index
].regs
= regs
;
278 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->wm_reg_sets
[index
].classes
); i
++)
279 screen
->wm_reg_sets
[index
].classes
[i
] = -1;
280 for (int i
= 0; i
< class_count
; i
++)
281 screen
->wm_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
282 screen
->wm_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
283 screen
->wm_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
287 brw_fs_alloc_reg_sets(struct intel_screen
*screen
)
289 brw_alloc_reg_set(screen
, 1);
290 brw_alloc_reg_set(screen
, 2);
294 count_to_loop_end(const bblock_t
*block
)
296 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
297 return block
->end_ip
;
300 /* Skip the first block, since we don't want to count the do the calling
303 for (block
= block
->next();
305 block
= block
->next()) {
306 if (block
->start()->opcode
== BRW_OPCODE_DO
)
308 if (block
->end()->opcode
== BRW_OPCODE_WHILE
) {
311 return block
->end_ip
;
314 unreachable("not reached");
318 * Sets up interference between thread payload registers and the virtual GRFs
319 * to be allocated for program temporaries.
321 * We want to be able to reallocate the payload for our virtual GRFs, notably
322 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
325 * The layout of the payload registers is:
327 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
328 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
329 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
331 * And we have payload_node_count nodes covering these registers in order
332 * (note that in SIMD16, a node is two registers).
335 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
336 int payload_node_count
,
337 int first_payload_node
)
342 int payload_last_use_ip
[payload_node_count
];
343 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
345 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
346 switch (inst
->opcode
) {
350 /* Since payload regs are deffed only at the start of the shader
351 * execution, any uses of the payload within a loop mean the live
352 * interval extends to the end of the outermost loop. Find the ip of
356 loop_end_ip
= count_to_loop_end(block
);
358 case BRW_OPCODE_WHILE
:
367 use_ip
= loop_end_ip
;
371 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
372 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
373 * the start (see interp_reg()).
375 for (int i
= 0; i
< inst
->sources
; i
++) {
376 if (inst
->src
[i
].file
== HW_REG
&&
377 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
378 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
;
379 if (node_nr
>= payload_node_count
)
382 payload_last_use_ip
[node_nr
] = use_ip
;
386 /* Special case instructions which have extra implied registers used. */
387 switch (inst
->opcode
) {
388 case SHADER_OPCODE_URB_WRITE_SIMD8
:
389 case FS_OPCODE_FB_WRITE
:
390 /* We could omit this for the !inst->header_present case, except that
391 * the simulator apparently incorrectly reads from g0/g1 instead of
392 * sideband. It also really freaks out driver developers to see g0
393 * used in unusual places, so just always reserve it.
395 payload_last_use_ip
[0] = use_ip
;
396 payload_last_use_ip
[1] = use_ip
;
399 case FS_OPCODE_LINTERP
:
400 /* On gen6+ in SIMD16, there are 4 adjacent registers used by
401 * PLN's sourcing of the deltas, while we list only the first one
402 * in the arguments. Pre-gen6, the deltas are computed in normal
407 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
408 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
409 BRW_GENERAL_REGISTER_FILE
) {
410 for (int i
= 1; i
< 4; ++i
) {
411 int node
= inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
+ i
;
412 assert(node
< payload_node_count
);
413 payload_last_use_ip
[node
] = use_ip
;
426 for (int i
= 0; i
< payload_node_count
; i
++) {
427 /* Mark the payload node as interfering with any virtual grf that is
428 * live between the start of the program and our last use of the payload
431 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
432 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
433 * in order to not have to worry about the uniform issue described in
434 * calculate_live_intervals().
436 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
437 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
442 for (int i
= 0; i
< payload_node_count
; i
++) {
443 /* Mark each payload node as being allocated to its physical register.
445 * The alternative would be to have per-physical-register classes, which
446 * would just be silly.
448 if (brw
->intelScreen
->devinfo
->gen
<= 5 && dispatch_width
== 16) {
449 /* We have to divide by 2 here because we only have even numbered
450 * registers. Some of the payload registers will be odd, but
451 * that's ok because their physical register numbers have already
452 * been assigned. The only thing this is used for is interference.
454 ra_set_node_reg(g
, first_payload_node
+ i
, i
/ 2);
456 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
462 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
464 * This is used in assign_regs() to decide which of the GRFs that we use as
465 * MRFs on gen7 get normally register allocated, and in register spilling to
466 * see if we can actually use MRFs to do spills without overwriting normal MRF
470 fs_visitor::get_used_mrfs(bool *mrf_used
)
472 int reg_width
= dispatch_width
/ 8;
474 memset(mrf_used
, 0, BRW_MAX_MRF
* sizeof(bool));
476 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
477 if (inst
->dst
.file
== MRF
) {
478 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
479 mrf_used
[reg
] = true;
480 if (reg_width
== 2) {
481 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
482 mrf_used
[reg
+ 4] = true;
484 mrf_used
[reg
+ 1] = true;
489 if (inst
->mlen
> 0) {
490 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
491 mrf_used
[inst
->base_mrf
+ i
] = true;
498 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
499 * messages (treated as MRFs in code generation).
502 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
504 bool mrf_used
[BRW_MAX_MRF
];
505 get_used_mrfs(mrf_used
);
507 for (int i
= 0; i
< BRW_MAX_MRF
; i
++) {
508 /* Mark each MRF reg node as being allocated to its physical register.
510 * The alternative would be to have per-physical-register classes, which
511 * would just be silly.
513 ra_set_node_reg(g
, first_mrf_node
+ i
, GEN7_MRF_HACK_START
+ i
);
515 /* Since we don't have any live/dead analysis on the MRFs, just mark all
516 * that are used as conflicting with all virtual GRFs.
519 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
520 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
527 is_last_send(fs_inst
*inst
)
529 switch (inst
->opcode
) {
530 case SHADER_OPCODE_URB_WRITE_SIMD8
:
531 case FS_OPCODE_FB_WRITE
:
540 fs_visitor::assign_regs(bool allow_spilling
)
542 struct intel_screen
*screen
= brw
->intelScreen
;
543 /* Most of this allocation was written for a reg_width of 1
544 * (dispatch_width == 8). In extending to SIMD16, the code was
545 * left in place and it was converted to have the hardware
546 * registers it's allocating be contiguous physical pairs of regs
547 * for reg_width == 2.
549 int reg_width
= dispatch_width
/ 8;
550 int hw_reg_mapping
[this->virtual_grf_count
];
551 int payload_node_count
= ALIGN(this->first_non_payload_grf
, reg_width
);
552 int rsi
= reg_width
- 1; /* Which screen->wm_reg_sets[] to use */
553 calculate_live_intervals();
555 int node_count
= this->virtual_grf_count
;
556 int first_payload_node
= node_count
;
557 node_count
+= payload_node_count
;
558 int first_mrf_hack_node
= node_count
;
560 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
562 ra_alloc_interference_graph(screen
->wm_reg_sets
[rsi
].regs
, node_count
);
564 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
565 unsigned size
= this->virtual_grf_sizes
[i
];
568 assert(size
<= ARRAY_SIZE(screen
->wm_reg_sets
[rsi
].classes
) &&
569 "Register allocation relies on split_virtual_grfs()");
570 c
= screen
->wm_reg_sets
[rsi
].classes
[size
- 1];
572 /* Special case: on pre-GEN6 hardware that supports PLN, the
573 * second operand of a PLN instruction needs to be an
574 * even-numbered register, so we have a special register class
575 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
576 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
577 * second operand of a PLN instruction (since it doesn't support
578 * any other interpolation modes). So all we need to do is find
579 * that register and set it to the appropriate class.
581 if (screen
->wm_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
582 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
&&
583 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
584 c
= screen
->wm_reg_sets
[rsi
].aligned_pairs_class
;
587 ra_set_node_class(g
, i
, c
);
589 for (int j
= 0; j
< i
; j
++) {
590 if (virtual_grf_interferes(i
, j
)) {
591 ra_add_node_interference(g
, i
, j
);
596 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
598 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
600 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
601 /* When we do send-from-GRF for FB writes, we need to ensure that
602 * the last write instruction sends from a high register. This is
603 * because the vertex fetcher wants to start filling the low
604 * payload registers while the pixel data port is still working on
605 * writing out the memory. If we don't do this, we get rendering
608 * We could just do "something high". Instead, we just pick the
609 * highest register that works.
611 if (is_last_send(inst
)) {
612 int size
= virtual_grf_sizes
[inst
->src
[0].reg
];
613 int reg
= screen
->wm_reg_sets
[rsi
].class_to_ra_reg_range
[size
] - 1;
614 ra_set_node_reg(g
, inst
->src
[0].reg
, reg
);
620 if (dispatch_width
> 8) {
621 /* In 16-wide dispatch we have an issue where a compressed
622 * instruction is actually two instructions executed simultaneiously.
623 * It's actually ok to have the source and destination registers be
624 * the same. In this case, each instruction over-writes its own
625 * source and there's no problem. The real problem here is if the
626 * source and destination registers are off by one. Then you can end
627 * up in a scenario where the first instruction over-writes the
628 * source of the second instruction. Since the compiler doesn't know
629 * about this level of granularity, we simply make the source and
630 * destination interfere.
632 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
633 if (inst
->dst
.file
!= GRF
)
636 for (int i
= 0; i
< inst
->sources
; ++i
) {
637 if (inst
->src
[i
].file
== GRF
) {
638 ra_add_node_interference(g
, inst
->dst
.reg
, inst
->src
[i
].reg
);
644 /* Debug of register spilling: Go spill everything. */
646 int reg
= choose_spill_reg(g
);
655 if (!ra_allocate(g
)) {
656 /* Failed to allocate registers. Spill a reg, and the caller will
657 * loop back into here to try again.
659 int reg
= choose_spill_reg(g
);
662 fail("no register to spill:\n");
663 dump_instructions(NULL
);
664 } else if (allow_spilling
) {
673 /* Get the chosen virtual registers for each node, and map virtual
674 * regs in the register classes back down to real hardware reg
677 this->grf_used
= payload_node_count
;
678 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
679 int reg
= ra_get_node_reg(g
, i
);
681 hw_reg_mapping
[i
] = screen
->wm_reg_sets
[rsi
].ra_reg_to_grf
[reg
];
682 this->grf_used
= MAX2(this->grf_used
,
683 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
]);
686 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
687 assign_reg(hw_reg_mapping
, &inst
->dst
);
688 for (int i
= 0; i
< inst
->sources
; i
++) {
689 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
693 this->virtual_grf_count
= this->grf_used
;
701 fs_visitor::emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg dst
,
702 uint32_t spill_offset
, int count
)
705 if (dispatch_width
== 16 && count
% 2 == 0) {
710 for (int i
= 0; i
< count
/ reg_size
; i
++) {
711 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
712 bool gen7_read
= brw
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
714 fs_inst
*unspill_inst
=
715 new(mem_ctx
) fs_inst(gen7_read
?
716 SHADER_OPCODE_GEN7_SCRATCH_READ
:
717 SHADER_OPCODE_GEN4_SCRATCH_READ
,
719 unspill_inst
->offset
= spill_offset
;
720 unspill_inst
->ir
= inst
->ir
;
721 unspill_inst
->annotation
= inst
->annotation
;
722 unspill_inst
->regs_written
= reg_size
;
725 unspill_inst
->base_mrf
= 14;
726 unspill_inst
->mlen
= 1; /* header contains offset */
728 inst
->insert_before(block
, unspill_inst
);
730 dst
.reg_offset
+= reg_size
;
731 spill_offset
+= reg_size
* REG_SIZE
;
736 fs_visitor::emit_spill(bblock_t
*block
, fs_inst
*inst
, fs_reg src
,
737 uint32_t spill_offset
, int count
)
740 int spill_base_mrf
= 14;
741 if (dispatch_width
== 16 && count
% 2 == 0) {
746 for (int i
= 0; i
< count
/ reg_size
; i
++) {
747 fs_inst
*spill_inst
=
748 new(mem_ctx
) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
749 reg_size
* 8, reg_null_f
, src
);
750 src
.reg_offset
+= reg_size
;
751 spill_inst
->offset
= spill_offset
+ i
* reg_size
* REG_SIZE
;
752 spill_inst
->ir
= inst
->ir
;
753 spill_inst
->annotation
= inst
->annotation
;
754 spill_inst
->mlen
= 1 + reg_size
; /* header, value */
755 spill_inst
->base_mrf
= spill_base_mrf
;
756 inst
->insert_after(block
, spill_inst
);
761 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
763 float loop_scale
= 1.0;
764 float spill_costs
[this->virtual_grf_count
];
765 bool no_spill
[this->virtual_grf_count
];
767 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
768 spill_costs
[i
] = 0.0;
772 /* Calculate costs for spilling nodes. Call it a cost of 1 per
773 * spill/unspill we'll have to do, and guess that the insides of
774 * loops run 10 times.
776 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
777 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
778 if (inst
->src
[i
].file
== GRF
) {
779 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
781 /* Register spilling logic assumes full-width registers; smeared
782 * registers have a width of 1 so if we try to spill them we'll
783 * generate invalid assembly. This shouldn't be a problem because
784 * smeared registers are only used as short-term temporaries when
785 * loading pull constants, so spilling them is unlikely to reduce
786 * register pressure anyhow.
788 if (!inst
->src
[i
].is_contiguous()) {
789 no_spill
[inst
->src
[i
].reg
] = true;
794 if (inst
->dst
.file
== GRF
) {
795 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
797 if (!inst
->dst
.is_contiguous()) {
798 no_spill
[inst
->dst
.reg
] = true;
802 switch (inst
->opcode
) {
808 case BRW_OPCODE_WHILE
:
812 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
813 if (inst
->src
[0].file
== GRF
)
814 no_spill
[inst
->src
[0].reg
] = true;
817 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
818 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
819 if (inst
->dst
.file
== GRF
)
820 no_spill
[inst
->dst
.reg
] = true;
828 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
830 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
833 return ra_get_best_spill_node(g
);
837 fs_visitor::spill_reg(int spill_reg
)
839 int size
= virtual_grf_sizes
[spill_reg
];
840 unsigned int spill_offset
= last_scratch
;
841 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
842 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
844 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
845 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
846 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
847 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
848 * depth), starting from m1. In summary: We may not be able to spill in
849 * SIMD16 mode, because we'd stomp the FB writes.
851 if (!spilled_any_registers
) {
852 bool mrf_used
[BRW_MAX_MRF
];
853 get_used_mrfs(mrf_used
);
855 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF
; i
++) {
857 fail("Register spilling not supported with m%d used", i
);
862 spilled_any_registers
= true;
865 last_scratch
+= size
* REG_SIZE
;
867 /* Generate spill/unspill instructions for the objects being
868 * spilled. Right now, we spill or unspill the whole thing to a
869 * virtual grf of the same size. For most instructions, though, we
870 * could just spill/unspill the GRF being accessed.
872 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
873 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
874 if (inst
->src
[i
].file
== GRF
&&
875 inst
->src
[i
].reg
== spill_reg
) {
876 int regs_read
= inst
->regs_read(this, i
);
877 int subset_spill_offset
= (spill_offset
+
878 REG_SIZE
* inst
->src
[i
].reg_offset
);
879 fs_reg
unspill_dst(GRF
, virtual_grf_alloc(regs_read
));
881 inst
->src
[i
].reg
= unspill_dst
.reg
;
882 inst
->src
[i
].reg_offset
= 0;
884 emit_unspill(block
, inst
, unspill_dst
, subset_spill_offset
,
889 if (inst
->dst
.file
== GRF
&&
890 inst
->dst
.reg
== spill_reg
) {
891 int subset_spill_offset
= (spill_offset
+
892 REG_SIZE
* inst
->dst
.reg_offset
);
893 fs_reg
spill_src(GRF
, virtual_grf_alloc(inst
->regs_written
));
895 inst
->dst
.reg
= spill_src
.reg
;
896 inst
->dst
.reg_offset
= 0;
898 /* If we're immediately spilling the register, we should not use
899 * destination dependency hints. Doing so will cause the GPU do
900 * try to read and write the register at the same time and may
903 inst
->no_dd_clear
= false;
904 inst
->no_dd_check
= false;
906 /* If our write is going to affect just part of the
907 * inst->regs_written(), then we need to unspill the destination
908 * since we write back out all of the regs_written().
910 if (inst
->is_partial_write())
911 emit_unspill(block
, inst
, spill_src
, subset_spill_offset
,
914 emit_spill(block
, inst
, spill_src
, subset_spill_offset
,
919 invalidate_live_intervals();