2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
34 assign_reg(int *reg_hw_locations
, fs_reg
*reg
, int reg_width
)
36 if (reg
->file
== GRF
) {
37 assert(reg
->reg_offset
>= 0);
38 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
* reg_width
;
44 fs_visitor::assign_regs_trivial()
46 int hw_reg_mapping
[this->virtual_grf_count
+ 1];
48 int reg_width
= dispatch_width
/ 8;
50 /* Note that compressed instructions require alignment to 2 registers. */
51 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
52 for (i
= 1; i
<= this->virtual_grf_count
; i
++) {
53 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
54 this->virtual_grf_sizes
[i
- 1] * reg_width
);
56 this->grf_used
= hw_reg_mapping
[this->virtual_grf_count
];
58 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
59 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
60 for (i
= 0; i
< inst
->sources
; i
++) {
61 assign_reg(hw_reg_mapping
, &inst
->src
[i
], reg_width
);
65 if (this->grf_used
>= max_grf
) {
66 fail("Ran out of regs on trivial allocator (%d/%d)\n",
67 this->grf_used
, max_grf
);
69 this->virtual_grf_count
= this->grf_used
;
75 brw_alloc_reg_set(struct intel_screen
*screen
, int reg_width
)
77 const struct brw_device_info
*devinfo
= screen
->devinfo
;
78 int base_reg_count
= BRW_MAX_GRF
/ reg_width
;
79 int index
= reg_width
- 1;
81 /* The registers used to make up almost all values handled in the compiler
82 * are a scalar value occupying a single register (or 2 registers in the
83 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
84 * multiplying allocated register numbers by 2). Things that were
85 * aggregates of scalar values at the GLSL level were split to scalar
86 * values by split_virtual_grfs().
88 * However, texture SEND messages return a series of contiguous registers
89 * to write into. We currently always ask for 4 registers, but we may
90 * convert that to use less some day.
92 * Additionally, on gen5 we need aligned pairs of registers for the PLN
93 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
96 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
97 * and we add in '3' to make indexing the array easier for the common case
98 * (since we'll probably want it for texturing later).
100 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
101 * means that we may need any size up to the sampler message size limit (11
105 int class_sizes
[BRW_MAX_MRF
];
107 if (devinfo
->gen
>= 7) {
108 for (class_count
= 0; class_count
< MAX_SAMPLER_MESSAGE_SIZE
;
110 class_sizes
[class_count
] = class_count
+ 1;
112 for (class_count
= 0; class_count
< 4; class_count
++)
113 class_sizes
[class_count
] = class_count
+ 1;
114 class_sizes
[class_count
++] = 8;
117 /* Compute the total number of registers across all classes. */
118 int ra_reg_count
= 0;
119 for (int i
= 0; i
< class_count
; i
++) {
120 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
123 uint8_t *ra_reg_to_grf
= ralloc_array(screen
, uint8_t, ra_reg_count
);
124 struct ra_regs
*regs
= ra_alloc_reg_set(screen
, ra_reg_count
);
125 if (devinfo
->gen
>= 6)
126 ra_set_allocate_round_robin(regs
);
127 int *classes
= ralloc_array(screen
, int, class_count
);
128 int aligned_pairs_class
= -1;
130 /* Now, add the registers to their classes, and add the conflicts
131 * between them and the base GRF registers (and also each other).
134 int pairs_base_reg
= 0;
135 int pairs_reg_count
= 0;
136 for (int i
= 0; i
< class_count
; i
++) {
137 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
138 classes
[i
] = ra_alloc_reg_class(regs
);
140 /* Save this off for the aligned pair class at the end. */
141 if (class_sizes
[i
] == 2) {
142 pairs_base_reg
= reg
;
143 pairs_reg_count
= class_reg_count
;
146 for (int j
= 0; j
< class_reg_count
; j
++) {
147 ra_class_add_reg(regs
, classes
[i
], reg
);
149 ra_reg_to_grf
[reg
] = j
;
151 for (int base_reg
= j
;
152 base_reg
< j
+ class_sizes
[i
];
154 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
160 assert(reg
== ra_reg_count
);
162 /* Add a special class for aligned pairs, which we'll put delta_x/y
163 * in on gen5 so that we can do PLN.
165 if (devinfo
->has_pln
&& reg_width
== 1 && devinfo
->gen
< 6) {
166 aligned_pairs_class
= ra_alloc_reg_class(regs
);
168 for (int i
= 0; i
< pairs_reg_count
; i
++) {
169 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
170 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
175 ra_set_finalize(regs
, NULL
);
177 screen
->wm_reg_sets
[index
].regs
= regs
;
178 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->wm_reg_sets
[index
].classes
); i
++)
179 screen
->wm_reg_sets
[index
].classes
[i
] = -1;
180 for (int i
= 0; i
< class_count
; i
++)
181 screen
->wm_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
182 screen
->wm_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
183 screen
->wm_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
187 brw_fs_alloc_reg_sets(struct intel_screen
*screen
)
189 brw_alloc_reg_set(screen
, 1);
190 brw_alloc_reg_set(screen
, 2);
194 count_to_loop_end(const bblock_t
*block
)
196 if (block
->end
->opcode
== BRW_OPCODE_WHILE
)
197 return block
->end_ip
;
200 /* Skip the first block, since we don't want to count the do the calling
203 for (block
= (bblock_t
*)block
->link
.next
;
205 block
= (bblock_t
*)block
->link
.next
) {
206 if (block
->start
->opcode
== BRW_OPCODE_DO
)
208 if (block
->end
->opcode
== BRW_OPCODE_WHILE
) {
211 return block
->end_ip
;
214 unreachable("not reached");
218 * Sets up interference between thread payload registers and the virtual GRFs
219 * to be allocated for program temporaries.
221 * We want to be able to reallocate the payload for our virtual GRFs, notably
222 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
225 * The layout of the payload registers is:
227 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
228 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
229 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
231 * And we have payload_node_count nodes covering these registers in order
232 * (note that in SIMD16, a node is two registers).
235 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
236 int payload_node_count
,
237 int first_payload_node
)
239 int reg_width
= dispatch_width
/ 8;
243 int payload_last_use_ip
[payload_node_count
];
244 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
246 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
247 switch (inst
->opcode
) {
251 /* Since payload regs are deffed only at the start of the shader
252 * execution, any uses of the payload within a loop mean the live
253 * interval extends to the end of the outermost loop. Find the ip of
257 loop_end_ip
= count_to_loop_end(block
);
259 case BRW_OPCODE_WHILE
:
268 use_ip
= loop_end_ip
;
272 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
273 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
274 * the start (see interp_reg()).
276 for (int i
= 0; i
< inst
->sources
; i
++) {
277 if (inst
->src
[i
].file
== HW_REG
&&
278 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
279 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
/ reg_width
;
280 if (node_nr
>= payload_node_count
)
283 payload_last_use_ip
[node_nr
] = use_ip
;
287 /* Special case instructions which have extra implied registers used. */
288 switch (inst
->opcode
) {
289 case FS_OPCODE_FB_WRITE
:
290 /* We could omit this for the !inst->header_present case, except that
291 * the simulator apparently incorrectly reads from g0/g1 instead of
292 * sideband. It also really freaks out driver developers to see g0
293 * used in unusual places, so just always reserve it.
295 payload_last_use_ip
[0 / reg_width
] = use_ip
;
296 payload_last_use_ip
[1 / reg_width
] = use_ip
;
299 case FS_OPCODE_LINTERP
:
300 /* On gen6+ in SIMD16, there are 4 adjacent registers (so 2 nodes)
301 * used by PLN's sourcing of the deltas, while we list only the first
302 * two in the arguments (1 node). Pre-gen6, the deltas are computed
307 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
308 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
309 BRW_GENERAL_REGISTER_FILE
) {
310 int sechalf_node
= (inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
/
312 assert(sechalf_node
< payload_node_count
);
313 payload_last_use_ip
[sechalf_node
] = use_ip
;
325 for (int i
= 0; i
< payload_node_count
; i
++) {
326 /* Mark the payload node as interfering with any virtual grf that is
327 * live between the start of the program and our last use of the payload
330 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
331 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
332 * in order to not have to worry about the uniform issue described in
333 * calculate_live_intervals().
335 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
336 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
341 for (int i
= 0; i
< payload_node_count
; i
++) {
342 /* Mark each payload node as being allocated to its physical register.
344 * The alternative would be to have per-physical-register classes, which
345 * would just be silly.
347 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
352 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
354 * This is used in assign_regs() to decide which of the GRFs that we use as
355 * MRFs on gen7 get normally register allocated, and in register spilling to
356 * see if we can actually use MRFs to do spills without overwriting normal MRF
360 fs_visitor::get_used_mrfs(bool *mrf_used
)
362 int reg_width
= dispatch_width
/ 8;
364 memset(mrf_used
, 0, BRW_MAX_MRF
* sizeof(bool));
366 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
367 if (inst
->dst
.file
== MRF
) {
368 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
369 mrf_used
[reg
] = true;
370 if (reg_width
== 2) {
371 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
372 mrf_used
[reg
+ 4] = true;
374 mrf_used
[reg
+ 1] = true;
379 if (inst
->mlen
> 0) {
380 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
381 mrf_used
[inst
->base_mrf
+ i
] = true;
388 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
389 * messages (treated as MRFs in code generation).
392 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
394 int reg_width
= dispatch_width
/ 8;
396 bool mrf_used
[BRW_MAX_MRF
];
397 get_used_mrfs(mrf_used
);
399 for (int i
= 0; i
< BRW_MAX_MRF
; i
++) {
400 /* Mark each MRF reg node as being allocated to its physical register.
402 * The alternative would be to have per-physical-register classes, which
403 * would just be silly.
405 ra_set_node_reg(g
, first_mrf_node
+ i
,
406 (GEN7_MRF_HACK_START
+ i
) / reg_width
);
408 /* Since we don't have any live/dead analysis on the MRFs, just mark all
409 * that are used as conflicting with all virtual GRFs.
412 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
413 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
420 fs_visitor::assign_regs(bool allow_spilling
)
422 struct intel_screen
*screen
= brw
->intelScreen
;
423 /* Most of this allocation was written for a reg_width of 1
424 * (dispatch_width == 8). In extending to SIMD16, the code was
425 * left in place and it was converted to have the hardware
426 * registers it's allocating be contiguous physical pairs of regs
427 * for reg_width == 2.
429 int reg_width
= dispatch_width
/ 8;
430 int hw_reg_mapping
[this->virtual_grf_count
];
431 int payload_node_count
= (ALIGN(this->first_non_payload_grf
, reg_width
) /
433 int rsi
= reg_width
- 1; /* Which screen->wm_reg_sets[] to use */
434 calculate_live_intervals();
436 int node_count
= this->virtual_grf_count
;
437 int first_payload_node
= node_count
;
438 node_count
+= payload_node_count
;
439 int first_mrf_hack_node
= node_count
;
441 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
442 struct ra_graph
*g
= ra_alloc_interference_graph(screen
->wm_reg_sets
[rsi
].regs
,
445 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
446 unsigned size
= this->virtual_grf_sizes
[i
];
449 assert(size
<= ARRAY_SIZE(screen
->wm_reg_sets
[rsi
].classes
) &&
450 "Register allocation relies on split_virtual_grfs()");
451 c
= screen
->wm_reg_sets
[rsi
].classes
[size
- 1];
453 /* Special case: on pre-GEN6 hardware that supports PLN, the
454 * second operand of a PLN instruction needs to be an
455 * even-numbered register, so we have a special register class
456 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
457 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
458 * second operand of a PLN instruction (since it doesn't support
459 * any other interpolation modes). So all we need to do is find
460 * that register and set it to the appropriate class.
462 if (screen
->wm_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
463 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
&&
464 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
465 c
= screen
->wm_reg_sets
[rsi
].aligned_pairs_class
;
468 ra_set_node_class(g
, i
, c
);
470 for (int j
= 0; j
< i
; j
++) {
471 if (virtual_grf_interferes(i
, j
)) {
472 ra_add_node_interference(g
, i
, j
);
477 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
479 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
481 /* Debug of register spilling: Go spill everything. */
483 int reg
= choose_spill_reg(g
);
492 if (!ra_allocate(g
)) {
493 /* Failed to allocate registers. Spill a reg, and the caller will
494 * loop back into here to try again.
496 int reg
= choose_spill_reg(g
);
499 fail("no register to spill:\n");
500 dump_instructions(NULL
);
501 } else if (allow_spilling
) {
510 /* Get the chosen virtual registers for each node, and map virtual
511 * regs in the register classes back down to real hardware reg
514 this->grf_used
= payload_node_count
* reg_width
;
515 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
516 int reg
= ra_get_node_reg(g
, i
);
518 hw_reg_mapping
[i
] = screen
->wm_reg_sets
[rsi
].ra_reg_to_grf
[reg
] * reg_width
;
519 this->grf_used
= MAX2(this->grf_used
,
520 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] *
524 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
525 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
526 for (int i
= 0; i
< inst
->sources
; i
++) {
527 assign_reg(hw_reg_mapping
, &inst
->src
[i
], reg_width
);
531 this->virtual_grf_count
= this->grf_used
;
539 fs_visitor::emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg dst
,
540 uint32_t spill_offset
, int count
)
542 for (int i
= 0; i
< count
; i
++) {
543 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
544 bool gen7_read
= brw
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
546 fs_inst
*unspill_inst
=
547 new(mem_ctx
) fs_inst(gen7_read
?
548 SHADER_OPCODE_GEN7_SCRATCH_READ
:
549 SHADER_OPCODE_GEN4_SCRATCH_READ
,
551 unspill_inst
->offset
= spill_offset
;
552 unspill_inst
->ir
= inst
->ir
;
553 unspill_inst
->annotation
= inst
->annotation
;
556 unspill_inst
->base_mrf
= 14;
557 unspill_inst
->mlen
= 1; /* header contains offset */
559 inst
->insert_before(block
, unspill_inst
);
562 spill_offset
+= dispatch_width
* sizeof(float);
567 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
569 float loop_scale
= 1.0;
570 float spill_costs
[this->virtual_grf_count
];
571 bool no_spill
[this->virtual_grf_count
];
573 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
574 spill_costs
[i
] = 0.0;
578 /* Calculate costs for spilling nodes. Call it a cost of 1 per
579 * spill/unspill we'll have to do, and guess that the insides of
580 * loops run 10 times.
582 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
583 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
584 if (inst
->src
[i
].file
== GRF
) {
585 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
587 /* Register spilling logic assumes full-width registers; smeared
588 * registers have a width of 1 so if we try to spill them we'll
589 * generate invalid assembly. This shouldn't be a problem because
590 * smeared registers are only used as short-term temporaries when
591 * loading pull constants, so spilling them is unlikely to reduce
592 * register pressure anyhow.
594 if (!inst
->src
[i
].is_contiguous()) {
595 no_spill
[inst
->src
[i
].reg
] = true;
600 if (inst
->dst
.file
== GRF
) {
601 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
603 if (!inst
->dst
.is_contiguous()) {
604 no_spill
[inst
->dst
.reg
] = true;
608 switch (inst
->opcode
) {
614 case BRW_OPCODE_WHILE
:
618 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
619 if (inst
->src
[0].file
== GRF
)
620 no_spill
[inst
->src
[0].reg
] = true;
623 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
624 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
625 if (inst
->dst
.file
== GRF
)
626 no_spill
[inst
->dst
.reg
] = true;
634 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
636 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
639 return ra_get_best_spill_node(g
);
643 fs_visitor::spill_reg(int spill_reg
)
645 int reg_size
= dispatch_width
* sizeof(float);
646 int size
= virtual_grf_sizes
[spill_reg
];
647 unsigned int spill_offset
= last_scratch
;
648 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
649 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
651 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
652 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
653 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
654 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
655 * depth), starting from m1. In summary: We may not be able to spill in
656 * SIMD16 mode, because we'd stomp the FB writes.
658 if (!spilled_any_registers
) {
659 bool mrf_used
[BRW_MAX_MRF
];
660 get_used_mrfs(mrf_used
);
662 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF
; i
++) {
664 fail("Register spilling not supported with m%d used", i
);
669 spilled_any_registers
= true;
672 last_scratch
+= size
* reg_size
;
674 /* Generate spill/unspill instructions for the objects being
675 * spilled. Right now, we spill or unspill the whole thing to a
676 * virtual grf of the same size. For most instructions, though, we
677 * could just spill/unspill the GRF being accessed.
679 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
680 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
681 if (inst
->src
[i
].file
== GRF
&&
682 inst
->src
[i
].reg
== spill_reg
) {
683 int regs_read
= inst
->regs_read(this, i
);
684 int subset_spill_offset
= (spill_offset
+
685 reg_size
* inst
->src
[i
].reg_offset
);
686 fs_reg
unspill_dst(GRF
, virtual_grf_alloc(regs_read
));
688 inst
->src
[i
].reg
= unspill_dst
.reg
;
689 inst
->src
[i
].reg_offset
= 0;
691 emit_unspill(block
, inst
, unspill_dst
, subset_spill_offset
,
696 if (inst
->dst
.file
== GRF
&&
697 inst
->dst
.reg
== spill_reg
) {
698 int subset_spill_offset
= (spill_offset
+
699 reg_size
* inst
->dst
.reg_offset
);
700 fs_reg
spill_src(GRF
, virtual_grf_alloc(inst
->regs_written
));
702 inst
->dst
.reg
= spill_src
.reg
;
703 inst
->dst
.reg_offset
= 0;
705 /* If our write is going to affect just part of the
706 * inst->regs_written(), then we need to unspill the destination
707 * since we write back out all of the regs_written().
709 if (inst
->predicate
|| inst
->force_uncompressed
||
710 inst
->force_sechalf
|| inst
->dst
.subreg_offset
) {
711 emit_unspill(block
, inst
, spill_src
, subset_spill_offset
,
715 for (int chan
= 0; chan
< inst
->regs_written
; chan
++) {
716 fs_inst
*spill_inst
=
717 new(mem_ctx
) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
718 reg_null_f
, spill_src
);
719 spill_src
.reg_offset
++;
720 spill_inst
->offset
= subset_spill_offset
+ chan
* reg_size
;
721 spill_inst
->ir
= inst
->ir
;
722 spill_inst
->annotation
= inst
->annotation
;
723 spill_inst
->mlen
= 1 + dispatch_width
/ 8; /* header, value */
724 spill_inst
->base_mrf
= spill_base_mrf
;
725 inst
->insert_after(block
, spill_inst
);
730 invalidate_live_intervals();