2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "glsl/glsl_types.h"
30 #include "glsl/ir_optimization.h"
33 assign_reg(int *reg_hw_locations
, fs_reg
*reg
, int reg_width
)
35 if (reg
->file
== GRF
) {
36 assert(reg
->reg_offset
>= 0);
37 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
* reg_width
;
43 fs_visitor::assign_regs_trivial()
45 int hw_reg_mapping
[this->virtual_grf_count
+ 1];
47 int reg_width
= dispatch_width
/ 8;
49 /* Note that compressed instructions require alignment to 2 registers. */
50 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
51 for (i
= 1; i
<= this->virtual_grf_count
; i
++) {
52 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
53 this->virtual_grf_sizes
[i
- 1] * reg_width
);
55 this->grf_used
= hw_reg_mapping
[this->virtual_grf_count
];
57 foreach_in_list(fs_inst
, inst
, &instructions
) {
58 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
59 for (i
= 0; i
< inst
->sources
; i
++) {
60 assign_reg(hw_reg_mapping
, &inst
->src
[i
], reg_width
);
64 if (this->grf_used
>= max_grf
) {
65 fail("Ran out of regs on trivial allocator (%d/%d)\n",
66 this->grf_used
, max_grf
);
68 this->virtual_grf_count
= this->grf_used
;
74 brw_alloc_reg_set(struct intel_screen
*screen
, int reg_width
)
76 const struct brw_device_info
*devinfo
= screen
->devinfo
;
77 int base_reg_count
= BRW_MAX_GRF
/ reg_width
;
78 int index
= reg_width
- 1;
80 /* The registers used to make up almost all values handled in the compiler
81 * are a scalar value occupying a single register (or 2 registers in the
82 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
83 * multiplying allocated register numbers by 2). Things that were
84 * aggregates of scalar values at the GLSL level were split to scalar
85 * values by split_virtual_grfs().
87 * However, texture SEND messages return a series of contiguous registers
88 * to write into. We currently always ask for 4 registers, but we may
89 * convert that to use less some day.
91 * Additionally, on gen5 we need aligned pairs of registers for the PLN
92 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
95 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
96 * and we add in '3' to make indexing the array easier for the common case
97 * (since we'll probably want it for texturing later).
99 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
100 * means that we may need any size up to the sampler message size limit (11
104 int class_sizes
[BRW_MAX_MRF
];
106 if (devinfo
->gen
>= 7) {
107 for (class_count
= 0; class_count
< MAX_SAMPLER_MESSAGE_SIZE
;
109 class_sizes
[class_count
] = class_count
+ 1;
111 for (class_count
= 0; class_count
< 4; class_count
++)
112 class_sizes
[class_count
] = class_count
+ 1;
113 class_sizes
[class_count
++] = 8;
116 /* Compute the total number of registers across all classes. */
117 int ra_reg_count
= 0;
118 for (int i
= 0; i
< class_count
; i
++) {
119 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
122 uint8_t *ra_reg_to_grf
= ralloc_array(screen
, uint8_t, ra_reg_count
);
123 struct ra_regs
*regs
= ra_alloc_reg_set(screen
, ra_reg_count
);
124 if (devinfo
->gen
>= 6)
125 ra_set_allocate_round_robin(regs
);
126 int *classes
= ralloc_array(screen
, int, class_count
);
127 int aligned_pairs_class
= -1;
129 /* Now, add the registers to their classes, and add the conflicts
130 * between them and the base GRF registers (and also each other).
133 int pairs_base_reg
= 0;
134 int pairs_reg_count
= 0;
135 for (int i
= 0; i
< class_count
; i
++) {
136 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
137 classes
[i
] = ra_alloc_reg_class(regs
);
139 /* Save this off for the aligned pair class at the end. */
140 if (class_sizes
[i
] == 2) {
141 pairs_base_reg
= reg
;
142 pairs_reg_count
= class_reg_count
;
145 for (int j
= 0; j
< class_reg_count
; j
++) {
146 ra_class_add_reg(regs
, classes
[i
], reg
);
148 ra_reg_to_grf
[reg
] = j
;
150 for (int base_reg
= j
;
151 base_reg
< j
+ class_sizes
[i
];
153 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
159 assert(reg
== ra_reg_count
);
161 /* Add a special class for aligned pairs, which we'll put delta_x/y
162 * in on gen5 so that we can do PLN.
164 if (devinfo
->has_pln
&& reg_width
== 1 && devinfo
->gen
< 6) {
165 aligned_pairs_class
= ra_alloc_reg_class(regs
);
167 for (int i
= 0; i
< pairs_reg_count
; i
++) {
168 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
169 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
174 ra_set_finalize(regs
, NULL
);
176 screen
->wm_reg_sets
[index
].regs
= regs
;
177 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->wm_reg_sets
[index
].classes
); i
++)
178 screen
->wm_reg_sets
[index
].classes
[i
] = -1;
179 for (int i
= 0; i
< class_count
; i
++)
180 screen
->wm_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
181 screen
->wm_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
182 screen
->wm_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
186 brw_fs_alloc_reg_sets(struct intel_screen
*screen
)
188 brw_alloc_reg_set(screen
, 1);
189 brw_alloc_reg_set(screen
, 2);
193 count_to_loop_end(fs_inst
*do_inst
)
197 for (fs_inst
*inst
= (fs_inst
*)do_inst
->next
;
199 inst
= (fs_inst
*)inst
->next
) {
200 switch (inst
->opcode
) {
204 case BRW_OPCODE_WHILE
:
216 * Sets up interference between thread payload registers and the virtual GRFs
217 * to be allocated for program temporaries.
219 * We want to be able to reallocate the payload for our virtual GRFs, notably
220 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
223 * The layout of the payload registers is:
225 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
226 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
227 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
229 * And we have payload_node_count nodes covering these registers in order
230 * (note that in SIMD16, a node is two registers).
233 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
234 int payload_node_count
,
235 int first_payload_node
)
237 int reg_width
= dispatch_width
/ 8;
241 int payload_last_use_ip
[payload_node_count
];
242 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
244 foreach_in_list(fs_inst
, inst
, &instructions
) {
245 switch (inst
->opcode
) {
249 /* Since payload regs are deffed only at the start of the shader
250 * execution, any uses of the payload within a loop mean the live
251 * interval extends to the end of the outermost loop. Find the ip of
255 loop_end_ip
= ip
+ count_to_loop_end(inst
);
257 case BRW_OPCODE_WHILE
:
266 use_ip
= loop_end_ip
;
270 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
271 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
272 * the start (see interp_reg()).
274 for (int i
= 0; i
< inst
->sources
; i
++) {
275 if (inst
->src
[i
].file
== HW_REG
&&
276 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
277 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
/ reg_width
;
278 if (node_nr
>= payload_node_count
)
281 payload_last_use_ip
[node_nr
] = use_ip
;
285 /* Special case instructions which have extra implied registers used. */
286 switch (inst
->opcode
) {
287 case FS_OPCODE_FB_WRITE
:
288 /* We could omit this for the !inst->header_present case, except that
289 * the simulator apparently incorrectly reads from g0/g1 instead of
290 * sideband. It also really freaks out driver developers to see g0
291 * used in unusual places, so just always reserve it.
293 payload_last_use_ip
[0 / reg_width
] = use_ip
;
294 payload_last_use_ip
[1 / reg_width
] = use_ip
;
297 case FS_OPCODE_LINTERP
:
298 /* On gen6+ in SIMD16, there are 4 adjacent registers (so 2 nodes)
299 * used by PLN's sourcing of the deltas, while we list only the first
300 * two in the arguments (1 node). Pre-gen6, the deltas are computed
305 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
306 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
307 BRW_GENERAL_REGISTER_FILE
) {
308 int sechalf_node
= (inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
/
310 assert(sechalf_node
< payload_node_count
);
311 payload_last_use_ip
[sechalf_node
] = use_ip
;
323 for (int i
= 0; i
< payload_node_count
; i
++) {
324 /* Mark the payload node as interfering with any virtual grf that is
325 * live between the start of the program and our last use of the payload
328 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
329 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
330 * in order to not have to worry about the uniform issue described in
331 * calculate_live_intervals().
333 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
334 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
339 for (int i
= 0; i
< payload_node_count
; i
++) {
340 /* Mark each payload node as being allocated to its physical register.
342 * The alternative would be to have per-physical-register classes, which
343 * would just be silly.
345 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
350 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
352 * This is used in assign_regs() to decide which of the GRFs that we use as
353 * MRFs on gen7 get normally register allocated, and in register spilling to
354 * see if we can actually use MRFs to do spills without overwriting normal MRF
358 fs_visitor::get_used_mrfs(bool *mrf_used
)
360 int reg_width
= dispatch_width
/ 8;
362 memset(mrf_used
, 0, BRW_MAX_MRF
* sizeof(bool));
364 foreach_in_list(fs_inst
, inst
, &instructions
) {
365 if (inst
->dst
.file
== MRF
) {
366 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
367 mrf_used
[reg
] = true;
368 if (reg_width
== 2) {
369 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
370 mrf_used
[reg
+ 4] = true;
372 mrf_used
[reg
+ 1] = true;
377 if (inst
->mlen
> 0) {
378 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
379 mrf_used
[inst
->base_mrf
+ i
] = true;
386 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
387 * messages (treated as MRFs in code generation).
390 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
392 int reg_width
= dispatch_width
/ 8;
394 bool mrf_used
[BRW_MAX_MRF
];
395 get_used_mrfs(mrf_used
);
397 for (int i
= 0; i
< BRW_MAX_MRF
; i
++) {
398 /* Mark each MRF reg node as being allocated to its physical register.
400 * The alternative would be to have per-physical-register classes, which
401 * would just be silly.
403 ra_set_node_reg(g
, first_mrf_node
+ i
,
404 (GEN7_MRF_HACK_START
+ i
) / reg_width
);
406 /* Since we don't have any live/dead analysis on the MRFs, just mark all
407 * that are used as conflicting with all virtual GRFs.
410 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
411 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
418 fs_visitor::assign_regs(bool allow_spilling
)
420 struct intel_screen
*screen
= brw
->intelScreen
;
421 /* Most of this allocation was written for a reg_width of 1
422 * (dispatch_width == 8). In extending to SIMD16, the code was
423 * left in place and it was converted to have the hardware
424 * registers it's allocating be contiguous physical pairs of regs
425 * for reg_width == 2.
427 int reg_width
= dispatch_width
/ 8;
428 int hw_reg_mapping
[this->virtual_grf_count
];
429 int payload_node_count
= (ALIGN(this->first_non_payload_grf
, reg_width
) /
431 int rsi
= reg_width
- 1; /* Which screen->wm_reg_sets[] to use */
432 calculate_live_intervals();
434 int node_count
= this->virtual_grf_count
;
435 int first_payload_node
= node_count
;
436 node_count
+= payload_node_count
;
437 int first_mrf_hack_node
= node_count
;
439 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
440 struct ra_graph
*g
= ra_alloc_interference_graph(screen
->wm_reg_sets
[rsi
].regs
,
443 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
444 unsigned size
= this->virtual_grf_sizes
[i
];
447 assert(size
<= ARRAY_SIZE(screen
->wm_reg_sets
[rsi
].classes
) &&
448 "Register allocation relies on split_virtual_grfs()");
449 c
= screen
->wm_reg_sets
[rsi
].classes
[size
- 1];
451 /* Special case: on pre-GEN6 hardware that supports PLN, the
452 * second operand of a PLN instruction needs to be an
453 * even-numbered register, so we have a special register class
454 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
455 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
456 * second operand of a PLN instruction (since it doesn't support
457 * any other interpolation modes). So all we need to do is find
458 * that register and set it to the appropriate class.
460 if (screen
->wm_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
461 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
462 c
= screen
->wm_reg_sets
[rsi
].aligned_pairs_class
;
465 ra_set_node_class(g
, i
, c
);
467 for (int j
= 0; j
< i
; j
++) {
468 if (virtual_grf_interferes(i
, j
)) {
469 ra_add_node_interference(g
, i
, j
);
474 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
476 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
478 /* Debug of register spilling: Go spill everything. */
480 int reg
= choose_spill_reg(g
);
489 if (!ra_allocate(g
)) {
490 /* Failed to allocate registers. Spill a reg, and the caller will
491 * loop back into here to try again.
493 int reg
= choose_spill_reg(g
);
496 fail("no register to spill:\n");
497 dump_instructions(NULL
);
498 } else if (allow_spilling
) {
507 /* Get the chosen virtual registers for each node, and map virtual
508 * regs in the register classes back down to real hardware reg
511 this->grf_used
= payload_node_count
* reg_width
;
512 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
513 int reg
= ra_get_node_reg(g
, i
);
515 hw_reg_mapping
[i
] = screen
->wm_reg_sets
[rsi
].ra_reg_to_grf
[reg
] * reg_width
;
516 this->grf_used
= MAX2(this->grf_used
,
517 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] *
521 foreach_in_list(fs_inst
, inst
, &instructions
) {
522 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
523 for (int i
= 0; i
< inst
->sources
; i
++) {
524 assign_reg(hw_reg_mapping
, &inst
->src
[i
], reg_width
);
528 this->virtual_grf_count
= this->grf_used
;
536 fs_visitor::emit_unspill(fs_inst
*inst
, fs_reg dst
, uint32_t spill_offset
,
539 for (int i
= 0; i
< count
; i
++) {
540 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
541 bool gen7_read
= brw
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
543 fs_inst
*unspill_inst
=
544 new(mem_ctx
) fs_inst(gen7_read
?
545 SHADER_OPCODE_GEN7_SCRATCH_READ
:
546 SHADER_OPCODE_GEN4_SCRATCH_READ
,
548 unspill_inst
->offset
= spill_offset
;
549 unspill_inst
->ir
= inst
->ir
;
550 unspill_inst
->annotation
= inst
->annotation
;
553 unspill_inst
->base_mrf
= 14;
554 unspill_inst
->mlen
= 1; /* header contains offset */
556 inst
->insert_before(unspill_inst
);
559 spill_offset
+= dispatch_width
* sizeof(float);
564 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
566 float loop_scale
= 1.0;
567 float spill_costs
[this->virtual_grf_count
];
568 bool no_spill
[this->virtual_grf_count
];
570 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
571 spill_costs
[i
] = 0.0;
575 /* Calculate costs for spilling nodes. Call it a cost of 1 per
576 * spill/unspill we'll have to do, and guess that the insides of
577 * loops run 10 times.
579 foreach_in_list(fs_inst
, inst
, &instructions
) {
580 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
581 if (inst
->src
[i
].file
== GRF
) {
582 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
584 /* Register spilling logic assumes full-width registers; smeared
585 * registers have a width of 1 so if we try to spill them we'll
586 * generate invalid assembly. This shouldn't be a problem because
587 * smeared registers are only used as short-term temporaries when
588 * loading pull constants, so spilling them is unlikely to reduce
589 * register pressure anyhow.
591 if (!inst
->src
[i
].is_contiguous()) {
592 no_spill
[inst
->src
[i
].reg
] = true;
597 if (inst
->dst
.file
== GRF
) {
598 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
600 if (!inst
->dst
.is_contiguous()) {
601 no_spill
[inst
->dst
.reg
] = true;
605 switch (inst
->opcode
) {
611 case BRW_OPCODE_WHILE
:
615 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
616 if (inst
->src
[0].file
== GRF
)
617 no_spill
[inst
->src
[0].reg
] = true;
620 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
621 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
622 if (inst
->dst
.file
== GRF
)
623 no_spill
[inst
->dst
.reg
] = true;
631 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
633 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
636 return ra_get_best_spill_node(g
);
640 fs_visitor::spill_reg(int spill_reg
)
642 int reg_size
= dispatch_width
* sizeof(float);
643 int size
= virtual_grf_sizes
[spill_reg
];
644 unsigned int spill_offset
= last_scratch
;
645 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
646 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
648 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
649 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
650 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
651 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
652 * depth), starting from m1. In summary: We may not be able to spill in
653 * SIMD16 mode, because we'd stomp the FB writes.
655 if (!spilled_any_registers
) {
656 bool mrf_used
[BRW_MAX_MRF
];
657 get_used_mrfs(mrf_used
);
659 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF
; i
++) {
661 fail("Register spilling not supported with m%d used", i
);
666 spilled_any_registers
= true;
669 last_scratch
+= size
* reg_size
;
671 /* Generate spill/unspill instructions for the objects being
672 * spilled. Right now, we spill or unspill the whole thing to a
673 * virtual grf of the same size. For most instructions, though, we
674 * could just spill/unspill the GRF being accessed.
676 foreach_in_list(fs_inst
, inst
, &instructions
) {
677 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
678 if (inst
->src
[i
].file
== GRF
&&
679 inst
->src
[i
].reg
== spill_reg
) {
680 int regs_read
= inst
->regs_read(this, i
);
681 int subset_spill_offset
= (spill_offset
+
682 reg_size
* inst
->src
[i
].reg_offset
);
683 fs_reg
unspill_dst(GRF
, virtual_grf_alloc(regs_read
));
685 inst
->src
[i
].reg
= unspill_dst
.reg
;
686 inst
->src
[i
].reg_offset
= 0;
688 emit_unspill(inst
, unspill_dst
, subset_spill_offset
, regs_read
);
692 if (inst
->dst
.file
== GRF
&&
693 inst
->dst
.reg
== spill_reg
) {
694 int subset_spill_offset
= (spill_offset
+
695 reg_size
* inst
->dst
.reg_offset
);
696 fs_reg
spill_src(GRF
, virtual_grf_alloc(inst
->regs_written
));
698 inst
->dst
.reg
= spill_src
.reg
;
699 inst
->dst
.reg_offset
= 0;
701 /* If our write is going to affect just part of the
702 * inst->regs_written(), then we need to unspill the destination
703 * since we write back out all of the regs_written().
705 if (inst
->predicate
|| inst
->force_uncompressed
||
706 inst
->force_sechalf
|| inst
->dst
.subreg_offset
) {
707 emit_unspill(inst
, spill_src
, subset_spill_offset
,
711 for (int chan
= 0; chan
< inst
->regs_written
; chan
++) {
712 fs_inst
*spill_inst
=
713 new(mem_ctx
) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
714 reg_null_f
, spill_src
);
715 spill_src
.reg_offset
++;
716 spill_inst
->offset
= subset_spill_offset
+ chan
* reg_size
;
717 spill_inst
->ir
= inst
->ir
;
718 spill_inst
->annotation
= inst
->annotation
;
719 spill_inst
->mlen
= 1 + dispatch_width
/ 8; /* header, value */
720 spill_inst
->base_mrf
= spill_base_mrf
;
721 inst
->insert_after(spill_inst
);
726 invalidate_live_intervals();