2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include "glsl/glsl_types.h"
30 #include "glsl/ir_optimization.h"
31 #include "glsl/ir_print_visitor.h"
34 assign_reg(int *reg_hw_locations
, fs_reg
*reg
, int reg_width
)
36 if (reg
->file
== GRF
) {
37 assert(reg
->reg_offset
>= 0);
38 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
* reg_width
;
44 fs_visitor::assign_regs_trivial()
46 int hw_reg_mapping
[this->virtual_grf_count
+ 1];
48 int reg_width
= dispatch_width
/ 8;
50 /* Note that compressed instructions require alignment to 2 registers. */
51 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
52 for (i
= 1; i
<= this->virtual_grf_count
; i
++) {
53 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
54 this->virtual_grf_sizes
[i
- 1] * reg_width
);
56 this->grf_used
= hw_reg_mapping
[this->virtual_grf_count
];
58 foreach_list(node
, &this->instructions
) {
59 fs_inst
*inst
= (fs_inst
*)node
;
61 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
62 assign_reg(hw_reg_mapping
, &inst
->src
[0], reg_width
);
63 assign_reg(hw_reg_mapping
, &inst
->src
[1], reg_width
);
64 assign_reg(hw_reg_mapping
, &inst
->src
[2], reg_width
);
67 if (this->grf_used
>= max_grf
) {
68 fail("Ran out of regs on trivial allocator (%d/%d)\n",
69 this->grf_used
, max_grf
);
75 brw_alloc_reg_set(struct brw_context
*brw
, int reg_width
)
77 struct intel_context
*intel
= &brw
->intel
;
78 int base_reg_count
= BRW_MAX_GRF
/ reg_width
;
79 int index
= reg_width
- 1;
81 /* The registers used to make up almost all values handled in the compiler
82 * are a scalar value occupying a single register (or 2 registers in the
83 * case of 16-wide, which is handled by dividing base_reg_count by 2 and
84 * multiplying allocated register numbers by 2). Things that were
85 * aggregates of scalar values at the GLSL level were split to scalar
86 * values by split_virtual_grfs().
88 * However, texture SEND messages return a series of contiguous registers.
89 * We currently always ask for 4 registers, but we may convert that to use
92 * Additionally, on gen5 we need aligned pairs of registers for the PLN
93 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
96 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
97 * and we add in '3' to make indexing the array easier for the common case
98 * (since we'll probably want it for texturing later).
100 const int class_count
= 5;
101 const int class_sizes
[class_count
] = {1, 2, 3, 4, 8};
103 /* Compute the total number of registers across all classes. */
104 int ra_reg_count
= 0;
105 for (int i
= 0; i
< class_count
; i
++) {
106 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
109 uint8_t *ra_reg_to_grf
= ralloc_array(brw
, uint8_t, ra_reg_count
);
110 struct ra_regs
*regs
= ra_alloc_reg_set(brw
, ra_reg_count
);
112 ra_set_allocate_round_robin(regs
);
113 int *classes
= ralloc_array(brw
, int, class_count
);
114 int aligned_pairs_class
= -1;
116 /* Now, add the registers to their classes, and add the conflicts
117 * between them and the base GRF registers (and also each other).
120 int pairs_base_reg
= 0;
121 int pairs_reg_count
= 0;
122 for (int i
= 0; i
< class_count
; i
++) {
123 int class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
124 classes
[i
] = ra_alloc_reg_class(regs
);
126 /* Save this off for the aligned pair class at the end. */
127 if (class_sizes
[i
] == 2) {
128 pairs_base_reg
= reg
;
129 pairs_reg_count
= class_reg_count
;
132 for (int j
= 0; j
< class_reg_count
; j
++) {
133 ra_class_add_reg(regs
, classes
[i
], reg
);
135 ra_reg_to_grf
[reg
] = j
;
137 for (int base_reg
= j
;
138 base_reg
< j
+ class_sizes
[i
];
140 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
146 assert(reg
== ra_reg_count
);
148 /* Add a special class for aligned pairs, which we'll put delta_x/y
149 * in on gen5 so that we can do PLN.
151 if (brw
->has_pln
&& reg_width
== 1 && intel
->gen
< 6) {
152 aligned_pairs_class
= ra_alloc_reg_class(regs
);
154 for (int i
= 0; i
< pairs_reg_count
; i
++) {
155 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
156 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
161 ra_set_finalize(regs
, NULL
);
163 brw
->wm
.reg_sets
[index
].regs
= regs
;
164 brw
->wm
.reg_sets
[index
].classes
= classes
;
165 brw
->wm
.reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
166 brw
->wm
.reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
170 brw_fs_alloc_reg_sets(struct brw_context
*brw
)
172 brw_alloc_reg_set(brw
, 1);
173 brw_alloc_reg_set(brw
, 2);
177 count_to_loop_end(fs_inst
*do_inst
)
181 for (fs_inst
*inst
= (fs_inst
*)do_inst
->next
;
183 inst
= (fs_inst
*)inst
->next
) {
184 switch (inst
->opcode
) {
188 case BRW_OPCODE_WHILE
:
200 * Sets up interference between thread payload registers and the virtual GRFs
201 * to be allocated for program temporaries.
203 * We want to be able to reallocate the payload for our virtual GRFs, notably
204 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
207 * The layout of the payload registers is:
209 * 0..nr_payload_regs-1: fixed function setup (including bary coordinates).
210 * nr_payload_regs..nr_payload_regs+curb_read_lengh-1: uniform data
211 * nr_payload_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
213 * And we have payload_node_count nodes covering these registers in order
214 * (note that in 16-wide, a node is two registers).
217 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
218 int payload_node_count
,
219 int first_payload_node
)
221 int reg_width
= dispatch_width
/ 8;
225 int payload_last_use_ip
[payload_node_count
];
226 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
228 foreach_list(node
, &this->instructions
) {
229 fs_inst
*inst
= (fs_inst
*)node
;
231 switch (inst
->opcode
) {
235 /* Since payload regs are deffed only at the start of the shader
236 * execution, any uses of the payload within a loop mean the live
237 * interval extends to the end of the outermost loop. Find the ip of
241 loop_end_ip
= ip
+ count_to_loop_end(inst
);
243 case BRW_OPCODE_WHILE
:
252 use_ip
= loop_end_ip
;
256 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
257 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
258 * the start (see interp_reg()).
260 for (int i
= 0; i
< 3; i
++) {
261 if (inst
->src
[i
].file
== FIXED_HW_REG
&&
262 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
263 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
/ reg_width
;
264 if (node_nr
>= payload_node_count
)
267 payload_last_use_ip
[node_nr
] = use_ip
;
271 /* Special case instructions which have extra implied registers used. */
272 switch (inst
->opcode
) {
273 case FS_OPCODE_FB_WRITE
:
274 /* We could omit this for the !inst->header_present case, except that
275 * the simulator apparently incorrectly reads from g0/g1 instead of
276 * sideband. It also really freaks out driver developers to see g0
277 * used in unusual places, so just always reserve it.
279 payload_last_use_ip
[0 / reg_width
] = use_ip
;
280 payload_last_use_ip
[1 / reg_width
] = use_ip
;
283 case FS_OPCODE_LINTERP
:
284 /* On gen6+ in 16-wide, there are 4 adjacent registers (so 2 nodes)
285 * used by PLN's sourcing of the deltas, while we list only the first
286 * two in the arguments (1 node). Pre-gen6, the deltas are computed
289 if (intel
->gen
>= 6) {
291 if (inst
->src
[delta_x_arg
].file
== FIXED_HW_REG
&&
292 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
293 BRW_GENERAL_REGISTER_FILE
) {
294 int sechalf_node
= (inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
/
296 assert(sechalf_node
< payload_node_count
);
297 payload_last_use_ip
[sechalf_node
] = use_ip
;
309 for (int i
= 0; i
< payload_node_count
; i
++) {
310 /* Mark the payload node as interfering with any virtual grf that is
311 * live between the start of the program and our last use of the payload
314 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
315 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
316 * in order to not have to worry about the uniform issue described in
317 * calculate_live_intervals().
319 if (this->virtual_grf_def
[j
] <= payload_last_use_ip
[i
] ||
320 this->virtual_grf_use
[j
] <= payload_last_use_ip
[i
]) {
321 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
326 for (int i
= 0; i
< payload_node_count
; i
++) {
327 /* Mark each payload node as being allocated to its physical register.
329 * The alternative would be to have per-physical-register classes, which
330 * would just be silly.
332 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
337 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
338 * messages (treated as MRFs in code generation).
341 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
343 int mrf_count
= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
344 int reg_width
= dispatch_width
/ 8;
346 /* Identify all the MRFs used in the program. */
347 bool mrf_used
[mrf_count
];
348 memset(mrf_used
, 0, sizeof(mrf_used
));
349 foreach_list(node
, &this->instructions
) {
350 fs_inst
*inst
= (fs_inst
*)node
;
352 if (inst
->dst
.file
== MRF
) {
353 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
354 mrf_used
[reg
] = true;
355 if (reg_width
== 2) {
356 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
357 mrf_used
[reg
+ 4] = true;
359 mrf_used
[reg
+ 1] = true;
364 if (inst
->mlen
> 0) {
365 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
366 mrf_used
[inst
->base_mrf
+ i
] = true;
371 for (int i
= 0; i
< mrf_count
; i
++) {
372 /* Mark each payload reg node as being allocated to its physical register.
374 * The alternative would be to have per-physical-register classes, which
375 * would just be silly.
377 ra_set_node_reg(g
, first_mrf_node
+ i
,
378 (GEN7_MRF_HACK_START
+ i
) / reg_width
);
380 /* Since we don't have any live/dead analysis on the MRFs, just mark all
381 * that are used as conflicting with all virtual GRFs.
384 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
385 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
392 fs_visitor::assign_regs()
394 /* Most of this allocation was written for a reg_width of 1
395 * (dispatch_width == 8). In extending to 16-wide, the code was
396 * left in place and it was converted to have the hardware
397 * registers it's allocating be contiguous physical pairs of regs
398 * for reg_width == 2.
400 int reg_width
= dispatch_width
/ 8;
401 int hw_reg_mapping
[this->virtual_grf_count
];
402 int payload_node_count
= (ALIGN(this->first_non_payload_grf
, reg_width
) /
404 int rsi
= reg_width
- 1; /* Which brw->wm.reg_sets[] to use */
405 calculate_live_intervals();
407 int node_count
= this->virtual_grf_count
;
408 int first_payload_node
= node_count
;
409 node_count
+= payload_node_count
;
410 int first_mrf_hack_node
= node_count
;
412 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
413 struct ra_graph
*g
= ra_alloc_interference_graph(brw
->wm
.reg_sets
[rsi
].regs
,
416 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
417 int size
= this->virtual_grf_sizes
[i
];
425 "Register allocation relies on split_virtual_grfs()");
426 c
= brw
->wm
.reg_sets
[rsi
].classes
[size
- 1];
429 /* Special case: on pre-GEN6 hardware that supports PLN, the
430 * second operand of a PLN instruction needs to be an
431 * even-numbered register, so we have a special register class
432 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
433 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
434 * second operand of a PLN instruction (since it doesn't support
435 * any other interpolation modes). So all we need to do is find
436 * that register and set it to the appropriate class.
438 if (brw
->wm
.reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
439 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
440 c
= brw
->wm
.reg_sets
[rsi
].aligned_pairs_class
;
443 ra_set_node_class(g
, i
, c
);
445 for (int j
= 0; j
< i
; j
++) {
446 if (virtual_grf_interferes(i
, j
)) {
447 ra_add_node_interference(g
, i
, j
);
452 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
454 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
456 if (!ra_allocate_no_spills(g
)) {
457 /* Failed to allocate registers. Spill a reg, and the caller will
458 * loop back into here to try again.
460 int reg
= choose_spill_reg(g
);
463 fail("no register to spill\n");
464 } else if (dispatch_width
== 16) {
465 fail("Failure to register allocate. Reduce number of live scalar "
466 "values to avoid this.");
477 /* Get the chosen virtual registers for each node, and map virtual
478 * regs in the register classes back down to real hardware reg
481 this->grf_used
= payload_node_count
* reg_width
;
482 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
483 int reg
= ra_get_node_reg(g
, i
);
485 hw_reg_mapping
[i
] = brw
->wm
.reg_sets
[rsi
].ra_reg_to_grf
[reg
] * reg_width
;
486 this->grf_used
= MAX2(this->grf_used
,
487 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] *
491 foreach_list(node
, &this->instructions
) {
492 fs_inst
*inst
= (fs_inst
*)node
;
494 assign_reg(hw_reg_mapping
, &inst
->dst
, reg_width
);
495 assign_reg(hw_reg_mapping
, &inst
->src
[0], reg_width
);
496 assign_reg(hw_reg_mapping
, &inst
->src
[1], reg_width
);
497 assign_reg(hw_reg_mapping
, &inst
->src
[2], reg_width
);
506 fs_visitor::emit_unspill(fs_inst
*inst
, fs_reg dst
, uint32_t spill_offset
)
508 fs_inst
*unspill_inst
= new(mem_ctx
) fs_inst(FS_OPCODE_UNSPILL
, dst
);
509 unspill_inst
->offset
= spill_offset
;
510 unspill_inst
->ir
= inst
->ir
;
511 unspill_inst
->annotation
= inst
->annotation
;
513 /* Choose a MRF that won't conflict with an MRF that's live across the
514 * spill. Nothing else will make it up to MRF 14/15.
516 unspill_inst
->base_mrf
= 14;
517 unspill_inst
->mlen
= 1; /* header contains offset */
518 inst
->insert_before(unspill_inst
);
522 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
524 float loop_scale
= 1.0;
525 float spill_costs
[this->virtual_grf_count
];
526 bool no_spill
[this->virtual_grf_count
];
528 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
529 spill_costs
[i
] = 0.0;
533 /* Calculate costs for spilling nodes. Call it a cost of 1 per
534 * spill/unspill we'll have to do, and guess that the insides of
535 * loops run 10 times.
537 foreach_list(node
, &this->instructions
) {
538 fs_inst
*inst
= (fs_inst
*)node
;
540 for (unsigned int i
= 0; i
< 3; i
++) {
541 if (inst
->src
[i
].file
== GRF
) {
542 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
544 /* Register spilling logic assumes full-width registers; smeared
545 * registers have a width of 1 so if we try to spill them we'll
546 * generate invalid assembly. This shouldn't be a problem because
547 * smeared registers are only used as short-term temporaries when
548 * loading pull constants, so spilling them is unlikely to reduce
549 * register pressure anyhow.
551 if (inst
->src
[i
].smear
>= 0) {
552 no_spill
[inst
->src
[i
].reg
] = true;
557 if (inst
->dst
.file
== GRF
) {
558 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
560 if (inst
->dst
.smear
>= 0) {
561 no_spill
[inst
->dst
.reg
] = true;
565 switch (inst
->opcode
) {
571 case BRW_OPCODE_WHILE
:
575 case FS_OPCODE_SPILL
:
576 if (inst
->src
[0].file
== GRF
)
577 no_spill
[inst
->src
[0].reg
] = true;
580 case FS_OPCODE_UNSPILL
:
581 if (inst
->dst
.file
== GRF
)
582 no_spill
[inst
->dst
.reg
] = true;
590 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
592 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
595 return ra_get_best_spill_node(g
);
599 fs_visitor::spill_reg(int spill_reg
)
601 int size
= virtual_grf_sizes
[spill_reg
];
602 unsigned int spill_offset
= c
->last_scratch
;
603 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
604 c
->last_scratch
+= size
* REG_SIZE
;
606 /* Generate spill/unspill instructions for the objects being
607 * spilled. Right now, we spill or unspill the whole thing to a
608 * virtual grf of the same size. For most instructions, though, we
609 * could just spill/unspill the GRF being accessed.
611 foreach_list(node
, &this->instructions
) {
612 fs_inst
*inst
= (fs_inst
*)node
;
614 for (unsigned int i
= 0; i
< 3; i
++) {
615 if (inst
->src
[i
].file
== GRF
&&
616 inst
->src
[i
].reg
== spill_reg
) {
617 inst
->src
[i
].reg
= virtual_grf_alloc(1);
618 emit_unspill(inst
, inst
->src
[i
],
619 spill_offset
+ REG_SIZE
* inst
->src
[i
].reg_offset
);
623 if (inst
->dst
.file
== GRF
&&
624 inst
->dst
.reg
== spill_reg
) {
625 int subset_spill_offset
= (spill_offset
+
626 REG_SIZE
* inst
->dst
.reg_offset
);
627 inst
->dst
.reg
= virtual_grf_alloc(inst
->regs_written
);
628 inst
->dst
.reg_offset
= 0;
630 /* If our write is going to affect just part of the
631 * inst->regs_written(), then we need to unspill the destination
632 * since we write back out all of the regs_written().
634 if (inst
->predicate
|| inst
->force_uncompressed
|| inst
->force_sechalf
) {
635 fs_reg unspill_reg
= inst
->dst
;
636 for (int chan
= 0; chan
< inst
->regs_written
; chan
++) {
637 emit_unspill(inst
, unspill_reg
,
638 subset_spill_offset
+ REG_SIZE
* chan
);
639 unspill_reg
.reg_offset
++;
643 fs_reg spill_src
= inst
->dst
;
644 spill_src
.reg_offset
= 0;
645 spill_src
.abs
= false;
646 spill_src
.negate
= false;
647 spill_src
.smear
= -1;
649 for (int chan
= 0; chan
< inst
->regs_written
; chan
++) {
650 fs_inst
*spill_inst
= new(mem_ctx
) fs_inst(FS_OPCODE_SPILL
,
651 reg_null_f
, spill_src
);
652 spill_src
.reg_offset
++;
653 spill_inst
->offset
= subset_spill_offset
+ chan
* REG_SIZE
;
654 spill_inst
->ir
= inst
->ir
;
655 spill_inst
->annotation
= inst
->annotation
;
656 spill_inst
->base_mrf
= 14;
657 spill_inst
->mlen
= 2; /* header, value */
658 inst
->insert_after(spill_inst
);
663 this->live_intervals_valid
= false;