src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 extern "C" {
  29
  30 #include <sys/types.h>
  31
  32 #include "main/macros.h"
  33 #include "main/shaderobj.h"
  34 #include "main/uniforms.h"
  35 #include "program/prog_parameter.h"
  36 #include "program/prog_print.h"
  37 #include "program/prog_optimize.h"
  38 #include "program/register_allocate.h"
  39 #include "program/sampler.h"
  40 #include "program/hash_table.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_wm.h"
  44 }
  45 #include "brw_fs.h"
  46 #include "../glsl/glsl_types.h"
  47 #include "../glsl/ir_optimization.h"
  48 #include "../glsl/ir_print_visitor.h"
  49
  50 static void
  51 assign_reg(int *reg_hw_locations, fs_reg *reg)
  52 {
  53    if (reg->file == GRF && reg->reg != 0) {
  54       assert(reg->reg_offset >= 0);
  55       reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
  56       reg->reg = 0;
  57    }
  58 }
  59
  60 void
  61 fs_visitor::assign_regs_trivial()
  62 {
  63    int last_grf = 0;
  64    int hw_reg_mapping[this->virtual_grf_next];
  65    int i;
  66
  67    hw_reg_mapping[0] = 0;
  68    hw_reg_mapping[1] = this->first_non_payload_grf;
  69    for (i = 2; i < this->virtual_grf_next; i++) {
  70       hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
  71                            this->virtual_grf_sizes[i - 1]);
  72    }
  73    last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
  74
  75    foreach_iter(exec_list_iterator, iter, this->instructions) {
  76       fs_inst *inst = (fs_inst *)iter.get();
  77
  78       assign_reg(hw_reg_mapping, &inst->dst);
  79       assign_reg(hw_reg_mapping, &inst->src[0]);
  80       assign_reg(hw_reg_mapping, &inst->src[1]);
  81    }
  82
  83    this->grf_used = last_grf + 1;
  84 }
  85
  86 bool
  87 fs_visitor::assign_regs()
  88 {
  89    int last_grf = 0;
  90    int hw_reg_mapping[this->virtual_grf_next + 1];
  91    int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
  92    int class_sizes[base_reg_count];
  93    int class_count = 0;
  94    int aligned_pair_class = -1;
  95
  96    calculate_live_intervals();
  97
  98    /* Set up the register classes.
  99     *
 100     * The base registers store a scalar value.  For texture samples,
 101     * we get virtual GRFs composed of 4 contiguous hw register.  For
 102     * structures and arrays, we store them as contiguous larger things
 103     * than that, though we should be able to do better most of the
 104     * time.
 105     */
 106    class_sizes[class_count++] = 1;
 107    if (brw->has_pln && intel->gen < 6) {
 108       /* Always set up the (unaligned) pairs for gen5, so we can find
 109        * them for making the aligned pair class.
 110        */
 111       class_sizes[class_count++] = 2;
 112    }
 113    for (int r = 1; r < this->virtual_grf_next; r++) {
 114       int i;
 115
 116       for (i = 0; i < class_count; i++) {
 117          if (class_sizes[i] == this->virtual_grf_sizes[r])
 118             break;
 119       }
 120       if (i == class_count) {
 121          if (this->virtual_grf_sizes[r] >= base_reg_count) {
 122             fprintf(stderr, "Object too large to register allocate.\n");
 123             this->fail = true;
 124          }
 125
 126          class_sizes[class_count++] = this->virtual_grf_sizes[r];
 127       }
 128    }
 129
 130    int ra_reg_count = 0;
 131    int class_base_reg[class_count];
 132    int class_reg_count[class_count];
 133    int classes[class_count + 1];
 134
 135    for (int i = 0; i < class_count; i++) {
 136       class_base_reg[i] = ra_reg_count;
 137       class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
 138       ra_reg_count += class_reg_count[i];
 139    }
 140
 141    struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
 142    for (int i = 0; i < class_count; i++) {
 143       classes[i] = ra_alloc_reg_class(regs);
 144
 145       for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 146          ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
 147       }
 148
 149       /* Add conflicts between our contiguous registers aliasing
 150        * base regs and other register classes' contiguous registers
 151        * that alias base regs, or the base regs themselves for classes[0].
 152        */
 153       for (int c = 0; c <= i; c++) {
 154          for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
 155             for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
 156                  c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
 157                  c_r++) {
 158
 159                if (0) {
 160                   printf("%d/%d conflicts %d/%d\n",
 161                          class_sizes[i], this->first_non_payload_grf + i_r,
 162                          class_sizes[c], this->first_non_payload_grf + c_r);
 163                }
 164
 165                ra_add_reg_conflict(regs,
 166                                    class_base_reg[i] + i_r,
 167                                    class_base_reg[c] + c_r);
 168             }
 169          }
 170       }
 171    }
 172
 173    /* Add a special class for aligned pairs, which we'll put delta_x/y
 174     * in on gen5 so that we can do PLN.
 175     */
 176    if (brw->has_pln && intel->gen < 6) {
 177       int reg_count = (base_reg_count - 1) / 2;
 178       int unaligned_pair_class = 1;
 179       assert(class_sizes[unaligned_pair_class] == 2);
 180
 181       aligned_pair_class = class_count;
 182       classes[aligned_pair_class] = ra_alloc_reg_class(regs);
 183       class_sizes[aligned_pair_class] = 2;
 184       class_base_reg[aligned_pair_class] = 0;
 185       class_reg_count[aligned_pair_class] = 0;
 186       int start = (this->first_non_payload_grf & 1) ? 1 : 0;
 187
 188       for (int i = 0; i < reg_count; i++) {
 189          ra_class_add_reg(regs, classes[aligned_pair_class],
 190                           class_base_reg[unaligned_pair_class] + i * 2 + start);
 191       }
 192       class_count++;
 193    }
 194
 195    ra_set_finalize(regs);
 196
 197    struct ra_graph *g = ra_alloc_interference_graph(regs,
 198                                                     this->virtual_grf_next);
 199    /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
 200     * with nodes.
 201     */
 202    ra_set_node_class(g, 0, classes[0]);
 203
 204    for (int i = 1; i < this->virtual_grf_next; i++) {
 205       for (int c = 0; c < class_count; c++) {
 206          if (class_sizes[c] == this->virtual_grf_sizes[i]) {
 207             if (aligned_pair_class >= 0 &&
 208                 this->delta_x.reg == i) {
 209                ra_set_node_class(g, i, classes[aligned_pair_class]);
 210             } else {
 211                ra_set_node_class(g, i, classes[c]);
 212             }
 213             break;
 214          }
 215       }
 216
 217       for (int j = 1; j < i; j++) {
 218          if (virtual_grf_interferes(i, j)) {
 219             ra_add_node_interference(g, i, j);
 220          }
 221       }
 222    }
 223
 224    if (!ra_allocate_no_spills(g)) {
 225       /* Failed to allocate registers.  Spill a reg, and the caller will
 226        * loop back into here to try again.
 227        */
 228       int reg = choose_spill_reg(g);
 229       if (reg == -1 || intel->gen >= 6) {
 230          this->fail = true;
 231       } else {
 232          spill_reg(reg);
 233       }
 234
 235
 236       ralloc_free(g);
 237       ralloc_free(regs);
 238
 239       return false;
 240    }
 241
 242    /* Get the chosen virtual registers for each node, and map virtual
 243     * regs in the register classes back down to real hardware reg
 244     * numbers.
 245     */
 246    hw_reg_mapping[0] = 0; /* unused */
 247    for (int i = 1; i < this->virtual_grf_next; i++) {
 248       int reg = ra_get_node_reg(g, i);
 249       int hw_reg = -1;
 250
 251       for (int c = 0; c < class_count; c++) {
 252          if (reg >= class_base_reg[c] &&
 253              reg < class_base_reg[c] + class_reg_count[c]) {
 254             hw_reg = reg - class_base_reg[c];
 255             break;
 256          }
 257       }
 258
 259       assert(hw_reg >= 0);
 260       hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
 261       last_grf = MAX2(last_grf,
 262                       hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
 263    }
 264
 265    foreach_iter(exec_list_iterator, iter, this->instructions) {
 266       fs_inst *inst = (fs_inst *)iter.get();
 267
 268       assign_reg(hw_reg_mapping, &inst->dst);
 269       assign_reg(hw_reg_mapping, &inst->src[0]);
 270       assign_reg(hw_reg_mapping, &inst->src[1]);
 271    }
 272
 273    this->grf_used = last_grf + 1;
 274
 275    ralloc_free(g);
 276    ralloc_free(regs);
 277
 278    return true;
 279 }
 280
 281 void
 282 fs_visitor::emit_unspill(fs_inst *inst, fs_reg dst, uint32_t spill_offset)
 283 {
 284    int size = virtual_grf_sizes[dst.reg];
 285    dst.reg_offset = 0;
 286
 287    for (int chan = 0; chan < size; chan++) {
 288       fs_inst *unspill_inst = new(mem_ctx) fs_inst(FS_OPCODE_UNSPILL,
 289                                                    dst);
 290       dst.reg_offset++;
 291       unspill_inst->offset = spill_offset + chan * REG_SIZE;
 292       unspill_inst->ir = inst->ir;
 293       unspill_inst->annotation = inst->annotation;
 294
 295       /* Choose a MRF that won't conflict with an MRF that's live across the
 296        * spill.  Nothing else will make it up to MRF 14/15.
 297        */
 298       unspill_inst->base_mrf = 14;
 299       unspill_inst->mlen = 1; /* header contains offset */
 300       inst->insert_before(unspill_inst);
 301    }
 302 }
 303
 304 int
 305 fs_visitor::choose_spill_reg(struct ra_graph *g)
 306 {
 307    float loop_scale = 1.0;
 308    float spill_costs[this->virtual_grf_next];
 309    bool no_spill[this->virtual_grf_next];
 310
 311    for (int i = 0; i < this->virtual_grf_next; i++) {
 312       spill_costs[i] = 0.0;
 313       no_spill[i] = false;
 314    }
 315
 316    /* Calculate costs for spilling nodes.  Call it a cost of 1 per
 317     * spill/unspill we'll have to do, and guess that the insides of
 318     * loops run 10 times.
 319     */
 320    foreach_iter(exec_list_iterator, iter, this->instructions) {
 321       fs_inst *inst = (fs_inst *)iter.get();
 322
 323       for (unsigned int i = 0; i < 3; i++) {
 324          if (inst->src[i].file == GRF) {
 325             int size = virtual_grf_sizes[inst->src[i].reg];
 326             spill_costs[inst->src[i].reg] += size * loop_scale;
 327          }
 328       }
 329
 330       if (inst->dst.file == GRF) {
 331          int size = virtual_grf_sizes[inst->dst.reg];
 332          spill_costs[inst->dst.reg] += size * loop_scale;
 333       }
 334
 335       switch (inst->opcode) {
 336
 337       case BRW_OPCODE_DO:
 338          loop_scale *= 10;
 339          break;
 340
 341       case BRW_OPCODE_WHILE:
 342          loop_scale /= 10;
 343          break;
 344
 345       case FS_OPCODE_SPILL:
 346          if (inst->src[0].file == GRF)
 347             no_spill[inst->src[0].reg] = true;
 348          break;
 349
 350       case FS_OPCODE_UNSPILL:
 351          if (inst->dst.file == GRF)
 352             no_spill[inst->dst.reg] = true;
 353          break;
 354       }
 355    }
 356
 357    for (int i = 0; i < this->virtual_grf_next; i++) {
 358       if (!no_spill[i])
 359          ra_set_node_spill_cost(g, i, spill_costs[i]);
 360    }
 361
 362    return ra_get_best_spill_node(g);
 363 }
 364
 365 void
 366 fs_visitor::spill_reg(int spill_reg)
 367 {
 368    int size = virtual_grf_sizes[spill_reg];
 369    unsigned int spill_offset = c->last_scratch;
 370    assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */
 371    c->last_scratch += size * REG_SIZE;
 372
 373    /* Generate spill/unspill instructions for the objects being
 374     * spilled.  Right now, we spill or unspill the whole thing to a
 375     * virtual grf of the same size.  For most instructions, though, we
 376     * could just spill/unspill the GRF being accessed.
 377     */
 378    foreach_iter(exec_list_iterator, iter, this->instructions) {
 379       fs_inst *inst = (fs_inst *)iter.get();
 380
 381       for (unsigned int i = 0; i < 3; i++) {
 382          if (inst->src[i].file == GRF &&
 383              inst->src[i].reg == spill_reg) {
 384             inst->src[i].reg = virtual_grf_alloc(size);
 385             emit_unspill(inst, inst->src[i], spill_offset);
 386          }
 387       }
 388
 389       if (inst->dst.file == GRF &&
 390           inst->dst.reg == spill_reg) {
 391          inst->dst.reg = virtual_grf_alloc(size);
 392
 393          /* Since we spill/unspill the whole thing even if we access
 394           * just a component, we may need to unspill before the
 395           * instruction we're spilling for.
 396           */
 397          if (size != 1 || inst->predicated) {
 398             emit_unspill(inst, inst->dst, spill_offset);
 399          }
 400
 401          fs_reg spill_src = inst->dst;
 402          spill_src.reg_offset = 0;
 403          spill_src.abs = false;
 404          spill_src.negate = false;
 405          spill_src.smear = -1;
 406
 407          for (int chan = 0; chan < size; chan++) {
 408             fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,
 409                                                        reg_null_f, spill_src);
 410             spill_src.reg_offset++;
 411             spill_inst->offset = spill_offset + chan * REG_SIZE;
 412             spill_inst->ir = inst->ir;
 413             spill_inst->annotation = inst->annotation;
 414             spill_inst->base_mrf = 14;
 415             spill_inst->mlen = 2; /* header, value */
 416             inst->insert_after(spill_inst);
 417          }
 418       }
 419    }
 420
 421    this->live_intervals_valid = false;
 422 }