2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include "glsl/glsl_types.h"
31 #include "glsl/ir_optimization.h"
34 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
36 if (reg
->file
== GRF
) {
37 assert(reg
->reg_offset
>= 0);
38 reg
->reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
44 fs_visitor::assign_regs_trivial()
46 int hw_reg_mapping
[this->virtual_grf_count
+ 1];
48 int reg_width
= dispatch_width
/ 8;
50 /* Note that compressed instructions require alignment to 2 registers. */
51 hw_reg_mapping
[0] = ALIGN(this->first_non_payload_grf
, reg_width
);
52 for (i
= 1; i
<= this->virtual_grf_count
; i
++) {
53 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
54 this->virtual_grf_sizes
[i
- 1]);
56 this->grf_used
= hw_reg_mapping
[this->virtual_grf_count
];
58 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
59 assign_reg(hw_reg_mapping
, &inst
->dst
);
60 for (i
= 0; i
< inst
->sources
; i
++) {
61 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
65 if (this->grf_used
>= max_grf
) {
66 fail("Ran out of regs on trivial allocator (%d/%d)\n",
67 this->grf_used
, max_grf
);
69 this->virtual_grf_count
= this->grf_used
;
75 brw_alloc_reg_set(struct intel_screen
*screen
, int reg_width
)
77 const struct brw_device_info
*devinfo
= screen
->devinfo
;
78 int base_reg_count
= BRW_MAX_GRF
;
79 int index
= reg_width
- 1;
81 /* The registers used to make up almost all values handled in the compiler
82 * are a scalar value occupying a single register (or 2 registers in the
83 * case of SIMD16, which is handled by dividing base_reg_count by 2 and
84 * multiplying allocated register numbers by 2). Things that were
85 * aggregates of scalar values at the GLSL level were split to scalar
86 * values by split_virtual_grfs().
88 * However, texture SEND messages return a series of contiguous registers
89 * to write into. We currently always ask for 4 registers, but we may
90 * convert that to use less some day.
92 * Additionally, on gen5 we need aligned pairs of registers for the PLN
93 * instruction, and on gen4 we need 8 contiguous regs for workaround simd16
96 * So we have a need for classes for 1, 2, 4, and 8 registers currently,
97 * and we add in '3' to make indexing the array easier for the common case
98 * (since we'll probably want it for texturing later).
100 * And, on gen7 and newer, we do texturing SEND messages from GRFs, which
101 * means that we may need any size up to the sampler message size limit (11
105 int class_sizes
[BRW_MAX_MRF
];
107 if (devinfo
->gen
>= 7) {
108 for (class_count
= 0; class_count
< BRW_MAX_MRF
; class_count
++)
109 class_sizes
[class_count
] = class_count
+ 1;
111 for (class_count
= 0; class_count
< 4; class_count
++)
112 class_sizes
[class_count
] = class_count
+ 1;
113 class_sizes
[class_count
++] = 8;
116 /* Compute the total number of registers across all classes. */
117 int ra_reg_count
= 0;
118 for (int i
= 0; i
< class_count
; i
++) {
119 if (devinfo
->gen
<= 5 && reg_width
== 2) {
122 * In order to reduce the hardware complexity, the following
123 * rules and restrictions apply to the compressed instruction:
125 * * Operand Alignment Rule: With the exceptions listed below, a
126 * source/destination operand in general should be aligned to
127 * even 256-bit physical register with a region size equal to
128 * two 256-bit physical register
130 ra_reg_count
+= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
132 ra_reg_count
+= base_reg_count
- (class_sizes
[i
] - 1);
136 uint8_t *ra_reg_to_grf
= ralloc_array(screen
, uint8_t, ra_reg_count
);
137 struct ra_regs
*regs
= ra_alloc_reg_set(screen
, ra_reg_count
);
138 if (devinfo
->gen
>= 6)
139 ra_set_allocate_round_robin(regs
);
140 int *classes
= ralloc_array(screen
, int, class_count
);
141 int aligned_pairs_class
= -1;
143 /* Now, add the registers to their classes, and add the conflicts
144 * between them and the base GRF registers (and also each other).
147 int pairs_base_reg
= 0;
148 int pairs_reg_count
= 0;
149 for (int i
= 0; i
< class_count
; i
++) {
151 if (devinfo
->gen
<= 5 && reg_width
== 2) {
152 class_reg_count
= (base_reg_count
- (class_sizes
[i
] - 1)) / 2;
154 class_reg_count
= base_reg_count
- (class_sizes
[i
] - 1);
156 classes
[i
] = ra_alloc_reg_class(regs
);
158 /* Save this off for the aligned pair class at the end. */
159 if (class_sizes
[i
] == 2) {
160 pairs_base_reg
= reg
;
161 pairs_reg_count
= class_reg_count
;
164 if (devinfo
->gen
<= 5 && reg_width
== 2) {
165 for (int j
= 0; j
< class_reg_count
; j
++) {
166 ra_class_add_reg(regs
, classes
[i
], reg
);
168 ra_reg_to_grf
[reg
] = j
* 2;
170 for (int base_reg
= j
* 2;
171 base_reg
< j
* 2 + class_sizes
[i
];
173 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
179 for (int j
= 0; j
< class_reg_count
; j
++) {
180 ra_class_add_reg(regs
, classes
[i
], reg
);
182 ra_reg_to_grf
[reg
] = j
;
184 for (int base_reg
= j
;
185 base_reg
< j
+ class_sizes
[i
];
187 ra_add_transitive_reg_conflict(regs
, base_reg
, reg
);
194 assert(reg
== ra_reg_count
);
196 /* Add a special class for aligned pairs, which we'll put delta_x/y
197 * in on gen5 so that we can do PLN.
199 if (devinfo
->has_pln
&& devinfo
->gen
< 6) {
200 aligned_pairs_class
= ra_alloc_reg_class(regs
);
202 for (int i
= 0; i
< pairs_reg_count
; i
++) {
203 if ((ra_reg_to_grf
[pairs_base_reg
+ i
] & 1) == 0) {
204 ra_class_add_reg(regs
, aligned_pairs_class
, pairs_base_reg
+ i
);
209 ra_set_finalize(regs
, NULL
);
211 screen
->wm_reg_sets
[index
].regs
= regs
;
212 for (unsigned i
= 0; i
< ARRAY_SIZE(screen
->wm_reg_sets
[index
].classes
); i
++)
213 screen
->wm_reg_sets
[index
].classes
[i
] = -1;
214 for (int i
= 0; i
< class_count
; i
++)
215 screen
->wm_reg_sets
[index
].classes
[class_sizes
[i
] - 1] = classes
[i
];
216 screen
->wm_reg_sets
[index
].ra_reg_to_grf
= ra_reg_to_grf
;
217 screen
->wm_reg_sets
[index
].aligned_pairs_class
= aligned_pairs_class
;
221 brw_fs_alloc_reg_sets(struct intel_screen
*screen
)
223 brw_alloc_reg_set(screen
, 1);
224 brw_alloc_reg_set(screen
, 2);
228 count_to_loop_end(const bblock_t
*block
)
230 if (block
->end()->opcode
== BRW_OPCODE_WHILE
)
231 return block
->end_ip
;
234 /* Skip the first block, since we don't want to count the do the calling
237 for (block
= block
->next();
239 block
= block
->next()) {
240 if (block
->start()->opcode
== BRW_OPCODE_DO
)
242 if (block
->end()->opcode
== BRW_OPCODE_WHILE
) {
245 return block
->end_ip
;
248 unreachable("not reached");
252 * Sets up interference between thread payload registers and the virtual GRFs
253 * to be allocated for program temporaries.
255 * We want to be able to reallocate the payload for our virtual GRFs, notably
256 * because the setup coefficients for a full set of 16 FS inputs takes up 8 of
259 * The layout of the payload registers is:
261 * 0..payload.num_regs-1: fixed function setup (including bary coordinates).
262 * payload.num_regs..payload.num_regs+curb_read_lengh-1: uniform data
263 * payload.num_regs+curb_read_lengh..first_non_payload_grf-1: setup coefficients.
265 * And we have payload_node_count nodes covering these registers in order
266 * (note that in SIMD16, a node is two registers).
269 fs_visitor::setup_payload_interference(struct ra_graph
*g
,
270 int payload_node_count
,
271 int first_payload_node
)
276 int payload_last_use_ip
[payload_node_count
];
277 memset(payload_last_use_ip
, 0, sizeof(payload_last_use_ip
));
279 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
280 switch (inst
->opcode
) {
284 /* Since payload regs are deffed only at the start of the shader
285 * execution, any uses of the payload within a loop mean the live
286 * interval extends to the end of the outermost loop. Find the ip of
290 loop_end_ip
= count_to_loop_end(block
);
292 case BRW_OPCODE_WHILE
:
301 use_ip
= loop_end_ip
;
305 /* Note that UNIFORM args have been turned into FIXED_HW_REG by
306 * assign_curbe_setup(), and interpolation uses fixed hardware regs from
307 * the start (see interp_reg()).
309 for (int i
= 0; i
< inst
->sources
; i
++) {
310 if (inst
->src
[i
].file
== HW_REG
&&
311 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
312 int node_nr
= inst
->src
[i
].fixed_hw_reg
.nr
;
313 if (node_nr
>= payload_node_count
)
316 payload_last_use_ip
[node_nr
] = use_ip
;
320 /* Special case instructions which have extra implied registers used. */
321 switch (inst
->opcode
) {
322 case FS_OPCODE_FB_WRITE
:
323 /* We could omit this for the !inst->header_present case, except that
324 * the simulator apparently incorrectly reads from g0/g1 instead of
325 * sideband. It also really freaks out driver developers to see g0
326 * used in unusual places, so just always reserve it.
328 payload_last_use_ip
[0] = use_ip
;
329 payload_last_use_ip
[1] = use_ip
;
332 case FS_OPCODE_LINTERP
:
333 /* On gen6+ in SIMD16, there are 4 adjacent registers used by
334 * PLN's sourcing of the deltas, while we list only the first one
335 * in the arguments. Pre-gen6, the deltas are computed in normal
340 if (inst
->src
[delta_x_arg
].file
== HW_REG
&&
341 inst
->src
[delta_x_arg
].fixed_hw_reg
.file
==
342 BRW_GENERAL_REGISTER_FILE
) {
343 for (int i
= 1; i
< 4; ++i
) {
344 int node
= inst
->src
[delta_x_arg
].fixed_hw_reg
.nr
+ i
;
345 assert(node
< payload_node_count
);
346 payload_last_use_ip
[node
] = use_ip
;
359 for (int i
= 0; i
< payload_node_count
; i
++) {
360 /* Mark the payload node as interfering with any virtual grf that is
361 * live between the start of the program and our last use of the payload
364 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
365 /* Note that we use a <= comparison, unlike virtual_grf_interferes(),
366 * in order to not have to worry about the uniform issue described in
367 * calculate_live_intervals().
369 if (this->virtual_grf_start
[j
] <= payload_last_use_ip
[i
]) {
370 ra_add_node_interference(g
, first_payload_node
+ i
, j
);
375 for (int i
= 0; i
< payload_node_count
; i
++) {
376 /* Mark each payload node as being allocated to its physical register.
378 * The alternative would be to have per-physical-register classes, which
379 * would just be silly.
381 ra_set_node_reg(g
, first_payload_node
+ i
, i
);
386 * Sets the mrf_used array to indicate which MRFs are used by the shader IR
388 * This is used in assign_regs() to decide which of the GRFs that we use as
389 * MRFs on gen7 get normally register allocated, and in register spilling to
390 * see if we can actually use MRFs to do spills without overwriting normal MRF
394 fs_visitor::get_used_mrfs(bool *mrf_used
)
396 int reg_width
= dispatch_width
/ 8;
398 memset(mrf_used
, 0, BRW_MAX_MRF
* sizeof(bool));
400 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
401 if (inst
->dst
.file
== MRF
) {
402 int reg
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
403 mrf_used
[reg
] = true;
404 if (reg_width
== 2) {
405 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
406 mrf_used
[reg
+ 4] = true;
408 mrf_used
[reg
+ 1] = true;
413 if (inst
->mlen
> 0) {
414 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
415 mrf_used
[inst
->base_mrf
+ i
] = true;
422 * Sets interference between virtual GRFs and usage of the high GRFs for SEND
423 * messages (treated as MRFs in code generation).
426 fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g
, int first_mrf_node
)
428 bool mrf_used
[BRW_MAX_MRF
];
429 get_used_mrfs(mrf_used
);
431 for (int i
= 0; i
< BRW_MAX_MRF
; i
++) {
432 /* Mark each MRF reg node as being allocated to its physical register.
434 * The alternative would be to have per-physical-register classes, which
435 * would just be silly.
437 ra_set_node_reg(g
, first_mrf_node
+ i
, GEN7_MRF_HACK_START
+ i
);
439 /* Since we don't have any live/dead analysis on the MRFs, just mark all
440 * that are used as conflicting with all virtual GRFs.
443 for (int j
= 0; j
< this->virtual_grf_count
; j
++) {
444 ra_add_node_interference(g
, first_mrf_node
+ i
, j
);
451 fs_visitor::assign_regs(bool allow_spilling
)
453 struct intel_screen
*screen
= brw
->intelScreen
;
454 /* Most of this allocation was written for a reg_width of 1
455 * (dispatch_width == 8). In extending to SIMD16, the code was
456 * left in place and it was converted to have the hardware
457 * registers it's allocating be contiguous physical pairs of regs
458 * for reg_width == 2.
460 int reg_width
= dispatch_width
/ 8;
461 int hw_reg_mapping
[this->virtual_grf_count
];
462 int payload_node_count
= ALIGN(this->first_non_payload_grf
, reg_width
);
463 int rsi
= reg_width
- 1; /* Which screen->wm_reg_sets[] to use */
464 calculate_live_intervals();
466 int node_count
= this->virtual_grf_count
;
467 int first_payload_node
= node_count
;
468 node_count
+= payload_node_count
;
469 int first_mrf_hack_node
= node_count
;
471 node_count
+= BRW_MAX_GRF
- GEN7_MRF_HACK_START
;
472 struct ra_graph
*g
= ra_alloc_interference_graph(screen
->wm_reg_sets
[rsi
].regs
,
475 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
476 unsigned size
= this->virtual_grf_sizes
[i
];
479 assert(size
<= ARRAY_SIZE(screen
->wm_reg_sets
[rsi
].classes
) &&
480 "Register allocation relies on split_virtual_grfs()");
481 c
= screen
->wm_reg_sets
[rsi
].classes
[size
- 1];
483 /* Special case: on pre-GEN6 hardware that supports PLN, the
484 * second operand of a PLN instruction needs to be an
485 * even-numbered register, so we have a special register class
486 * wm_aligned_pairs_class to handle this case. pre-GEN6 always
487 * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
488 * second operand of a PLN instruction (since it doesn't support
489 * any other interpolation modes). So all we need to do is find
490 * that register and set it to the appropriate class.
492 if (screen
->wm_reg_sets
[rsi
].aligned_pairs_class
>= 0 &&
493 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].file
== GRF
&&
494 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg
== i
) {
495 c
= screen
->wm_reg_sets
[rsi
].aligned_pairs_class
;
498 ra_set_node_class(g
, i
, c
);
500 for (int j
= 0; j
< i
; j
++) {
501 if (virtual_grf_interferes(i
, j
)) {
502 ra_add_node_interference(g
, i
, j
);
507 setup_payload_interference(g
, payload_node_count
, first_payload_node
);
509 setup_mrf_hack_interference(g
, first_mrf_hack_node
);
511 if (dispatch_width
> 8) {
512 /* In 16-wide dispatch we have an issue where a compressed
513 * instruction is actually two instructions executed simultaneiously.
514 * It's actually ok to have the source and destination registers be
515 * the same. In this case, each instruction over-writes its own
516 * source and there's no problem. The real problem here is if the
517 * source and destination registers are off by one. Then you can end
518 * up in a scenario where the first instruction over-writes the
519 * source of the second instruction. Since the compiler doesn't know
520 * about this level of granularity, we simply make the source and
521 * destination interfere.
523 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
524 if (inst
->dst
.file
!= GRF
)
527 for (int i
= 0; i
< inst
->sources
; ++i
) {
528 if (inst
->src
[i
].file
== GRF
) {
529 ra_add_node_interference(g
, inst
->dst
.reg
, inst
->src
[i
].reg
);
535 /* Debug of register spilling: Go spill everything. */
537 int reg
= choose_spill_reg(g
);
546 if (!ra_allocate(g
)) {
547 /* Failed to allocate registers. Spill a reg, and the caller will
548 * loop back into here to try again.
550 int reg
= choose_spill_reg(g
);
553 fail("no register to spill:\n");
554 dump_instructions(NULL
);
555 } else if (allow_spilling
) {
564 /* Get the chosen virtual registers for each node, and map virtual
565 * regs in the register classes back down to real hardware reg
568 this->grf_used
= payload_node_count
;
569 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
570 int reg
= ra_get_node_reg(g
, i
);
572 hw_reg_mapping
[i
] = screen
->wm_reg_sets
[rsi
].ra_reg_to_grf
[reg
];
573 this->grf_used
= MAX2(this->grf_used
,
574 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
]);
577 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
578 assign_reg(hw_reg_mapping
, &inst
->dst
);
579 for (int i
= 0; i
< inst
->sources
; i
++) {
580 assign_reg(hw_reg_mapping
, &inst
->src
[i
]);
584 this->virtual_grf_count
= this->grf_used
;
592 fs_visitor::emit_unspill(bblock_t
*block
, fs_inst
*inst
, fs_reg dst
,
593 uint32_t spill_offset
, int count
)
599 for (int i
= 0; i
< count
/ reg_size
; i
++) {
600 /* The gen7 descriptor-based offset is 12 bits of HWORD units. */
601 bool gen7_read
= brw
->gen
>= 7 && spill_offset
< (1 << 12) * REG_SIZE
;
603 fs_inst
*unspill_inst
=
604 new(mem_ctx
) fs_inst(gen7_read
?
605 SHADER_OPCODE_GEN7_SCRATCH_READ
:
606 SHADER_OPCODE_GEN4_SCRATCH_READ
,
608 unspill_inst
->offset
= spill_offset
;
609 unspill_inst
->ir
= inst
->ir
;
610 unspill_inst
->annotation
= inst
->annotation
;
613 unspill_inst
->base_mrf
= 14;
614 unspill_inst
->mlen
= 1; /* header contains offset */
616 inst
->insert_before(block
, unspill_inst
);
618 dst
.reg_offset
+= reg_size
;
619 spill_offset
+= reg_size
* 8 * sizeof(float);
624 fs_visitor::emit_spill(bblock_t
*block
, fs_inst
*inst
, fs_reg src
,
625 uint32_t spill_offset
, int count
)
627 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
633 for (int i
= 0; i
< count
/ reg_size
; i
++) {
634 fs_inst
*spill_inst
=
635 new(mem_ctx
) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
637 src
.reg_offset
+= reg_size
;
638 spill_inst
->offset
= spill_offset
+ i
* reg_size
;
639 spill_inst
->ir
= inst
->ir
;
640 spill_inst
->annotation
= inst
->annotation
;
641 spill_inst
->mlen
= 1 + reg_size
; /* header, value */
642 spill_inst
->base_mrf
= spill_base_mrf
;
643 inst
->insert_after(block
, spill_inst
);
648 fs_visitor::choose_spill_reg(struct ra_graph
*g
)
650 float loop_scale
= 1.0;
651 float spill_costs
[this->virtual_grf_count
];
652 bool no_spill
[this->virtual_grf_count
];
654 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
655 spill_costs
[i
] = 0.0;
659 /* Calculate costs for spilling nodes. Call it a cost of 1 per
660 * spill/unspill we'll have to do, and guess that the insides of
661 * loops run 10 times.
663 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
664 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
665 if (inst
->src
[i
].file
== GRF
) {
666 spill_costs
[inst
->src
[i
].reg
] += loop_scale
;
668 /* Register spilling logic assumes full-width registers; smeared
669 * registers have a width of 1 so if we try to spill them we'll
670 * generate invalid assembly. This shouldn't be a problem because
671 * smeared registers are only used as short-term temporaries when
672 * loading pull constants, so spilling them is unlikely to reduce
673 * register pressure anyhow.
675 if (!inst
->src
[i
].is_contiguous()) {
676 no_spill
[inst
->src
[i
].reg
] = true;
681 if (inst
->dst
.file
== GRF
) {
682 spill_costs
[inst
->dst
.reg
] += inst
->regs_written
* loop_scale
;
684 if (!inst
->dst
.is_contiguous()) {
685 no_spill
[inst
->dst
.reg
] = true;
689 switch (inst
->opcode
) {
695 case BRW_OPCODE_WHILE
:
699 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
700 if (inst
->src
[0].file
== GRF
)
701 no_spill
[inst
->src
[0].reg
] = true;
704 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
705 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
706 if (inst
->dst
.file
== GRF
)
707 no_spill
[inst
->dst
.reg
] = true;
715 for (int i
= 0; i
< this->virtual_grf_count
; i
++) {
717 ra_set_node_spill_cost(g
, i
, spill_costs
[i
]);
720 return ra_get_best_spill_node(g
);
724 fs_visitor::spill_reg(int spill_reg
)
726 int reg_size
= dispatch_width
* sizeof(float);
727 int size
= virtual_grf_sizes
[spill_reg
];
728 unsigned int spill_offset
= last_scratch
;
729 assert(ALIGN(spill_offset
, 16) == spill_offset
); /* oword read/write req. */
730 int spill_base_mrf
= dispatch_width
> 8 ? 13 : 14;
732 /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
733 * using up to 11 MRFs starting from either m1 or m2, and fb writes can use
734 * up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
735 * m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
736 * depth), starting from m1. In summary: We may not be able to spill in
737 * SIMD16 mode, because we'd stomp the FB writes.
739 if (!spilled_any_registers
) {
740 bool mrf_used
[BRW_MAX_MRF
];
741 get_used_mrfs(mrf_used
);
743 for (int i
= spill_base_mrf
; i
< BRW_MAX_MRF
; i
++) {
745 fail("Register spilling not supported with m%d used", i
);
750 spilled_any_registers
= true;
753 last_scratch
+= size
* reg_size
;
755 /* Generate spill/unspill instructions for the objects being
756 * spilled. Right now, we spill or unspill the whole thing to a
757 * virtual grf of the same size. For most instructions, though, we
758 * could just spill/unspill the GRF being accessed.
760 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
761 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
762 if (inst
->src
[i
].file
== GRF
&&
763 inst
->src
[i
].reg
== spill_reg
) {
764 int regs_read
= inst
->regs_read(this, i
);
765 int subset_spill_offset
= (spill_offset
+
766 reg_size
* inst
->src
[i
].reg_offset
);
767 fs_reg
unspill_dst(GRF
, virtual_grf_alloc(regs_read
));
769 inst
->src
[i
].reg
= unspill_dst
.reg
;
770 inst
->src
[i
].reg_offset
= 0;
772 emit_unspill(block
, inst
, unspill_dst
, subset_spill_offset
,
777 if (inst
->dst
.file
== GRF
&&
778 inst
->dst
.reg
== spill_reg
) {
779 int subset_spill_offset
= (spill_offset
+
780 reg_size
* inst
->dst
.reg_offset
);
781 fs_reg
spill_src(GRF
, virtual_grf_alloc(inst
->regs_written
));
783 inst
->dst
.reg
= spill_src
.reg
;
784 inst
->dst
.reg_offset
= 0;
786 /* If our write is going to affect just part of the
787 * inst->regs_written(), then we need to unspill the destination
788 * since we write back out all of the regs_written().
790 if (inst
->is_partial_write())
791 emit_unspill(block
, inst
, spill_src
, subset_spill_offset
,
794 emit_spill(block
, inst
, spill_src
, subset_spill_offset
,
799 invalidate_live_intervals();