src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_fs_live_variables.h"
  45
  46 static bool
  47 is_nop_mov(const fs_inst *inst)
  48 {
  49    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  50       fs_reg dst = inst->dst;
  51       for (int i = 0; i < inst->sources; i++) {
  52          dst.reg_offset = i;
  53          if (!dst.equals(inst->src[i])) {
  54             return false;
  55          }
  56       }
  57       return true;
  58    } else if (inst->opcode == BRW_OPCODE_MOV) {
  59       return inst->dst.equals(inst->src[0]);
  60    }
  61
  62    return false;
  63 }
  64
  65 static bool
  66 is_copy_payload(const fs_inst *inst, int src_size)
  67 {
  68    if (src_size != inst->sources)
  69       return false;
  70
  71    const int reg = inst->src[0].reg;
  72    if (inst->src[0].reg_offset != 0)
  73       return false;
  74
  75    for (int i = 1; i < inst->sources; i++) {
  76       if (inst->src[i].reg != reg ||
  77           inst->src[i].reg_offset != i) {
  78          return false;
  79       }
  80    }
  81    return true;
  82 }
  83
  84 static bool
  85 is_coalesce_candidate(const fs_inst *inst, const int *virtual_grf_sizes)
  86 {
  87    if ((inst->opcode != BRW_OPCODE_MOV &&
  88         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  89        inst->is_partial_write() ||
  90        inst->saturate ||
  91        inst->src[0].file != GRF ||
  92        inst->src[0].negate ||
  93        inst->src[0].abs ||
  94        !inst->src[0].is_contiguous() ||
  95        inst->dst.file != GRF ||
  96        inst->dst.type != inst->src[0].type) {
  97       return false;
  98    }
  99
 100    if (virtual_grf_sizes[inst->src[0].reg] >
 101        virtual_grf_sizes[inst->dst.reg])
 102       return false;
 103
 104    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 105       if (!is_copy_payload(inst, virtual_grf_sizes[inst->src[0].reg])) {
 106          return false;
 107       }
 108    }
 109
 110    return true;
 111 }
 112
 113 static bool
 114 can_coalesce_vars(brw::fs_live_variables *live_intervals,
 115                   const exec_list *instructions, const fs_inst *inst,
 116                   int var_to, int var_from)
 117 {
 118    if (!live_intervals->vars_interfere(var_from, var_to))
 119       return true;
 120
 121    int start_to = live_intervals->start[var_to];
 122    int end_to = live_intervals->end[var_to];
 123    int start_from = live_intervals->start[var_from];
 124    int end_from = live_intervals->end[var_from];
 125
 126    /* Variables interfere and one line range isn't a subset of the other. */
 127    if ((end_to > end_from && start_from < start_to) ||
 128        (end_from > end_to && start_to < start_from))
 129       return false;
 130
 131    int start_ip = MIN2(start_to, start_from);
 132    int scan_ip = -1;
 133
 134    foreach_in_list(fs_inst, scan_inst, instructions) {
 135       scan_ip++;
 136
 137       if (scan_ip < start_ip)
 138          continue;
 139
 140       if (scan_inst->is_control_flow())
 141          return false;
 142
 143       if (scan_ip <= live_intervals->start[var_to])
 144          continue;
 145
 146       if (scan_ip > live_intervals->end[var_to])
 147          break;
 148
 149       if (scan_inst->dst.equals(inst->dst) ||
 150           scan_inst->dst.equals(inst->src[0]))
 151          return false;
 152    }
 153
 154    return true;
 155 }
 156
 157 bool
 158 fs_visitor::register_coalesce()
 159 {
 160    bool progress = false;
 161
 162    calculate_live_intervals();
 163
 164    int src_size = 0;
 165    int channels_remaining = 0;
 166    int reg_from = -1, reg_to = -1;
 167    int reg_to_offset[MAX_SAMPLER_MESSAGE_SIZE];
 168    fs_inst *mov[MAX_SAMPLER_MESSAGE_SIZE];
 169    int var_to[MAX_SAMPLER_MESSAGE_SIZE];
 170    int var_from[MAX_SAMPLER_MESSAGE_SIZE];
 171
 172    foreach_in_list(fs_inst, inst, &instructions) {
 173       if (!is_coalesce_candidate(inst, virtual_grf_sizes))
 174          continue;
 175
 176       if (is_nop_mov(inst)) {
 177          inst->opcode = BRW_OPCODE_NOP;
 178          progress = true;
 179          continue;
 180       }
 181
 182       if (reg_from != inst->src[0].reg) {
 183          reg_from = inst->src[0].reg;
 184
 185          src_size = virtual_grf_sizes[inst->src[0].reg];
 186          assert(src_size <= MAX_SAMPLER_MESSAGE_SIZE);
 187
 188          channels_remaining = src_size;
 189          memset(mov, 0, sizeof(mov));
 190
 191          reg_to = inst->dst.reg;
 192       }
 193
 194       if (reg_to != inst->dst.reg)
 195          continue;
 196
 197       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 198          for (int i = 0; i < src_size; i++) {
 199             reg_to_offset[i] = i;
 200          }
 201          mov[0] = inst;
 202          channels_remaining -= inst->sources;
 203       } else {
 204          const int offset = inst->src[0].reg_offset;
 205          reg_to_offset[offset] = inst->dst.reg_offset;
 206          mov[offset] = inst;
 207          channels_remaining--;
 208       }
 209
 210       if (channels_remaining)
 211          continue;
 212
 213       bool can_coalesce = true;
 214       for (int i = 0; i < src_size; i++) {
 215          var_to[i] = live_intervals->var_from_vgrf[reg_to] + reg_to_offset[i];
 216          var_from[i] = live_intervals->var_from_vgrf[reg_from] + i;
 217
 218          if (!can_coalesce_vars(live_intervals, &instructions, inst,
 219                                 var_to[i], var_from[i])) {
 220             can_coalesce = false;
 221             reg_from = -1;
 222             break;
 223          }
 224       }
 225
 226       if (!can_coalesce)
 227          continue;
 228
 229       progress = true;
 230       bool was_load_payload = inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD;
 231
 232       for (int i = 0; i < src_size; i++) {
 233          if (mov[i]) {
 234             mov[i]->opcode = BRW_OPCODE_NOP;
 235             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 236             mov[i]->dst = reg_undef;
 237             for (int j = 0; j < mov[i]->sources; j++) {
 238                mov[i]->src[j] = reg_undef;
 239             }
 240          }
 241       }
 242
 243       foreach_in_list(fs_inst, scan_inst, &instructions) {
 244          for (int i = 0; i < src_size; i++) {
 245             if (mov[i] || was_load_payload) {
 246                if (scan_inst->dst.file == GRF &&
 247                    scan_inst->dst.reg == reg_from &&
 248                    scan_inst->dst.reg_offset == i) {
 249                   scan_inst->dst.reg = reg_to;
 250                   scan_inst->dst.reg_offset = reg_to_offset[i];
 251                }
 252                for (int j = 0; j < scan_inst->sources; j++) {
 253                   if (scan_inst->src[j].file == GRF &&
 254                       scan_inst->src[j].reg == reg_from &&
 255                       scan_inst->src[j].reg_offset == i) {
 256                      scan_inst->src[j].reg = reg_to;
 257                      scan_inst->src[j].reg_offset = reg_to_offset[i];
 258                   }
 259                }
 260             }
 261          }
 262       }
 263
 264       for (int i = 0; i < src_size; i++) {
 265          live_intervals->start[var_to[i]] =
 266             MIN2(live_intervals->start[var_to[i]],
 267                  live_intervals->start[var_from[i]]);
 268          live_intervals->end[var_to[i]] =
 269             MAX2(live_intervals->end[var_to[i]],
 270                  live_intervals->end[var_from[i]]);
 271       }
 272       reg_from = -1;
 273    }
 274
 275    if (progress) {
 276       foreach_in_list_safe(fs_inst, inst, &instructions) {
 277          if (inst->opcode == BRW_OPCODE_NOP) {
 278             inst->remove();
 279          }
 280       }
 281
 282       invalidate_live_intervals();
 283    }
 284
 285    return progress;
 286 }