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24 /** @file brw_fs_register_coalesce.cpp
26 * Implements register coalescing: Checks if the two registers involved in a
27 * raw move don't interfere, in which case they can both be stored in the same
28 * place and the MOV removed.
30 * To do this, all uses of the source of the MOV in the shader are replaced
31 * with the destination of the MOV. For example:
33 * add vgrf3:F, vgrf1:F, vgrf2:F
34 * mov vgrf4:F, vgrf3:F
35 * mul vgrf5:F, vgrf5:F, vgrf4:F
39 * add vgrf4:F, vgrf1:F, vgrf2:F
40 * mul vgrf5:F, vgrf5:F, vgrf4:F
44 #include "brw_fs_live_variables.h"
47 is_nop_mov(const fs_inst
*inst
)
49 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
50 fs_reg dst
= inst
->dst
;
51 for (int i
= 0; i
< inst
->sources
; i
++) {
53 if (!dst
.equals(inst
->src
[i
])) {
58 } else if (inst
->opcode
== BRW_OPCODE_MOV
) {
59 return inst
->dst
.equals(inst
->src
[0]);
66 is_copy_payload(const fs_inst
*inst
, int src_size
)
68 if (src_size
!= inst
->sources
)
71 const int reg
= inst
->src
[0].reg
;
72 if (inst
->src
[0].reg_offset
!= 0)
75 for (int i
= 1; i
< inst
->sources
; i
++) {
76 if (inst
->src
[i
].reg
!= reg
||
77 inst
->src
[i
].reg_offset
!= i
) {
85 is_coalesce_candidate(const fs_inst
*inst
, const int *virtual_grf_sizes
)
87 if ((inst
->opcode
!= BRW_OPCODE_MOV
&&
88 inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
) ||
89 inst
->is_partial_write() ||
91 inst
->src
[0].file
!= GRF
||
92 inst
->src
[0].negate
||
94 !inst
->src
[0].is_contiguous() ||
95 inst
->dst
.file
!= GRF
||
96 inst
->dst
.type
!= inst
->src
[0].type
) {
100 if (virtual_grf_sizes
[inst
->src
[0].reg
] >
101 virtual_grf_sizes
[inst
->dst
.reg
])
104 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
105 if (!is_copy_payload(inst
, virtual_grf_sizes
[inst
->src
[0].reg
])) {
114 can_coalesce_vars(brw::fs_live_variables
*live_intervals
,
115 const exec_list
*instructions
, const fs_inst
*inst
,
116 int var_to
, int var_from
)
118 if (!live_intervals
->vars_interfere(var_from
, var_to
))
121 int start_to
= live_intervals
->start
[var_to
];
122 int end_to
= live_intervals
->end
[var_to
];
123 int start_from
= live_intervals
->start
[var_from
];
124 int end_from
= live_intervals
->end
[var_from
];
126 /* Variables interfere and one line range isn't a subset of the other. */
127 if ((end_to
> end_from
&& start_from
< start_to
) ||
128 (end_from
> end_to
&& start_to
< start_from
))
131 int start_ip
= MIN2(start_to
, start_from
);
134 foreach_in_list(fs_inst
, scan_inst
, instructions
) {
137 if (scan_ip
< start_ip
)
140 if (scan_inst
->is_control_flow())
143 if (scan_ip
<= live_intervals
->start
[var_to
])
146 if (scan_ip
> live_intervals
->end
[var_to
])
149 if (scan_inst
->dst
.equals(inst
->dst
) ||
150 scan_inst
->dst
.equals(inst
->src
[0]))
158 fs_visitor::register_coalesce()
160 bool progress
= false;
162 calculate_live_intervals();
165 int channels_remaining
= 0;
166 int reg_from
= -1, reg_to
= -1;
167 int reg_to_offset
[MAX_SAMPLER_MESSAGE_SIZE
];
168 fs_inst
*mov
[MAX_SAMPLER_MESSAGE_SIZE
];
169 int var_to
[MAX_SAMPLER_MESSAGE_SIZE
];
170 int var_from
[MAX_SAMPLER_MESSAGE_SIZE
];
172 foreach_in_list(fs_inst
, inst
, &instructions
) {
173 if (!is_coalesce_candidate(inst
, virtual_grf_sizes
))
176 if (is_nop_mov(inst
)) {
177 inst
->opcode
= BRW_OPCODE_NOP
;
182 if (reg_from
!= inst
->src
[0].reg
) {
183 reg_from
= inst
->src
[0].reg
;
185 src_size
= virtual_grf_sizes
[inst
->src
[0].reg
];
186 assert(src_size
<= MAX_SAMPLER_MESSAGE_SIZE
);
188 channels_remaining
= src_size
;
189 memset(mov
, 0, sizeof(mov
));
191 reg_to
= inst
->dst
.reg
;
194 if (reg_to
!= inst
->dst
.reg
)
197 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
198 for (int i
= 0; i
< src_size
; i
++) {
199 reg_to_offset
[i
] = i
;
202 channels_remaining
-= inst
->sources
;
204 const int offset
= inst
->src
[0].reg_offset
;
205 reg_to_offset
[offset
] = inst
->dst
.reg_offset
;
207 channels_remaining
--;
210 if (channels_remaining
)
213 bool can_coalesce
= true;
214 for (int i
= 0; i
< src_size
; i
++) {
215 var_to
[i
] = live_intervals
->var_from_vgrf
[reg_to
] + reg_to_offset
[i
];
216 var_from
[i
] = live_intervals
->var_from_vgrf
[reg_from
] + i
;
218 if (!can_coalesce_vars(live_intervals
, &instructions
, inst
,
219 var_to
[i
], var_from
[i
])) {
220 can_coalesce
= false;
230 bool was_load_payload
= inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
;
232 for (int i
= 0; i
< src_size
; i
++) {
234 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
235 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
236 mov
[i
]->dst
= reg_undef
;
237 for (int j
= 0; j
< mov
[i
]->sources
; j
++) {
238 mov
[i
]->src
[j
] = reg_undef
;
243 foreach_in_list(fs_inst
, scan_inst
, &instructions
) {
244 for (int i
= 0; i
< src_size
; i
++) {
245 if (mov
[i
] || was_load_payload
) {
246 if (scan_inst
->dst
.file
== GRF
&&
247 scan_inst
->dst
.reg
== reg_from
&&
248 scan_inst
->dst
.reg_offset
== i
) {
249 scan_inst
->dst
.reg
= reg_to
;
250 scan_inst
->dst
.reg_offset
= reg_to_offset
[i
];
252 for (int j
= 0; j
< scan_inst
->sources
; j
++) {
253 if (scan_inst
->src
[j
].file
== GRF
&&
254 scan_inst
->src
[j
].reg
== reg_from
&&
255 scan_inst
->src
[j
].reg_offset
== i
) {
256 scan_inst
->src
[j
].reg
= reg_to
;
257 scan_inst
->src
[j
].reg_offset
= reg_to_offset
[i
];
264 for (int i
= 0; i
< src_size
; i
++) {
265 live_intervals
->start
[var_to
[i
]] =
266 MIN2(live_intervals
->start
[var_to
[i
]],
267 live_intervals
->start
[var_from
[i
]]);
268 live_intervals
->end
[var_to
[i
]] =
269 MAX2(live_intervals
->end
[var_to
[i
]],
270 live_intervals
->end
[var_from
[i
]]);
276 foreach_in_list_safe(fs_inst
, inst
, &instructions
) {
277 if (inst
->opcode
== BRW_OPCODE_NOP
) {
282 invalidate_live_intervals();