src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_cfg.h"
  45 #include "brw_fs_live_variables.h"
  46
  47 static bool
  48 is_nop_mov(const fs_inst *inst)
  49 {
  50    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  51       fs_reg dst = inst->dst;
  52       for (int i = 0; i < inst->sources; i++) {
  53          dst.reg_offset = i;
  54          if (!dst.equals(inst->src[i])) {
  55             return false;
  56          }
  57       }
  58       return true;
  59    } else if (inst->opcode == BRW_OPCODE_MOV) {
  60       return inst->dst.equals(inst->src[0]);
  61    }
  62
  63    return false;
  64 }
  65
  66 static bool
  67 is_copy_payload(const fs_visitor *v, const fs_inst *inst)
  68 {
  69    if (v->virtual_grf_sizes[inst->src[0].reg] != inst->regs_written)
  70       return false;
  71
  72    fs_reg reg = inst->src[0];
  73
  74    for (int i = 0; i < inst->sources; i++)
  75       if (!inst->src[i].equals(offset(reg, i)))
  76          return false;
  77
  78    return true;
  79 }
  80
  81 static bool
  82 is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
  83 {
  84    if ((inst->opcode != BRW_OPCODE_MOV &&
  85         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  86        inst->is_partial_write() ||
  87        inst->saturate ||
  88        inst->src[0].file != GRF ||
  89        inst->src[0].negate ||
  90        inst->src[0].abs ||
  91        !inst->src[0].is_contiguous() ||
  92        inst->dst.file != GRF ||
  93        inst->dst.type != inst->src[0].type) {
  94       return false;
  95    }
  96
  97    if (v->virtual_grf_sizes[inst->src[0].reg] >
  98        v->virtual_grf_sizes[inst->dst.reg])
  99       return false;
 100
 101    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 102       if (!is_copy_payload(v, inst)) {
 103          return false;
 104       }
 105    }
 106
 107    return true;
 108 }
 109
 110 static bool
 111 can_coalesce_vars(brw::fs_live_variables *live_intervals,
 112                   const cfg_t *cfg, const fs_inst *inst,
 113                   int var_to, int var_from)
 114 {
 115    if (!live_intervals->vars_interfere(var_from, var_to))
 116       return true;
 117
 118    int start_to = live_intervals->start[var_to];
 119    int end_to = live_intervals->end[var_to];
 120    int start_from = live_intervals->start[var_from];
 121    int end_from = live_intervals->end[var_from];
 122
 123    /* Variables interfere and one line range isn't a subset of the other. */
 124    if ((end_to > end_from && start_from < start_to) ||
 125        (end_from > end_to && start_to < start_from))
 126       return false;
 127
 128    int start_ip = MIN2(start_to, start_from);
 129    int scan_ip = -1;
 130
 131    foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 132       scan_ip++;
 133
 134       if (scan_ip < start_ip)
 135          continue;
 136
 137       if (scan_inst->is_control_flow())
 138          return false;
 139
 140       if (scan_ip <= live_intervals->start[var_to])
 141          continue;
 142
 143       if (scan_ip > live_intervals->end[var_to])
 144          return true;
 145
 146       if (scan_inst->dst.equals(inst->dst) ||
 147           scan_inst->dst.equals(inst->src[0]))
 148          return false;
 149    }
 150
 151    return true;
 152 }
 153
 154 bool
 155 fs_visitor::register_coalesce()
 156 {
 157    bool progress = false;
 158
 159    calculate_live_intervals();
 160
 161    int src_size = 0;
 162    int channels_remaining = 0;
 163    int reg_from = -1, reg_to = -1;
 164    int reg_to_offset[MAX_VGRF_SIZE];
 165    fs_inst *mov[MAX_VGRF_SIZE];
 166    int var_to[MAX_VGRF_SIZE];
 167    int var_from[MAX_VGRF_SIZE];
 168
 169    foreach_block_and_inst(block, fs_inst, inst, cfg) {
 170       if (!is_coalesce_candidate(this, inst))
 171          continue;
 172
 173       if (is_nop_mov(inst)) {
 174          inst->opcode = BRW_OPCODE_NOP;
 175          progress = true;
 176          continue;
 177       }
 178
 179       if (reg_from != inst->src[0].reg) {
 180          reg_from = inst->src[0].reg;
 181
 182          src_size = virtual_grf_sizes[inst->src[0].reg];
 183          assert(src_size <= MAX_VGRF_SIZE);
 184
 185          assert(inst->src[0].width % 8 == 0);
 186          channels_remaining = src_size;
 187          memset(mov, 0, sizeof(mov));
 188
 189          reg_to = inst->dst.reg;
 190       }
 191
 192       if (reg_to != inst->dst.reg)
 193          continue;
 194
 195       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 196          for (int i = 0; i < src_size; i++) {
 197             reg_to_offset[i] = i;
 198          }
 199          mov[0] = inst;
 200          channels_remaining -= inst->regs_written;
 201       } else {
 202          const int offset = inst->src[0].reg_offset;
 203          if (mov[offset]) {
 204             /* This is the second time that this offset in the register has
 205              * been set.  This means, in particular, that inst->dst was
 206              * live before this instruction and that the live ranges of
 207              * inst->dst and inst->src[0] overlap and we can't coalesce the
 208              * two variables.  Let's ensure that doesn't happen.
 209              */
 210             channels_remaining = -1;
 211             continue;
 212          }
 213          reg_to_offset[offset] = inst->dst.reg_offset;
 214          if (inst->src[0].width == 16)
 215             reg_to_offset[offset + 1] = inst->dst.reg_offset + 1;
 216          mov[offset] = inst;
 217          channels_remaining -= inst->regs_written;
 218       }
 219
 220       if (channels_remaining)
 221          continue;
 222
 223       bool can_coalesce = true;
 224       for (int i = 0; i < src_size; i++) {
 225          if (reg_to_offset[i] != reg_to_offset[0] + i) {
 226             /* Registers are out-of-order. */
 227             can_coalesce = false;
 228             reg_from = -1;
 229             break;
 230          }
 231
 232          var_to[i] = live_intervals->var_from_vgrf[reg_to] + reg_to_offset[i];
 233          var_from[i] = live_intervals->var_from_vgrf[reg_from] + i;
 234
 235          if (!can_coalesce_vars(live_intervals, cfg, inst,
 236                                 var_to[i], var_from[i])) {
 237             can_coalesce = false;
 238             reg_from = -1;
 239             break;
 240          }
 241       }
 242
 243       if (!can_coalesce)
 244          continue;
 245
 246       progress = true;
 247       bool was_load_payload = inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD;
 248
 249       for (int i = 0; i < src_size; i++) {
 250          if (mov[i]) {
 251             mov[i]->opcode = BRW_OPCODE_NOP;
 252             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 253             mov[i]->dst = reg_undef;
 254             for (int j = 0; j < mov[i]->sources; j++) {
 255                mov[i]->src[j] = reg_undef;
 256             }
 257          }
 258       }
 259
 260       foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 261          for (int i = 0; i < src_size; i++) {
 262             if (mov[i] || was_load_payload) {
 263                if (scan_inst->dst.file == GRF &&
 264                    scan_inst->dst.reg == reg_from &&
 265                    scan_inst->dst.reg_offset == i) {
 266                   scan_inst->dst.reg = reg_to;
 267                   scan_inst->dst.reg_offset = reg_to_offset[i];
 268                }
 269                for (int j = 0; j < scan_inst->sources; j++) {
 270                   if (scan_inst->src[j].file == GRF &&
 271                       scan_inst->src[j].reg == reg_from &&
 272                       scan_inst->src[j].reg_offset == i) {
 273                      scan_inst->src[j].reg = reg_to;
 274                      scan_inst->src[j].reg_offset = reg_to_offset[i];
 275                   }
 276                }
 277             }
 278          }
 279       }
 280
 281       for (int i = 0; i < src_size; i++) {
 282          live_intervals->start[var_to[i]] =
 283             MIN2(live_intervals->start[var_to[i]],
 284                  live_intervals->start[var_from[i]]);
 285          live_intervals->end[var_to[i]] =
 286             MAX2(live_intervals->end[var_to[i]],
 287                  live_intervals->end[var_from[i]]);
 288       }
 289       reg_from = -1;
 290    }
 291
 292    if (progress) {
 293       foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
 294          if (inst->opcode == BRW_OPCODE_NOP) {
 295             inst->remove(block);
 296          }
 297       }
 298
 299       invalidate_live_intervals();
 300    }
 301
 302    return progress;
 303 }