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24 /** @file brw_fs_register_coalesce.cpp
26 * Implements register coalescing: Checks if the two registers involved in a
27 * raw move don't interfere, in which case they can both be stored in the same
28 * place and the MOV removed.
30 * To do this, all uses of the source of the MOV in the shader are replaced
31 * with the destination of the MOV. For example:
33 * add vgrf3:F, vgrf1:F, vgrf2:F
34 * mov vgrf4:F, vgrf3:F
35 * mul vgrf5:F, vgrf5:F, vgrf4:F
39 * add vgrf4:F, vgrf1:F, vgrf2:F
40 * mul vgrf5:F, vgrf5:F, vgrf4:F
45 #include "brw_fs_live_variables.h"
48 is_nop_mov(const fs_inst
*inst
)
50 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
51 fs_reg dst
= inst
->dst
;
52 for (int i
= 0; i
< inst
->sources
; i
++) {
54 if (!dst
.equals(inst
->src
[i
])) {
59 } else if (inst
->opcode
== BRW_OPCODE_MOV
) {
60 return inst
->dst
.equals(inst
->src
[0]);
67 is_coalesce_candidate(const fs_visitor
*v
, const fs_inst
*inst
)
69 if ((inst
->opcode
!= BRW_OPCODE_MOV
&&
70 inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
) ||
71 inst
->is_partial_write() ||
73 inst
->src
[0].file
!= GRF
||
74 inst
->src
[0].negate
||
76 !inst
->src
[0].is_contiguous() ||
77 inst
->dst
.file
!= GRF
||
78 inst
->dst
.type
!= inst
->src
[0].type
) {
82 if (v
->alloc
.sizes
[inst
->src
[0].reg
] >
83 v
->alloc
.sizes
[inst
->dst
.reg
])
86 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
87 if (!inst
->is_copy_payload(v
->alloc
)) {
96 can_coalesce_vars(brw::fs_live_variables
*live_intervals
,
97 const cfg_t
*cfg
, const fs_inst
*inst
,
98 int var_to
, int var_from
)
100 if (!live_intervals
->vars_interfere(var_from
, var_to
))
103 int start_to
= live_intervals
->start
[var_to
];
104 int end_to
= live_intervals
->end
[var_to
];
105 int start_from
= live_intervals
->start
[var_from
];
106 int end_from
= live_intervals
->end
[var_from
];
108 /* Variables interfere and one line range isn't a subset of the other. */
109 if ((end_to
> end_from
&& start_from
< start_to
) ||
110 (end_from
> end_to
&& start_to
< start_from
))
113 int start_ip
= MIN2(start_to
, start_from
);
116 foreach_block_and_inst(block
, fs_inst
, scan_inst
, cfg
) {
119 if (scan_ip
< start_ip
)
122 if (scan_inst
->is_control_flow())
125 if (scan_ip
<= live_intervals
->start
[var_to
])
128 if (scan_ip
> live_intervals
->end
[var_to
])
131 if (scan_inst
->dst
.equals(inst
->dst
) ||
132 scan_inst
->dst
.equals(inst
->src
[0]))
140 fs_visitor::register_coalesce()
142 bool progress
= false;
144 calculate_live_intervals();
147 int channels_remaining
= 0;
148 int reg_from
= -1, reg_to
= -1;
149 int reg_to_offset
[MAX_VGRF_SIZE
];
150 fs_inst
*mov
[MAX_VGRF_SIZE
];
151 int var_to
[MAX_VGRF_SIZE
];
152 int var_from
[MAX_VGRF_SIZE
];
154 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
155 if (!is_coalesce_candidate(this, inst
))
158 if (is_nop_mov(inst
)) {
159 inst
->opcode
= BRW_OPCODE_NOP
;
164 if (reg_from
!= inst
->src
[0].reg
) {
165 reg_from
= inst
->src
[0].reg
;
167 src_size
= alloc
.sizes
[inst
->src
[0].reg
];
168 assert(src_size
<= MAX_VGRF_SIZE
);
170 channels_remaining
= src_size
;
171 memset(mov
, 0, sizeof(mov
));
173 reg_to
= inst
->dst
.reg
;
176 if (reg_to
!= inst
->dst
.reg
)
179 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
180 for (int i
= 0; i
< src_size
; i
++) {
181 reg_to_offset
[i
] = i
;
184 channels_remaining
-= inst
->regs_written
;
186 const int offset
= inst
->src
[0].reg_offset
;
188 /* This is the second time that this offset in the register has
189 * been set. This means, in particular, that inst->dst was
190 * live before this instruction and that the live ranges of
191 * inst->dst and inst->src[0] overlap and we can't coalesce the
192 * two variables. Let's ensure that doesn't happen.
194 channels_remaining
= -1;
197 reg_to_offset
[offset
] = inst
->dst
.reg_offset
;
198 if (inst
->regs_written
> 1)
199 reg_to_offset
[offset
+ 1] = inst
->dst
.reg_offset
+ 1;
201 channels_remaining
-= inst
->regs_written
;
204 if (channels_remaining
)
207 bool can_coalesce
= true;
208 for (int i
= 0; i
< src_size
; i
++) {
209 if (reg_to_offset
[i
] != reg_to_offset
[0] + i
) {
210 /* Registers are out-of-order. */
211 can_coalesce
= false;
216 var_to
[i
] = live_intervals
->var_from_vgrf
[reg_to
] + reg_to_offset
[i
];
217 var_from
[i
] = live_intervals
->var_from_vgrf
[reg_from
] + i
;
219 if (!can_coalesce_vars(live_intervals
, cfg
, inst
,
220 var_to
[i
], var_from
[i
])) {
221 can_coalesce
= false;
232 for (int i
= 0; i
< src_size
; i
++) {
234 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
235 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
236 mov
[i
]->dst
= reg_undef
;
237 for (int j
= 0; j
< mov
[i
]->sources
; j
++) {
238 mov
[i
]->src
[j
] = reg_undef
;
243 foreach_block_and_inst(block
, fs_inst
, scan_inst
, cfg
) {
244 if (scan_inst
->dst
.file
== GRF
&&
245 scan_inst
->dst
.reg
== reg_from
) {
246 scan_inst
->dst
.reg
= reg_to
;
247 scan_inst
->dst
.reg_offset
=
248 reg_to_offset
[scan_inst
->dst
.reg_offset
];
251 for (int j
= 0; j
< scan_inst
->sources
; j
++) {
252 if (scan_inst
->src
[j
].file
== GRF
&&
253 scan_inst
->src
[j
].reg
== reg_from
) {
254 scan_inst
->src
[j
].reg
= reg_to
;
255 scan_inst
->src
[j
].reg_offset
=
256 reg_to_offset
[scan_inst
->src
[j
].reg_offset
];
261 for (int i
= 0; i
< src_size
; i
++) {
262 live_intervals
->start
[var_to
[i
]] =
263 MIN2(live_intervals
->start
[var_to
[i
]],
264 live_intervals
->start
[var_from
[i
]]);
265 live_intervals
->end
[var_to
[i
]] =
266 MAX2(live_intervals
->end
[var_to
[i
]],
267 live_intervals
->end
[var_from
[i
]]);
273 foreach_block_and_inst_safe (block
, backend_instruction
, inst
, cfg
) {
274 if (inst
->opcode
== BRW_OPCODE_NOP
) {
279 invalidate_live_intervals();