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24 /** @file brw_fs_register_coalesce.cpp
26 * Implements register coalescing: Checks if the two registers involved in a
27 * raw move don't interfere, in which case they can both be stored in the same
28 * place and the MOV removed.
30 * To do this, all uses of the source of the MOV in the shader are replaced
31 * with the destination of the MOV. For example:
33 * add vgrf3:F, vgrf1:F, vgrf2:F
34 * mov vgrf4:F, vgrf3:F
35 * mul vgrf5:F, vgrf5:F, vgrf4:F
39 * add vgrf4:F, vgrf1:F, vgrf2:F
40 * mul vgrf5:F, vgrf5:F, vgrf4:F
45 #include "brw_fs_live_variables.h"
48 is_nop_mov(const fs_inst
*inst
)
50 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
51 fs_reg dst
= inst
->dst
;
52 for (int i
= 0; i
< inst
->sources
; i
++) {
54 if (!dst
.equals(inst
->src
[i
])) {
59 } else if (inst
->opcode
== BRW_OPCODE_MOV
) {
60 return inst
->dst
.equals(inst
->src
[0]);
67 is_copy_payload(const fs_inst
*inst
, int src_size
)
69 if (src_size
!= inst
->sources
)
72 const int reg
= inst
->src
[0].reg
;
73 if (inst
->src
[0].reg_offset
!= 0)
76 for (int i
= 1; i
< inst
->sources
; i
++) {
77 if (inst
->src
[i
].reg
!= reg
||
78 inst
->src
[i
].reg_offset
!= i
) {
86 is_coalesce_candidate(const fs_inst
*inst
, const int *virtual_grf_sizes
)
88 if ((inst
->opcode
!= BRW_OPCODE_MOV
&&
89 inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
) ||
90 inst
->is_partial_write() ||
92 inst
->src
[0].file
!= GRF
||
93 inst
->src
[0].negate
||
95 !inst
->src
[0].is_contiguous() ||
96 inst
->dst
.file
!= GRF
||
97 inst
->dst
.type
!= inst
->src
[0].type
) {
101 if (virtual_grf_sizes
[inst
->src
[0].reg
] >
102 virtual_grf_sizes
[inst
->dst
.reg
])
105 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
106 if (!is_copy_payload(inst
, virtual_grf_sizes
[inst
->src
[0].reg
])) {
115 can_coalesce_vars(brw::fs_live_variables
*live_intervals
,
116 const exec_list
*instructions
, const fs_inst
*inst
,
117 int var_to
, int var_from
)
119 if (!live_intervals
->vars_interfere(var_from
, var_to
))
122 int start_to
= live_intervals
->start
[var_to
];
123 int end_to
= live_intervals
->end
[var_to
];
124 int start_from
= live_intervals
->start
[var_from
];
125 int end_from
= live_intervals
->end
[var_from
];
127 /* Variables interfere and one line range isn't a subset of the other. */
128 if ((end_to
> end_from
&& start_from
< start_to
) ||
129 (end_from
> end_to
&& start_to
< start_from
))
132 int start_ip
= MIN2(start_to
, start_from
);
135 foreach_in_list(fs_inst
, scan_inst
, instructions
) {
138 if (scan_ip
< start_ip
)
141 if (scan_inst
->is_control_flow())
144 if (scan_ip
<= live_intervals
->start
[var_to
])
147 if (scan_ip
> live_intervals
->end
[var_to
])
150 if (scan_inst
->dst
.equals(inst
->dst
) ||
151 scan_inst
->dst
.equals(inst
->src
[0]))
159 fs_visitor::register_coalesce()
161 bool progress
= false;
163 calculate_live_intervals();
166 int channels_remaining
= 0;
167 int reg_from
= -1, reg_to
= -1;
168 int reg_to_offset
[MAX_SAMPLER_MESSAGE_SIZE
];
169 fs_inst
*mov
[MAX_SAMPLER_MESSAGE_SIZE
];
170 int var_to
[MAX_SAMPLER_MESSAGE_SIZE
];
171 int var_from
[MAX_SAMPLER_MESSAGE_SIZE
];
173 foreach_in_list(fs_inst
, inst
, &instructions
) {
174 if (!is_coalesce_candidate(inst
, virtual_grf_sizes
))
177 if (is_nop_mov(inst
)) {
178 inst
->opcode
= BRW_OPCODE_NOP
;
183 if (reg_from
!= inst
->src
[0].reg
) {
184 reg_from
= inst
->src
[0].reg
;
186 src_size
= virtual_grf_sizes
[inst
->src
[0].reg
];
187 assert(src_size
<= MAX_SAMPLER_MESSAGE_SIZE
);
189 channels_remaining
= src_size
;
190 memset(mov
, 0, sizeof(mov
));
192 reg_to
= inst
->dst
.reg
;
195 if (reg_to
!= inst
->dst
.reg
)
198 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
199 for (int i
= 0; i
< src_size
; i
++) {
200 reg_to_offset
[i
] = i
;
203 channels_remaining
-= inst
->sources
;
205 const int offset
= inst
->src
[0].reg_offset
;
206 reg_to_offset
[offset
] = inst
->dst
.reg_offset
;
208 channels_remaining
--;
211 if (channels_remaining
)
214 bool can_coalesce
= true;
215 for (int i
= 0; i
< src_size
; i
++) {
216 var_to
[i
] = live_intervals
->var_from_vgrf
[reg_to
] + reg_to_offset
[i
];
217 var_from
[i
] = live_intervals
->var_from_vgrf
[reg_from
] + i
;
219 if (!can_coalesce_vars(live_intervals
, &instructions
, inst
,
220 var_to
[i
], var_from
[i
])) {
221 can_coalesce
= false;
231 bool was_load_payload
= inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
;
233 for (int i
= 0; i
< src_size
; i
++) {
235 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
236 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
237 mov
[i
]->dst
= reg_undef
;
238 for (int j
= 0; j
< mov
[i
]->sources
; j
++) {
239 mov
[i
]->src
[j
] = reg_undef
;
244 foreach_in_list(fs_inst
, scan_inst
, &instructions
) {
245 for (int i
= 0; i
< src_size
; i
++) {
246 if (mov
[i
] || was_load_payload
) {
247 if (scan_inst
->dst
.file
== GRF
&&
248 scan_inst
->dst
.reg
== reg_from
&&
249 scan_inst
->dst
.reg_offset
== i
) {
250 scan_inst
->dst
.reg
= reg_to
;
251 scan_inst
->dst
.reg_offset
= reg_to_offset
[i
];
253 for (int j
= 0; j
< scan_inst
->sources
; j
++) {
254 if (scan_inst
->src
[j
].file
== GRF
&&
255 scan_inst
->src
[j
].reg
== reg_from
&&
256 scan_inst
->src
[j
].reg_offset
== i
) {
257 scan_inst
->src
[j
].reg
= reg_to
;
258 scan_inst
->src
[j
].reg_offset
= reg_to_offset
[i
];
265 for (int i
= 0; i
< src_size
; i
++) {
266 live_intervals
->start
[var_to
[i
]] =
267 MIN2(live_intervals
->start
[var_to
[i
]],
268 live_intervals
->start
[var_from
[i
]]);
269 live_intervals
->end
[var_to
[i
]] =
270 MAX2(live_intervals
->end
[var_to
[i
]],
271 live_intervals
->end
[var_from
[i
]]);
277 foreach_block_and_inst_safe (block
, backend_instruction
, inst
, cfg
) {
278 if (inst
->opcode
== BRW_OPCODE_NOP
) {
283 invalidate_live_intervals(false);