src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_cfg.h"
  45 #include "brw_fs_live_variables.h"
  46
  47 static bool
  48 is_nop_mov(const fs_inst *inst)
  49 {
  50    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  51       fs_reg dst = inst->dst;
  52       for (int i = 0; i < inst->sources; i++) {
  53          dst.reg_offset = i;
  54          if (!dst.equals(inst->src[i])) {
  55             return false;
  56          }
  57       }
  58       return true;
  59    } else if (inst->opcode == BRW_OPCODE_MOV) {
  60       return inst->dst.equals(inst->src[0]);
  61    }
  62
  63    return false;
  64 }
  65
  66 static bool
  67 is_copy_payload(const fs_inst *inst, int src_size)
  68 {
  69    if (src_size != inst->sources)
  70       return false;
  71
  72    const int reg = inst->src[0].reg;
  73    if (inst->src[0].reg_offset != 0)
  74       return false;
  75
  76    for (int i = 1; i < inst->sources; i++) {
  77       if (inst->src[i].reg != reg ||
  78           inst->src[i].reg_offset != i) {
  79          return false;
  80       }
  81    }
  82    return true;
  83 }
  84
  85 static bool
  86 is_coalesce_candidate(const fs_inst *inst, const int *virtual_grf_sizes)
  87 {
  88    if ((inst->opcode != BRW_OPCODE_MOV &&
  89         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  90        inst->is_partial_write() ||
  91        inst->saturate ||
  92        inst->src[0].file != GRF ||
  93        inst->src[0].negate ||
  94        inst->src[0].abs ||
  95        !inst->src[0].is_contiguous() ||
  96        inst->dst.file != GRF ||
  97        inst->dst.type != inst->src[0].type) {
  98       return false;
  99    }
 100
 101    if (virtual_grf_sizes[inst->src[0].reg] >
 102        virtual_grf_sizes[inst->dst.reg])
 103       return false;
 104
 105    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 106       if (!is_copy_payload(inst, virtual_grf_sizes[inst->src[0].reg])) {
 107          return false;
 108       }
 109    }
 110
 111    return true;
 112 }
 113
 114 static bool
 115 can_coalesce_vars(brw::fs_live_variables *live_intervals,
 116                   const exec_list *instructions, const fs_inst *inst,
 117                   int var_to, int var_from)
 118 {
 119    if (!live_intervals->vars_interfere(var_from, var_to))
 120       return true;
 121
 122    int start_to = live_intervals->start[var_to];
 123    int end_to = live_intervals->end[var_to];
 124    int start_from = live_intervals->start[var_from];
 125    int end_from = live_intervals->end[var_from];
 126
 127    /* Variables interfere and one line range isn't a subset of the other. */
 128    if ((end_to > end_from && start_from < start_to) ||
 129        (end_from > end_to && start_to < start_from))
 130       return false;
 131
 132    int start_ip = MIN2(start_to, start_from);
 133    int scan_ip = -1;
 134
 135    foreach_in_list(fs_inst, scan_inst, instructions) {
 136       scan_ip++;
 137
 138       if (scan_ip < start_ip)
 139          continue;
 140
 141       if (scan_inst->is_control_flow())
 142          return false;
 143
 144       if (scan_ip <= live_intervals->start[var_to])
 145          continue;
 146
 147       if (scan_ip > live_intervals->end[var_to])
 148          break;
 149
 150       if (scan_inst->dst.equals(inst->dst) ||
 151           scan_inst->dst.equals(inst->src[0]))
 152          return false;
 153    }
 154
 155    return true;
 156 }
 157
 158 bool
 159 fs_visitor::register_coalesce()
 160 {
 161    bool progress = false;
 162
 163    calculate_live_intervals();
 164
 165    int src_size = 0;
 166    int channels_remaining = 0;
 167    int reg_from = -1, reg_to = -1;
 168    int reg_to_offset[MAX_SAMPLER_MESSAGE_SIZE];
 169    fs_inst *mov[MAX_SAMPLER_MESSAGE_SIZE];
 170    int var_to[MAX_SAMPLER_MESSAGE_SIZE];
 171    int var_from[MAX_SAMPLER_MESSAGE_SIZE];
 172
 173    foreach_in_list(fs_inst, inst, &instructions) {
 174       if (!is_coalesce_candidate(inst, virtual_grf_sizes))
 175          continue;
 176
 177       if (is_nop_mov(inst)) {
 178          inst->opcode = BRW_OPCODE_NOP;
 179          progress = true;
 180          continue;
 181       }
 182
 183       if (reg_from != inst->src[0].reg) {
 184          reg_from = inst->src[0].reg;
 185
 186          src_size = virtual_grf_sizes[inst->src[0].reg];
 187          assert(src_size <= MAX_SAMPLER_MESSAGE_SIZE);
 188
 189          channels_remaining = src_size;
 190          memset(mov, 0, sizeof(mov));
 191
 192          reg_to = inst->dst.reg;
 193       }
 194
 195       if (reg_to != inst->dst.reg)
 196          continue;
 197
 198       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 199          for (int i = 0; i < src_size; i++) {
 200             reg_to_offset[i] = i;
 201          }
 202          mov[0] = inst;
 203          channels_remaining -= inst->sources;
 204       } else {
 205          const int offset = inst->src[0].reg_offset;
 206          reg_to_offset[offset] = inst->dst.reg_offset;
 207          mov[offset] = inst;
 208          channels_remaining--;
 209       }
 210
 211       if (channels_remaining)
 212          continue;
 213
 214       bool can_coalesce = true;
 215       for (int i = 0; i < src_size; i++) {
 216          var_to[i] = live_intervals->var_from_vgrf[reg_to] + reg_to_offset[i];
 217          var_from[i] = live_intervals->var_from_vgrf[reg_from] + i;
 218
 219          if (!can_coalesce_vars(live_intervals, &instructions, inst,
 220                                 var_to[i], var_from[i])) {
 221             can_coalesce = false;
 222             reg_from = -1;
 223             break;
 224          }
 225       }
 226
 227       if (!can_coalesce)
 228          continue;
 229
 230       progress = true;
 231       bool was_load_payload = inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD;
 232
 233       for (int i = 0; i < src_size; i++) {
 234          if (mov[i]) {
 235             mov[i]->opcode = BRW_OPCODE_NOP;
 236             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 237             mov[i]->dst = reg_undef;
 238             for (int j = 0; j < mov[i]->sources; j++) {
 239                mov[i]->src[j] = reg_undef;
 240             }
 241          }
 242       }
 243
 244       foreach_in_list(fs_inst, scan_inst, &instructions) {
 245          for (int i = 0; i < src_size; i++) {
 246             if (mov[i] || was_load_payload) {
 247                if (scan_inst->dst.file == GRF &&
 248                    scan_inst->dst.reg == reg_from &&
 249                    scan_inst->dst.reg_offset == i) {
 250                   scan_inst->dst.reg = reg_to;
 251                   scan_inst->dst.reg_offset = reg_to_offset[i];
 252                }
 253                for (int j = 0; j < scan_inst->sources; j++) {
 254                   if (scan_inst->src[j].file == GRF &&
 255                       scan_inst->src[j].reg == reg_from &&
 256                       scan_inst->src[j].reg_offset == i) {
 257                      scan_inst->src[j].reg = reg_to;
 258                      scan_inst->src[j].reg_offset = reg_to_offset[i];
 259                   }
 260                }
 261             }
 262          }
 263       }
 264
 265       for (int i = 0; i < src_size; i++) {
 266          live_intervals->start[var_to[i]] =
 267             MIN2(live_intervals->start[var_to[i]],
 268                  live_intervals->start[var_from[i]]);
 269          live_intervals->end[var_to[i]] =
 270             MAX2(live_intervals->end[var_to[i]],
 271                  live_intervals->end[var_from[i]]);
 272       }
 273       reg_from = -1;
 274    }
 275
 276    if (progress) {
 277       foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
 278          if (inst->opcode == BRW_OPCODE_NOP) {
 279             inst->remove(block);
 280          }
 281       }
 282
 283       invalidate_live_intervals();
 284    }
 285
 286    return progress;
 287 }