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24 /** @file brw_fs_register_coalesce.cpp
26 * Implements register coalescing: Checks if the two registers involved in a
27 * raw move don't interfere, in which case they can both be stored in the same
28 * place and the MOV removed.
30 * To do this, all uses of the source of the MOV in the shader are replaced
31 * with the destination of the MOV. For example:
33 * add vgrf3:F, vgrf1:F, vgrf2:F
34 * mov vgrf4:F, vgrf3:F
35 * mul vgrf5:F, vgrf5:F, vgrf4:F
39 * add vgrf4:F, vgrf1:F, vgrf2:F
40 * mul vgrf5:F, vgrf5:F, vgrf4:F
45 #include "brw_fs_live_variables.h"
48 is_nop_mov(const fs_inst
*inst
)
50 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
51 fs_reg dst
= inst
->dst
;
52 for (int i
= 0; i
< inst
->sources
; i
++) {
54 if (!dst
.equals(inst
->src
[i
])) {
59 } else if (inst
->opcode
== BRW_OPCODE_MOV
) {
60 return inst
->dst
.equals(inst
->src
[0]);
67 is_copy_payload(const fs_visitor
*v
, const fs_inst
*inst
)
69 if (v
->virtual_grf_sizes
[inst
->src
[0].reg
] != inst
->regs_written
)
72 fs_reg reg
= inst
->src
[0];
74 for (int i
= 0; i
< inst
->sources
; i
++)
75 if (!inst
->src
[i
].equals(offset(reg
, i
)))
82 is_coalesce_candidate(const fs_visitor
*v
, const fs_inst
*inst
)
84 if ((inst
->opcode
!= BRW_OPCODE_MOV
&&
85 inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
) ||
86 inst
->is_partial_write() ||
88 inst
->src
[0].file
!= GRF
||
89 inst
->src
[0].negate
||
91 !inst
->src
[0].is_contiguous() ||
92 inst
->dst
.file
!= GRF
||
93 inst
->dst
.type
!= inst
->src
[0].type
) {
97 if (v
->virtual_grf_sizes
[inst
->src
[0].reg
] >
98 v
->virtual_grf_sizes
[inst
->dst
.reg
])
101 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
102 if (!is_copy_payload(v
, inst
)) {
111 can_coalesce_vars(brw::fs_live_variables
*live_intervals
,
112 const cfg_t
*cfg
, const fs_inst
*inst
,
113 int var_to
, int var_from
)
115 if (!live_intervals
->vars_interfere(var_from
, var_to
))
118 int start_to
= live_intervals
->start
[var_to
];
119 int end_to
= live_intervals
->end
[var_to
];
120 int start_from
= live_intervals
->start
[var_from
];
121 int end_from
= live_intervals
->end
[var_from
];
123 /* Variables interfere and one line range isn't a subset of the other. */
124 if ((end_to
> end_from
&& start_from
< start_to
) ||
125 (end_from
> end_to
&& start_to
< start_from
))
128 int start_ip
= MIN2(start_to
, start_from
);
131 foreach_block_and_inst(block
, fs_inst
, scan_inst
, cfg
) {
134 if (scan_ip
< start_ip
)
137 if (scan_inst
->is_control_flow())
140 if (scan_ip
<= live_intervals
->start
[var_to
])
143 if (scan_ip
> live_intervals
->end
[var_to
])
146 if (scan_inst
->dst
.equals(inst
->dst
) ||
147 scan_inst
->dst
.equals(inst
->src
[0]))
155 fs_visitor::register_coalesce()
157 bool progress
= false;
159 calculate_live_intervals();
162 int channels_remaining
= 0;
163 int reg_from
= -1, reg_to
= -1;
164 int reg_to_offset
[MAX_SAMPLER_MESSAGE_SIZE
];
165 fs_inst
*mov
[MAX_SAMPLER_MESSAGE_SIZE
];
166 int var_to
[MAX_SAMPLER_MESSAGE_SIZE
];
167 int var_from
[MAX_SAMPLER_MESSAGE_SIZE
];
169 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
170 if (!is_coalesce_candidate(this, inst
))
173 if (is_nop_mov(inst
)) {
174 inst
->opcode
= BRW_OPCODE_NOP
;
179 if (reg_from
!= inst
->src
[0].reg
) {
180 reg_from
= inst
->src
[0].reg
;
182 src_size
= virtual_grf_sizes
[inst
->src
[0].reg
];
183 assert(src_size
<= MAX_SAMPLER_MESSAGE_SIZE
);
185 assert(inst
->src
[0].width
% 8 == 0);
186 channels_remaining
= src_size
;
187 memset(mov
, 0, sizeof(mov
));
189 reg_to
= inst
->dst
.reg
;
192 if (reg_to
!= inst
->dst
.reg
)
195 if (inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
) {
196 for (int i
= 0; i
< src_size
; i
++) {
197 reg_to_offset
[i
] = i
;
200 channels_remaining
-= inst
->regs_written
;
202 const int offset
= inst
->src
[0].reg_offset
;
203 reg_to_offset
[offset
] = inst
->dst
.reg_offset
;
204 if (inst
->src
[0].width
== 16)
205 reg_to_offset
[offset
+ 1] = inst
->dst
.reg_offset
+ 1;
207 channels_remaining
-= inst
->regs_written
;
210 if (channels_remaining
)
213 bool can_coalesce
= true;
214 for (int i
= 0; i
< src_size
; i
++) {
215 var_to
[i
] = live_intervals
->var_from_vgrf
[reg_to
] + reg_to_offset
[i
];
216 var_from
[i
] = live_intervals
->var_from_vgrf
[reg_from
] + i
;
218 if (!can_coalesce_vars(live_intervals
, cfg
, inst
,
219 var_to
[i
], var_from
[i
])) {
220 can_coalesce
= false;
230 bool was_load_payload
= inst
->opcode
== SHADER_OPCODE_LOAD_PAYLOAD
;
232 for (int i
= 0; i
< src_size
; i
++) {
234 mov
[i
]->opcode
= BRW_OPCODE_NOP
;
235 mov
[i
]->conditional_mod
= BRW_CONDITIONAL_NONE
;
236 mov
[i
]->dst
= reg_undef
;
237 for (int j
= 0; j
< mov
[i
]->sources
; j
++) {
238 mov
[i
]->src
[j
] = reg_undef
;
243 foreach_block_and_inst(block
, fs_inst
, scan_inst
, cfg
) {
244 for (int i
= 0; i
< src_size
; i
++) {
245 if (mov
[i
] || was_load_payload
) {
246 if (scan_inst
->dst
.file
== GRF
&&
247 scan_inst
->dst
.reg
== reg_from
&&
248 scan_inst
->dst
.reg_offset
== i
) {
249 scan_inst
->dst
.reg
= reg_to
;
250 scan_inst
->dst
.reg_offset
= reg_to_offset
[i
];
252 for (int j
= 0; j
< scan_inst
->sources
; j
++) {
253 if (scan_inst
->src
[j
].file
== GRF
&&
254 scan_inst
->src
[j
].reg
== reg_from
&&
255 scan_inst
->src
[j
].reg_offset
== i
) {
256 scan_inst
->src
[j
].reg
= reg_to
;
257 scan_inst
->src
[j
].reg_offset
= reg_to_offset
[i
];
264 for (int i
= 0; i
< src_size
; i
++) {
265 live_intervals
->start
[var_to
[i
]] =
266 MIN2(live_intervals
->start
[var_to
[i
]],
267 live_intervals
->start
[var_from
[i
]]);
268 live_intervals
->end
[var_to
[i
]] =
269 MAX2(live_intervals
->end
[var_to
[i
]],
270 live_intervals
->end
[var_from
[i
]]);
276 foreach_block_and_inst_safe (block
, backend_instruction
, inst
, cfg
) {
277 if (inst
->opcode
== BRW_OPCODE_NOP
) {
282 invalidate_live_intervals();