src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_cfg.h"
  45 #include "brw_fs_live_variables.h"
  46
  47 static bool
  48 is_nop_mov(const fs_inst *inst)
  49 {
  50    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  51       fs_reg dst = inst->dst;
  52       for (int i = 0; i < inst->sources; i++) {
  53          dst.reg_offset = i;
  54          if (!dst.equals(inst->src[i])) {
  55             return false;
  56          }
  57       }
  58       return true;
  59    } else if (inst->opcode == BRW_OPCODE_MOV) {
  60       return inst->dst.equals(inst->src[0]);
  61    }
  62
  63    return false;
  64 }
  65
  66 static bool
  67 is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
  68 {
  69    if ((inst->opcode != BRW_OPCODE_MOV &&
  70         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  71        inst->is_partial_write() ||
  72        inst->saturate ||
  73        inst->src[0].file != GRF ||
  74        inst->src[0].negate ||
  75        inst->src[0].abs ||
  76        !inst->src[0].is_contiguous() ||
  77        inst->dst.file != GRF ||
  78        inst->dst.type != inst->src[0].type) {
  79       return false;
  80    }
  81
  82    if (v->alloc.sizes[inst->src[0].reg] >
  83        v->alloc.sizes[inst->dst.reg])
  84       return false;
  85
  86    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  87       if (!inst->is_copy_payload(v->alloc)) {
  88          return false;
  89       }
  90    }
  91
  92    return true;
  93 }
  94
  95 static bool
  96 can_coalesce_vars(brw::fs_live_variables *live_intervals,
  97                   const cfg_t *cfg, const fs_inst *inst,
  98                   int var_to, int var_from)
  99 {
 100    if (!live_intervals->vars_interfere(var_from, var_to))
 101       return true;
 102
 103    int start_to = live_intervals->start[var_to];
 104    int end_to = live_intervals->end[var_to];
 105    int start_from = live_intervals->start[var_from];
 106    int end_from = live_intervals->end[var_from];
 107
 108    /* Variables interfere and one line range isn't a subset of the other. */
 109    if ((end_to > end_from && start_from < start_to) ||
 110        (end_from > end_to && start_to < start_from))
 111       return false;
 112
 113    int start_ip = MIN2(start_to, start_from);
 114    int scan_ip = -1;
 115
 116    foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 117       scan_ip++;
 118
 119       if (scan_ip < start_ip)
 120          continue;
 121
 122       if (scan_inst->is_control_flow())
 123          return false;
 124
 125       if (scan_ip <= live_intervals->start[var_to])
 126          continue;
 127
 128       if (scan_ip > live_intervals->end[var_to])
 129          return true;
 130
 131       if (scan_inst->dst.equals(inst->dst) ||
 132           scan_inst->dst.equals(inst->src[0]))
 133          return false;
 134    }
 135
 136    return true;
 137 }
 138
 139 bool
 140 fs_visitor::register_coalesce()
 141 {
 142    bool progress = false;
 143
 144    calculate_live_intervals();
 145
 146    int src_size = 0;
 147    int channels_remaining = 0;
 148    int reg_from = -1, reg_to = -1;
 149    int reg_to_offset[MAX_VGRF_SIZE];
 150    fs_inst *mov[MAX_VGRF_SIZE];
 151    int var_to[MAX_VGRF_SIZE];
 152    int var_from[MAX_VGRF_SIZE];
 153
 154    foreach_block_and_inst(block, fs_inst, inst, cfg) {
 155       if (!is_coalesce_candidate(this, inst))
 156          continue;
 157
 158       if (is_nop_mov(inst)) {
 159          inst->opcode = BRW_OPCODE_NOP;
 160          progress = true;
 161          continue;
 162       }
 163
 164       if (reg_from != inst->src[0].reg) {
 165          reg_from = inst->src[0].reg;
 166
 167          src_size = alloc.sizes[inst->src[0].reg];
 168          assert(src_size <= MAX_VGRF_SIZE);
 169
 170          assert(inst->src[0].width % 8 == 0);
 171          channels_remaining = src_size;
 172          memset(mov, 0, sizeof(mov));
 173
 174          reg_to = inst->dst.reg;
 175       }
 176
 177       if (reg_to != inst->dst.reg)
 178          continue;
 179
 180       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 181          for (int i = 0; i < src_size; i++) {
 182             reg_to_offset[i] = i;
 183          }
 184          mov[0] = inst;
 185          channels_remaining -= inst->regs_written;
 186       } else {
 187          const int offset = inst->src[0].reg_offset;
 188          if (mov[offset]) {
 189             /* This is the second time that this offset in the register has
 190              * been set.  This means, in particular, that inst->dst was
 191              * live before this instruction and that the live ranges of
 192              * inst->dst and inst->src[0] overlap and we can't coalesce the
 193              * two variables.  Let's ensure that doesn't happen.
 194              */
 195             channels_remaining = -1;
 196             continue;
 197          }
 198          reg_to_offset[offset] = inst->dst.reg_offset;
 199          if (inst->exec_size == 16)
 200             reg_to_offset[offset + 1] = inst->dst.reg_offset + 1;
 201          mov[offset] = inst;
 202          channels_remaining -= inst->regs_written;
 203       }
 204
 205       if (channels_remaining)
 206          continue;
 207
 208       bool can_coalesce = true;
 209       for (int i = 0; i < src_size; i++) {
 210          if (reg_to_offset[i] != reg_to_offset[0] + i) {
 211             /* Registers are out-of-order. */
 212             can_coalesce = false;
 213             reg_from = -1;
 214             break;
 215          }
 216
 217          var_to[i] = live_intervals->var_from_vgrf[reg_to] + reg_to_offset[i];
 218          var_from[i] = live_intervals->var_from_vgrf[reg_from] + i;
 219
 220          if (!can_coalesce_vars(live_intervals, cfg, inst,
 221                                 var_to[i], var_from[i])) {
 222             can_coalesce = false;
 223             reg_from = -1;
 224             break;
 225          }
 226       }
 227
 228       if (!can_coalesce)
 229          continue;
 230
 231       progress = true;
 232       bool was_load_payload = inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD;
 233
 234       for (int i = 0; i < src_size; i++) {
 235          if (mov[i]) {
 236             mov[i]->opcode = BRW_OPCODE_NOP;
 237             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 238             mov[i]->dst = reg_undef;
 239             for (int j = 0; j < mov[i]->sources; j++) {
 240                mov[i]->src[j] = reg_undef;
 241             }
 242          }
 243       }
 244
 245       foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 246          for (int i = 0; i < src_size; i++) {
 247             if (mov[i] || was_load_payload) {
 248                if (scan_inst->dst.file == GRF &&
 249                    scan_inst->dst.reg == reg_from &&
 250                    scan_inst->dst.reg_offset == i) {
 251                   scan_inst->dst.reg = reg_to;
 252                   scan_inst->dst.reg_offset = reg_to_offset[i];
 253                }
 254                for (int j = 0; j < scan_inst->sources; j++) {
 255                   if (scan_inst->src[j].file == GRF &&
 256                       scan_inst->src[j].reg == reg_from &&
 257                       scan_inst->src[j].reg_offset == i) {
 258                      scan_inst->src[j].reg = reg_to;
 259                      scan_inst->src[j].reg_offset = reg_to_offset[i];
 260                   }
 261                }
 262             }
 263          }
 264       }
 265
 266       for (int i = 0; i < src_size; i++) {
 267          live_intervals->start[var_to[i]] =
 268             MIN2(live_intervals->start[var_to[i]],
 269                  live_intervals->start[var_from[i]]);
 270          live_intervals->end[var_to[i]] =
 271             MAX2(live_intervals->end[var_to[i]],
 272                  live_intervals->end[var_from[i]]);
 273       }
 274       reg_from = -1;
 275    }
 276
 277    if (progress) {
 278       foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
 279          if (inst->opcode == BRW_OPCODE_NOP) {
 280             inst->remove(block);
 281          }
 282       }
 283
 284       invalidate_live_intervals();
 285    }
 286
 287    return progress;
 288 }