src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_cfg.h"
  45 #include "brw_fs_live_variables.h"
  46
  47 static bool
  48 is_nop_mov(const fs_inst *inst)
  49 {
  50    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  51       fs_reg dst = inst->dst;
  52       for (int i = 0; i < inst->sources; i++) {
  53          dst.offset = i * REG_SIZE + dst.offset % REG_SIZE;
  54          if (!dst.equals(inst->src[i])) {
  55             return false;
  56          }
  57       }
  58       return true;
  59    } else if (inst->opcode == BRW_OPCODE_MOV) {
  60       return inst->dst.equals(inst->src[0]);
  61    }
  62
  63    return false;
  64 }
  65
  66 static bool
  67 is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst)
  68 {
  69    if ((inst->opcode != BRW_OPCODE_MOV &&
  70         inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) ||
  71        inst->is_partial_write() ||
  72        inst->saturate ||
  73        inst->src[0].file != VGRF ||
  74        inst->src[0].negate ||
  75        inst->src[0].abs ||
  76        !inst->src[0].is_contiguous() ||
  77        inst->dst.file != VGRF ||
  78        inst->dst.type != inst->src[0].type) {
  79       return false;
  80    }
  81
  82    if (v->alloc.sizes[inst->src[0].nr] >
  83        v->alloc.sizes[inst->dst.nr])
  84       return false;
  85
  86    if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
  87       if (!inst->is_copy_payload(v->alloc)) {
  88          return false;
  89       }
  90    }
  91
  92    return true;
  93 }
  94
  95 static bool
  96 can_coalesce_vars(brw::fs_live_variables *live_intervals,
  97                   const cfg_t *cfg, const fs_inst *inst,
  98                   int dst_var, int src_var)
  99 {
 100    if (!live_intervals->vars_interfere(src_var, dst_var))
 101       return true;
 102
 103    int dst_start = live_intervals->start[dst_var];
 104    int dst_end = live_intervals->end[dst_var];
 105    int src_start = live_intervals->start[src_var];
 106    int src_end = live_intervals->end[src_var];
 107
 108    /* Variables interfere and one line range isn't a subset of the other. */
 109    if ((dst_end > src_end && src_start < dst_start) ||
 110        (src_end > dst_end && dst_start < src_start))
 111       return false;
 112
 113    /* Check for a write to either register in the intersection of their live
 114     * ranges.
 115     */
 116    int start_ip = MAX2(dst_start, src_start);
 117    int end_ip = MIN2(dst_end, src_end);
 118
 119    foreach_block(block, cfg) {
 120       if (block->end_ip < start_ip)
 121          continue;
 122
 123       int scan_ip = block->start_ip - 1;
 124
 125       foreach_inst_in_block(fs_inst, scan_inst, block) {
 126          scan_ip++;
 127
 128          /* Ignore anything before the intersection of the live ranges */
 129          if (scan_ip < start_ip)
 130             continue;
 131
 132          /* Ignore the copying instruction itself */
 133          if (scan_inst == inst)
 134             continue;
 135
 136          if (scan_ip > end_ip)
 137             return true; /* registers do not interfere */
 138
 139          if (scan_inst->overwrites_reg(inst->dst) ||
 140              scan_inst->overwrites_reg(inst->src[0]))
 141             return false; /* registers interfere */
 142       }
 143    }
 144
 145    return true;
 146 }
 147
 148 bool
 149 fs_visitor::register_coalesce()
 150 {
 151    bool progress = false;
 152
 153    calculate_live_intervals();
 154
 155    int src_size = 0;
 156    int channels_remaining = 0;
 157    int src_reg = -1, dst_reg = -1;
 158    int dst_reg_offset[MAX_VGRF_SIZE];
 159    fs_inst *mov[MAX_VGRF_SIZE];
 160    int dst_var[MAX_VGRF_SIZE];
 161    int src_var[MAX_VGRF_SIZE];
 162
 163    foreach_block_and_inst(block, fs_inst, inst, cfg) {
 164       if (!is_coalesce_candidate(this, inst))
 165          continue;
 166
 167       if (is_nop_mov(inst)) {
 168          inst->opcode = BRW_OPCODE_NOP;
 169          progress = true;
 170          continue;
 171       }
 172
 173       if (src_reg != inst->src[0].nr) {
 174          src_reg = inst->src[0].nr;
 175
 176          src_size = alloc.sizes[inst->src[0].nr];
 177          assert(src_size <= MAX_VGRF_SIZE);
 178
 179          channels_remaining = src_size;
 180          memset(mov, 0, sizeof(mov));
 181
 182          dst_reg = inst->dst.nr;
 183       }
 184
 185       if (dst_reg != inst->dst.nr)
 186          continue;
 187
 188       if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
 189          for (int i = 0; i < src_size; i++) {
 190             dst_reg_offset[i] = i;
 191          }
 192          mov[0] = inst;
 193          channels_remaining -= inst->regs_written;
 194       } else {
 195          const int offset = inst->src[0].offset / REG_SIZE;
 196          if (mov[offset]) {
 197             /* This is the second time that this offset in the register has
 198              * been set.  This means, in particular, that inst->dst was
 199              * live before this instruction and that the live ranges of
 200              * inst->dst and inst->src[0] overlap and we can't coalesce the
 201              * two variables.  Let's ensure that doesn't happen.
 202              */
 203             channels_remaining = -1;
 204             continue;
 205          }
 206          dst_reg_offset[offset] = inst->dst.offset / REG_SIZE;
 207          if (inst->regs_written > 1)
 208             dst_reg_offset[offset + 1] = inst->dst.offset / REG_SIZE + 1;
 209          mov[offset] = inst;
 210          channels_remaining -= inst->regs_written;
 211       }
 212
 213       if (channels_remaining)
 214          continue;
 215
 216       bool can_coalesce = true;
 217       for (int i = 0; i < src_size; i++) {
 218          if (dst_reg_offset[i] != dst_reg_offset[0] + i) {
 219             /* Registers are out-of-order. */
 220             can_coalesce = false;
 221             src_reg = -1;
 222             break;
 223          }
 224
 225          dst_var[i] = live_intervals->var_from_vgrf[dst_reg] + dst_reg_offset[i];
 226          src_var[i] = live_intervals->var_from_vgrf[src_reg] + i;
 227
 228          if (!can_coalesce_vars(live_intervals, cfg, inst,
 229                                 dst_var[i], src_var[i])) {
 230             can_coalesce = false;
 231             src_reg = -1;
 232             break;
 233          }
 234       }
 235
 236       if (!can_coalesce)
 237          continue;
 238
 239       progress = true;
 240
 241       for (int i = 0; i < src_size; i++) {
 242          if (mov[i]) {
 243             mov[i]->opcode = BRW_OPCODE_NOP;
 244             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 245             mov[i]->dst = reg_undef;
 246             for (int j = 0; j < mov[i]->sources; j++) {
 247                mov[i]->src[j] = reg_undef;
 248             }
 249          }
 250       }
 251
 252       foreach_block_and_inst(block, fs_inst, scan_inst, cfg) {
 253          if (scan_inst->dst.file == VGRF &&
 254              scan_inst->dst.nr == src_reg) {
 255             scan_inst->dst.nr = dst_reg;
 256             scan_inst->dst.offset = scan_inst->dst.offset % REG_SIZE +
 257                dst_reg_offset[scan_inst->dst.offset / REG_SIZE] * REG_SIZE;
 258          }
 259
 260          for (int j = 0; j < scan_inst->sources; j++) {
 261             if (scan_inst->src[j].file == VGRF &&
 262                 scan_inst->src[j].nr == src_reg) {
 263                scan_inst->src[j].nr = dst_reg;
 264                scan_inst->src[j].offset = scan_inst->src[j].offset % REG_SIZE +
 265                   dst_reg_offset[scan_inst->src[j].offset / REG_SIZE] * REG_SIZE;
 266             }
 267          }
 268       }
 269
 270       for (int i = 0; i < src_size; i++) {
 271          live_intervals->start[dst_var[i]] =
 272             MIN2(live_intervals->start[dst_var[i]],
 273                  live_intervals->start[src_var[i]]);
 274          live_intervals->end[dst_var[i]] =
 275             MAX2(live_intervals->end[dst_var[i]],
 276                  live_intervals->end[src_var[i]]);
 277       }
 278       src_reg = -1;
 279    }
 280
 281    if (progress) {
 282       foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) {
 283          if (inst->opcode == BRW_OPCODE_NOP) {
 284             inst->remove(block);
 285          }
 286       }
 287
 288       invalidate_live_intervals();
 289    }
 290
 291    return progress;
 292 }