src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_fs_register_coalesce.cpp
  25  *
  26  * Implements register coalescing: Checks if the two registers involved in a
  27  * raw move don't interfere, in which case they can both be stored in the same
  28  * place and the MOV removed.
  29  *
  30  * To do this, all uses of the source of the MOV in the shader are replaced
  31  * with the destination of the MOV. For example:
  32  *
  33  * add vgrf3:F, vgrf1:F, vgrf2:F
  34  * mov vgrf4:F, vgrf3:F
  35  * mul vgrf5:F, vgrf5:F, vgrf4:F
  36  *
  37  * becomes
  38  *
  39  * add vgrf4:F, vgrf1:F, vgrf2:F
  40  * mul vgrf5:F, vgrf5:F, vgrf4:F
  41  */
  42
  43 #include "brw_fs.h"
  44 #include "brw_fs_live_variables.h"
  45
  46 static bool
  47 is_nop_mov(const fs_inst *inst)
  48 {
  49    if (inst->opcode == BRW_OPCODE_MOV) {
  50       return inst->dst.equals(inst->src[0]);
  51    }
  52
  53    return false;
  54 }
  55
  56 static bool
  57 is_coalesce_candidate(const fs_inst *inst, const int *virtual_grf_sizes)
  58 {
  59    if (inst->opcode != BRW_OPCODE_MOV ||
  60        inst->is_partial_write() ||
  61        inst->saturate ||
  62        inst->src[0].file != GRF ||
  63        inst->src[0].negate ||
  64        inst->src[0].abs ||
  65        !inst->src[0].is_contiguous() ||
  66        inst->dst.file != GRF ||
  67        inst->dst.type != inst->src[0].type) {
  68       return false;
  69    }
  70
  71    if (virtual_grf_sizes[inst->src[0].reg] >
  72        virtual_grf_sizes[inst->dst.reg])
  73       return false;
  74
  75    return true;
  76 }
  77
  78 static bool
  79 can_coalesce_vars(brw::fs_live_variables *live_intervals,
  80                   const exec_list *instructions, const fs_inst *inst, int ip,
  81                   int var_to, int var_from)
  82 {
  83    if (!live_intervals->vars_interfere(var_from, var_to))
  84       return true;
  85
  86    assert(ip >= live_intervals->start[var_to]);
  87
  88    fs_inst *scan_inst;
  89    for (scan_inst = (fs_inst *)inst->next;
  90         !scan_inst->is_tail_sentinel() && ip <= live_intervals->end[var_to];
  91         scan_inst = (fs_inst *)scan_inst->next, ip++) {
  92       if (scan_inst->opcode == BRW_OPCODE_WHILE)
  93          return false;
  94
  95       if (scan_inst->dst.equals(inst->dst) ||
  96           scan_inst->dst.equals(inst->src[0]))
  97          return false;
  98    }
  99
 100    return true;
 101 }
 102
 103 bool
 104 fs_visitor::register_coalesce()
 105 {
 106    bool progress = false;
 107
 108    calculate_live_intervals();
 109
 110    int src_size = 0;
 111    int channels_remaining = 0;
 112    int reg_from = -1, reg_to = -1;
 113    int reg_to_offset[MAX_SAMPLER_MESSAGE_SIZE];
 114    fs_inst *mov[MAX_SAMPLER_MESSAGE_SIZE];
 115    int var_to[MAX_SAMPLER_MESSAGE_SIZE];
 116    int var_from[MAX_SAMPLER_MESSAGE_SIZE];
 117    int ip = -1;
 118
 119    foreach_list(node, &this->instructions) {
 120       fs_inst *inst = (fs_inst *)node;
 121       ip++;
 122
 123       if (!is_coalesce_candidate(inst, virtual_grf_sizes))
 124          continue;
 125
 126       if (is_nop_mov(inst)) {
 127          inst->opcode = BRW_OPCODE_NOP;
 128          progress = true;
 129          continue;
 130       }
 131
 132       if (reg_from != inst->src[0].reg) {
 133          reg_from = inst->src[0].reg;
 134
 135          src_size = virtual_grf_sizes[inst->src[0].reg];
 136          assert(src_size <= MAX_SAMPLER_MESSAGE_SIZE);
 137
 138          channels_remaining = src_size;
 139          memset(mov, 0, sizeof(mov));
 140
 141          reg_to = inst->dst.reg;
 142       }
 143
 144       if (reg_to != inst->dst.reg)
 145          continue;
 146
 147       const int offset = inst->src[0].reg_offset;
 148       reg_to_offset[offset] = inst->dst.reg_offset;
 149       mov[offset] = inst;
 150       channels_remaining--;
 151
 152       if (channels_remaining)
 153          continue;
 154
 155       bool can_coalesce = true;
 156       for (int i = 0; i < src_size; i++) {
 157          var_to[i] = live_intervals->var_from_vgrf[reg_to] + reg_to_offset[i];
 158          var_from[i] = live_intervals->var_from_vgrf[reg_from] + i;
 159
 160          if (!can_coalesce_vars(live_intervals, &instructions, inst, ip,
 161                                 var_to[i], var_from[i])) {
 162             can_coalesce = false;
 163             reg_from = -1;
 164             break;
 165          }
 166       }
 167
 168       if (!can_coalesce)
 169          continue;
 170
 171       progress = true;
 172
 173       for (int i = 0; i < src_size; i++) {
 174          if (mov[i]) {
 175             mov[i]->opcode = BRW_OPCODE_NOP;
 176             mov[i]->conditional_mod = BRW_CONDITIONAL_NONE;
 177             mov[i]->dst = reg_undef;
 178             mov[i]->src[0] = reg_undef;
 179             mov[i]->src[1] = reg_undef;
 180             mov[i]->src[2] = reg_undef;
 181          }
 182       }
 183
 184       foreach_list(node, &this->instructions) {
 185          fs_inst *scan_inst = (fs_inst *)node;
 186
 187          for (int i = 0; i < src_size; i++) {
 188             if (mov[i]) {
 189                if (scan_inst->dst.file == GRF &&
 190                    scan_inst->dst.reg == reg_from &&
 191                    scan_inst->dst.reg_offset == i) {
 192                   scan_inst->dst.reg = reg_to;
 193                   scan_inst->dst.reg_offset = reg_to_offset[i];
 194                }
 195                for (int j = 0; j < 3; j++) {
 196                   if (scan_inst->src[j].file == GRF &&
 197                       scan_inst->src[j].reg == reg_from &&
 198                       scan_inst->src[j].reg_offset == i) {
 199                      scan_inst->src[j].reg = reg_to;
 200                      scan_inst->src[j].reg_offset = reg_to_offset[i];
 201                   }
 202                }
 203             }
 204          }
 205       }
 206
 207       for (int i = 0; i < src_size; i++) {
 208          live_intervals->start[var_to[i]] =
 209             MIN2(live_intervals->start[var_to[i]],
 210                  live_intervals->start[var_from[i]]);
 211          live_intervals->end[var_to[i]] =
 212             MAX2(live_intervals->end[var_to[i]],
 213                  live_intervals->end[var_from[i]]);
 214       }
 215       reg_from = -1;
 216    }
 217
 218    if (progress) {
 219       foreach_list_safe(node, &this->instructions) {
 220          fs_inst *inst = (fs_inst *)node;
 221
 222          if (inst->opcode == BRW_OPCODE_NOP) {
 223             inst->remove();
 224          }
 225       }
 226
 227       invalidate_live_intervals();
 228    }
 229
 230    return progress;
 231 }