2 * Copyright © 2013-2015 Intel Corporation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include "brw_fs_surface_builder.h"
30 namespace surface_access
{
33 * Generate a logical send opcode for a surface message and return
37 emit_send(const fs_builder
&bld
, enum opcode opcode
,
38 const fs_reg
&addr
, const fs_reg
&src
, const fs_reg
&surface
,
39 unsigned dims
, unsigned arg
, unsigned rsize
,
40 brw_predicate pred
= BRW_PREDICATE_NONE
)
42 /* Reduce the dynamically uniform surface index to a single
45 const fs_reg usurface
= bld
.emit_uniformize(surface
);
46 const fs_reg srcs
[] = {
47 addr
, src
, usurface
, fs_reg(dims
), fs_reg(arg
)
49 const fs_reg dst
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, rsize
);
50 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
52 inst
->regs_written
= rsize
* bld
.dispatch_width() / 8;
53 inst
->predicate
= pred
;
59 * Emit an untyped surface read opcode. \p dims determines the number
60 * of components of the address and \p size the number of components of
64 emit_untyped_read(const fs_builder
&bld
,
65 const fs_reg
&surface
, const fs_reg
&addr
,
66 unsigned dims
, unsigned size
,
69 return emit_send(bld
, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
,
70 addr
, fs_reg(), surface
, dims
, size
, size
, pred
);
74 * Emit an untyped surface write opcode. \p dims determines the number
75 * of components of the address and \p size the number of components of
79 emit_untyped_write(const fs_builder
&bld
, const fs_reg
&surface
,
80 const fs_reg
&addr
, const fs_reg
&src
,
81 unsigned dims
, unsigned size
,
84 emit_send(bld
, SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
,
85 addr
, src
, surface
, dims
, size
, 0, pred
);
89 * Emit an untyped surface atomic opcode. \p dims determines the number
90 * of components of the address and \p rsize the number of components of
91 * the returned value (either zero or one).
94 emit_untyped_atomic(const fs_builder
&bld
,
95 const fs_reg
&surface
, const fs_reg
&addr
,
96 const fs_reg
&src0
, const fs_reg
&src1
,
97 unsigned dims
, unsigned rsize
, unsigned op
,
100 /* FINISHME: Factor out this frequently recurring pattern into a
103 const unsigned n
= (src0
.file
!= BAD_FILE
) + (src1
.file
!= BAD_FILE
);
104 const fs_reg srcs
[] = { src0
, src1
};
105 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, n
);
106 bld
.LOAD_PAYLOAD(tmp
, srcs
, n
, 0);
108 return emit_send(bld
, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
,
109 addr
, tmp
, surface
, dims
, op
, rsize
, pred
);
113 * Emit a typed surface read opcode. \p dims determines the number of
114 * components of the address and \p size the number of components of the
118 emit_typed_read(const fs_builder
&bld
, const fs_reg
&surface
,
119 const fs_reg
&addr
, unsigned dims
, unsigned size
)
121 return emit_send(bld
, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
,
122 addr
, fs_reg(), surface
, dims
, size
, size
);
126 * Emit a typed surface write opcode. \p dims determines the number of
127 * components of the address and \p size the number of components of the
131 emit_typed_write(const fs_builder
&bld
, const fs_reg
&surface
,
132 const fs_reg
&addr
, const fs_reg
&src
,
133 unsigned dims
, unsigned size
)
135 emit_send(bld
, SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
,
136 addr
, src
, surface
, dims
, size
, 0);
140 * Emit a typed surface atomic opcode. \p dims determines the number of
141 * components of the address and \p rsize the number of components of
142 * the returned value (either zero or one).
145 emit_typed_atomic(const fs_builder
&bld
, const fs_reg
&surface
,
147 const fs_reg
&src0
, const fs_reg
&src1
,
148 unsigned dims
, unsigned rsize
, unsigned op
,
151 /* FINISHME: Factor out this frequently recurring pattern into a
154 const unsigned n
= (src0
.file
!= BAD_FILE
) + (src1
.file
!= BAD_FILE
);
155 const fs_reg srcs
[] = { src0
, src1
};
156 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, n
);
157 bld
.LOAD_PAYLOAD(tmp
, srcs
, n
, 0);
159 return emit_send(bld
, SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
,
160 addr
, tmp
, surface
, dims
, op
, rsize
);