2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_optimization.h"
51 #include "glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (ir
->mode
== ir_var_in
) {
62 if (!strcmp(ir
->name
, "gl_FragCoord")) {
63 reg
= emit_fragcoord_interpolation(ir
);
64 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
65 reg
= emit_frontfacing_interpolation(ir
);
67 reg
= emit_general_interpolation(ir
);
70 hash_table_insert(this->variable_ht
, reg
, ir
);
72 } else if (ir
->mode
== ir_var_out
) {
73 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
76 assert(ir
->location
== FRAG_RESULT_DATA0
);
77 assert(ir
->index
== 1);
78 this->dual_src_output
= *reg
;
79 } else if (ir
->location
== FRAG_RESULT_COLOR
) {
80 /* Writing gl_FragColor outputs to all color regions. */
81 for (unsigned int i
= 0; i
< MAX2(c
->key
.nr_color_regions
, 1); i
++) {
82 this->outputs
[i
] = *reg
;
83 this->output_components
[i
] = 4;
85 } else if (ir
->location
== FRAG_RESULT_DEPTH
) {
86 this->frag_depth
= ir
;
88 /* gl_FragData or a user-defined FS output */
89 assert(ir
->location
>= FRAG_RESULT_DATA0
&&
90 ir
->location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
93 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
94 : ir
->type
->vector_elements
;
96 /* General color output. */
97 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
98 int output
= ir
->location
- FRAG_RESULT_DATA0
+ i
;
99 this->outputs
[output
] = *reg
;
100 this->outputs
[output
].reg_offset
+= vector_elements
* i
;
101 this->output_components
[output
] = vector_elements
;
104 } else if (ir
->mode
== ir_var_uniform
) {
105 int param_index
= c
->prog_data
.nr_params
;
107 if (c
->dispatch_width
== 16) {
108 if (!variable_storage(ir
)) {
109 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
114 if (!strncmp(ir
->name
, "gl_", 3)) {
115 setup_builtin_uniform_values(ir
);
117 setup_uniform_values(ir
->location
, ir
->type
);
120 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
121 reg
->type
= brw_type_for_base_type(ir
->type
);
125 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
127 hash_table_insert(this->variable_ht
, reg
, ir
);
131 fs_visitor::visit(ir_dereference_variable
*ir
)
133 fs_reg
*reg
= variable_storage(ir
->var
);
138 fs_visitor::visit(ir_dereference_record
*ir
)
140 const glsl_type
*struct_type
= ir
->record
->type
;
142 ir
->record
->accept(this);
144 unsigned int offset
= 0;
145 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
146 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
148 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
150 this->result
.reg_offset
+= offset
;
151 this->result
.type
= brw_type_for_base_type(ir
->type
);
155 fs_visitor::visit(ir_dereference_array
*ir
)
160 ir
->array
->accept(this);
161 index
= ir
->array_index
->as_constant();
163 element_size
= type_size(ir
->type
);
164 this->result
.type
= brw_type_for_base_type(ir
->type
);
167 assert(this->result
.file
== UNIFORM
|| this->result
.file
== GRF
);
168 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
170 assert(!"FINISHME: non-constant array element");
174 /* Instruction selection: Produce a MOV.sat instead of
175 * MIN(MAX(val, 0), 1) when possible.
178 fs_visitor::try_emit_saturate(ir_expression
*ir
)
180 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
185 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
187 sat_val
->accept(this);
188 fs_reg src
= this->result
;
190 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
192 /* If the last instruction from our accept() didn't generate our
193 * src, generate a saturated MOV
195 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
196 if (!modify
|| modify
->regs_written() != 1) {
197 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
198 inst
->saturate
= true;
200 modify
->saturate
= true;
209 fs_visitor::try_emit_mad(ir_expression
*ir
, int mul_arg
)
211 /* 3-src instructions were introduced in gen6. */
215 /* MAD can only handle floating-point data. */
216 if (ir
->type
!= glsl_type::float_type
)
219 ir_rvalue
*nonmul
= ir
->operands
[1 - mul_arg
];
220 ir_expression
*mul
= ir
->operands
[mul_arg
]->as_expression();
222 if (!mul
|| mul
->operation
!= ir_binop_mul
)
225 if (nonmul
->as_constant() ||
226 mul
->operands
[0]->as_constant() ||
227 mul
->operands
[1]->as_constant())
230 nonmul
->accept(this);
231 fs_reg src0
= this->result
;
233 mul
->operands
[0]->accept(this);
234 fs_reg src1
= this->result
;
236 mul
->operands
[1]->accept(this);
237 fs_reg src2
= this->result
;
239 this->result
= fs_reg(this, ir
->type
);
240 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
246 fs_visitor::visit(ir_expression
*ir
)
248 unsigned int operand
;
252 assert(ir
->get_num_operands() <= 2);
254 if (try_emit_saturate(ir
))
256 if (ir
->operation
== ir_binop_add
) {
257 if (try_emit_mad(ir
, 0) || try_emit_mad(ir
, 1))
261 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
262 ir
->operands
[operand
]->accept(this);
263 if (this->result
.file
== BAD_FILE
) {
265 fail("Failed to get tree for expression operand:\n");
266 ir
->operands
[operand
]->accept(&v
);
268 op
[operand
] = this->result
;
270 /* Matrix expression operands should have been broken down to vector
271 * operations already.
273 assert(!ir
->operands
[operand
]->type
->is_matrix());
274 /* And then those vector operands should have been broken down to scalar.
276 assert(!ir
->operands
[operand
]->type
->is_vector());
279 /* Storage for our result. If our result goes into an assignment, it will
280 * just get copy-propagated out, so no worries.
282 this->result
= fs_reg(this, ir
->type
);
284 switch (ir
->operation
) {
285 case ir_unop_logic_not
:
286 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
287 * ones complement of the whole register, not just bit 0.
289 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
292 op
[0].negate
= !op
[0].negate
;
293 this->result
= op
[0];
297 op
[0].negate
= false;
298 this->result
= op
[0];
301 temp
= fs_reg(this, ir
->type
);
303 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
305 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
306 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
307 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
308 inst
->predicated
= true;
310 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
311 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
312 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
313 inst
->predicated
= true;
317 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
321 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
324 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
328 assert(!"not reached: should be handled by ir_explog_to_explog2");
331 case ir_unop_sin_reduced
:
332 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
335 case ir_unop_cos_reduced
:
336 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
340 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
343 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
347 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
350 assert(!"not reached: should be handled by ir_sub_to_add_neg");
354 if (ir
->type
->is_integer()) {
355 /* For integer multiplication, the MUL uses the low 16 bits
356 * of one of the operands (src0 on gen6, src1 on gen7). The
357 * MACH accumulates in the contribution of the upper 16 bits
360 * FINISHME: Emit just the MUL if we know an operand is small
363 if (intel
->gen
>= 7 && c
->dispatch_width
== 16)
364 fail("16-wide explicit accumulator operands unsupported\n");
366 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
368 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
369 emit(BRW_OPCODE_MACH
, reg_null_d
, op
[0], op
[1]);
370 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(acc
));
372 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
376 if (intel
->gen
>= 7 && c
->dispatch_width
== 16)
377 fail("16-wide INTDIV unsupported\n");
379 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
380 assert(ir
->type
->is_integer());
381 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
384 if (intel
->gen
>= 7 && c
->dispatch_width
== 16)
385 fail("16-wide INTDIV unsupported\n");
387 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
388 assert(ir
->type
->is_integer());
389 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
393 case ir_binop_greater
:
394 case ir_binop_lequal
:
395 case ir_binop_gequal
:
397 case ir_binop_all_equal
:
398 case ir_binop_nequal
:
399 case ir_binop_any_nequal
:
401 /* original gen4 does implicit conversion before comparison. */
403 temp
.type
= op
[0].type
;
405 resolve_ud_negate(&op
[0]);
406 resolve_ud_negate(&op
[1]);
408 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
409 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
411 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
412 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
415 case ir_binop_logic_xor
:
416 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
419 case ir_binop_logic_or
:
420 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
423 case ir_binop_logic_and
:
424 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
429 assert(!"not reached: should be handled by brw_fs_channel_expressions");
433 assert(!"not reached: should be handled by lower_noise");
436 case ir_quadop_vector
:
437 assert(!"not reached: should be handled by lower_quadop_vector");
441 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
445 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
448 case ir_unop_bitcast_i2f
:
449 case ir_unop_bitcast_u2f
:
450 op
[0].type
= BRW_REGISTER_TYPE_F
;
451 this->result
= op
[0];
454 case ir_unop_bitcast_f2u
:
455 op
[0].type
= BRW_REGISTER_TYPE_UD
;
456 this->result
= op
[0];
459 case ir_unop_bitcast_f2i
:
460 op
[0].type
= BRW_REGISTER_TYPE_D
;
461 this->result
= op
[0];
467 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
471 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], fs_reg(1));
474 temp
= fs_reg(this, glsl_type::int_type
);
475 emit(BRW_OPCODE_AND
, temp
, op
[0], fs_reg(1));
476 emit(BRW_OPCODE_MOV
, this->result
, temp
);
480 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
));
481 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
482 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
485 assert(op
[0].type
== BRW_REGISTER_TYPE_D
);
487 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0));
488 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
489 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
493 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
496 op
[0].negate
= !op
[0].negate
;
497 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
498 this->result
.negate
= true;
501 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
504 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
506 case ir_unop_round_even
:
507 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
511 resolve_ud_negate(&op
[0]);
512 resolve_ud_negate(&op
[1]);
514 if (intel
->gen
>= 6) {
515 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
516 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
518 /* Unalias the destination */
519 this->result
= fs_reg(this, ir
->type
);
521 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
522 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
524 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
525 inst
->predicated
= true;
529 resolve_ud_negate(&op
[0]);
530 resolve_ud_negate(&op
[1]);
532 if (intel
->gen
>= 6) {
533 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
534 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
536 /* Unalias the destination */
537 this->result
= fs_reg(this, ir
->type
);
539 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
540 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
542 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
543 inst
->predicated
= true;
548 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
551 case ir_unop_bit_not
:
552 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
554 case ir_binop_bit_and
:
555 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
557 case ir_binop_bit_xor
:
558 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
560 case ir_binop_bit_or
:
561 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
564 case ir_binop_lshift
:
565 inst
= emit(BRW_OPCODE_SHL
, this->result
, op
[0], op
[1]);
568 case ir_binop_rshift
:
569 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
570 inst
= emit(BRW_OPCODE_ASR
, this->result
, op
[0], op
[1]);
572 inst
= emit(BRW_OPCODE_SHR
, this->result
, op
[0], op
[1]);
578 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
579 const glsl_type
*type
, bool predicated
)
581 switch (type
->base_type
) {
582 case GLSL_TYPE_FLOAT
:
586 for (unsigned int i
= 0; i
< type
->components(); i
++) {
587 l
.type
= brw_type_for_base_type(type
);
588 r
.type
= brw_type_for_base_type(type
);
590 if (predicated
|| !l
.equals(r
)) {
591 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
592 inst
->predicated
= predicated
;
599 case GLSL_TYPE_ARRAY
:
600 for (unsigned int i
= 0; i
< type
->length
; i
++) {
601 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
605 case GLSL_TYPE_STRUCT
:
606 for (unsigned int i
= 0; i
< type
->length
; i
++) {
607 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
612 case GLSL_TYPE_SAMPLER
:
616 assert(!"not reached");
621 /* If the RHS processing resulted in an instruction generating a
622 * temporary value, and it would be easy to rewrite the instruction to
623 * generate its result right into the LHS instead, do so. This ends
624 * up reliably removing instructions where it can be tricky to do so
625 * later without real UD chain information.
628 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
631 fs_inst
*pre_rhs_inst
,
632 fs_inst
*last_rhs_inst
)
634 /* Only attempt if we're doing a direct assignment. */
636 !(ir
->lhs
->type
->is_scalar() ||
637 (ir
->lhs
->type
->is_vector() &&
638 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
641 /* Make sure the last instruction generated our source reg. */
642 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
648 /* If last_rhs_inst wrote a different number of components than our LHS,
649 * we can't safely rewrite it.
651 if (ir
->lhs
->type
->vector_elements
!= modify
->regs_written())
654 /* Success! Rewrite the instruction. */
661 fs_visitor::visit(ir_assignment
*ir
)
666 /* FINISHME: arrays on the lhs */
667 ir
->lhs
->accept(this);
670 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
672 ir
->rhs
->accept(this);
675 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
677 assert(l
.file
!= BAD_FILE
);
678 assert(r
.file
!= BAD_FILE
);
680 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
684 emit_bool_to_cond_code(ir
->condition
);
687 if (ir
->lhs
->type
->is_scalar() ||
688 ir
->lhs
->type
->is_vector()) {
689 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
690 if (ir
->write_mask
& (1 << i
)) {
691 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
693 inst
->predicated
= true;
699 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
704 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
715 if (ir
->shadow_comparitor
) {
716 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
717 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
718 coordinate
.reg_offset
++;
720 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
723 if (ir
->op
== ir_tex
) {
724 /* There's no plain shadow compare message, so we use shadow
725 * compare with a bias of 0.0.
727 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
729 } else if (ir
->op
== ir_txb
) {
730 ir
->lod_info
.bias
->accept(this);
731 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
734 assert(ir
->op
== ir_txl
);
735 ir
->lod_info
.lod
->accept(this);
736 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
740 ir
->shadow_comparitor
->accept(this);
741 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
743 } else if (ir
->op
== ir_tex
) {
744 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
745 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
746 coordinate
.reg_offset
++;
748 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
750 } else if (ir
->op
== ir_txd
) {
751 ir
->lod_info
.grad
.dPdx
->accept(this);
752 fs_reg dPdx
= this->result
;
754 ir
->lod_info
.grad
.dPdy
->accept(this);
755 fs_reg dPdy
= this->result
;
757 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
758 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
759 coordinate
.reg_offset
++;
761 /* the slots for u and v are always present, but r is optional */
762 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
765 * dPdx = dudx, dvdx, drdx
766 * dPdy = dudy, dvdy, drdy
768 * 1-arg: Does not exist.
770 * 2-arg: dudx dvdx dudy dvdy
771 * dPdx.x dPdx.y dPdy.x dPdy.y
774 * 3-arg: dudx dvdx drdx dudy dvdy drdy
775 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
778 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
779 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
782 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
784 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
785 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
788 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
789 } else if (ir
->op
== ir_txs
) {
790 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
792 ir
->lod_info
.lod
->accept(this);
793 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
796 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
797 * instructions. We'll need to do SIMD16 here.
800 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
802 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
803 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
805 coordinate
.reg_offset
++;
808 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
809 * be necessary for TXF (ld), but seems wise to do for all messages.
811 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
812 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
815 /* lod/bias appears after u/v/r. */
818 if (ir
->op
== ir_txb
) {
819 ir
->lod_info
.bias
->accept(this);
820 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
823 ir
->lod_info
.lod
->accept(this);
824 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, this->result
.type
),
829 /* The unused upper half. */
834 /* Now, since we're doing simd16, the return is 2 interleaved
835 * vec4s where the odd-indexed ones are junk. We'll need to move
836 * this weirdness around to the expected layout.
839 const glsl_type
*vec_type
=
840 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
841 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
842 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
843 : BRW_REGISTER_TYPE_F
;
846 fs_inst
*inst
= NULL
;
849 inst
= emit(SHADER_OPCODE_TEX
, dst
);
852 inst
= emit(FS_OPCODE_TXB
, dst
);
855 inst
= emit(SHADER_OPCODE_TXL
, dst
);
858 inst
= emit(SHADER_OPCODE_TXD
, dst
);
861 inst
= emit(SHADER_OPCODE_TXS
, dst
);
864 inst
= emit(SHADER_OPCODE_TXF
, dst
);
867 inst
->base_mrf
= base_mrf
;
869 inst
->header_present
= true;
872 for (int i
= 0; i
< 4; i
++) {
873 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
874 orig_dst
.reg_offset
++;
882 /* gen5's sampler has slots for u, v, r, array index, then optional
883 * parameters like shadow comparitor or LOD bias. If optional
884 * parameters aren't present, those base slots are optional and don't
885 * need to be included in the message.
887 * We don't fill in the unnecessary slots regardless, which may look
888 * surprising in the disassembly.
891 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
896 int reg_width
= c
->dispatch_width
/ 8;
897 bool header_present
= false;
898 const int vector_elements
=
899 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
901 if (ir
->offset
!= NULL
&& ir
->op
== ir_txf
) {
902 /* It appears that the ld instruction used for txf does its
903 * address bounds check before adding in the offset. To work
904 * around this, just add the integer offset to the integer texel
905 * coordinate, and don't put the offset in the header.
907 ir_constant
*offset
= ir
->offset
->as_constant();
908 for (int i
= 0; i
< vector_elements
; i
++) {
910 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
913 coordinate
.reg_offset
++;
917 /* The offsets set up by the ir_texture visitor are in the
918 * m1 header, so we can't go headerless.
920 header_present
= true;
925 for (int i
= 0; i
< vector_elements
; i
++) {
927 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
, coordinate
.type
),
929 coordinate
.reg_offset
++;
932 mlen
+= vector_elements
* reg_width
;
934 if (ir
->shadow_comparitor
) {
935 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
937 ir
->shadow_comparitor
->accept(this);
938 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
942 fs_inst
*inst
= NULL
;
945 inst
= emit(SHADER_OPCODE_TEX
, dst
);
948 ir
->lod_info
.bias
->accept(this);
949 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
950 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
953 inst
= emit(FS_OPCODE_TXB
, dst
);
957 ir
->lod_info
.lod
->accept(this);
958 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
959 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
962 inst
= emit(SHADER_OPCODE_TXL
, dst
);
965 ir
->lod_info
.grad
.dPdx
->accept(this);
966 fs_reg dPdx
= this->result
;
968 ir
->lod_info
.grad
.dPdy
->accept(this);
969 fs_reg dPdy
= this->result
;
971 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
975 * dPdx = dudx, dvdx, drdx
976 * dPdy = dudy, dvdy, drdy
978 * Load up these values:
979 * - dudx dudy dvdx dvdy drdx drdy
980 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
982 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
983 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
987 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
992 inst
= emit(SHADER_OPCODE_TXD
, dst
);
996 ir
->lod_info
.lod
->accept(this);
997 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
999 inst
= emit(SHADER_OPCODE_TXS
, dst
);
1002 mlen
= header_present
+ 4 * reg_width
;
1004 ir
->lod_info
.lod
->accept(this);
1005 emit(BRW_OPCODE_MOV
,
1006 fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
1008 inst
= emit(SHADER_OPCODE_TXF
, dst
);
1011 inst
->base_mrf
= base_mrf
;
1013 inst
->header_present
= header_present
;
1016 fail("Message length >11 disallowed by hardware\n");
1023 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
1028 int reg_width
= c
->dispatch_width
/ 8;
1029 bool header_present
= false;
1032 if (ir
->offset
&& ir
->op
!= ir_txf
) {
1033 /* The offsets set up by the ir_texture visitor are in the
1034 * m1 header, so we can't go headerless.
1036 header_present
= true;
1041 if (ir
->shadow_comparitor
) {
1042 ir
->shadow_comparitor
->accept(this);
1043 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1047 /* Set up the LOD info */
1052 ir
->lod_info
.bias
->accept(this);
1053 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1057 ir
->lod_info
.lod
->accept(this);
1058 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
1062 if (c
->dispatch_width
== 16)
1063 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1065 ir
->lod_info
.grad
.dPdx
->accept(this);
1066 fs_reg dPdx
= this->result
;
1068 ir
->lod_info
.grad
.dPdy
->accept(this);
1069 fs_reg dPdy
= this->result
;
1071 /* Load dPdx and the coordinate together:
1072 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1074 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1075 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
);
1076 coordinate
.reg_offset
++;
1079 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
1083 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
1090 ir
->lod_info
.lod
->accept(this);
1091 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
1095 /* It appears that the ld instruction used for txf does its
1096 * address bounds check before adding in the offset. To work
1097 * around this, just add the integer offset to the integer texel
1098 * coordinate, and don't put the offset in the header.
1101 ir_constant
*offset
= ir
->offset
->as_constant();
1102 offsets
[0] = offset
->value
.i
[0];
1103 offsets
[1] = offset
->value
.i
[1];
1104 offsets
[2] = offset
->value
.i
[2];
1106 memset(offsets
, 0, sizeof(offsets
));
1109 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1110 emit(BRW_OPCODE_ADD
,
1111 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
, offsets
[0]);
1112 coordinate
.reg_offset
++;
1115 ir
->lod_info
.lod
->accept(this);
1116 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), this->result
);
1119 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1120 emit(BRW_OPCODE_ADD
,
1121 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
, offsets
[i
]);
1122 coordinate
.reg_offset
++;
1128 /* Set up the coordinate (except for cases where it was done above) */
1129 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1130 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1131 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
);
1132 coordinate
.reg_offset
++;
1137 /* Generate the SEND */
1138 fs_inst
*inst
= NULL
;
1140 case ir_tex
: inst
= emit(SHADER_OPCODE_TEX
, dst
); break;
1141 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1142 case ir_txl
: inst
= emit(SHADER_OPCODE_TXL
, dst
); break;
1143 case ir_txd
: inst
= emit(SHADER_OPCODE_TXD
, dst
); break;
1144 case ir_txf
: inst
= emit(SHADER_OPCODE_TXF
, dst
); break;
1145 case ir_txs
: inst
= emit(SHADER_OPCODE_TXS
, dst
); break;
1147 inst
->base_mrf
= base_mrf
;
1149 inst
->header_present
= header_present
;
1152 fail("Message length >11 disallowed by hardware\n");
1159 fs_visitor::visit(ir_texture
*ir
)
1161 fs_inst
*inst
= NULL
;
1163 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1164 sampler
= fp
->Base
.SamplerUnits
[sampler
];
1167 ir
->coordinate
->accept(this);
1168 fs_reg coordinate
= this->result
;
1170 /* Should be lowered by do_lower_texture_projection */
1171 assert(!ir
->projector
);
1173 bool needs_gl_clamp
= true;
1175 fs_reg scale_x
, scale_y
;
1177 /* The 965 requires the EU to do the normalization of GL rectangle
1178 * texture coordinates. We use the program parameter state
1179 * tracking to get the scaling factor.
1181 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
&&
1183 (intel
->gen
>= 6 && (c
->key
.tex
.gl_clamp_mask
[0] & (1 << sampler
) ||
1184 c
->key
.tex
.gl_clamp_mask
[1] & (1 << sampler
))))) {
1185 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1186 int tokens
[STATE_LENGTH
] = {
1188 STATE_TEXRECT_SCALE
,
1194 if (c
->dispatch_width
== 16) {
1195 fail("rectangle scale uniform setup not supported on 16-wide\n");
1196 this->result
= fs_reg(this, ir
->type
);
1200 scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1201 scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1203 GLuint index
= _mesa_add_state_reference(params
,
1204 (gl_state_index
*)tokens
);
1206 this->param_index
[c
->prog_data
.nr_params
] = index
;
1207 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1208 c
->prog_data
.nr_params
++;
1209 this->param_index
[c
->prog_data
.nr_params
] = index
;
1210 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1211 c
->prog_data
.nr_params
++;
1214 /* The 965 requires the EU to do the normalization of GL rectangle
1215 * texture coordinates. We use the program parameter state
1216 * tracking to get the scaling factor.
1218 if (intel
->gen
< 6 &&
1219 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1220 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1221 fs_reg src
= coordinate
;
1224 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1227 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1228 } else if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1229 /* On gen6+, the sampler handles the rectangle coordinates
1230 * natively, without needing rescaling. But that means we have
1231 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1232 * not [0, 1] like the default case below.
1234 needs_gl_clamp
= false;
1236 for (int i
= 0; i
< 2; i
++) {
1237 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1238 fs_reg chan
= coordinate
;
1239 chan
.reg_offset
+= i
;
1241 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, brw_imm_f(0.0));
1242 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1244 /* Our parameter comes in as 1.0/width or 1.0/height,
1245 * because that's what people normally want for doing
1246 * texture rectangle handling. We need width or height
1247 * for clamping, but we don't care enough to make a new
1248 * parameter type, so just invert back.
1250 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1251 emit(BRW_OPCODE_MOV
, limit
, i
== 0 ? scale_x
: scale_y
);
1252 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1254 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1255 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1260 if (ir
->coordinate
&& needs_gl_clamp
) {
1261 for (unsigned int i
= 0;
1262 i
< MIN2(ir
->coordinate
->type
->vector_elements
, 3); i
++) {
1263 if (c
->key
.tex
.gl_clamp_mask
[i
] & (1 << sampler
)) {
1264 fs_reg chan
= coordinate
;
1265 chan
.reg_offset
+= i
;
1267 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, chan
, chan
);
1268 inst
->saturate
= true;
1273 /* Writemasking doesn't eliminate channels on SIMD8 texture
1274 * samples, so don't worry about them.
1276 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1278 if (intel
->gen
>= 7) {
1279 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
1280 } else if (intel
->gen
>= 5) {
1281 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
1283 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
1286 /* The header is set up by generate_tex() when necessary. */
1287 inst
->src
[0] = reg_undef
;
1289 if (ir
->offset
!= NULL
&& ir
->op
!= ir_txf
)
1290 inst
->texture_offset
= brw_texture_offset(ir
->offset
->as_constant());
1292 inst
->sampler
= sampler
;
1294 if (ir
->shadow_comparitor
)
1295 inst
->shadow_compare
= true;
1297 swizzle_result(ir
, dst
, sampler
);
1301 * Swizzle the result of a texture result. This is necessary for
1302 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1305 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1307 this->result
= orig_val
;
1309 if (ir
->op
== ir_txs
)
1312 if (ir
->type
== glsl_type::float_type
) {
1313 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1314 assert(ir
->sampler
->type
->sampler_shadow
);
1315 } else if (c
->key
.tex
.swizzles
[sampler
] != SWIZZLE_NOOP
) {
1316 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1318 for (int i
= 0; i
< 4; i
++) {
1319 int swiz
= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1320 fs_reg l
= swizzled_result
;
1323 if (swiz
== SWIZZLE_ZERO
) {
1324 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1325 } else if (swiz
== SWIZZLE_ONE
) {
1326 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1328 fs_reg r
= orig_val
;
1329 r
.reg_offset
+= GET_SWZ(c
->key
.tex
.swizzles
[sampler
], i
);
1330 emit(BRW_OPCODE_MOV
, l
, r
);
1333 this->result
= swizzled_result
;
1338 fs_visitor::visit(ir_swizzle
*ir
)
1340 ir
->val
->accept(this);
1341 fs_reg val
= this->result
;
1343 if (ir
->type
->vector_elements
== 1) {
1344 this->result
.reg_offset
+= ir
->mask
.x
;
1348 fs_reg result
= fs_reg(this, ir
->type
);
1349 this->result
= result
;
1351 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1352 fs_reg channel
= val
;
1370 channel
.reg_offset
+= swiz
;
1371 emit(BRW_OPCODE_MOV
, result
, channel
);
1372 result
.reg_offset
++;
1377 fs_visitor::visit(ir_discard
*ir
)
1379 assert(ir
->condition
== NULL
); /* FINISHME */
1381 emit(FS_OPCODE_DISCARD
);
1385 fs_visitor::visit(ir_constant
*ir
)
1387 /* Set this->result to reg at the bottom of the function because some code
1388 * paths will cause this visitor to be applied to other fields. This will
1389 * cause the value stored in this->result to be modified.
1391 * Make reg constant so that it doesn't get accidentally modified along the
1392 * way. Yes, I actually had this problem. :(
1394 const fs_reg
reg(this, ir
->type
);
1395 fs_reg dst_reg
= reg
;
1397 if (ir
->type
->is_array()) {
1398 const unsigned size
= type_size(ir
->type
->fields
.array
);
1400 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1401 ir
->array_elements
[i
]->accept(this);
1402 fs_reg src_reg
= this->result
;
1404 dst_reg
.type
= src_reg
.type
;
1405 for (unsigned j
= 0; j
< size
; j
++) {
1406 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1407 src_reg
.reg_offset
++;
1408 dst_reg
.reg_offset
++;
1411 } else if (ir
->type
->is_record()) {
1412 foreach_list(node
, &ir
->components
) {
1413 ir_constant
*const field
= (ir_constant
*) node
;
1414 const unsigned size
= type_size(field
->type
);
1416 field
->accept(this);
1417 fs_reg src_reg
= this->result
;
1419 dst_reg
.type
= src_reg
.type
;
1420 for (unsigned j
= 0; j
< size
; j
++) {
1421 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1422 src_reg
.reg_offset
++;
1423 dst_reg
.reg_offset
++;
1427 const unsigned size
= type_size(ir
->type
);
1429 for (unsigned i
= 0; i
< size
; i
++) {
1430 switch (ir
->type
->base_type
) {
1431 case GLSL_TYPE_FLOAT
:
1432 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1434 case GLSL_TYPE_UINT
:
1435 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1438 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1440 case GLSL_TYPE_BOOL
:
1441 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1444 assert(!"Non-float/uint/int/bool constant");
1446 dst_reg
.reg_offset
++;
1454 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1456 ir_expression
*expr
= ir
->as_expression();
1462 assert(expr
->get_num_operands() <= 2);
1463 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1464 assert(expr
->operands
[i
]->type
->is_scalar());
1466 expr
->operands
[i
]->accept(this);
1467 op
[i
] = this->result
;
1469 resolve_ud_negate(&op
[i
]);
1472 switch (expr
->operation
) {
1473 case ir_unop_logic_not
:
1474 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1475 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1478 case ir_binop_logic_xor
:
1479 case ir_binop_logic_or
:
1480 case ir_binop_logic_and
:
1484 if (intel
->gen
>= 6) {
1485 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1487 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1489 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1493 if (intel
->gen
>= 6) {
1494 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1496 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1498 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1501 case ir_binop_greater
:
1502 case ir_binop_gequal
:
1504 case ir_binop_lequal
:
1505 case ir_binop_equal
:
1506 case ir_binop_all_equal
:
1507 case ir_binop_nequal
:
1508 case ir_binop_any_nequal
:
1509 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
1510 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
1512 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1513 inst
->conditional_mod
=
1514 brw_conditional_for_comparison(expr
->operation
);
1518 assert(!"not reached");
1519 fail("bad cond code\n");
1528 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1529 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1533 * Emit a gen6 IF statement with the comparison folded into the IF
1537 fs_visitor::emit_if_gen6(ir_if
*ir
)
1539 ir_expression
*expr
= ir
->condition
->as_expression();
1546 assert(expr
->get_num_operands() <= 2);
1547 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1548 assert(expr
->operands
[i
]->type
->is_scalar());
1550 expr
->operands
[i
]->accept(this);
1551 op
[i
] = this->result
;
1554 switch (expr
->operation
) {
1555 case ir_unop_logic_not
:
1556 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1557 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1560 case ir_binop_logic_xor
:
1561 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1562 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1565 case ir_binop_logic_or
:
1566 temp
= fs_reg(this, glsl_type::bool_type
);
1567 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1568 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1569 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1572 case ir_binop_logic_and
:
1573 temp
= fs_reg(this, glsl_type::bool_type
);
1574 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1575 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1576 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1580 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1581 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1585 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1586 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1589 case ir_binop_greater
:
1590 case ir_binop_gequal
:
1592 case ir_binop_lequal
:
1593 case ir_binop_equal
:
1594 case ir_binop_all_equal
:
1595 case ir_binop_nequal
:
1596 case ir_binop_any_nequal
:
1597 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1598 inst
->conditional_mod
=
1599 brw_conditional_for_comparison(expr
->operation
);
1602 assert(!"not reached");
1603 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1604 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1605 fail("bad condition\n");
1611 ir
->condition
->accept(this);
1613 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1614 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1618 fs_visitor::visit(ir_if
*ir
)
1622 if (intel
->gen
< 6 && c
->dispatch_width
== 16) {
1623 fail("Can't support (non-uniform) control flow on 16-wide\n");
1626 /* Don't point the annotation at the if statement, because then it plus
1627 * the then and else blocks get printed.
1629 this->base_ir
= ir
->condition
;
1631 if (intel
->gen
== 6) {
1634 emit_bool_to_cond_code(ir
->condition
);
1636 inst
= emit(BRW_OPCODE_IF
);
1637 inst
->predicated
= true;
1640 foreach_list(node
, &ir
->then_instructions
) {
1641 ir_instruction
*ir
= (ir_instruction
*)node
;
1647 if (!ir
->else_instructions
.is_empty()) {
1648 emit(BRW_OPCODE_ELSE
);
1650 foreach_list(node
, &ir
->else_instructions
) {
1651 ir_instruction
*ir
= (ir_instruction
*)node
;
1658 emit(BRW_OPCODE_ENDIF
);
1662 fs_visitor::visit(ir_loop
*ir
)
1664 fs_reg counter
= reg_undef
;
1666 if (intel
->gen
< 6 && c
->dispatch_width
== 16) {
1667 fail("Can't support (non-uniform) control flow on 16-wide\n");
1671 this->base_ir
= ir
->counter
;
1672 ir
->counter
->accept(this);
1673 counter
= *(variable_storage(ir
->counter
));
1676 this->base_ir
= ir
->from
;
1677 ir
->from
->accept(this);
1679 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1683 this->base_ir
= NULL
;
1684 emit(BRW_OPCODE_DO
);
1687 this->base_ir
= ir
->to
;
1688 ir
->to
->accept(this);
1690 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1691 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1693 inst
= emit(BRW_OPCODE_BREAK
);
1694 inst
->predicated
= true;
1697 foreach_list(node
, &ir
->body_instructions
) {
1698 ir_instruction
*ir
= (ir_instruction
*)node
;
1704 if (ir
->increment
) {
1705 this->base_ir
= ir
->increment
;
1706 ir
->increment
->accept(this);
1707 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1710 this->base_ir
= NULL
;
1711 emit(BRW_OPCODE_WHILE
);
1715 fs_visitor::visit(ir_loop_jump
*ir
)
1718 case ir_loop_jump::jump_break
:
1719 emit(BRW_OPCODE_BREAK
);
1721 case ir_loop_jump::jump_continue
:
1722 emit(BRW_OPCODE_CONTINUE
);
1728 fs_visitor::visit(ir_call
*ir
)
1730 assert(!"FINISHME");
1734 fs_visitor::visit(ir_return
*ir
)
1736 assert(!"FINISHME");
1740 fs_visitor::visit(ir_function
*ir
)
1742 /* Ignore function bodies other than main() -- we shouldn't see calls to
1743 * them since they should all be inlined before we get to ir_to_mesa.
1745 if (strcmp(ir
->name
, "main") == 0) {
1746 const ir_function_signature
*sig
;
1749 sig
= ir
->matching_signature(&empty
);
1753 foreach_list(node
, &sig
->body
) {
1754 ir_instruction
*ir
= (ir_instruction
*)node
;
1763 fs_visitor::visit(ir_function_signature
*ir
)
1765 assert(!"not reached");
1770 fs_visitor::emit(fs_inst inst
)
1772 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1775 if (force_uncompressed_stack
> 0)
1776 list_inst
->force_uncompressed
= true;
1777 else if (force_sechalf_stack
> 0)
1778 list_inst
->force_sechalf
= true;
1780 list_inst
->annotation
= this->current_annotation
;
1781 list_inst
->ir
= this->base_ir
;
1783 this->instructions
.push_tail(list_inst
);
1788 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1790 fs_visitor::emit_dummy_fs()
1792 int reg_width
= c
->dispatch_width
/ 8;
1794 /* Everyone's favorite color. */
1795 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
));
1796 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
));
1797 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
));
1798 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
));
1801 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1802 write
->base_mrf
= 2;
1803 write
->mlen
= 4 * reg_width
;
1807 /* The register location here is relative to the start of the URB
1808 * data. It will get adjusted to be a real location before
1809 * generate_code() time.
1812 fs_visitor::interp_reg(int location
, int channel
)
1814 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1815 int stride
= (channel
& 1) * 4;
1817 assert(urb_setup
[location
] != -1);
1819 return brw_vec1_grf(regnr
, stride
);
1822 /** Emits the interpolation for the varying inputs. */
1824 fs_visitor::emit_interpolation_setup_gen4()
1826 this->current_annotation
= "compute pixel centers";
1827 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1828 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1829 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1830 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1832 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1833 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1835 this->current_annotation
= "compute pixel deltas from v0";
1837 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1838 fs_reg(this, glsl_type::vec2_type
);
1839 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1840 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1841 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1843 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1844 fs_reg(this, glsl_type::float_type
);
1845 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1846 fs_reg(this, glsl_type::float_type
);
1848 emit(BRW_OPCODE_ADD
, this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1849 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1850 emit(BRW_OPCODE_ADD
, this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1851 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1853 this->current_annotation
= "compute pos.w and 1/pos.w";
1854 /* Compute wpos.w. It's always in our setup, since it's needed to
1855 * interpolate the other attributes.
1857 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1858 emit(FS_OPCODE_LINTERP
, wpos_w
,
1859 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1860 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1861 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1862 /* Compute the pixel 1/W value from wpos.w. */
1863 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1864 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1865 this->current_annotation
= NULL
;
1868 /** Emits the interpolation for the varying inputs. */
1870 fs_visitor::emit_interpolation_setup_gen6()
1872 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1874 /* If the pixel centers end up used, the setup is the same as for gen4. */
1875 this->current_annotation
= "compute pixel centers";
1876 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1877 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1878 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1879 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1880 emit(BRW_OPCODE_ADD
,
1882 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1883 fs_reg(brw_imm_v(0x10101010)));
1884 emit(BRW_OPCODE_ADD
,
1886 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1887 fs_reg(brw_imm_v(0x11001100)));
1889 /* As of gen6, we can no longer mix float and int sources. We have
1890 * to turn the integer pixel centers into floats for their actual
1893 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1894 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1895 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1896 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1898 this->current_annotation
= "compute pos.w";
1899 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1900 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1901 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1903 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1904 uint8_t reg
= c
->barycentric_coord_reg
[i
];
1905 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
1906 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
1909 this->current_annotation
= NULL
;
1913 fs_visitor::emit_color_write(int target
, int index
, int first_color_mrf
)
1915 int reg_width
= c
->dispatch_width
/ 8;
1917 fs_reg color
= outputs
[target
];
1920 /* If there's no color data to be written, skip it. */
1921 if (color
.file
== BAD_FILE
)
1924 color
.reg_offset
+= index
;
1926 if (c
->dispatch_width
== 8 || intel
->gen
>= 6) {
1927 /* SIMD8 write looks like:
1933 * gen6 SIMD16 DP write looks like:
1943 inst
= emit(BRW_OPCODE_MOV
,
1944 fs_reg(MRF
, first_color_mrf
+ index
* reg_width
, color
.type
),
1946 inst
->saturate
= c
->key
.clamp_fragment_color
;
1948 /* pre-gen6 SIMD16 single source DP write looks like:
1958 if (brw
->has_compr4
) {
1959 /* By setting the high bit of the MRF register number, we
1960 * indicate that we want COMPR4 mode - instead of doing the
1961 * usual destination + 1 for the second half we get
1964 inst
= emit(BRW_OPCODE_MOV
,
1965 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
,
1968 inst
->saturate
= c
->key
.clamp_fragment_color
;
1970 push_force_uncompressed();
1971 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
,
1974 inst
->saturate
= c
->key
.clamp_fragment_color
;
1975 pop_force_uncompressed();
1977 push_force_sechalf();
1978 color
.sechalf
= true;
1979 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4,
1982 inst
->saturate
= c
->key
.clamp_fragment_color
;
1983 pop_force_sechalf();
1984 color
.sechalf
= false;
1990 fs_visitor::emit_fb_writes()
1992 this->current_annotation
= "FB write header";
1993 bool header_present
= true;
1994 /* We can potentially have a message length of up to 15, so we have to set
1995 * base_mrf to either 0 or 1 in order to fit in m0..m15.
1999 int reg_width
= c
->dispatch_width
/ 8;
2000 bool do_dual_src
= this->dual_src_output
.file
!= BAD_FILE
;
2002 if (c
->dispatch_width
== 16 && do_dual_src
) {
2003 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2004 do_dual_src
= false;
2007 /* From the Sandy Bridge PRM, volume 4, page 198:
2009 * "Dispatched Pixel Enables. One bit per pixel indicating
2010 * which pixels were originally enabled when the thread was
2011 * dispatched. This field is only required for the end-of-
2012 * thread message and on all dual-source messages."
2014 if (intel
->gen
>= 6 &&
2015 !this->fp
->UsesKill
&&
2017 c
->key
.nr_color_regions
== 1) {
2018 header_present
= false;
2021 if (header_present
) {
2026 if (c
->aa_dest_stencil_reg
) {
2027 push_force_uncompressed();
2028 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
2029 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
2030 pop_force_uncompressed();
2033 /* Reserve space for color. It'll be filled in per MRT below. */
2035 nr
+= 4 * reg_width
;
2039 if (c
->source_depth_to_render_target
) {
2040 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
2041 /* For outputting oDepth on gen6, SIMD8 writes have to be
2042 * used. This would require 8-wide moves of each half to
2043 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2044 * Just bail on doing so for now.
2046 fail("Missing support for simd16 depth writes on gen6\n");
2049 if (c
->computes_depth
) {
2050 /* Hand over gl_FragDepth. */
2051 assert(this->frag_depth
);
2052 fs_reg depth
= *(variable_storage(this->frag_depth
));
2054 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
2056 /* Pass through the payload depth. */
2057 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
2058 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
2063 if (c
->dest_depth_reg
) {
2064 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
2065 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
2070 fs_reg src0
= this->outputs
[0];
2071 fs_reg src1
= this->dual_src_output
;
2073 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2075 for (int i
= 0; i
< 4; i
++) {
2076 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
2077 fs_reg(MRF
, color_mrf
+ i
, src0
.type
),
2080 inst
->saturate
= c
->key
.clamp_fragment_color
;
2083 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2085 for (int i
= 0; i
< 4; i
++) {
2086 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
2087 fs_reg(MRF
, color_mrf
+ 4 + i
, src1
.type
),
2090 inst
->saturate
= c
->key
.clamp_fragment_color
;
2093 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2095 inst
->base_mrf
= base_mrf
;
2096 inst
->mlen
= nr
- base_mrf
;
2098 inst
->header_present
= header_present
;
2100 c
->prog_data
.dual_src_blend
= true;
2101 this->current_annotation
= NULL
;
2105 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
2106 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
2107 "FB write target %d",
2109 for (unsigned i
= 0; i
< this->output_components
[target
]; i
++)
2110 emit_color_write(target
, i
, color_mrf
);
2112 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2113 inst
->target
= target
;
2114 inst
->base_mrf
= base_mrf
;
2115 inst
->mlen
= nr
- base_mrf
;
2116 if (target
== c
->key
.nr_color_regions
- 1)
2118 inst
->header_present
= header_present
;
2121 if (c
->key
.nr_color_regions
== 0) {
2122 /* Even if there's no color buffers enabled, we still need to send
2123 * alpha out the pipeline to our null renderbuffer to support
2124 * alpha-testing, alpha-to-coverage, and so on.
2126 emit_color_write(0, 3, color_mrf
);
2128 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2129 inst
->base_mrf
= base_mrf
;
2130 inst
->mlen
= nr
- base_mrf
;
2132 inst
->header_present
= header_present
;
2135 this->current_annotation
= NULL
;
2139 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2141 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2145 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2146 emit(BRW_OPCODE_MOV
, temp
, *reg
);
2151 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
2153 if (rvalue
->type
!= glsl_type::bool_type
)
2156 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
2157 emit(BRW_OPCODE_AND
, temp
, *reg
, fs_reg(1));
2161 fs_visitor::fs_visitor(struct brw_wm_compile
*c
, struct gl_shader_program
*prog
,
2162 struct brw_shader
*shader
)
2167 this->fp
= (struct gl_fragment_program
*)
2168 prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
]->Program
;
2170 this->intel
= &brw
->intel
;
2171 this->ctx
= &intel
->ctx
;
2172 this->mem_ctx
= ralloc_context(NULL
);
2173 this->shader
= shader
;
2174 this->failed
= false;
2175 this->variable_ht
= hash_table_ctor(0,
2176 hash_table_pointer_hash
,
2177 hash_table_pointer_compare
);
2179 /* There's a question that appears to be left open in the spec:
2180 * How do implicit dst conversions interact with the CMP
2181 * instruction or conditional mods? On gen6, the instruction:
2183 * CMP null<d> src0<f> src1<f>
2185 * will do src1 - src0 and compare that result as if it was an
2186 * integer. On gen4, it will do src1 - src0 as float, convert
2187 * the result to int, and compare as int. In between, it
2188 * appears that it does src1 - src0 and does the compare in the
2189 * execution type so dst type doesn't matter.
2191 if (this->intel
->gen
> 4)
2192 this->reg_null_cmp
= reg_null_d
;
2194 this->reg_null_cmp
= reg_null_f
;
2196 this->frag_depth
= NULL
;
2197 memset(this->outputs
, 0, sizeof(this->outputs
));
2198 this->first_non_payload_grf
= 0;
2199 this->max_grf
= intel
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
2201 this->current_annotation
= NULL
;
2202 this->base_ir
= NULL
;
2204 this->virtual_grf_sizes
= NULL
;
2205 this->virtual_grf_count
= 0;
2206 this->virtual_grf_array_size
= 0;
2207 this->virtual_grf_def
= NULL
;
2208 this->virtual_grf_use
= NULL
;
2209 this->live_intervals_valid
= false;
2211 this->force_uncompressed_stack
= 0;
2212 this->force_sechalf_stack
= 0;
2215 fs_visitor::~fs_visitor()
2217 ralloc_free(this->mem_ctx
);
2218 hash_table_dtor(this->variable_ht
);