2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "program/prog_parameter.h"
37 #include "program/prog_print.h"
38 #include "program/prog_optimize.h"
39 #include "util/register_allocate.h"
40 #include "program/sampler.h"
41 #include "program/hash_table.h"
42 #include "brw_context.h"
47 #include "main/uniforms.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
52 fs_visitor::visit(ir_variable
*ir
)
56 if (variable_storage(ir
))
59 if (ir
->data
.mode
== ir_var_shader_in
) {
60 if (!strcmp(ir
->name
, "gl_FragCoord")) {
61 reg
= emit_fragcoord_interpolation(ir
);
62 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
63 reg
= emit_frontfacing_interpolation();
65 reg
= emit_general_interpolation(ir
);
68 hash_table_insert(this->variable_ht
, reg
, ir
);
70 } else if (ir
->data
.mode
== ir_var_shader_out
) {
71 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
73 if (ir
->data
.index
> 0) {
74 assert(ir
->data
.location
== FRAG_RESULT_DATA0
);
75 assert(ir
->data
.index
== 1);
76 this->dual_src_output
= *reg
;
77 this->do_dual_src
= true;
78 } else if (ir
->data
.location
== FRAG_RESULT_COLOR
) {
79 /* Writing gl_FragColor outputs to all color regions. */
80 assert(stage
== MESA_SHADER_FRAGMENT
);
81 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
82 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
83 this->outputs
[i
] = *reg
;
84 this->output_components
[i
] = 4;
86 } else if (ir
->data
.location
== FRAG_RESULT_DEPTH
) {
87 this->frag_depth
= *reg
;
88 } else if (ir
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
89 this->sample_mask
= *reg
;
91 /* gl_FragData or a user-defined FS output */
92 assert(ir
->data
.location
>= FRAG_RESULT_DATA0
&&
93 ir
->data
.location
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
);
96 ir
->type
->is_array() ? ir
->type
->fields
.array
->vector_elements
97 : ir
->type
->vector_elements
;
99 /* General color output. */
100 for (unsigned int i
= 0; i
< MAX2(1, ir
->type
->length
); i
++) {
101 int output
= ir
->data
.location
- FRAG_RESULT_DATA0
+ i
;
102 this->outputs
[output
] = offset(*reg
, vector_elements
* i
);
103 this->output_components
[output
] = vector_elements
;
106 } else if (ir
->data
.mode
== ir_var_uniform
) {
107 int param_index
= uniforms
;
109 /* Thanks to the lower_ubo_reference pass, we will see only
110 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
111 * variables, so no need for them to be in variable_ht.
113 * Some uniforms, such as samplers and atomic counters, have no actual
114 * storage, so we should ignore them.
116 if (ir
->is_in_uniform_block() || type_size(ir
->type
) == 0)
119 if (dispatch_width
== 16) {
120 if (!variable_storage(ir
)) {
121 fail("Failed to find uniform '%s' in SIMD16\n", ir
->name
);
126 param_size
[param_index
] = type_size(ir
->type
);
127 if (!strncmp(ir
->name
, "gl_", 3)) {
128 setup_builtin_uniform_values(ir
);
130 setup_uniform_values(ir
);
133 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
134 reg
->type
= brw_type_for_base_type(ir
->type
);
136 } else if (ir
->data
.mode
== ir_var_system_value
) {
137 if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_POS
) {
138 reg
= emit_samplepos_setup();
139 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_ID
) {
140 reg
= emit_sampleid_setup();
141 } else if (ir
->data
.location
== SYSTEM_VALUE_SAMPLE_MASK_IN
) {
142 assert(brw
->gen
>= 7);
144 fs_reg(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
145 BRW_REGISTER_TYPE_D
));
150 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
152 hash_table_insert(this->variable_ht
, reg
, ir
);
156 fs_visitor::visit(ir_dereference_variable
*ir
)
158 fs_reg
*reg
= variable_storage(ir
->var
);
161 fail("Failed to find variable storage for %s\n", ir
->var
->name
);
162 this->result
= fs_reg(reg_null_d
);
169 fs_visitor::visit(ir_dereference_record
*ir
)
171 const glsl_type
*struct_type
= ir
->record
->type
;
173 ir
->record
->accept(this);
175 unsigned int off
= 0;
176 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
177 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
179 off
+= type_size(struct_type
->fields
.structure
[i
].type
);
181 this->result
= offset(this->result
, off
);
182 this->result
.type
= brw_type_for_base_type(ir
->type
);
186 fs_visitor::visit(ir_dereference_array
*ir
)
188 ir_constant
*constant_index
;
190 int element_size
= type_size(ir
->type
);
192 constant_index
= ir
->array_index
->as_constant();
194 ir
->array
->accept(this);
196 src
.type
= brw_type_for_base_type(ir
->type
);
198 if (constant_index
) {
199 assert(src
.file
== UNIFORM
|| src
.file
== GRF
|| src
.file
== HW_REG
);
200 src
= offset(src
, constant_index
->value
.i
[0] * element_size
);
202 /* Variable index array dereference. We attach the variable index
203 * component to the reg as a pointer to a register containing the
204 * offset. Currently only uniform arrays are supported in this patch,
205 * and that reladdr pointer is resolved by
206 * move_uniform_array_access_to_pull_constants(). All other array types
207 * are lowered by lower_variable_index_to_cond_assign().
209 ir
->array_index
->accept(this);
212 index_reg
= fs_reg(this, glsl_type::int_type
);
213 emit(BRW_OPCODE_MUL
, index_reg
, this->result
, fs_reg(element_size
));
216 emit(BRW_OPCODE_ADD
, index_reg
, *src
.reladdr
, index_reg
);
219 src
.reladdr
= ralloc(mem_ctx
, fs_reg
);
220 memcpy(src
.reladdr
, &index_reg
, sizeof(index_reg
));
226 fs_visitor::emit_lrp(const fs_reg
&dst
, const fs_reg
&x
, const fs_reg
&y
,
230 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
231 fs_reg y_times_a
= fs_reg(this, glsl_type::float_type
);
232 fs_reg one_minus_a
= fs_reg(this, glsl_type::float_type
);
233 fs_reg x_times_one_minus_a
= fs_reg(this, glsl_type::float_type
);
235 emit(MUL(y_times_a
, y
, a
));
237 fs_reg negative_a
= a
;
238 negative_a
.negate
= !a
.negate
;
239 emit(ADD(one_minus_a
, negative_a
, fs_reg(1.0f
)));
240 emit(MUL(x_times_one_minus_a
, x
, one_minus_a
));
242 emit(ADD(dst
, x_times_one_minus_a
, y_times_a
));
244 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
245 * we need to reorder the operands.
247 emit(LRP(dst
, a
, y
, x
));
252 fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod
, const fs_reg
&dst
,
253 const fs_reg
&src0
, const fs_reg
&src1
)
258 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
259 inst
->conditional_mod
= conditionalmod
;
261 emit(CMP(reg_null_d
, src0
, src1
, conditionalmod
));
263 inst
= emit(BRW_OPCODE_SEL
, dst
, src0
, src1
);
264 inst
->predicate
= BRW_PREDICATE_NORMAL
;
269 fs_visitor::try_emit_saturate(ir_expression
*ir
)
271 if (ir
->operation
!= ir_unop_saturate
)
274 ir_rvalue
*sat_val
= ir
->operands
[0];
276 fs_inst
*pre_inst
= (fs_inst
*) this->instructions
.get_tail();
278 sat_val
->accept(this);
279 fs_reg src
= this->result
;
281 fs_inst
*last_inst
= (fs_inst
*) this->instructions
.get_tail();
283 /* If the last instruction from our accept() generated our
284 * src, just set the saturate flag instead of emmitting a separate mov.
286 fs_inst
*modify
= get_instruction_generating_reg(pre_inst
, last_inst
, src
);
287 if (modify
&& modify
->regs_written
== modify
->dst
.width
/ 8 &&
288 modify
->can_do_saturate()) {
289 modify
->saturate
= true;
298 fs_visitor::try_emit_mad(ir_expression
*ir
)
300 /* 3-src instructions were introduced in gen6. */
304 /* MAD can only handle floating-point data. */
305 if (ir
->type
!= glsl_type::float_type
)
308 ir_rvalue
*nonmul
= ir
->operands
[1];
309 ir_expression
*mul
= ir
->operands
[0]->as_expression();
311 if (!mul
|| mul
->operation
!= ir_binop_mul
) {
312 nonmul
= ir
->operands
[0];
313 mul
= ir
->operands
[1]->as_expression();
315 if (!mul
|| mul
->operation
!= ir_binop_mul
)
319 if (nonmul
->as_constant() ||
320 mul
->operands
[0]->as_constant() ||
321 mul
->operands
[1]->as_constant())
324 nonmul
->accept(this);
325 fs_reg src0
= this->result
;
327 mul
->operands
[0]->accept(this);
328 fs_reg src1
= this->result
;
330 mul
->operands
[1]->accept(this);
331 fs_reg src2
= this->result
;
333 this->result
= fs_reg(this, ir
->type
);
334 emit(BRW_OPCODE_MAD
, this->result
, src0
, src1
, src2
);
340 pack_pixel_offset(float x
)
342 /* Clamp upper end of the range to +7/16. See explanation in non-constant
343 * offset case below. */
344 int n
= MIN2((int)(x
* 16), 7);
349 fs_visitor::emit_interpolate_expression(ir_expression
*ir
)
351 /* in SIMD16 mode, the pixel interpolator returns coords interleaved
352 * 8 channels at a time, same as the barycentric coords presented in
353 * the FS payload. this requires a bit of extra work to support.
355 no16("interpolate_at_* not yet supported in SIMD16 mode.");
357 assert(stage
== MESA_SHADER_FRAGMENT
);
358 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
360 ir_dereference
* deref
= ir
->operands
[0]->as_dereference();
361 ir_swizzle
* swiz
= NULL
;
363 /* the api does not allow a swizzle here, but the varying packing code
364 * may have pushed one into here.
366 swiz
= ir
->operands
[0]->as_swizzle();
368 deref
= swiz
->val
->as_dereference();
371 ir_variable
* var
= deref
->variable_referenced();
374 /* 1. collect interpolation factors */
376 fs_reg dst_x
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 2, 1));
377 fs_reg dst_y
= offset(dst_x
, 1);
379 /* for most messages, we need one reg of ignored data; the hardware requires mlen==1
380 * even when there is no payload. in the per-slot offset case, we'll replace this with
381 * the proper source data. */
382 fs_reg src
= fs_reg(this, glsl_type::float_type
);
383 int mlen
= 1; /* one reg unless overriden */
384 int reg_width
= dispatch_width
/ 8;
387 switch (ir
->operation
) {
388 case ir_unop_interpolate_at_centroid
:
389 inst
= emit(FS_OPCODE_INTERPOLATE_AT_CENTROID
, dst_x
, src
, fs_reg(0u));
392 case ir_binop_interpolate_at_sample
: {
393 ir_constant
*sample_num
= ir
->operands
[1]->as_constant();
394 assert(sample_num
|| !"nonconstant sample number should have been lowered.");
396 unsigned msg_data
= sample_num
->value
.i
[0] << 4;
397 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE
, dst_x
, src
, fs_reg(msg_data
));
401 case ir_binop_interpolate_at_offset
: {
402 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
404 unsigned msg_data
= pack_pixel_offset(const_offset
->value
.f
[0]) |
405 (pack_pixel_offset(const_offset
->value
.f
[1]) << 4);
406 inst
= emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
, dst_x
, src
,
409 /* pack the operands: hw wants offsets as 4 bit signed ints */
410 ir
->operands
[1]->accept(this);
411 src
= fs_reg(this, glsl_type::ivec2_type
);
413 for (int i
= 0; i
< 2; i
++) {
414 fs_reg temp
= fs_reg(this, glsl_type::float_type
);
415 emit(MUL(temp
, this->result
, fs_reg(16.0f
)));
416 emit(MOV(src2
, temp
)); /* float to int */
418 /* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 requires
419 * that we support a maximum offset of +0.5, which isn't representable
420 * in a S0.4 value -- if we didn't clamp it, we'd end up with -8/16,
421 * which is the opposite of what the shader author wanted.
423 * This is legal due to ARB_gpu_shader5's quantization rules:
425 * "Not all values of <offset> may be supported; x and y offsets may
426 * be rounded to fixed-point values with the number of fraction bits
427 * given by the implementation-dependent constant
428 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
431 fs_inst
*inst
= emit(BRW_OPCODE_SEL
, src2
, src2
, fs_reg(7));
432 inst
->conditional_mod
= BRW_CONDITIONAL_L
; /* min(src2, 7) */
434 src2
= offset(src2
, 1);
435 this->result
= offset(this->result
, 1);
438 mlen
= 2 * reg_width
;
439 inst
= emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
, dst_x
, src
,
446 unreachable("not reached");
450 inst
->regs_written
= 2 * reg_width
; /* 2 floats per slot returned */
451 inst
->pi_noperspective
= var
->determine_interpolation_mode(key
->flat_shade
) ==
452 INTERP_QUALIFIER_NOPERSPECTIVE
;
454 /* 2. emit linterp */
456 fs_reg
res(this, ir
->type
);
459 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
460 int ch
= swiz
? ((*(int *)&swiz
->mask
) >> 2*i
) & 3 : i
;
461 emit(FS_OPCODE_LINTERP
, res
,
463 fs_reg(interp_reg(var
->data
.location
, ch
)));
464 res
= offset(res
, 1);
469 fs_visitor::visit(ir_expression
*ir
)
471 unsigned int operand
;
474 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
476 assert(ir
->get_num_operands() <= 3);
478 if (try_emit_saturate(ir
))
481 /* Deal with the real oddball stuff first */
482 switch (ir
->operation
) {
484 if (try_emit_mad(ir
))
489 ir
->operands
[1]->accept(this);
490 op
[1] = this->result
;
491 ir
->operands
[2]->accept(this);
492 op
[2] = this->result
;
494 emit_bool_to_cond_code(ir
->operands
[0]);
496 this->result
= fs_reg(this, ir
->type
);
497 inst
= emit(SEL(this->result
, op
[1], op
[2]));
498 inst
->predicate
= BRW_PREDICATE_NORMAL
;
501 case ir_unop_interpolate_at_centroid
:
502 case ir_binop_interpolate_at_offset
:
503 case ir_binop_interpolate_at_sample
:
504 emit_interpolate_expression(ir
);
511 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
512 ir
->operands
[operand
]->accept(this);
513 if (this->result
.file
== BAD_FILE
) {
514 fail("Failed to get tree for expression operand:\n");
515 ir
->operands
[operand
]->fprint(stderr
);
516 fprintf(stderr
, "\n");
518 assert(this->result
.file
== GRF
|| this->result
.file
== UNIFORM
);
519 op
[operand
] = this->result
;
521 /* Matrix expression operands should have been broken down to vector
522 * operations already.
524 assert(!ir
->operands
[operand
]->type
->is_matrix());
525 /* And then those vector operands should have been broken down to scalar.
527 assert(!ir
->operands
[operand
]->type
->is_vector());
530 /* Storage for our result. If our result goes into an assignment, it will
531 * just get copy-propagated out, so no worries.
533 this->result
= fs_reg(this, ir
->type
);
535 switch (ir
->operation
) {
536 case ir_unop_logic_not
:
537 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
538 emit(NOT(this->result
, op
[0]));
540 emit(XOR(this->result
, op
[0], fs_reg(1u)));
544 op
[0].negate
= !op
[0].negate
;
545 emit(MOV(this->result
, op
[0]));
549 op
[0].negate
= false;
550 emit(MOV(this->result
, op
[0]));
553 if (ir
->type
->is_float()) {
554 /* AND(val, 0x80000000) gives the sign bit.
556 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
559 emit(CMP(reg_null_f
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
561 op
[0].type
= BRW_REGISTER_TYPE_UD
;
562 this->result
.type
= BRW_REGISTER_TYPE_UD
;
563 emit(AND(this->result
, op
[0], fs_reg(0x80000000u
)));
565 inst
= emit(OR(this->result
, this->result
, fs_reg(0x3f800000u
)));
566 inst
->predicate
= BRW_PREDICATE_NORMAL
;
568 this->result
.type
= BRW_REGISTER_TYPE_F
;
570 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
571 * -> non-negative val generates 0x00000000.
572 * Predicated OR sets 1 if val is positive.
574 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_G
));
576 emit(ASR(this->result
, op
[0], fs_reg(31)));
578 inst
= emit(OR(this->result
, this->result
, fs_reg(1)));
579 inst
->predicate
= BRW_PREDICATE_NORMAL
;
583 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
587 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
590 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
594 unreachable("not reached: should be handled by ir_explog_to_explog2");
596 case ir_unop_sin_reduced
:
597 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
600 case ir_unop_cos_reduced
:
601 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
605 /* Select one of the two opcodes based on the glHint value. */
606 if (fs_key
->high_quality_derivatives
)
607 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
609 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
612 case ir_unop_dFdx_coarse
:
613 emit(FS_OPCODE_DDX_COARSE
, this->result
, op
[0]);
616 case ir_unop_dFdx_fine
:
617 emit(FS_OPCODE_DDX_FINE
, this->result
, op
[0]);
621 /* Select one of the two opcodes based on the glHint value. */
622 if (fs_key
->high_quality_derivatives
)
623 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
625 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
628 case ir_unop_dFdy_coarse
:
629 emit(FS_OPCODE_DDY_COARSE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
632 case ir_unop_dFdy_fine
:
633 emit(FS_OPCODE_DDY_FINE
, result
, op
[0], fs_reg(fs_key
->render_to_fbo
));
637 emit(ADD(this->result
, op
[0], op
[1]));
640 unreachable("not reached: should be handled by ir_sub_to_add_neg");
643 if (brw
->gen
< 8 && ir
->type
->is_integer()) {
644 /* For integer multiplication, the MUL uses the low 16 bits
645 * of one of the operands (src0 on gen6, src1 on gen7). The
646 * MACH accumulates in the contribution of the upper 16 bits
649 if (ir
->operands
[0]->is_uint16_constant()) {
651 emit(MUL(this->result
, op
[0], op
[1]));
653 emit(MUL(this->result
, op
[1], op
[0]));
654 } else if (ir
->operands
[1]->is_uint16_constant()) {
656 emit(MUL(this->result
, op
[1], op
[0]));
658 emit(MUL(this->result
, op
[0], op
[1]));
661 no16("SIMD16 explicit accumulator operands unsupported\n");
663 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
666 emit(MUL(acc
, op
[0], op
[1]));
667 emit(MACH(reg_null_d
, op
[0], op
[1]));
668 emit(MOV(this->result
, fs_reg(acc
)));
671 emit(MUL(this->result
, op
[0], op
[1]));
674 case ir_binop_imul_high
: {
676 no16("SIMD16 explicit accumulator operands unsupported\n");
678 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
681 fs_inst
*mul
= emit(MUL(acc
, op
[0], op
[1]));
682 emit(MACH(this->result
, op
[0], op
[1]));
684 /* Until Gen8, integer multiplies read 32-bits from one source, and
685 * 16-bits from the other, and relying on the MACH instruction to
686 * generate the high bits of the result.
688 * On Gen8, the multiply instruction does a full 32x32-bit multiply,
689 * but in order to do a 64x64-bit multiply we have to simulate the
690 * previous behavior and then use a MACH instruction.
692 * FINISHME: Don't use source modifiers on src1.
695 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
696 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
697 if (mul
->src
[1].type
== BRW_REGISTER_TYPE_D
) {
698 mul
->src
[1].type
= BRW_REGISTER_TYPE_W
;
700 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
707 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
708 assert(ir
->type
->is_integer());
709 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
711 case ir_binop_carry
: {
713 no16("SIMD16 explicit accumulator operands unsupported\n");
715 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
716 BRW_REGISTER_TYPE_UD
);
718 emit(ADDC(reg_null_ud
, op
[0], op
[1]));
719 emit(MOV(this->result
, fs_reg(acc
)));
722 case ir_binop_borrow
: {
724 no16("SIMD16 explicit accumulator operands unsupported\n");
726 struct brw_reg acc
= retype(brw_acc_reg(dispatch_width
),
727 BRW_REGISTER_TYPE_UD
);
729 emit(SUBB(reg_null_ud
, op
[0], op
[1]));
730 emit(MOV(this->result
, fs_reg(acc
)));
734 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
735 assert(ir
->type
->is_integer());
736 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
740 case ir_binop_greater
:
741 case ir_binop_lequal
:
742 case ir_binop_gequal
:
744 case ir_binop_all_equal
:
745 case ir_binop_nequal
:
746 case ir_binop_any_nequal
:
747 if (ctx
->Const
.UniformBooleanTrue
== 1) {
748 resolve_bool_comparison(ir
->operands
[0], &op
[0]);
749 resolve_bool_comparison(ir
->operands
[1], &op
[1]);
752 emit(CMP(this->result
, op
[0], op
[1],
753 brw_conditional_for_comparison(ir
->operation
)));
756 case ir_binop_logic_xor
:
757 emit(XOR(this->result
, op
[0], op
[1]));
760 case ir_binop_logic_or
:
761 emit(OR(this->result
, op
[0], op
[1]));
764 case ir_binop_logic_and
:
765 emit(AND(this->result
, op
[0], op
[1]));
770 unreachable("not reached: should be handled by brw_fs_channel_expressions");
773 unreachable("not reached: should be handled by lower_noise");
775 case ir_quadop_vector
:
776 unreachable("not reached: should be handled by lower_quadop_vector");
778 case ir_binop_vector_extract
:
779 unreachable("not reached: should be handled by lower_vec_index_to_cond_assign()");
781 case ir_triop_vector_insert
:
782 unreachable("not reached: should be handled by lower_vector_insert()");
785 unreachable("not reached: should be handled by ldexp_to_arith()");
788 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
792 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
795 case ir_unop_bitcast_i2f
:
796 case ir_unop_bitcast_u2f
:
797 op
[0].type
= BRW_REGISTER_TYPE_F
;
798 this->result
= op
[0];
801 case ir_unop_bitcast_f2u
:
802 op
[0].type
= BRW_REGISTER_TYPE_UD
;
803 this->result
= op
[0];
806 case ir_unop_bitcast_f2i
:
807 op
[0].type
= BRW_REGISTER_TYPE_D
;
808 this->result
= op
[0];
814 emit(MOV(this->result
, op
[0]));
818 emit(AND(this->result
, op
[0], fs_reg(1)));
821 if (ctx
->Const
.UniformBooleanTrue
!= 1) {
822 op
[0].type
= BRW_REGISTER_TYPE_UD
;
823 this->result
.type
= BRW_REGISTER_TYPE_UD
;
824 emit(AND(this->result
, op
[0], fs_reg(0x3f800000u
)));
825 this->result
.type
= BRW_REGISTER_TYPE_F
;
827 temp
= fs_reg(this, glsl_type::int_type
);
828 emit(AND(temp
, op
[0], fs_reg(1u)));
829 emit(MOV(this->result
, temp
));
834 emit(CMP(this->result
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
837 emit(CMP(this->result
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
841 emit(RNDZ(this->result
, op
[0]));
844 op
[0].negate
= !op
[0].negate
;
845 emit(RNDD(this->result
, op
[0]));
846 this->result
.negate
= true;
849 emit(RNDD(this->result
, op
[0]));
852 emit(FRC(this->result
, op
[0]));
854 case ir_unop_round_even
:
855 emit(RNDE(this->result
, op
[0]));
860 resolve_ud_negate(&op
[0]);
861 resolve_ud_negate(&op
[1]);
862 emit_minmax(ir
->operation
== ir_binop_min
?
863 BRW_CONDITIONAL_L
: BRW_CONDITIONAL_GE
,
864 this->result
, op
[0], op
[1]);
866 case ir_unop_pack_snorm_2x16
:
867 case ir_unop_pack_snorm_4x8
:
868 case ir_unop_pack_unorm_2x16
:
869 case ir_unop_pack_unorm_4x8
:
870 case ir_unop_unpack_snorm_2x16
:
871 case ir_unop_unpack_snorm_4x8
:
872 case ir_unop_unpack_unorm_2x16
:
873 case ir_unop_unpack_unorm_4x8
:
874 case ir_unop_unpack_half_2x16
:
875 case ir_unop_pack_half_2x16
:
876 unreachable("not reached: should be handled by lower_packing_builtins");
877 case ir_unop_unpack_half_2x16_split_x
:
878 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, this->result
, op
[0]);
880 case ir_unop_unpack_half_2x16_split_y
:
881 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, this->result
, op
[0]);
884 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
887 case ir_unop_bitfield_reverse
:
888 emit(BFREV(this->result
, op
[0]));
890 case ir_unop_bit_count
:
891 emit(CBIT(this->result
, op
[0]));
893 case ir_unop_find_msb
:
894 temp
= fs_reg(this, glsl_type::uint_type
);
895 emit(FBH(temp
, op
[0]));
897 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
898 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
899 * subtract the result from 31 to convert the MSB count into an LSB count.
902 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
903 emit(MOV(this->result
, temp
));
904 emit(CMP(reg_null_d
, this->result
, fs_reg(-1), BRW_CONDITIONAL_NZ
));
907 inst
= emit(ADD(this->result
, temp
, fs_reg(31)));
908 inst
->predicate
= BRW_PREDICATE_NORMAL
;
910 case ir_unop_find_lsb
:
911 emit(FBL(this->result
, op
[0]));
913 case ir_unop_saturate
:
914 inst
= emit(MOV(this->result
, op
[0]));
915 inst
->saturate
= true;
917 case ir_triop_bitfield_extract
:
918 /* Note that the instruction's argument order is reversed from GLSL
921 emit(BFE(this->result
, op
[2], op
[1], op
[0]));
924 emit(BFI1(this->result
, op
[0], op
[1]));
927 emit(BFI2(this->result
, op
[0], op
[1], op
[2]));
929 case ir_quadop_bitfield_insert
:
930 unreachable("not reached: should be handled by "
931 "lower_instructions::bitfield_insert_to_bfm_bfi");
933 case ir_unop_bit_not
:
934 emit(NOT(this->result
, op
[0]));
936 case ir_binop_bit_and
:
937 emit(AND(this->result
, op
[0], op
[1]));
939 case ir_binop_bit_xor
:
940 emit(XOR(this->result
, op
[0], op
[1]));
942 case ir_binop_bit_or
:
943 emit(OR(this->result
, op
[0], op
[1]));
946 case ir_binop_lshift
:
947 emit(SHL(this->result
, op
[0], op
[1]));
950 case ir_binop_rshift
:
951 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
952 emit(ASR(this->result
, op
[0], op
[1]));
954 emit(SHR(this->result
, op
[0], op
[1]));
956 case ir_binop_pack_half_2x16_split
:
957 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, this->result
, op
[0], op
[1]);
959 case ir_binop_ubo_load
: {
960 /* This IR node takes a constant uniform block and a constant or
961 * variable byte offset within the block and loads a vector from that.
963 ir_constant
*const_uniform_block
= ir
->operands
[0]->as_constant();
964 ir_constant
*const_offset
= ir
->operands
[1]->as_constant();
967 if (const_uniform_block
) {
968 /* The block index is a constant, so just emit the binding table entry
971 surf_index
= fs_reg(stage_prog_data
->binding_table
.ubo_start
+
972 const_uniform_block
->value
.u
[0]);
974 /* The block index is not a constant. Evaluate the index expression
975 * per-channel and add the base UBO index; the generator will select
976 * a value from any live channel.
978 surf_index
= fs_reg(this, glsl_type::uint_type
);
979 emit(ADD(surf_index
, op
[0],
980 fs_reg(stage_prog_data
->binding_table
.ubo_start
)))
981 ->force_writemask_all
= true;
983 /* Assume this may touch any UBO. It would be nice to provide
984 * a tighter bound, but the array information is already lowered away.
986 brw_mark_surface_used(prog_data
,
987 stage_prog_data
->binding_table
.ubo_start
+
988 shader_prog
->NumUniformBlocks
- 1);
992 fs_reg packed_consts
= fs_reg(this, glsl_type::float_type
);
993 packed_consts
.type
= result
.type
;
995 fs_reg const_offset_reg
= fs_reg(const_offset
->value
.u
[0] & ~15);
996 emit(new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
997 packed_consts
, surf_index
, const_offset_reg
));
999 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1000 packed_consts
.set_smear(const_offset
->value
.u
[0] % 16 / 4 + i
);
1002 /* The std140 packing rules don't allow vectors to cross 16-byte
1003 * boundaries, and a reg is 32 bytes.
1005 assert(packed_consts
.subreg_offset
< 32);
1007 /* UBO bools are any nonzero value. We consider bools to be
1008 * values with the low bit set to 1. Convert them using CMP.
1010 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
) {
1011 emit(CMP(result
, packed_consts
, fs_reg(0u), BRW_CONDITIONAL_NZ
));
1013 emit(MOV(result
, packed_consts
));
1016 result
= offset(result
, 1);
1019 /* Turn the byte offset into a dword offset. */
1020 fs_reg base_offset
= fs_reg(this, glsl_type::int_type
);
1021 emit(SHR(base_offset
, op
[1], fs_reg(2)));
1023 for (int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1024 emit(VARYING_PULL_CONSTANT_LOAD(result
, surf_index
,
1027 if (ir
->type
->base_type
== GLSL_TYPE_BOOL
)
1028 emit(CMP(result
, result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
1030 result
= offset(result
, 1);
1034 result
.reg_offset
= 0;
1039 /* Note that the instruction's argument order is reversed from GLSL
1042 emit(MAD(this->result
, op
[2], op
[1], op
[0]));
1046 emit_lrp(this->result
, op
[0], op
[1], op
[2]);
1050 case ir_unop_interpolate_at_centroid
:
1051 case ir_binop_interpolate_at_offset
:
1052 case ir_binop_interpolate_at_sample
:
1053 unreachable("already handled above");
1059 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1060 const glsl_type
*type
, bool predicated
)
1062 switch (type
->base_type
) {
1063 case GLSL_TYPE_FLOAT
:
1064 case GLSL_TYPE_UINT
:
1066 case GLSL_TYPE_BOOL
:
1067 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1068 l
.type
= brw_type_for_base_type(type
);
1069 r
.type
= brw_type_for_base_type(type
);
1071 if (predicated
|| !l
.equals(r
)) {
1072 fs_inst
*inst
= emit(MOV(l
, r
));
1073 inst
->predicate
= predicated
? BRW_PREDICATE_NORMAL
: BRW_PREDICATE_NONE
;
1080 case GLSL_TYPE_ARRAY
:
1081 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1082 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1086 case GLSL_TYPE_STRUCT
:
1087 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1088 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1093 case GLSL_TYPE_SAMPLER
:
1094 case GLSL_TYPE_IMAGE
:
1095 case GLSL_TYPE_ATOMIC_UINT
:
1098 case GLSL_TYPE_VOID
:
1099 case GLSL_TYPE_ERROR
:
1100 case GLSL_TYPE_INTERFACE
:
1101 unreachable("not reached");
1105 /* If the RHS processing resulted in an instruction generating a
1106 * temporary value, and it would be easy to rewrite the instruction to
1107 * generate its result right into the LHS instead, do so. This ends
1108 * up reliably removing instructions where it can be tricky to do so
1109 * later without real UD chain information.
1112 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
1115 fs_inst
*pre_rhs_inst
,
1116 fs_inst
*last_rhs_inst
)
1118 /* Only attempt if we're doing a direct assignment. */
1119 if (ir
->condition
||
1120 !(ir
->lhs
->type
->is_scalar() ||
1121 (ir
->lhs
->type
->is_vector() &&
1122 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
1125 /* Make sure the last instruction generated our source reg. */
1126 fs_inst
*modify
= get_instruction_generating_reg(pre_rhs_inst
,
1132 /* If last_rhs_inst wrote a different number of components than our LHS,
1133 * we can't safely rewrite it.
1135 if (virtual_grf_sizes
[dst
.reg
] != modify
->regs_written
)
1138 /* Success! Rewrite the instruction. */
1145 fs_visitor::visit(ir_assignment
*ir
)
1150 /* FINISHME: arrays on the lhs */
1151 ir
->lhs
->accept(this);
1154 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1156 ir
->rhs
->accept(this);
1159 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
1161 assert(l
.file
!= BAD_FILE
);
1162 assert(r
.file
!= BAD_FILE
);
1164 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
1167 if (ir
->condition
) {
1168 emit_bool_to_cond_code(ir
->condition
);
1171 if (ir
->lhs
->type
->is_scalar() ||
1172 ir
->lhs
->type
->is_vector()) {
1173 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1174 if (ir
->write_mask
& (1 << i
)) {
1175 inst
= emit(MOV(l
, r
));
1177 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1183 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1188 fs_visitor::emit_texture_gen4(ir_texture_opcode op
, fs_reg dst
,
1189 fs_reg coordinate
, int coord_components
,
1191 fs_reg lod
, fs_reg dPdy
, int grad_components
,
1196 bool simd16
= false;
1202 if (shadow_c
.file
!= BAD_FILE
) {
1203 for (int i
= 0; i
< coord_components
; i
++) {
1204 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1205 coordinate
= offset(coordinate
, 1);
1208 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
1209 * the unused slots must be zeroed.
1211 for (int i
= coord_components
; i
< 3; i
++) {
1212 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1217 /* There's no plain shadow compare message, so we use shadow
1218 * compare with a bias of 0.0.
1220 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
)));
1222 } else if (op
== ir_txb
|| op
== ir_txl
) {
1223 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), lod
));
1226 unreachable("Should not get here.");
1229 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), shadow_c
));
1231 } else if (op
== ir_tex
) {
1232 for (int i
= 0; i
< coord_components
; i
++) {
1233 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1234 coordinate
= offset(coordinate
, 1);
1236 /* zero the others. */
1237 for (int i
= coord_components
; i
<3; i
++) {
1238 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), fs_reg(0.0f
)));
1240 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1242 } else if (op
== ir_txd
) {
1245 for (int i
= 0; i
< coord_components
; i
++) {
1246 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
));
1247 coordinate
= offset(coordinate
, 1);
1249 /* the slots for u and v are always present, but r is optional */
1250 mlen
+= MAX2(coord_components
, 2);
1253 * dPdx = dudx, dvdx, drdx
1254 * dPdy = dudy, dvdy, drdy
1256 * 1-arg: Does not exist.
1258 * 2-arg: dudx dvdx dudy dvdy
1259 * dPdx.x dPdx.y dPdy.x dPdy.y
1262 * 3-arg: dudx dvdx drdx dudy dvdy drdy
1263 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
1264 * m5 m6 m7 m8 m9 m10
1266 for (int i
= 0; i
< grad_components
; i
++) {
1267 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdx
));
1268 dPdx
= offset(dPdx
, 1);
1270 mlen
+= MAX2(grad_components
, 2);
1272 for (int i
= 0; i
< grad_components
; i
++) {
1273 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
), dPdy
));
1274 dPdy
= offset(dPdy
, 1);
1276 mlen
+= MAX2(grad_components
, 2);
1277 } else if (op
== ir_txs
) {
1278 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
1280 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), lod
));
1283 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1284 * instructions. We'll need to do SIMD16 here.
1287 assert(op
== ir_txb
|| op
== ir_txl
|| op
== ir_txf
);
1289 for (int i
= 0; i
< coord_components
; i
++) {
1290 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2, coordinate
.type
),
1292 coordinate
= offset(coordinate
, 1);
1295 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
1296 * be necessary for TXF (ld), but seems wise to do for all messages.
1298 for (int i
= coord_components
; i
< 3; i
++) {
1299 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
)));
1302 /* lod/bias appears after u/v/r. */
1305 emit(MOV(fs_reg(MRF
, base_mrf
+ mlen
, lod
.type
), lod
));
1308 /* The unused upper half. */
1313 /* Now, since we're doing simd16, the return is 2 interleaved
1314 * vec4s where the odd-indexed ones are junk. We'll need to move
1315 * this weirdness around to the expected layout.
1318 dst
= fs_reg(GRF
, virtual_grf_alloc(8), orig_dst
.type
);
1323 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1324 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1325 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1326 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1327 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1328 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1330 unreachable("not reached");
1333 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1334 inst
->base_mrf
= base_mrf
;
1336 inst
->header_present
= true;
1337 inst
->regs_written
= simd16
? 8 : 4;
1340 for (int i
= 0; i
< 4; i
++) {
1341 emit(MOV(orig_dst
, dst
));
1342 orig_dst
= offset(orig_dst
, 1);
1343 dst
= offset(dst
, 2);
1350 /* gen5's sampler has slots for u, v, r, array index, then optional
1351 * parameters like shadow comparitor or LOD bias. If optional
1352 * parameters aren't present, those base slots are optional and don't
1353 * need to be included in the message.
1355 * We don't fill in the unnecessary slots regardless, which may look
1356 * surprising in the disassembly.
1359 fs_visitor::emit_texture_gen5(ir_texture_opcode op
, fs_reg dst
,
1360 fs_reg coordinate
, int vector_elements
,
1362 fs_reg lod
, fs_reg lod2
, int grad_components
,
1363 fs_reg sample_index
, uint32_t sampler
,
1366 int reg_width
= dispatch_width
/ 8;
1367 bool header_present
= false;
1369 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
, dispatch_width
);
1370 fs_reg msg_coords
= message
;
1373 /* The offsets set up by the ir_texture visitor are in the
1374 * m1 header, so we can't go headerless.
1376 header_present
= true;
1380 for (int i
= 0; i
< vector_elements
; i
++) {
1381 emit(MOV(retype(offset(msg_coords
, i
), coordinate
.type
), coordinate
));
1382 coordinate
= offset(coordinate
, 1);
1384 fs_reg msg_end
= offset(msg_coords
, vector_elements
);
1385 fs_reg msg_lod
= offset(msg_coords
, 4);
1387 if (shadow_c
.file
!= BAD_FILE
) {
1388 fs_reg msg_shadow
= msg_lod
;
1389 emit(MOV(msg_shadow
, shadow_c
));
1390 msg_lod
= offset(msg_shadow
, 1);
1397 opcode
= SHADER_OPCODE_TEX
;
1400 emit(MOV(msg_lod
, lod
));
1401 msg_end
= offset(msg_lod
, 1);
1403 opcode
= FS_OPCODE_TXB
;
1406 emit(MOV(msg_lod
, lod
));
1407 msg_end
= offset(msg_lod
, 1);
1409 opcode
= SHADER_OPCODE_TXL
;
1414 * dPdx = dudx, dvdx, drdx
1415 * dPdy = dudy, dvdy, drdy
1417 * Load up these values:
1418 * - dudx dudy dvdx dvdy drdx drdy
1419 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1422 for (int i
= 0; i
< grad_components
; i
++) {
1423 emit(MOV(msg_end
, lod
));
1424 lod
= offset(lod
, 1);
1425 msg_end
= offset(msg_end
, 1);
1427 emit(MOV(msg_end
, lod2
));
1428 lod2
= offset(lod2
, 1);
1429 msg_end
= offset(msg_end
, 1);
1432 opcode
= SHADER_OPCODE_TXD
;
1436 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
1437 emit(MOV(msg_lod
, lod
));
1438 msg_end
= offset(msg_lod
, 1);
1440 opcode
= SHADER_OPCODE_TXS
;
1442 case ir_query_levels
:
1444 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1445 msg_end
= offset(msg_lod
, 1);
1447 opcode
= SHADER_OPCODE_TXS
;
1450 msg_lod
= offset(msg_coords
, 3);
1451 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
));
1452 msg_end
= offset(msg_lod
, 1);
1454 opcode
= SHADER_OPCODE_TXF
;
1457 msg_lod
= offset(msg_coords
, 3);
1459 emit(MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1461 emit(MOV(retype(offset(msg_lod
, 1), BRW_REGISTER_TYPE_UD
), sample_index
));
1462 msg_end
= offset(msg_lod
, 2);
1464 opcode
= SHADER_OPCODE_TXF_CMS
;
1467 opcode
= SHADER_OPCODE_LOD
;
1470 opcode
= SHADER_OPCODE_TG4
;
1473 unreachable("not reached");
1476 fs_inst
*inst
= emit(opcode
, dst
, reg_undef
, fs_reg(sampler
));
1477 inst
->base_mrf
= message
.reg
;
1478 inst
->mlen
= msg_end
.reg
- message
.reg
;
1479 inst
->header_present
= header_present
;
1480 inst
->regs_written
= 4 * reg_width
;
1482 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1483 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1484 " disallowed by hardware\n");
1491 is_high_sampler(struct brw_context
*brw
, fs_reg sampler
)
1493 if (brw
->gen
< 8 && !brw
->is_haswell
)
1496 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
1500 fs_visitor::emit_texture_gen7(ir_texture_opcode op
, fs_reg dst
,
1501 fs_reg coordinate
, int coord_components
,
1503 fs_reg lod
, fs_reg lod2
, int grad_components
,
1504 fs_reg sample_index
, fs_reg mcs
, fs_reg sampler
,
1505 fs_reg offset_value
)
1507 int reg_width
= dispatch_width
/ 8;
1508 bool header_present
= false;
1510 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, MAX_SAMPLER_MESSAGE_SIZE
);
1511 for (int i
= 0; i
< MAX_SAMPLER_MESSAGE_SIZE
; i
++) {
1512 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1516 if (op
== ir_tg4
|| offset_value
.file
!= BAD_FILE
||
1517 is_high_sampler(brw
, sampler
)) {
1518 /* For general texture offsets (no txf workaround), we need a header to
1519 * put them in. Note that for SIMD16 we're making space for two actual
1520 * hardware registers here, so the emit will have to fix up for this.
1522 * * ir4_tg4 needs to place its channel select in the header,
1523 * for interaction with ARB_texture_swizzle
1525 * The sampler index is only 4-bits, so for larger sampler numbers we
1526 * need to offset the Sampler State Pointer in the header.
1528 header_present
= true;
1529 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
1533 if (shadow_c
.file
!= BAD_FILE
) {
1534 emit(MOV(sources
[length
], shadow_c
));
1538 bool has_nonconstant_offset
=
1539 offset_value
.file
!= BAD_FILE
&& offset_value
.file
!= IMM
;
1540 bool coordinate_done
= false;
1542 /* Set up the LOD info */
1548 emit(MOV(sources
[length
], lod
));
1552 emit(MOV(sources
[length
], lod
));
1556 no16("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1558 /* Load dPdx and the coordinate together:
1559 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1561 for (int i
= 0; i
< coord_components
; i
++) {
1562 emit(MOV(sources
[length
], coordinate
));
1563 coordinate
= offset(coordinate
, 1);
1566 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1567 * only derivatives for (u, v, r).
1569 if (i
< grad_components
) {
1570 emit(MOV(sources
[length
], lod
));
1571 lod
= offset(lod
, 1);
1574 emit(MOV(sources
[length
], lod2
));
1575 lod2
= offset(lod2
, 1);
1580 coordinate_done
= true;
1584 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
));
1587 case ir_query_levels
:
1588 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), fs_reg(0u)));
1592 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1593 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1594 coordinate
= offset(coordinate
, 1);
1597 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
));
1600 for (int i
= 1; i
< coord_components
; i
++) {
1601 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1602 coordinate
= offset(coordinate
, 1);
1606 coordinate_done
= true;
1609 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
));
1612 /* data from the multisample control surface */
1613 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
));
1616 /* there is no offsetting for this message; just copy in the integer
1617 * texture coordinates
1619 for (int i
= 0; i
< coord_components
; i
++) {
1620 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
));
1621 coordinate
= offset(coordinate
, 1);
1625 coordinate_done
= true;
1628 if (has_nonconstant_offset
) {
1629 if (shadow_c
.file
!= BAD_FILE
)
1630 no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
1632 /* More crazy intermixing */
1633 for (int i
= 0; i
< 2; i
++) { /* u, v */
1634 emit(MOV(sources
[length
], coordinate
));
1635 coordinate
= offset(coordinate
, 1);
1639 for (int i
= 0; i
< 2; i
++) { /* offu, offv */
1640 emit(MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
));
1641 offset_value
= offset(offset_value
, 1);
1645 if (coord_components
== 3) { /* r if present */
1646 emit(MOV(sources
[length
], coordinate
));
1647 coordinate
= offset(coordinate
, 1);
1651 coordinate_done
= true;
1656 /* Set up the coordinate (except for cases where it was done above) */
1657 if (!coordinate_done
) {
1658 for (int i
= 0; i
< coord_components
; i
++) {
1659 emit(MOV(sources
[length
], coordinate
));
1660 coordinate
= offset(coordinate
, 1);
1667 mlen
= length
* reg_width
- header_present
;
1669 mlen
= length
* reg_width
;
1671 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
1672 BRW_REGISTER_TYPE_F
);
1673 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
1675 /* Generate the SEND */
1678 case ir_tex
: opcode
= SHADER_OPCODE_TEX
; break;
1679 case ir_txb
: opcode
= FS_OPCODE_TXB
; break;
1680 case ir_txl
: opcode
= SHADER_OPCODE_TXL
; break;
1681 case ir_txd
: opcode
= SHADER_OPCODE_TXD
; break;
1682 case ir_txf
: opcode
= SHADER_OPCODE_TXF
; break;
1683 case ir_txf_ms
: opcode
= SHADER_OPCODE_TXF_CMS
; break;
1684 case ir_txs
: opcode
= SHADER_OPCODE_TXS
; break;
1685 case ir_query_levels
: opcode
= SHADER_OPCODE_TXS
; break;
1686 case ir_lod
: opcode
= SHADER_OPCODE_LOD
; break;
1688 if (has_nonconstant_offset
)
1689 opcode
= SHADER_OPCODE_TG4_OFFSET
;
1691 opcode
= SHADER_OPCODE_TG4
;
1694 unreachable("not reached");
1696 fs_inst
*inst
= emit(opcode
, dst
, src_payload
, sampler
);
1697 inst
->base_mrf
= -1;
1699 inst
->header_present
= header_present
;
1700 inst
->regs_written
= 4 * reg_width
;
1702 if (inst
->mlen
> MAX_SAMPLER_MESSAGE_SIZE
) {
1703 fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE
)
1704 " disallowed by hardware\n");
1711 fs_visitor::rescale_texcoord(fs_reg coordinate
, const glsl_type
*coord_type
,
1712 bool is_rect
, uint32_t sampler
, int texunit
)
1714 fs_inst
*inst
= NULL
;
1715 bool needs_gl_clamp
= true;
1716 fs_reg scale_x
, scale_y
;
1717 const struct brw_sampler_prog_key_data
*tex
=
1718 (stage
== MESA_SHADER_FRAGMENT
) ?
1719 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1722 /* The 965 requires the EU to do the normalization of GL rectangle
1723 * texture coordinates. We use the program parameter state
1724 * tracking to get the scaling factor.
1728 (brw
->gen
>= 6 && (tex
->gl_clamp_mask
[0] & (1 << sampler
) ||
1729 tex
->gl_clamp_mask
[1] & (1 << sampler
))))) {
1730 struct gl_program_parameter_list
*params
= prog
->Parameters
;
1731 int tokens
[STATE_LENGTH
] = {
1733 STATE_TEXRECT_SCALE
,
1739 no16("rectangle scale uniform setup not supported on SIMD16\n");
1740 if (dispatch_width
== 16) {
1744 GLuint index
= _mesa_add_state_reference(params
,
1745 (gl_state_index
*)tokens
);
1746 /* Try to find existing copies of the texrect scale uniforms. */
1747 for (unsigned i
= 0; i
< uniforms
; i
++) {
1748 if (stage_prog_data
->param
[i
] ==
1749 &prog
->Parameters
->ParameterValues
[index
][0]) {
1750 scale_x
= fs_reg(UNIFORM
, i
);
1751 scale_y
= fs_reg(UNIFORM
, i
+ 1);
1756 /* If we didn't already set them up, do so now. */
1757 if (scale_x
.file
== BAD_FILE
) {
1758 scale_x
= fs_reg(UNIFORM
, uniforms
);
1759 scale_y
= fs_reg(UNIFORM
, uniforms
+ 1);
1761 stage_prog_data
->param
[uniforms
++] =
1762 &prog
->Parameters
->ParameterValues
[index
][0];
1763 stage_prog_data
->param
[uniforms
++] =
1764 &prog
->Parameters
->ParameterValues
[index
][1];
1768 /* The 965 requires the EU to do the normalization of GL rectangle
1769 * texture coordinates. We use the program parameter state
1770 * tracking to get the scaling factor.
1772 if (brw
->gen
< 6 && is_rect
) {
1773 fs_reg dst
= fs_reg(this, coord_type
);
1774 fs_reg src
= coordinate
;
1777 emit(MUL(dst
, src
, scale_x
));
1778 dst
= offset(dst
, 1);
1779 src
= offset(src
, 1);
1780 emit(MUL(dst
, src
, scale_y
));
1781 } else if (is_rect
) {
1782 /* On gen6+, the sampler handles the rectangle coordinates
1783 * natively, without needing rescaling. But that means we have
1784 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1785 * not [0, 1] like the default case below.
1787 needs_gl_clamp
= false;
1789 for (int i
= 0; i
< 2; i
++) {
1790 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1791 fs_reg chan
= coordinate
;
1792 chan
= offset(chan
, i
);
1794 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, fs_reg(0.0f
));
1795 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1797 /* Our parameter comes in as 1.0/width or 1.0/height,
1798 * because that's what people normally want for doing
1799 * texture rectangle handling. We need width or height
1800 * for clamping, but we don't care enough to make a new
1801 * parameter type, so just invert back.
1803 fs_reg limit
= fs_reg(this, glsl_type::float_type
);
1804 emit(MOV(limit
, i
== 0 ? scale_x
: scale_y
));
1805 emit(SHADER_OPCODE_RCP
, limit
, limit
);
1807 inst
= emit(BRW_OPCODE_SEL
, chan
, chan
, limit
);
1808 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1813 if (coord_type
&& needs_gl_clamp
) {
1814 for (unsigned int i
= 0; i
< MIN2(coord_type
->vector_elements
, 3); i
++) {
1815 if (tex
->gl_clamp_mask
[i
] & (1 << sampler
)) {
1816 fs_reg chan
= coordinate
;
1817 chan
= offset(chan
, i
);
1819 fs_inst
*inst
= emit(MOV(chan
, chan
));
1820 inst
->saturate
= true;
1827 /* Sample from the MCS surface attached to this multisample texture. */
1829 fs_visitor::emit_mcs_fetch(fs_reg coordinate
, int components
, fs_reg sampler
)
1831 int reg_width
= dispatch_width
/ 8;
1832 fs_reg payload
= fs_reg(GRF
, virtual_grf_alloc(components
* reg_width
),
1833 BRW_REGISTER_TYPE_F
);
1834 fs_reg dest
= fs_reg(this, glsl_type::uvec4_type
);
1835 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, components
);
1837 /* parameters are: u, v, r; missing parameters are treated as zero */
1838 for (int i
= 0; i
< components
; i
++) {
1839 sources
[i
] = fs_reg(this, glsl_type::float_type
);
1840 emit(MOV(retype(sources
[i
], BRW_REGISTER_TYPE_D
), coordinate
));
1841 coordinate
= offset(coordinate
, 1);
1844 emit(LOAD_PAYLOAD(payload
, sources
, components
));
1846 fs_inst
*inst
= emit(SHADER_OPCODE_TXF_MCS
, dest
, payload
, sampler
);
1847 inst
->base_mrf
= -1;
1848 inst
->mlen
= components
* reg_width
;
1849 inst
->header_present
= false;
1850 inst
->regs_written
= 4 * reg_width
; /* we only care about one reg of
1851 * response, but the sampler always
1859 fs_visitor::emit_texture(ir_texture_opcode op
,
1860 const glsl_type
*dest_type
,
1861 fs_reg coordinate
, const struct glsl_type
*coord_type
,
1863 fs_reg lod
, fs_reg lod2
, int grad_components
,
1864 fs_reg sample_index
,
1865 fs_reg offset_value
, unsigned offset_components
,
1867 int gather_component
,
1871 fs_reg sampler_reg
, int texunit
)
1873 const struct brw_sampler_prog_key_data
*tex
=
1874 (stage
== MESA_SHADER_FRAGMENT
) ?
1875 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1877 fs_inst
*inst
= NULL
;
1880 /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
1881 * emitting anything other than setting up the constant result.
1883 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], gather_component
);
1884 if (swiz
== SWIZZLE_ZERO
|| swiz
== SWIZZLE_ONE
) {
1886 fs_reg res
= fs_reg(this, glsl_type::vec4_type
);
1889 for (int i
=0; i
<4; i
++) {
1890 emit(MOV(res
, fs_reg(swiz
== SWIZZLE_ZERO
? 0.0f
: 1.0f
)));
1891 res
= offset(res
, 1);
1897 if (coordinate
.file
!= BAD_FILE
) {
1898 /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
1899 * samplers. This should only be a problem with GL_CLAMP on Gen7.
1901 coordinate
= rescale_texcoord(coordinate
, coord_type
, is_rect
,
1905 /* Writemasking doesn't eliminate channels on SIMD8 texture
1906 * samples, so don't worry about them.
1908 fs_reg
dst(this, glsl_type::get_instance(dest_type
->base_type
, 4, 1));
1910 int coord_components
= coord_type
? coord_type
->vector_elements
: 0;
1912 if (brw
->gen
>= 7) {
1913 inst
= emit_texture_gen7(op
, dst
, coordinate
, coord_components
,
1914 shadow_c
, lod
, lod2
, grad_components
,
1915 sample_index
, mcs
, sampler_reg
,
1917 } else if (brw
->gen
>= 5) {
1918 inst
= emit_texture_gen5(op
, dst
, coordinate
, coord_components
,
1919 shadow_c
, lod
, lod2
, grad_components
,
1920 sample_index
, sampler
,
1921 offset_value
.file
!= BAD_FILE
);
1923 inst
= emit_texture_gen4(op
, dst
, coordinate
, coord_components
,
1924 shadow_c
, lod
, lod2
, grad_components
,
1928 if (shadow_c
.file
!= BAD_FILE
)
1929 inst
->shadow_compare
= true;
1931 if (offset_value
.file
== IMM
)
1932 inst
->offset
= offset_value
.fixed_hw_reg
.dw1
.ud
;
1936 gather_channel(gather_component
, sampler
) << 16; /* M0.2:16-17 */
1939 emit_gen6_gather_wa(tex
->gen6_gather_wa
[sampler
], dst
);
1942 /* fixup #layers for cube map arrays */
1943 if (op
== ir_txs
&& is_cube_array
) {
1944 fs_reg depth
= offset(dst
, 2);
1945 fs_reg fixed_depth
= fs_reg(this, glsl_type::int_type
);
1946 emit_math(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, fs_reg(6));
1948 fs_reg
*fixed_payload
= ralloc_array(mem_ctx
, fs_reg
, inst
->regs_written
);
1949 int components
= inst
->regs_written
/ (dst
.width
/ 8);
1950 for (int i
= 0; i
< components
; i
++) {
1952 fixed_payload
[i
] = fixed_depth
;
1954 fixed_payload
[i
] = offset(dst
, i
);
1957 emit(LOAD_PAYLOAD(dst
, fixed_payload
, components
));
1960 swizzle_result(op
, dest_type
->vector_elements
, dst
, sampler
);
1964 fs_visitor::visit(ir_texture
*ir
)
1966 const struct brw_sampler_prog_key_data
*tex
=
1967 (stage
== MESA_SHADER_FRAGMENT
) ?
1968 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
1972 _mesa_get_sampler_uniform_value(ir
->sampler
, shader_prog
, prog
);
1974 ir_rvalue
*nonconst_sampler_index
=
1975 _mesa_get_sampler_array_nonconst_index(ir
->sampler
);
1977 /* Handle non-constant sampler array indexing */
1979 if (nonconst_sampler_index
) {
1980 /* The highest sampler which may be used by this operation is
1981 * the last element of the array. Mark it here, because the generator
1982 * doesn't have enough information to determine the bound.
1984 uint32_t array_size
= ir
->sampler
->as_dereference_array()
1985 ->array
->type
->array_size();
1987 uint32_t max_used
= sampler
+ array_size
- 1;
1988 if (ir
->op
== ir_tg4
&& brw
->gen
< 8) {
1989 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
1991 max_used
+= stage_prog_data
->binding_table
.texture_start
;
1994 brw_mark_surface_used(prog_data
, max_used
);
1996 /* Emit code to evaluate the actual indexing expression */
1997 nonconst_sampler_index
->accept(this);
1998 fs_reg
temp(this, glsl_type::uint_type
);
1999 emit(ADD(temp
, this->result
, fs_reg(sampler
)))
2000 ->force_writemask_all
= true;
2003 /* Single sampler, or constant array index; the indexing expression
2004 * is just an immediate.
2006 sampler_reg
= fs_reg(sampler
);
2009 /* FINISHME: We're failing to recompile our programs when the sampler is
2010 * updated. This only matters for the texture rectangle scale parameters
2011 * (pre-gen6, or gen6+ with GL_CLAMP).
2013 int texunit
= prog
->SamplerUnits
[sampler
];
2015 /* Should be lowered by do_lower_texture_projection */
2016 assert(!ir
->projector
);
2018 /* Should be lowered */
2019 assert(!ir
->offset
|| !ir
->offset
->type
->is_array());
2021 /* Generate code to compute all the subexpression trees. This has to be
2022 * done before loading any values into MRFs for the sampler message since
2023 * generating these values may involve SEND messages that need the MRFs.
2026 const glsl_type
*coord_type
= NULL
;
2027 if (ir
->coordinate
) {
2028 coord_type
= ir
->coordinate
->type
;
2029 ir
->coordinate
->accept(this);
2030 coordinate
= this->result
;
2033 fs_reg shadow_comparitor
;
2034 if (ir
->shadow_comparitor
) {
2035 ir
->shadow_comparitor
->accept(this);
2036 shadow_comparitor
= this->result
;
2039 fs_reg offset_value
;
2040 int offset_components
= 0;
2042 ir_constant
*const_offset
= ir
->offset
->as_constant();
2044 /* Store the header bitfield in an IMM register. This allows us to
2045 * use offset_value.file to distinguish between no offset, a constant
2046 * offset, and a non-constant offset.
2049 fs_reg(brw_texture_offset(ctx
, const_offset
->value
.i
,
2050 const_offset
->type
->vector_elements
));
2052 ir
->offset
->accept(this);
2053 offset_value
= this->result
;
2055 offset_components
= ir
->offset
->type
->vector_elements
;
2058 fs_reg lod
, lod2
, sample_index
, mcs
;
2059 int grad_components
= 0;
2064 case ir_query_levels
:
2067 ir
->lod_info
.bias
->accept(this);
2071 ir
->lod_info
.grad
.dPdx
->accept(this);
2074 ir
->lod_info
.grad
.dPdy
->accept(this);
2075 lod2
= this->result
;
2077 grad_components
= ir
->lod_info
.grad
.dPdx
->type
->vector_elements
;
2082 ir
->lod_info
.lod
->accept(this);
2086 ir
->lod_info
.sample_index
->accept(this);
2087 sample_index
= this->result
;
2089 if (brw
->gen
>= 7 && tex
->compressed_multisample_layout_mask
& (1<<sampler
))
2090 mcs
= emit_mcs_fetch(coordinate
, ir
->coordinate
->type
->vector_elements
,
2096 unreachable("Unrecognized texture opcode");
2099 int gather_component
= 0;
2100 if (ir
->op
== ir_tg4
)
2101 gather_component
= ir
->lod_info
.component
->as_constant()->value
.i
[0];
2104 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
;
2106 bool is_cube_array
=
2107 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2108 ir
->sampler
->type
->sampler_array
;
2110 emit_texture(ir
->op
, ir
->type
, coordinate
, coord_type
, shadow_comparitor
,
2111 lod
, lod2
, grad_components
, sample_index
, offset_value
,
2112 offset_components
, mcs
, gather_component
,
2113 is_cube_array
, is_rect
, sampler
, sampler_reg
, texunit
);
2117 * Apply workarounds for Gen6 gather with UINT/SINT
2120 fs_visitor::emit_gen6_gather_wa(uint8_t wa
, fs_reg dst
)
2125 int width
= (wa
& WA_8BIT
) ? 8 : 16;
2127 for (int i
= 0; i
< 4; i
++) {
2128 fs_reg dst_f
= retype(dst
, BRW_REGISTER_TYPE_F
);
2129 /* Convert from UNORM to UINT */
2130 emit(MUL(dst_f
, dst_f
, fs_reg((float)((1 << width
) - 1))));
2131 emit(MOV(dst
, dst_f
));
2134 /* Reinterpret the UINT value as a signed INT value by
2135 * shifting the sign bit into place, then shifting back
2138 emit(SHL(dst
, dst
, fs_reg(32 - width
)));
2139 emit(ASR(dst
, dst
, fs_reg(32 - width
)));
2142 dst
= offset(dst
, 1);
2147 * Set up the gather channel based on the swizzle, for gather4.
2150 fs_visitor::gather_channel(int orig_chan
, uint32_t sampler
)
2152 const struct brw_sampler_prog_key_data
*tex
=
2153 (stage
== MESA_SHADER_FRAGMENT
) ?
2154 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
2156 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], orig_chan
);
2158 case SWIZZLE_X
: return 0;
2160 /* gather4 sampler is broken for green channel on RG32F --
2161 * we must ask for blue instead.
2163 if (tex
->gather_channel_quirk_mask
& (1<<sampler
))
2166 case SWIZZLE_Z
: return 2;
2167 case SWIZZLE_W
: return 3;
2169 unreachable("Not reached"); /* zero, one swizzles handled already */
2174 * Swizzle the result of a texture result. This is necessary for
2175 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
2178 fs_visitor::swizzle_result(ir_texture_opcode op
, int dest_components
,
2179 fs_reg orig_val
, uint32_t sampler
)
2181 if (op
== ir_query_levels
) {
2182 /* # levels is in .w */
2183 this->result
= offset(orig_val
, 3);
2187 this->result
= orig_val
;
2189 /* txs,lod don't actually sample the texture, so swizzling the result
2192 if (op
== ir_txs
|| op
== ir_lod
|| op
== ir_tg4
)
2195 const struct brw_sampler_prog_key_data
*tex
=
2196 (stage
== MESA_SHADER_FRAGMENT
) ?
2197 &((brw_wm_prog_key
*) this->key
)->tex
: NULL
;
2200 if (dest_components
== 1) {
2201 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
2202 } else if (tex
->swizzles
[sampler
] != SWIZZLE_NOOP
) {
2203 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
2204 swizzled_result
.type
= orig_val
.type
;
2206 for (int i
= 0; i
< 4; i
++) {
2207 int swiz
= GET_SWZ(tex
->swizzles
[sampler
], i
);
2208 fs_reg l
= swizzled_result
;
2211 if (swiz
== SWIZZLE_ZERO
) {
2212 emit(MOV(l
, fs_reg(0.0f
)));
2213 } else if (swiz
== SWIZZLE_ONE
) {
2214 emit(MOV(l
, fs_reg(1.0f
)));
2216 emit(MOV(l
, offset(orig_val
,
2217 GET_SWZ(tex
->swizzles
[sampler
], i
))));
2220 this->result
= swizzled_result
;
2225 fs_visitor::visit(ir_swizzle
*ir
)
2227 ir
->val
->accept(this);
2228 fs_reg val
= this->result
;
2230 if (ir
->type
->vector_elements
== 1) {
2231 this->result
= offset(this->result
, ir
->mask
.x
);
2235 fs_reg result
= fs_reg(this, ir
->type
);
2236 this->result
= result
;
2238 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
2239 fs_reg channel
= val
;
2257 emit(MOV(result
, offset(channel
, swiz
)));
2258 result
= offset(result
, 1);
2263 fs_visitor::visit(ir_discard
*ir
)
2265 assert(ir
->condition
== NULL
); /* FINISHME */
2267 /* We track our discarded pixels in f0.1. By predicating on it, we can
2268 * update just the flag bits that aren't yet discarded. By emitting a
2269 * CMP of g0 != g0, all our currently executing channels will get turned
2272 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2273 BRW_REGISTER_TYPE_UW
));
2274 fs_inst
*cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
2275 BRW_CONDITIONAL_NZ
));
2276 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2277 cmp
->flag_subreg
= 1;
2279 if (brw
->gen
>= 6) {
2280 /* For performance, after a discard, jump to the end of the shader.
2281 * Only jump if all relevant channels have been discarded.
2283 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
2284 discard_jump
->flag_subreg
= 1;
2286 discard_jump
->predicate
= (dispatch_width
== 8)
2287 ? BRW_PREDICATE_ALIGN1_ANY8H
2288 : BRW_PREDICATE_ALIGN1_ANY16H
;
2289 discard_jump
->predicate_inverse
= true;
2294 fs_visitor::visit(ir_constant
*ir
)
2296 /* Set this->result to reg at the bottom of the function because some code
2297 * paths will cause this visitor to be applied to other fields. This will
2298 * cause the value stored in this->result to be modified.
2300 * Make reg constant so that it doesn't get accidentally modified along the
2301 * way. Yes, I actually had this problem. :(
2303 const fs_reg
reg(this, ir
->type
);
2304 fs_reg dst_reg
= reg
;
2306 if (ir
->type
->is_array()) {
2307 const unsigned size
= type_size(ir
->type
->fields
.array
);
2309 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
2310 ir
->array_elements
[i
]->accept(this);
2311 fs_reg src_reg
= this->result
;
2313 dst_reg
.type
= src_reg
.type
;
2314 for (unsigned j
= 0; j
< size
; j
++) {
2315 emit(MOV(dst_reg
, src_reg
));
2316 src_reg
= offset(src_reg
, 1);
2317 dst_reg
= offset(dst_reg
, 1);
2320 } else if (ir
->type
->is_record()) {
2321 foreach_in_list(ir_constant
, field
, &ir
->components
) {
2322 const unsigned size
= type_size(field
->type
);
2324 field
->accept(this);
2325 fs_reg src_reg
= this->result
;
2327 dst_reg
.type
= src_reg
.type
;
2328 for (unsigned j
= 0; j
< size
; j
++) {
2329 emit(MOV(dst_reg
, src_reg
));
2330 src_reg
= offset(src_reg
, 1);
2331 dst_reg
= offset(dst_reg
, 1);
2335 const unsigned size
= type_size(ir
->type
);
2337 for (unsigned i
= 0; i
< size
; i
++) {
2338 switch (ir
->type
->base_type
) {
2339 case GLSL_TYPE_FLOAT
:
2340 emit(MOV(dst_reg
, fs_reg(ir
->value
.f
[i
])));
2342 case GLSL_TYPE_UINT
:
2343 emit(MOV(dst_reg
, fs_reg(ir
->value
.u
[i
])));
2346 emit(MOV(dst_reg
, fs_reg(ir
->value
.i
[i
])));
2348 case GLSL_TYPE_BOOL
:
2350 fs_reg(ir
->value
.b
[i
] != 0 ? ctx
->Const
.UniformBooleanTrue
2354 unreachable("Non-float/uint/int/bool constant");
2356 dst_reg
= offset(dst_reg
, 1);
2364 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
2366 ir_expression
*expr
= ir
->as_expression();
2368 if (!expr
|| expr
->operation
== ir_binop_ubo_load
) {
2371 fs_inst
*inst
= emit(AND(reg_null_d
, this->result
, fs_reg(1)));
2372 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2379 assert(expr
->get_num_operands() <= 3);
2380 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2381 assert(expr
->operands
[i
]->type
->is_scalar());
2383 expr
->operands
[i
]->accept(this);
2384 op
[i
] = this->result
;
2386 resolve_ud_negate(&op
[i
]);
2389 switch (expr
->operation
) {
2390 case ir_unop_logic_not
:
2391 inst
= emit(AND(reg_null_d
, op
[0], fs_reg(1)));
2392 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2395 case ir_binop_logic_xor
:
2396 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2397 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2398 emit(XOR(dst
, op
[0], op
[1]));
2399 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1u)));
2400 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2402 inst
= emit(XOR(reg_null_d
, op
[0], op
[1]));
2403 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2407 case ir_binop_logic_or
:
2408 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2409 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2410 emit(OR(dst
, op
[0], op
[1]));
2411 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1u)));
2412 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2414 inst
= emit(OR(reg_null_d
, op
[0], op
[1]));
2415 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2419 case ir_binop_logic_and
:
2420 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2421 fs_reg dst
= fs_reg(this, glsl_type::uint_type
);
2422 emit(AND(dst
, op
[0], op
[1]));
2423 inst
= emit(AND(reg_null_d
, dst
, fs_reg(1u)));
2424 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2426 inst
= emit(AND(reg_null_d
, op
[0], op
[1]));
2427 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2432 if (brw
->gen
>= 6) {
2433 emit(CMP(reg_null_d
, op
[0], fs_reg(0.0f
), BRW_CONDITIONAL_NZ
));
2435 inst
= emit(MOV(reg_null_f
, op
[0]));
2436 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2441 if (brw
->gen
>= 6) {
2442 emit(CMP(reg_null_d
, op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2444 inst
= emit(MOV(reg_null_d
, op
[0]));
2445 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2449 case ir_binop_greater
:
2450 case ir_binop_gequal
:
2452 case ir_binop_lequal
:
2453 case ir_binop_equal
:
2454 case ir_binop_all_equal
:
2455 case ir_binop_nequal
:
2456 case ir_binop_any_nequal
:
2457 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2458 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2459 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2462 emit(CMP(reg_null_d
, op
[0], op
[1],
2463 brw_conditional_for_comparison(expr
->operation
)));
2466 case ir_triop_csel
: {
2467 /* Expand the boolean condition into the flag register. */
2468 inst
= emit(MOV(reg_null_d
, op
[0]));
2469 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2471 /* Select which boolean to return. */
2472 fs_reg
temp(this, expr
->operands
[1]->type
);
2473 inst
= emit(SEL(temp
, op
[1], op
[2]));
2474 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2476 /* Expand the result to a condition code. */
2477 inst
= emit(MOV(reg_null_d
, temp
));
2478 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2483 unreachable("not reached");
2488 * Emit a gen6 IF statement with the comparison folded into the IF
2492 fs_visitor::emit_if_gen6(ir_if
*ir
)
2494 ir_expression
*expr
= ir
->condition
->as_expression();
2496 if (expr
&& expr
->operation
!= ir_binop_ubo_load
) {
2501 assert(expr
->get_num_operands() <= 3);
2502 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
2503 assert(expr
->operands
[i
]->type
->is_scalar());
2505 expr
->operands
[i
]->accept(this);
2506 op
[i
] = this->result
;
2509 switch (expr
->operation
) {
2510 case ir_unop_logic_not
:
2511 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_Z
));
2514 case ir_binop_logic_xor
:
2515 emit(IF(op
[0], op
[1], BRW_CONDITIONAL_NZ
));
2518 case ir_binop_logic_or
:
2519 temp
= fs_reg(this, glsl_type::bool_type
);
2520 emit(OR(temp
, op
[0], op
[1]));
2521 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2524 case ir_binop_logic_and
:
2525 temp
= fs_reg(this, glsl_type::bool_type
);
2526 emit(AND(temp
, op
[0], op
[1]));
2527 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2531 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
2532 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2536 emit(IF(op
[0], fs_reg(0), BRW_CONDITIONAL_NZ
));
2539 case ir_binop_greater
:
2540 case ir_binop_gequal
:
2542 case ir_binop_lequal
:
2543 case ir_binop_equal
:
2544 case ir_binop_all_equal
:
2545 case ir_binop_nequal
:
2546 case ir_binop_any_nequal
:
2547 if (ctx
->Const
.UniformBooleanTrue
== 1) {
2548 resolve_bool_comparison(expr
->operands
[0], &op
[0]);
2549 resolve_bool_comparison(expr
->operands
[1], &op
[1]);
2552 emit(IF(op
[0], op
[1],
2553 brw_conditional_for_comparison(expr
->operation
)));
2556 case ir_triop_csel
: {
2557 /* Expand the boolean condition into the flag register. */
2558 fs_inst
*inst
= emit(MOV(reg_null_d
, op
[0]));
2559 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
2561 /* Select which boolean to use as the result. */
2562 fs_reg
temp(this, expr
->operands
[1]->type
);
2563 inst
= emit(SEL(temp
, op
[1], op
[2]));
2564 inst
->predicate
= BRW_PREDICATE_NORMAL
;
2566 emit(IF(temp
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2571 unreachable("not reached");
2575 ir
->condition
->accept(this);
2576 emit(IF(this->result
, fs_reg(0), BRW_CONDITIONAL_NZ
));
2580 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
2582 * Many GLSL shaders contain the following pattern:
2584 * x = condition ? foo : bar
2586 * The compiler emits an ir_if tree for this, since each subexpression might be
2587 * a complex tree that could have side-effects or short-circuit logic.
2589 * However, the common case is to simply select one of two constants or
2590 * variable values---which is exactly what SEL is for. In this case, the
2591 * assembly looks like:
2599 * which can be easily translated into:
2601 * (+f0) SEL dst src0 src1
2603 * If src0 is an immediate value, we promote it to a temporary GRF.
2606 fs_visitor::try_replace_with_sel()
2608 fs_inst
*endif_inst
= (fs_inst
*) instructions
.get_tail();
2609 assert(endif_inst
->opcode
== BRW_OPCODE_ENDIF
);
2611 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
2613 BRW_OPCODE_IF
, BRW_OPCODE_MOV
, BRW_OPCODE_ELSE
, BRW_OPCODE_MOV
,
2616 fs_inst
*match
= (fs_inst
*) endif_inst
->prev
;
2617 for (int i
= 0; i
< 4; i
++) {
2618 if (match
->is_head_sentinel() || match
->opcode
!= opcodes
[4-i
-1])
2620 match
= (fs_inst
*) match
->prev
;
2623 /* The opcodes match; it looks like the right sequence of instructions. */
2624 fs_inst
*else_mov
= (fs_inst
*) endif_inst
->prev
;
2625 fs_inst
*then_mov
= (fs_inst
*) else_mov
->prev
->prev
;
2626 fs_inst
*if_inst
= (fs_inst
*) then_mov
->prev
;
2628 /* Check that the MOVs are the right form. */
2629 if (then_mov
->dst
.equals(else_mov
->dst
) &&
2630 !then_mov
->is_partial_write() &&
2631 !else_mov
->is_partial_write()) {
2633 /* Remove the matched instructions; we'll emit a SEL to replace them. */
2634 while (!if_inst
->next
->is_tail_sentinel())
2635 if_inst
->next
->exec_node::remove();
2636 if_inst
->exec_node::remove();
2638 /* Only the last source register can be a constant, so if the MOV in
2639 * the "then" clause uses a constant, we need to put it in a temporary.
2641 fs_reg
src0(then_mov
->src
[0]);
2642 if (src0
.file
== IMM
) {
2643 src0
= fs_reg(this, glsl_type::float_type
);
2644 src0
.type
= then_mov
->src
[0].type
;
2645 emit(MOV(src0
, then_mov
->src
[0]));
2649 if (if_inst
->conditional_mod
) {
2650 /* Sandybridge-specific IF with embedded comparison */
2651 emit(CMP(reg_null_d
, if_inst
->src
[0], if_inst
->src
[1],
2652 if_inst
->conditional_mod
));
2653 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2654 sel
->predicate
= BRW_PREDICATE_NORMAL
;
2656 /* Separate CMP and IF instructions */
2657 sel
= emit(BRW_OPCODE_SEL
, then_mov
->dst
, src0
, else_mov
->src
[0]);
2658 sel
->predicate
= if_inst
->predicate
;
2659 sel
->predicate_inverse
= if_inst
->predicate_inverse
;
2665 fs_visitor::visit(ir_if
*ir
)
2668 no16("Can't support (non-uniform) control flow on SIMD16\n");
2671 /* Don't point the annotation at the if statement, because then it plus
2672 * the then and else blocks get printed.
2674 this->base_ir
= ir
->condition
;
2676 if (brw
->gen
== 6) {
2679 emit_bool_to_cond_code(ir
->condition
);
2681 emit(IF(BRW_PREDICATE_NORMAL
));
2684 foreach_in_list(ir_instruction
, ir_
, &ir
->then_instructions
) {
2685 this->base_ir
= ir_
;
2689 if (!ir
->else_instructions
.is_empty()) {
2690 emit(BRW_OPCODE_ELSE
);
2692 foreach_in_list(ir_instruction
, ir_
, &ir
->else_instructions
) {
2693 this->base_ir
= ir_
;
2698 emit(BRW_OPCODE_ENDIF
);
2700 try_replace_with_sel();
2704 fs_visitor::visit(ir_loop
*ir
)
2707 no16("Can't support (non-uniform) control flow on SIMD16\n");
2710 this->base_ir
= NULL
;
2711 emit(BRW_OPCODE_DO
);
2713 foreach_in_list(ir_instruction
, ir_
, &ir
->body_instructions
) {
2714 this->base_ir
= ir_
;
2718 this->base_ir
= NULL
;
2719 emit(BRW_OPCODE_WHILE
);
2723 fs_visitor::visit(ir_loop_jump
*ir
)
2726 case ir_loop_jump::jump_break
:
2727 emit(BRW_OPCODE_BREAK
);
2729 case ir_loop_jump::jump_continue
:
2730 emit(BRW_OPCODE_CONTINUE
);
2736 fs_visitor::visit_atomic_counter_intrinsic(ir_call
*ir
)
2738 ir_dereference
*deref
= static_cast<ir_dereference
*>(
2739 ir
->actual_parameters
.get_head());
2740 ir_variable
*location
= deref
->variable_referenced();
2741 unsigned surf_index
= (stage_prog_data
->binding_table
.abo_start
+
2742 location
->data
.binding
);
2744 /* Calculate the surface offset */
2745 fs_reg
offset(this, glsl_type::uint_type
);
2746 ir_dereference_array
*deref_array
= deref
->as_dereference_array();
2749 deref_array
->array_index
->accept(this);
2751 fs_reg
tmp(this, glsl_type::uint_type
);
2752 emit(MUL(tmp
, this->result
, fs_reg(ATOMIC_COUNTER_SIZE
)));
2753 emit(ADD(offset
, tmp
, fs_reg(location
->data
.atomic
.offset
)));
2755 offset
= fs_reg(location
->data
.atomic
.offset
);
2758 /* Emit the appropriate machine instruction */
2759 const char *callee
= ir
->callee
->function_name();
2760 ir
->return_deref
->accept(this);
2761 fs_reg dst
= this->result
;
2763 if (!strcmp("__intrinsic_atomic_read", callee
)) {
2764 emit_untyped_surface_read(surf_index
, dst
, offset
);
2766 } else if (!strcmp("__intrinsic_atomic_increment", callee
)) {
2767 emit_untyped_atomic(BRW_AOP_INC
, surf_index
, dst
, offset
,
2768 fs_reg(), fs_reg());
2770 } else if (!strcmp("__intrinsic_atomic_predecrement", callee
)) {
2771 emit_untyped_atomic(BRW_AOP_PREDEC
, surf_index
, dst
, offset
,
2772 fs_reg(), fs_reg());
2777 fs_visitor::visit(ir_call
*ir
)
2779 const char *callee
= ir
->callee
->function_name();
2781 if (!strcmp("__intrinsic_atomic_read", callee
) ||
2782 !strcmp("__intrinsic_atomic_increment", callee
) ||
2783 !strcmp("__intrinsic_atomic_predecrement", callee
)) {
2784 visit_atomic_counter_intrinsic(ir
);
2786 unreachable("Unsupported intrinsic.");
2791 fs_visitor::visit(ir_return
*)
2793 unreachable("FINISHME");
2797 fs_visitor::visit(ir_function
*ir
)
2799 /* Ignore function bodies other than main() -- we shouldn't see calls to
2800 * them since they should all be inlined before we get to ir_to_mesa.
2802 if (strcmp(ir
->name
, "main") == 0) {
2803 const ir_function_signature
*sig
;
2806 sig
= ir
->matching_signature(NULL
, &empty
, false);
2810 foreach_in_list(ir_instruction
, ir_
, &sig
->body
) {
2811 this->base_ir
= ir_
;
2818 fs_visitor::visit(ir_function_signature
*)
2820 unreachable("not reached");
2824 fs_visitor::visit(ir_emit_vertex
*)
2826 unreachable("not reached");
2830 fs_visitor::visit(ir_end_primitive
*)
2832 unreachable("not reached");
2836 fs_visitor::emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
2837 fs_reg dst
, fs_reg offset
, fs_reg src0
,
2841 (stage
== MESA_SHADER_FRAGMENT
) &&
2842 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2843 int reg_width
= dispatch_width
/ 8;
2846 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 4);
2848 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
2849 /* Initialize the sample mask in the message header. */
2850 emit(MOV(sources
[0], fs_reg(0u)))
2851 ->force_writemask_all
= true;
2854 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
2855 ->force_writemask_all
= true;
2857 emit(MOV(component(sources
[0], 7),
2858 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2859 ->force_writemask_all
= true;
2863 /* Set the atomic operation offset. */
2864 sources
[1] = fs_reg(this, glsl_type::uint_type
);
2865 emit(MOV(sources
[1], offset
));
2868 /* Set the atomic operation arguments. */
2869 if (src0
.file
!= BAD_FILE
) {
2870 sources
[length
] = fs_reg(this, glsl_type::uint_type
);
2871 emit(MOV(sources
[length
], src0
));
2875 if (src1
.file
!= BAD_FILE
) {
2876 sources
[length
] = fs_reg(this, glsl_type::uint_type
);
2877 emit(MOV(sources
[length
], src1
));
2881 int mlen
= 1 + (length
- 1) * reg_width
;
2882 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
2883 BRW_REGISTER_TYPE_UD
);
2884 emit(LOAD_PAYLOAD(src_payload
, sources
, length
));
2886 /* Emit the instruction. */
2887 fs_inst
*inst
= emit(SHADER_OPCODE_UNTYPED_ATOMIC
, dst
, src_payload
,
2888 fs_reg(atomic_op
), fs_reg(surf_index
));
2893 fs_visitor::emit_untyped_surface_read(unsigned surf_index
, fs_reg dst
,
2897 (stage
== MESA_SHADER_FRAGMENT
) &&
2898 ((brw_wm_prog_data
*) this->prog_data
)->uses_kill
;
2899 int reg_width
= dispatch_width
/ 8;
2901 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
2903 sources
[0] = fs_reg(GRF
, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD
);
2904 /* Initialize the sample mask in the message header. */
2905 emit(MOV(sources
[0], fs_reg(0u)))
2906 ->force_writemask_all
= true;
2909 emit(MOV(component(sources
[0], 7), brw_flag_reg(0, 1)))
2910 ->force_writemask_all
= true;
2912 emit(MOV(component(sources
[0], 7),
2913 retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD
)))
2914 ->force_writemask_all
= true;
2917 /* Set the surface read offset. */
2918 sources
[1] = fs_reg(this, glsl_type::uint_type
);
2919 emit(MOV(sources
[1], offset
));
2921 int mlen
= 1 + reg_width
;
2922 fs_reg src_payload
= fs_reg(GRF
, virtual_grf_alloc(mlen
),
2923 BRW_REGISTER_TYPE_UD
);
2924 fs_inst
*inst
= emit(LOAD_PAYLOAD(src_payload
, sources
, 2));
2926 /* Emit the instruction. */
2927 inst
= emit(SHADER_OPCODE_UNTYPED_SURFACE_READ
, dst
, src_payload
,
2928 fs_reg(surf_index
));
2933 fs_visitor::emit(fs_inst
*inst
)
2935 if (dispatch_width
== 16 && inst
->exec_size
== 8)
2936 inst
->force_uncompressed
= true;
2938 inst
->annotation
= this->current_annotation
;
2939 inst
->ir
= this->base_ir
;
2941 this->instructions
.push_tail(inst
);
2947 fs_visitor::emit(exec_list list
)
2949 foreach_in_list_safe(fs_inst
, inst
, &list
) {
2950 inst
->exec_node::remove();
2955 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2957 fs_visitor::emit_dummy_fs()
2959 int reg_width
= dispatch_width
/ 8;
2961 /* Everyone's favorite color. */
2962 emit(MOV(fs_reg(MRF
, 2 + 0 * reg_width
), fs_reg(1.0f
)));
2963 emit(MOV(fs_reg(MRF
, 2 + 1 * reg_width
), fs_reg(0.0f
)));
2964 emit(MOV(fs_reg(MRF
, 2 + 2 * reg_width
), fs_reg(1.0f
)));
2965 emit(MOV(fs_reg(MRF
, 2 + 3 * reg_width
), fs_reg(0.0f
)));
2968 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
2969 write
->base_mrf
= 2;
2970 write
->mlen
= 4 * reg_width
;
2974 /* The register location here is relative to the start of the URB
2975 * data. It will get adjusted to be a real location before
2976 * generate_code() time.
2979 fs_visitor::interp_reg(int location
, int channel
)
2981 assert(stage
== MESA_SHADER_FRAGMENT
);
2982 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
2983 int regnr
= prog_data
->urb_setup
[location
] * 2 + channel
/ 2;
2984 int stride
= (channel
& 1) * 4;
2986 assert(prog_data
->urb_setup
[location
] != -1);
2988 return brw_vec1_grf(regnr
, stride
);
2991 /** Emits the interpolation for the varying inputs. */
2993 fs_visitor::emit_interpolation_setup_gen4()
2995 this->current_annotation
= "compute pixel centers";
2996 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
2997 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
2998 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
2999 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3001 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
3002 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
3004 this->current_annotation
= "compute pixel deltas from v0";
3006 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3007 fs_reg(this, glsl_type::vec2_type
);
3008 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3009 offset(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
], 1);
3011 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3012 fs_reg(this, glsl_type::float_type
);
3013 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
3014 fs_reg(this, glsl_type::float_type
);
3016 emit(ADD(this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3017 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0)))));
3018 emit(ADD(this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3019 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1)))));
3021 this->current_annotation
= "compute pos.w and 1/pos.w";
3022 /* Compute wpos.w. It's always in our setup, since it's needed to
3023 * interpolate the other attributes.
3025 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
3026 emit(FS_OPCODE_LINTERP
, wpos_w
,
3027 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3028 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
3029 interp_reg(VARYING_SLOT_POS
, 3));
3030 /* Compute the pixel 1/W value from wpos.w. */
3031 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
3032 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
3033 this->current_annotation
= NULL
;
3036 /** Emits the interpolation for the varying inputs. */
3038 fs_visitor::emit_interpolation_setup_gen6()
3040 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
3042 /* If the pixel centers end up used, the setup is the same as for gen4. */
3043 this->current_annotation
= "compute pixel centers";
3044 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
3045 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
3046 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
3047 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
3048 emit(ADD(int_pixel_x
,
3049 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
3050 fs_reg(brw_imm_v(0x10101010))));
3051 emit(ADD(int_pixel_y
,
3052 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
3053 fs_reg(brw_imm_v(0x11001100))));
3055 /* As of gen6, we can no longer mix float and int sources. We have
3056 * to turn the integer pixel centers into floats for their actual
3059 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
3060 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
3061 emit(MOV(this->pixel_x
, int_pixel_x
));
3062 emit(MOV(this->pixel_y
, int_pixel_y
));
3064 this->current_annotation
= "compute pos.w";
3065 this->pixel_w
= fs_reg(brw_vec8_grf(payload
.source_w_reg
, 0));
3066 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
3067 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
3069 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3070 uint8_t reg
= payload
.barycentric_coord_reg
[i
];
3071 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
3072 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
3075 this->current_annotation
= NULL
;
3079 fs_visitor::setup_color_payload(fs_reg
*dst
, fs_reg color
, unsigned components
)
3081 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3084 if (color
.file
== BAD_FILE
) {
3085 return 4 * (dispatch_width
/ 8);
3088 uint8_t colors_enabled
;
3089 if (components
== 0) {
3090 /* We want to write one component to the alpha channel */
3091 colors_enabled
= 0x8;
3093 /* Enable the first components-many channels */
3094 colors_enabled
= (1 << components
) - 1;
3097 if (dispatch_width
== 8 || brw
->gen
>= 6) {
3098 /* SIMD8 write looks like:
3104 * gen6 SIMD16 DP write looks like:
3115 for (unsigned i
= 0; i
< 4; ++i
) {
3116 if (colors_enabled
& (1 << i
)) {
3117 dst
[len
] = fs_reg(GRF
, virtual_grf_alloc(color
.width
/ 8),
3118 color
.type
, color
.width
);
3119 inst
= emit(MOV(dst
[len
], offset(color
, i
)));
3120 inst
->saturate
= key
->clamp_fragment_color
;
3121 } else if (color
.width
== 16) {
3122 /* We need two BAD_FILE slots for a 16-wide color */
3129 /* pre-gen6 SIMD16 single source DP write looks like:
3139 for (unsigned i
= 0; i
< 4; ++i
) {
3140 if (colors_enabled
& (1 << i
)) {
3141 dst
[i
] = fs_reg(GRF
, virtual_grf_alloc(1), color
.type
);
3142 inst
= emit(MOV(dst
[i
], half(offset(color
, i
), 0)));
3143 inst
->saturate
= key
->clamp_fragment_color
;
3145 dst
[i
+ 4] = fs_reg(GRF
, virtual_grf_alloc(1), color
.type
);
3146 inst
= emit(MOV(dst
[i
+ 4], half(offset(color
, i
), 1)));
3147 inst
->saturate
= key
->clamp_fragment_color
;
3148 inst
->force_sechalf
= true;
3155 static enum brw_conditional_mod
3156 cond_for_alpha_func(GLenum func
)
3160 return BRW_CONDITIONAL_G
;
3162 return BRW_CONDITIONAL_GE
;
3164 return BRW_CONDITIONAL_L
;
3166 return BRW_CONDITIONAL_LE
;
3168 return BRW_CONDITIONAL_EQ
;
3170 return BRW_CONDITIONAL_NEQ
;
3172 unreachable("Not reached");
3177 * Alpha test support for when we compile it into the shader instead
3178 * of using the normal fixed-function alpha test.
3181 fs_visitor::emit_alpha_test()
3183 assert(stage
== MESA_SHADER_FRAGMENT
);
3184 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3185 this->current_annotation
= "Alpha test";
3188 if (key
->alpha_test_func
== GL_ALWAYS
)
3191 if (key
->alpha_test_func
== GL_NEVER
) {
3193 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3194 BRW_REGISTER_TYPE_UW
));
3195 cmp
= emit(CMP(reg_null_f
, some_reg
, some_reg
,
3196 BRW_CONDITIONAL_NEQ
));
3199 fs_reg color
= offset(outputs
[0], 3);
3201 /* f0.1 &= func(color, ref) */
3202 cmp
= emit(CMP(reg_null_f
, color
, fs_reg(key
->alpha_test_ref
),
3203 cond_for_alpha_func(key
->alpha_test_func
)));
3205 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3206 cmp
->flag_subreg
= 1;
3210 fs_visitor::emit_single_fb_write(fs_reg color0
, fs_reg color1
,
3211 fs_reg src0_alpha
, unsigned components
)
3213 assert(stage
== MESA_SHADER_FRAGMENT
);
3214 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3215 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3217 this->current_annotation
= "FB write header";
3218 bool header_present
= true;
3219 int reg_size
= dispatch_width
/ 8;
3221 /* We can potentially have a message length of up to 15, so we have to set
3222 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3224 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 15);
3227 /* From the Sandy Bridge PRM, volume 4, page 198:
3229 * "Dispatched Pixel Enables. One bit per pixel indicating
3230 * which pixels were originally enabled when the thread was
3231 * dispatched. This field is only required for the end-of-
3232 * thread message and on all dual-source messages."
3234 if (brw
->gen
>= 6 &&
3235 (brw
->is_haswell
|| brw
->gen
>= 8 || !prog_data
->uses_kill
) &&
3236 color1
.file
== BAD_FILE
&&
3237 key
->nr_color_regions
== 1) {
3238 header_present
= false;
3242 /* Allocate 2 registers for a header */
3245 if (payload
.aa_dest_stencil_reg
) {
3246 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(1));
3247 emit(MOV(sources
[length
],
3248 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0))));
3252 prog_data
->uses_omask
=
3253 prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
3254 if (prog_data
->uses_omask
) {
3255 this->current_annotation
= "FB write oMask";
3256 assert(this->sample_mask
.file
!= BAD_FILE
);
3257 /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
3258 * it's unsinged single words, one vgrf is always 16-wide.
3260 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(1),
3261 BRW_REGISTER_TYPE_UW
, 16);
3262 emit(FS_OPCODE_SET_OMASK
, sources
[length
], this->sample_mask
);
3266 if (color0
.file
== BAD_FILE
) {
3267 /* Even if there's no color buffers enabled, we still need to send
3268 * alpha out the pipeline to our null renderbuffer to support
3269 * alpha-testing, alpha-to-coverage, and so on.
3271 length
+= setup_color_payload(sources
+ length
, this->outputs
[0], 0);
3272 } else if (color1
.file
== BAD_FILE
) {
3273 if (src0_alpha
.file
!= BAD_FILE
) {
3274 sources
[length
] = fs_reg(GRF
, virtual_grf_alloc(reg_size
),
3275 src0_alpha
.type
, src0_alpha
.width
);
3276 fs_inst
*inst
= emit(MOV(sources
[length
], src0_alpha
));
3277 inst
->saturate
= key
->clamp_fragment_color
;
3281 length
+= setup_color_payload(sources
+ length
, color0
, components
);
3283 length
+= setup_color_payload(sources
+ length
, color0
, components
);
3284 length
+= setup_color_payload(sources
+ length
, color1
, components
);
3287 if (source_depth_to_render_target
) {
3288 if (brw
->gen
== 6) {
3289 /* For outputting oDepth on gen6, SIMD8 writes have to be
3290 * used. This would require SIMD8 moves of each half to
3291 * message regs, kind of like pre-gen5 SIMD16 FB writes.
3292 * Just bail on doing so for now.
3294 no16("Missing support for simd16 depth writes on gen6\n");
3297 sources
[length
] = fs_reg(this, glsl_type::float_type
);
3298 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3299 /* Hand over gl_FragDepth. */
3300 assert(this->frag_depth
.file
!= BAD_FILE
);
3301 emit(MOV(sources
[length
], this->frag_depth
));
3303 /* Pass through the payload depth. */
3304 emit(MOV(sources
[length
],
3305 fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
3310 if (payload
.dest_depth_reg
) {
3311 sources
[length
] = fs_reg(this, glsl_type::float_type
);
3312 emit(MOV(sources
[length
],
3313 fs_reg(brw_vec8_grf(payload
.dest_depth_reg
, 0))));
3319 if (brw
->gen
>= 7) {
3320 /* Send from the GRF */
3321 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3322 load
= emit(LOAD_PAYLOAD(payload
, sources
, length
));
3323 payload
.reg
= virtual_grf_alloc(load
->regs_written
);
3324 load
->dst
= payload
;
3325 write
= emit(FS_OPCODE_FB_WRITE
, reg_undef
, payload
);
3326 write
->base_mrf
= -1;
3328 /* Send from the MRF */
3329 load
= emit(LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3331 write
= emit(FS_OPCODE_FB_WRITE
);
3332 write
->base_mrf
= 1;
3335 write
->mlen
= load
->regs_written
;
3336 write
->header_present
= header_present
;
3337 if ((brw
->gen
>= 8 || brw
->is_haswell
) && prog_data
->uses_kill
) {
3338 write
->predicate
= BRW_PREDICATE_NORMAL
;
3339 write
->flag_subreg
= 1;
3345 fs_visitor::emit_fb_writes()
3347 assert(stage
== MESA_SHADER_FRAGMENT
);
3348 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3349 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3352 no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
3353 if (dispatch_width
== 16)
3354 do_dual_src
= false;
3359 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3360 emit_shader_time_end();
3362 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3363 "FB dual-source write");
3364 inst
= emit_single_fb_write(this->outputs
[0], this->dual_src_output
,
3367 prog_data
->dual_src_blend
= true;
3368 } else if (key
->nr_color_regions
> 0) {
3369 for (int target
= 0; target
< key
->nr_color_regions
; target
++) {
3370 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
3371 "FB write target %d",
3374 if (brw
->gen
>= 6 && key
->replicate_alpha
&& target
!= 0)
3375 src0_alpha
= offset(outputs
[0], 3);
3377 if (target
== key
->nr_color_regions
- 1 &&
3378 (INTEL_DEBUG
& DEBUG_SHADER_TIME
))
3379 emit_shader_time_end();
3381 inst
= emit_single_fb_write(this->outputs
[target
], reg_undef
,
3383 this->output_components
[target
]);
3384 inst
->target
= target
;
3387 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
3388 emit_shader_time_end();
3390 /* Even if there's no color buffers enabled, we still need to send
3391 * alpha out the pipeline to our null renderbuffer to support
3392 * alpha-testing, alpha-to-coverage, and so on.
3394 inst
= emit_single_fb_write(reg_undef
, reg_undef
, reg_undef
, 0);
3399 this->current_annotation
= NULL
;
3403 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
3405 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
3409 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
3410 emit(MOV(temp
, *reg
));
3415 fs_visitor::resolve_bool_comparison(ir_rvalue
*rvalue
, fs_reg
*reg
)
3417 assert(ctx
->Const
.UniformBooleanTrue
== 1);
3419 if (rvalue
->type
!= glsl_type::bool_type
)
3422 fs_reg temp
= fs_reg(this, glsl_type::bool_type
);
3423 emit(AND(temp
, *reg
, fs_reg(1u)));
3427 fs_visitor::fs_visitor(struct brw_context
*brw
,
3429 const struct brw_wm_prog_key
*key
,
3430 struct brw_wm_prog_data
*prog_data
,
3431 struct gl_shader_program
*shader_prog
,
3432 struct gl_fragment_program
*fp
,
3433 unsigned dispatch_width
)
3434 : backend_visitor(brw
, shader_prog
, &fp
->Base
, &prog_data
->base
,
3435 MESA_SHADER_FRAGMENT
),
3436 reg_null_f(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_F
)),
3437 reg_null_d(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_D
)),
3438 reg_null_ud(retype(brw_null_vec(dispatch_width
), BRW_REGISTER_TYPE_UD
)),
3439 key(key
), prog_data(&prog_data
->base
),
3440 dispatch_width(dispatch_width
)
3442 this->mem_ctx
= mem_ctx
;
3449 this->failed
= false;
3450 this->simd16_unsupported
= false;
3451 this->no16_msg
= NULL
;
3452 this->variable_ht
= hash_table_ctor(0,
3453 hash_table_pointer_hash
,
3454 hash_table_pointer_compare
);
3456 memset(&this->payload
, 0, sizeof(this->payload
));
3457 memset(this->outputs
, 0, sizeof(this->outputs
));
3458 memset(this->output_components
, 0, sizeof(this->output_components
));
3459 this->source_depth_to_render_target
= false;
3460 this->runtime_check_aads_emit
= false;
3461 this->first_non_payload_grf
= 0;
3462 this->max_grf
= brw
->gen
>= 7 ? GEN7_MRF_HACK_START
: BRW_MAX_GRF
;
3464 this->current_annotation
= NULL
;
3465 this->base_ir
= NULL
;
3467 this->virtual_grf_sizes
= NULL
;
3468 this->virtual_grf_count
= 0;
3469 this->virtual_grf_array_size
= 0;
3470 this->virtual_grf_start
= NULL
;
3471 this->virtual_grf_end
= NULL
;
3472 this->live_intervals
= NULL
;
3473 this->regs_live_at_ip
= NULL
;
3476 this->last_scratch
= 0;
3477 this->pull_constant_loc
= NULL
;
3478 this->push_constant_loc
= NULL
;
3480 this->spilled_any_registers
= false;
3481 this->do_dual_src
= false;
3483 if (dispatch_width
== 8)
3484 this->param_size
= rzalloc_array(mem_ctx
, int, stage_prog_data
->nr_params
);
3487 fs_visitor::~fs_visitor()
3489 hash_table_dtor(this->variable_ht
);