2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_visitor.cpp
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
32 #include <sys/types.h>
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
47 #include "brw_shader.h"
49 #include "glsl/glsl_types.h"
50 #include "glsl/ir_optimization.h"
51 #include "glsl/ir_print_visitor.h"
54 fs_visitor::visit(ir_variable
*ir
)
58 if (variable_storage(ir
))
61 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
62 this->frag_color
= ir
;
63 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
65 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
66 this->frag_depth
= ir
;
69 if (ir
->mode
== ir_var_in
) {
70 if (!strcmp(ir
->name
, "gl_FragCoord")) {
71 reg
= emit_fragcoord_interpolation(ir
);
72 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
73 reg
= emit_frontfacing_interpolation(ir
);
75 reg
= emit_general_interpolation(ir
);
78 hash_table_insert(this->variable_ht
, reg
, ir
);
82 if (ir
->mode
== ir_var_uniform
) {
83 int param_index
= c
->prog_data
.nr_params
;
85 if (c
->dispatch_width
== 16) {
86 if (!variable_storage(ir
)) {
87 fail("Failed to find uniform '%s' in 16-wide\n", ir
->name
);
92 if (!strncmp(ir
->name
, "gl_", 3)) {
93 setup_builtin_uniform_values(ir
);
95 setup_uniform_values(ir
->location
, ir
->type
);
98 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
99 reg
->type
= brw_type_for_base_type(ir
->type
);
103 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
105 hash_table_insert(this->variable_ht
, reg
, ir
);
109 fs_visitor::visit(ir_dereference_variable
*ir
)
111 fs_reg
*reg
= variable_storage(ir
->var
);
116 fs_visitor::visit(ir_dereference_record
*ir
)
118 const glsl_type
*struct_type
= ir
->record
->type
;
120 ir
->record
->accept(this);
122 unsigned int offset
= 0;
123 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
124 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
126 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
128 this->result
.reg_offset
+= offset
;
129 this->result
.type
= brw_type_for_base_type(ir
->type
);
133 fs_visitor::visit(ir_dereference_array
*ir
)
138 ir
->array
->accept(this);
139 index
= ir
->array_index
->as_constant();
141 element_size
= type_size(ir
->type
);
142 this->result
.type
= brw_type_for_base_type(ir
->type
);
145 assert(this->result
.file
== UNIFORM
|| this->result
.file
== GRF
);
146 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
148 assert(!"FINISHME: non-constant array element");
152 /* Instruction selection: Produce a MOV.sat instead of
153 * MIN(MAX(val, 0), 1) when possible.
156 fs_visitor::try_emit_saturate(ir_expression
*ir
)
158 ir_rvalue
*sat_val
= ir
->as_rvalue_to_saturate();
163 sat_val
->accept(this);
164 fs_reg src
= this->result
;
166 this->result
= fs_reg(this, ir
->type
);
167 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, this->result
, src
);
168 inst
->saturate
= true;
174 fs_visitor::visit(ir_expression
*ir
)
176 unsigned int operand
;
180 assert(ir
->get_num_operands() <= 2);
182 if (try_emit_saturate(ir
))
185 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
186 ir
->operands
[operand
]->accept(this);
187 if (this->result
.file
== BAD_FILE
) {
189 fail("Failed to get tree for expression operand:\n");
190 ir
->operands
[operand
]->accept(&v
);
192 op
[operand
] = this->result
;
194 /* Matrix expression operands should have been broken down to vector
195 * operations already.
197 assert(!ir
->operands
[operand
]->type
->is_matrix());
198 /* And then those vector operands should have been broken down to scalar.
200 assert(!ir
->operands
[operand
]->type
->is_vector());
203 /* Storage for our result. If our result goes into an assignment, it will
204 * just get copy-propagated out, so no worries.
206 this->result
= fs_reg(this, ir
->type
);
208 switch (ir
->operation
) {
209 case ir_unop_logic_not
:
210 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
211 * ones complement of the whole register, not just bit 0.
213 emit(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1));
216 op
[0].negate
= !op
[0].negate
;
217 this->result
= op
[0];
221 op
[0].negate
= false;
222 this->result
= op
[0];
225 temp
= fs_reg(this, ir
->type
);
227 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
));
229 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
230 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
231 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
));
232 inst
->predicated
= true;
234 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
));
235 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
236 inst
= emit(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
));
237 inst
->predicated
= true;
241 emit_math(SHADER_OPCODE_RCP
, this->result
, op
[0]);
245 emit_math(SHADER_OPCODE_EXP2
, this->result
, op
[0]);
248 emit_math(SHADER_OPCODE_LOG2
, this->result
, op
[0]);
252 assert(!"not reached: should be handled by ir_explog_to_explog2");
255 case ir_unop_sin_reduced
:
256 emit_math(SHADER_OPCODE_SIN
, this->result
, op
[0]);
259 case ir_unop_cos_reduced
:
260 emit_math(SHADER_OPCODE_COS
, this->result
, op
[0]);
264 emit(FS_OPCODE_DDX
, this->result
, op
[0]);
267 emit(FS_OPCODE_DDY
, this->result
, op
[0]);
271 emit(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]);
274 assert(!"not reached: should be handled by ir_sub_to_add_neg");
278 if (ir
->type
->is_integer()) {
279 /* For integer multiplication, the MUL uses the low 16 bits
280 * of one of the operands (src0 on gen6, src1 on gen7). The
281 * MACH accumulates in the contribution of the upper 16 bits
284 * FINISHME: Emit just the MUL if we know an operand is small
287 struct brw_reg acc
= retype(brw_acc_reg(), BRW_REGISTER_TYPE_D
);
289 emit(BRW_OPCODE_MUL
, acc
, op
[0], op
[1]);
290 emit(BRW_OPCODE_MACH
, reg_null_d
, op
[0], op
[1]);
291 emit(BRW_OPCODE_MOV
, this->result
, fs_reg(acc
));
293 emit(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]);
297 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
298 assert(ir
->type
->is_integer());
299 emit_math(SHADER_OPCODE_INT_QUOTIENT
, this->result
, op
[0], op
[1]);
302 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
303 assert(ir
->type
->is_integer());
304 emit_math(SHADER_OPCODE_INT_REMAINDER
, this->result
, op
[0], op
[1]);
308 case ir_binop_greater
:
309 case ir_binop_lequal
:
310 case ir_binop_gequal
:
312 case ir_binop_all_equal
:
313 case ir_binop_nequal
:
314 case ir_binop_any_nequal
:
316 /* original gen4 does implicit conversion before comparison. */
318 temp
.type
= op
[0].type
;
320 resolve_ud_negate(&op
[0]);
321 resolve_ud_negate(&op
[1]);
323 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], op
[1]);
324 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->operation
);
325 emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1));
328 case ir_binop_logic_xor
:
329 emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
332 case ir_binop_logic_or
:
333 emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
336 case ir_binop_logic_and
:
337 emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
342 assert(!"not reached: should be handled by brw_fs_channel_expressions");
346 assert(!"not reached: should be handled by lower_noise");
349 case ir_quadop_vector
:
350 assert(!"not reached: should be handled by lower_quadop_vector");
354 emit_math(SHADER_OPCODE_SQRT
, this->result
, op
[0]);
358 emit_math(SHADER_OPCODE_RSQ
, this->result
, op
[0]);
362 op
[0].type
= BRW_REGISTER_TYPE_UD
;
363 this->result
= op
[0];
366 op
[0].type
= BRW_REGISTER_TYPE_D
;
367 this->result
= op
[0];
374 emit(BRW_OPCODE_MOV
, this->result
, op
[0]);
379 /* original gen4 does implicit conversion before comparison. */
381 temp
.type
= op
[0].type
;
383 resolve_ud_negate(&op
[0]);
385 inst
= emit(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
));
386 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
387 inst
= emit(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(1));
391 emit(BRW_OPCODE_RNDZ
, this->result
, op
[0]);
394 op
[0].negate
= !op
[0].negate
;
395 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
396 this->result
.negate
= true;
399 inst
= emit(BRW_OPCODE_RNDD
, this->result
, op
[0]);
402 inst
= emit(BRW_OPCODE_FRC
, this->result
, op
[0]);
404 case ir_unop_round_even
:
405 emit(BRW_OPCODE_RNDE
, this->result
, op
[0]);
409 resolve_ud_negate(&op
[0]);
410 resolve_ud_negate(&op
[1]);
412 if (intel
->gen
>= 6) {
413 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
414 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
416 /* Unalias the destination */
417 this->result
= fs_reg(this, ir
->type
);
419 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
420 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
422 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
423 inst
->predicated
= true;
427 resolve_ud_negate(&op
[0]);
428 resolve_ud_negate(&op
[1]);
430 if (intel
->gen
>= 6) {
431 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
432 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
434 /* Unalias the destination */
435 this->result
= fs_reg(this, ir
->type
);
437 inst
= emit(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]);
438 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
440 inst
= emit(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]);
441 inst
->predicated
= true;
446 emit_math(SHADER_OPCODE_POW
, this->result
, op
[0], op
[1]);
449 case ir_unop_bit_not
:
450 inst
= emit(BRW_OPCODE_NOT
, this->result
, op
[0]);
452 case ir_binop_bit_and
:
453 inst
= emit(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]);
455 case ir_binop_bit_xor
:
456 inst
= emit(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]);
458 case ir_binop_bit_or
:
459 inst
= emit(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]);
462 case ir_binop_lshift
:
463 inst
= emit(BRW_OPCODE_SHL
, this->result
, op
[0], op
[1]);
466 case ir_binop_rshift
:
467 if (ir
->type
->base_type
== GLSL_TYPE_INT
)
468 inst
= emit(BRW_OPCODE_ASR
, this->result
, op
[0], op
[1]);
470 inst
= emit(BRW_OPCODE_SHR
, this->result
, op
[0], op
[1]);
476 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
477 const glsl_type
*type
, bool predicated
)
479 switch (type
->base_type
) {
480 case GLSL_TYPE_FLOAT
:
484 for (unsigned int i
= 0; i
< type
->components(); i
++) {
485 l
.type
= brw_type_for_base_type(type
);
486 r
.type
= brw_type_for_base_type(type
);
488 if (predicated
|| !l
.equals(&r
)) {
489 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, l
, r
);
490 inst
->predicated
= predicated
;
497 case GLSL_TYPE_ARRAY
:
498 for (unsigned int i
= 0; i
< type
->length
; i
++) {
499 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
503 case GLSL_TYPE_STRUCT
:
504 for (unsigned int i
= 0; i
< type
->length
; i
++) {
505 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
510 case GLSL_TYPE_SAMPLER
:
514 assert(!"not reached");
519 /* If the RHS processing resulted in an instruction generating a
520 * temporary value, and it would be easy to rewrite the instruction to
521 * generate its result right into the LHS instead, do so. This ends
522 * up reliably removing instructions where it can be tricky to do so
523 * later without real UD chain information.
526 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment
*ir
,
529 fs_inst
*pre_rhs_inst
,
530 fs_inst
*last_rhs_inst
)
532 if (pre_rhs_inst
== last_rhs_inst
)
533 return false; /* No instructions generated to work with. */
535 /* Only attempt if we're doing a direct assignment. */
537 !(ir
->lhs
->type
->is_scalar() ||
538 (ir
->lhs
->type
->is_vector() &&
539 ir
->write_mask
== (1 << ir
->lhs
->type
->vector_elements
) - 1)))
542 /* Make sure the last instruction generated our source reg. */
543 if (last_rhs_inst
->predicated
||
544 last_rhs_inst
->force_uncompressed
||
545 last_rhs_inst
->force_sechalf
||
546 !src
.equals(&last_rhs_inst
->dst
))
549 /* Success! Rewrite the instruction. */
550 last_rhs_inst
->dst
= dst
;
556 fs_visitor::visit(ir_assignment
*ir
)
561 /* FINISHME: arrays on the lhs */
562 ir
->lhs
->accept(this);
565 fs_inst
*pre_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
567 ir
->rhs
->accept(this);
570 fs_inst
*last_rhs_inst
= (fs_inst
*) this->instructions
.get_tail();
572 assert(l
.file
!= BAD_FILE
);
573 assert(r
.file
!= BAD_FILE
);
575 if (try_rewrite_rhs_to_dst(ir
, l
, r
, pre_rhs_inst
, last_rhs_inst
))
579 emit_bool_to_cond_code(ir
->condition
);
582 if (ir
->lhs
->type
->is_scalar() ||
583 ir
->lhs
->type
->is_vector()) {
584 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
585 if (ir
->write_mask
& (1 << i
)) {
586 inst
= emit(BRW_OPCODE_MOV
, l
, r
);
588 inst
->predicated
= true;
594 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
599 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
610 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
611 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
612 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
613 fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
614 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
615 inst
->saturate
= true;
617 coordinate
.reg_offset
++;
619 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
622 if (ir
->op
== ir_tex
) {
623 /* There's no plain shadow compare message, so we use shadow
624 * compare with a bias of 0.0.
626 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), fs_reg(0.0f
));
628 } else if (ir
->op
== ir_txb
) {
629 ir
->lod_info
.bias
->accept(this);
630 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
633 assert(ir
->op
== ir_txl
);
634 ir
->lod_info
.lod
->accept(this);
635 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
639 ir
->shadow_comparitor
->accept(this);
640 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
642 } else if (ir
->op
== ir_tex
) {
643 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
644 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
646 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
647 inst
->saturate
= true;
648 coordinate
.reg_offset
++;
650 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
652 } else if (ir
->op
== ir_txd
) {
653 ir
->lod_info
.grad
.dPdx
->accept(this);
654 fs_reg dPdx
= this->result
;
656 ir
->lod_info
.grad
.dPdy
->accept(this);
657 fs_reg dPdy
= this->result
;
659 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
660 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
), coordinate
);
661 coordinate
.reg_offset
++;
663 /* the slots for u and v are always present, but r is optional */
664 mlen
+= MAX2(ir
->coordinate
->type
->vector_elements
, 2);
667 * dPdx = dudx, dvdx, drdx
668 * dPdy = dudy, dvdy, drdy
670 * 1-arg: Does not exist.
672 * 2-arg: dudx dvdx dudy dvdy
673 * dPdx.x dPdx.y dPdy.x dPdy.y
676 * 3-arg: dudx dvdx drdx dudy dvdy drdy
677 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
680 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
681 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
684 mlen
+= MAX2(ir
->lod_info
.grad
.dPdx
->type
->vector_elements
, 2);
686 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdy
->type
->vector_elements
; i
++) {
687 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
690 mlen
+= MAX2(ir
->lod_info
.grad
.dPdy
->type
->vector_elements
, 2);
691 } else if (ir
->op
== ir_txs
) {
692 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
694 ir
->lod_info
.lod
->accept(this);
695 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
698 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
699 * instructions. We'll need to do SIMD16 here.
702 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
|| ir
->op
== ir_txf
);
704 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
705 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
,
706 base_mrf
+ mlen
+ i
* 2,
709 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
710 inst
->saturate
= true;
711 coordinate
.reg_offset
++;
714 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
715 * be necessary for TXF (ld), but seems wise to do for all messages.
717 for (int i
= ir
->coordinate
->type
->vector_elements
; i
< 3; i
++) {
718 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2), fs_reg(0.0f
));
721 /* lod/bias appears after u/v/r. */
724 if (ir
->op
== ir_txb
) {
725 ir
->lod_info
.bias
->accept(this);
726 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
729 ir
->lod_info
.lod
->accept(this);
730 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, this->result
.type
),
735 /* The unused upper half. */
740 /* Now, since we're doing simd16, the return is 2 interleaved
741 * vec4s where the odd-indexed ones are junk. We'll need to move
742 * this weirdness around to the expected layout.
745 const glsl_type
*vec_type
=
746 glsl_type::get_instance(ir
->type
->base_type
, 4, 1);
747 dst
= fs_reg(this, glsl_type::get_array_instance(vec_type
, 2));
748 dst
.type
= intel
->is_g4x
? brw_type_for_base_type(ir
->type
)
749 : BRW_REGISTER_TYPE_F
;
752 fs_inst
*inst
= NULL
;
755 inst
= emit(FS_OPCODE_TEX
, dst
);
758 inst
= emit(FS_OPCODE_TXB
, dst
);
761 inst
= emit(FS_OPCODE_TXL
, dst
);
764 inst
= emit(FS_OPCODE_TXD
, dst
);
767 inst
= emit(FS_OPCODE_TXS
, dst
);
770 inst
= emit(FS_OPCODE_TXF
, dst
);
773 inst
->base_mrf
= base_mrf
;
775 inst
->header_present
= true;
778 for (int i
= 0; i
< 4; i
++) {
779 emit(BRW_OPCODE_MOV
, orig_dst
, dst
);
780 orig_dst
.reg_offset
++;
788 /* gen5's sampler has slots for u, v, r, array index, then optional
789 * parameters like shadow comparitor or LOD bias. If optional
790 * parameters aren't present, those base slots are optional and don't
791 * need to be included in the message.
793 * We don't fill in the unnecessary slots regardless, which may look
794 * surprising in the disassembly.
797 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
802 int reg_width
= c
->dispatch_width
/ 8;
803 bool header_present
= false;
804 const int vector_elements
=
805 ir
->coordinate
? ir
->coordinate
->type
->vector_elements
: 0;
808 /* The offsets set up by the ir_texture visitor are in the
809 * m1 header, so we can't go headerless.
811 header_present
= true;
816 for (int i
= 0; i
< vector_elements
; i
++) {
817 fs_inst
*inst
= emit(BRW_OPCODE_MOV
,
818 fs_reg(MRF
, base_mrf
+ mlen
+ i
* reg_width
,
821 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
822 inst
->saturate
= true;
823 coordinate
.reg_offset
++;
825 mlen
+= vector_elements
* reg_width
;
827 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
828 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
830 ir
->shadow_comparitor
->accept(this);
831 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
835 fs_inst
*inst
= NULL
;
838 inst
= emit(FS_OPCODE_TEX
, dst
);
841 ir
->lod_info
.bias
->accept(this);
842 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
843 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
846 inst
= emit(FS_OPCODE_TXB
, dst
);
850 ir
->lod_info
.lod
->accept(this);
851 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
);
852 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
855 inst
= emit(FS_OPCODE_TXL
, dst
);
858 ir
->lod_info
.grad
.dPdx
->accept(this);
859 fs_reg dPdx
= this->result
;
861 ir
->lod_info
.grad
.dPdy
->accept(this);
862 fs_reg dPdy
= this->result
;
864 mlen
= MAX2(mlen
, header_present
+ 4 * reg_width
); /* skip over 'ai' */
868 * dPdx = dudx, dvdx, drdx
869 * dPdy = dudy, dvdy, drdy
871 * Load up these values:
872 * - dudx dudy dvdx dvdy drdx drdy
873 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
875 for (int i
= 0; i
< ir
->lod_info
.grad
.dPdx
->type
->vector_elements
; i
++) {
876 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
880 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
885 inst
= emit(FS_OPCODE_TXD
, dst
);
889 ir
->lod_info
.lod
->accept(this);
890 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
892 inst
= emit(FS_OPCODE_TXS
, dst
);
895 mlen
= header_present
+ 4 * reg_width
;
897 ir
->lod_info
.lod
->accept(this);
899 fs_reg(MRF
, base_mrf
+ mlen
- reg_width
, BRW_REGISTER_TYPE_UD
),
901 inst
= emit(FS_OPCODE_TXF
, dst
);
904 inst
->base_mrf
= base_mrf
;
906 inst
->header_present
= header_present
;
909 fail("Message length >11 disallowed by hardware\n");
916 fs_visitor::emit_texture_gen7(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
,
921 int reg_width
= c
->dispatch_width
/ 8;
922 bool header_present
= false;
925 /* The offsets set up by the ir_texture visitor are in the
926 * m1 header, so we can't go headerless.
928 header_present
= true;
933 if (ir
->shadow_comparitor
&& ir
->op
!= ir_txd
) {
934 ir
->shadow_comparitor
->accept(this);
935 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
939 /* Set up the LOD info */
944 ir
->lod_info
.bias
->accept(this);
945 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
949 ir
->lod_info
.lod
->accept(this);
950 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
);
954 if (c
->dispatch_width
== 16)
955 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
957 ir
->lod_info
.grad
.dPdx
->accept(this);
958 fs_reg dPdx
= this->result
;
960 ir
->lod_info
.grad
.dPdy
->accept(this);
961 fs_reg dPdy
= this->result
;
963 /* Load dPdx and the coordinate together:
964 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
966 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
967 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
969 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
970 inst
->saturate
= true;
971 coordinate
.reg_offset
++;
974 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdx
);
978 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), dPdy
);
985 ir
->lod_info
.lod
->accept(this);
986 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_UD
), this->result
);
990 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
992 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
);
993 coordinate
.reg_offset
++;
996 ir
->lod_info
.lod
->accept(this);
997 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), this->result
);
1000 for (int i
= 1; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1001 emit(BRW_OPCODE_MOV
,
1002 fs_reg(MRF
, base_mrf
+ mlen
, BRW_REGISTER_TYPE_D
), coordinate
);
1003 coordinate
.reg_offset
++;
1009 /* Set up the coordinate (except for cases where it was done above) */
1010 if (ir
->op
!= ir_txd
&& ir
->op
!= ir_txs
&& ir
->op
!= ir_txf
) {
1011 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1012 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1014 if (i
< 3 && c
->key
.gl_clamp_mask
[i
] & (1 << sampler
))
1015 inst
->saturate
= true;
1016 coordinate
.reg_offset
++;
1021 /* Generate the SEND */
1022 fs_inst
*inst
= NULL
;
1024 case ir_tex
: inst
= emit(FS_OPCODE_TEX
, dst
); break;
1025 case ir_txb
: inst
= emit(FS_OPCODE_TXB
, dst
); break;
1026 case ir_txl
: inst
= emit(FS_OPCODE_TXL
, dst
); break;
1027 case ir_txd
: inst
= emit(FS_OPCODE_TXD
, dst
); break;
1028 case ir_txf
: inst
= emit(FS_OPCODE_TXF
, dst
); break;
1029 case ir_txs
: inst
= emit(FS_OPCODE_TXS
, dst
); break;
1031 inst
->base_mrf
= base_mrf
;
1033 inst
->header_present
= header_present
;
1036 fail("Message length >11 disallowed by hardware\n");
1043 fs_visitor::visit(ir_texture
*ir
)
1045 fs_inst
*inst
= NULL
;
1047 int sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
, prog
, &fp
->Base
);
1048 sampler
= fp
->Base
.SamplerUnits
[sampler
];
1050 /* Our hardware doesn't have a sample_d_c message, so shadow compares
1051 * for textureGrad/TXD need to be emulated with instructions.
1053 bool hw_compare_supported
= ir
->op
!= ir_txd
;
1054 if (ir
->shadow_comparitor
&& !hw_compare_supported
) {
1055 assert(c
->key
.compare_funcs
[sampler
] != GL_NONE
);
1056 /* No need to even sample for GL_ALWAYS or GL_NEVER...bail early */
1057 if (c
->key
.compare_funcs
[sampler
] == GL_ALWAYS
)
1058 return swizzle_result(ir
, fs_reg(1.0f
), sampler
);
1059 else if (c
->key
.compare_funcs
[sampler
] == GL_NEVER
)
1060 return swizzle_result(ir
, fs_reg(0.0f
), sampler
);
1064 ir
->coordinate
->accept(this);
1065 fs_reg coordinate
= this->result
;
1067 if (ir
->offset
!= NULL
) {
1068 ir_constant
*offset
= ir
->offset
->as_constant();
1069 assert(offset
!= NULL
);
1071 signed char offsets
[3];
1072 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++)
1073 offsets
[i
] = (signed char) offset
->value
.i
[i
];
1075 /* Combine all three offsets into a single unsigned dword:
1077 * bits 11:8 - U Offset (X component)
1078 * bits 7:4 - V Offset (Y component)
1079 * bits 3:0 - R Offset (Z component)
1081 unsigned offset_bits
= 0;
1082 for (unsigned i
= 0; i
< ir
->offset
->type
->vector_elements
; i
++) {
1083 const unsigned shift
= 4 * (2 - i
);
1084 offset_bits
|= (offsets
[i
] << shift
) & (0xF << shift
);
1087 /* Explicitly set up the message header by copying g0 to msg reg m1. */
1088 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 1, BRW_REGISTER_TYPE_UD
),
1089 fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)));
1091 /* Then set the offset bits in DWord 2 of the message header. */
1092 emit(BRW_OPCODE_MOV
,
1093 fs_reg(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 1, 2),
1094 BRW_REGISTER_TYPE_UD
)),
1095 fs_reg(brw_imm_uw(offset_bits
)));
1098 /* Should be lowered by do_lower_texture_projection */
1099 assert(!ir
->projector
);
1101 /* The 965 requires the EU to do the normalization of GL rectangle
1102 * texture coordinates. We use the program parameter state
1103 * tracking to get the scaling factor.
1105 if (intel
->gen
< 6 &&
1106 ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1107 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1108 int tokens
[STATE_LENGTH
] = {
1110 STATE_TEXRECT_SCALE
,
1116 if (c
->dispatch_width
== 16) {
1117 fail("rectangle scale uniform setup not supported on 16-wide\n");
1118 this->result
= fs_reg(this, ir
->type
);
1122 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
] =
1124 c
->prog_data
.param_convert
[c
->prog_data
.nr_params
+ 1] =
1127 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1128 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1129 GLuint index
= _mesa_add_state_reference(params
,
1130 (gl_state_index
*)tokens
);
1132 this->param_index
[c
->prog_data
.nr_params
] = index
;
1133 this->param_offset
[c
->prog_data
.nr_params
] = 0;
1134 c
->prog_data
.nr_params
++;
1135 this->param_index
[c
->prog_data
.nr_params
] = index
;
1136 this->param_offset
[c
->prog_data
.nr_params
] = 1;
1137 c
->prog_data
.nr_params
++;
1139 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1140 fs_reg src
= coordinate
;
1143 emit(BRW_OPCODE_MUL
, dst
, src
, scale_x
);
1146 emit(BRW_OPCODE_MUL
, dst
, src
, scale_y
);
1149 /* Writemasking doesn't eliminate channels on SIMD8 texture
1150 * samples, so don't worry about them.
1152 fs_reg dst
= fs_reg(this, glsl_type::get_instance(ir
->type
->base_type
, 4, 1));
1154 if (intel
->gen
>= 7) {
1155 inst
= emit_texture_gen7(ir
, dst
, coordinate
, sampler
);
1156 } else if (intel
->gen
>= 5) {
1157 inst
= emit_texture_gen5(ir
, dst
, coordinate
, sampler
);
1159 inst
= emit_texture_gen4(ir
, dst
, coordinate
, sampler
);
1162 /* If there's an offset, we already set up m1. To avoid the implied move,
1163 * use the null register. Otherwise, we want an implied move from g0.
1165 if (ir
->offset
!= NULL
|| !inst
->header_present
)
1166 inst
->src
[0] = reg_undef
;
1168 inst
->src
[0] = fs_reg(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1170 inst
->sampler
= sampler
;
1172 if (ir
->shadow_comparitor
) {
1173 if (hw_compare_supported
) {
1174 inst
->shadow_compare
= true;
1176 ir
->shadow_comparitor
->accept(this);
1177 fs_reg ref
= this->result
;
1180 dst
= fs_reg(this, glsl_type::vec4_type
);
1182 /* FINISHME: This needs to be done pre-filtering. */
1184 uint32_t conditional
= 0;
1185 switch (c
->key
.compare_funcs
[sampler
]) {
1186 /* GL_ALWAYS and GL_NEVER were handled at the top of the function */
1187 case GL_LESS
: conditional
= BRW_CONDITIONAL_L
; break;
1188 case GL_GREATER
: conditional
= BRW_CONDITIONAL_G
; break;
1189 case GL_LEQUAL
: conditional
= BRW_CONDITIONAL_LE
; break;
1190 case GL_GEQUAL
: conditional
= BRW_CONDITIONAL_GE
; break;
1191 case GL_EQUAL
: conditional
= BRW_CONDITIONAL_EQ
; break;
1192 case GL_NOTEQUAL
: conditional
= BRW_CONDITIONAL_NEQ
; break;
1193 default: assert(!"Should not get here: bad shadow compare function");
1196 /* Use conditional moves to load 0 or 1 as the result */
1197 this->current_annotation
= "manual shadow comparison";
1198 for (int i
= 0; i
< 4; i
++) {
1199 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(0.0f
));
1201 inst
= emit(BRW_OPCODE_CMP
, reg_null_f
, ref
, value
);
1202 inst
->conditional_mod
= conditional
;
1204 inst
= emit(BRW_OPCODE_MOV
, dst
, fs_reg(1.0f
));
1205 inst
->predicated
= true;
1214 swizzle_result(ir
, dst
, sampler
);
1218 * Swizzle the result of a texture result. This is necessary for
1219 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1222 fs_visitor::swizzle_result(ir_texture
*ir
, fs_reg orig_val
, int sampler
)
1224 this->result
= orig_val
;
1226 if (ir
->type
== glsl_type::float_type
) {
1227 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1228 assert(ir
->sampler
->type
->sampler_shadow
);
1229 } else if (c
->key
.tex_swizzles
[sampler
] != SWIZZLE_NOOP
) {
1230 fs_reg swizzled_result
= fs_reg(this, glsl_type::vec4_type
);
1232 for (int i
= 0; i
< 4; i
++) {
1233 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1234 fs_reg l
= swizzled_result
;
1237 if (swiz
== SWIZZLE_ZERO
) {
1238 emit(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
));
1239 } else if (swiz
== SWIZZLE_ONE
) {
1240 emit(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
));
1242 fs_reg r
= orig_val
;
1243 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[sampler
], i
);
1244 emit(BRW_OPCODE_MOV
, l
, r
);
1247 this->result
= swizzled_result
;
1252 fs_visitor::visit(ir_swizzle
*ir
)
1254 ir
->val
->accept(this);
1255 fs_reg val
= this->result
;
1257 if (ir
->type
->vector_elements
== 1) {
1258 this->result
.reg_offset
+= ir
->mask
.x
;
1262 fs_reg result
= fs_reg(this, ir
->type
);
1263 this->result
= result
;
1265 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1266 fs_reg channel
= val
;
1284 channel
.reg_offset
+= swiz
;
1285 emit(BRW_OPCODE_MOV
, result
, channel
);
1286 result
.reg_offset
++;
1291 fs_visitor::visit(ir_discard
*ir
)
1293 assert(ir
->condition
== NULL
); /* FINISHME */
1295 emit(FS_OPCODE_DISCARD
);
1296 kill_emitted
= true;
1300 fs_visitor::visit(ir_constant
*ir
)
1302 /* Set this->result to reg at the bottom of the function because some code
1303 * paths will cause this visitor to be applied to other fields. This will
1304 * cause the value stored in this->result to be modified.
1306 * Make reg constant so that it doesn't get accidentally modified along the
1307 * way. Yes, I actually had this problem. :(
1309 const fs_reg
reg(this, ir
->type
);
1310 fs_reg dst_reg
= reg
;
1312 if (ir
->type
->is_array()) {
1313 const unsigned size
= type_size(ir
->type
->fields
.array
);
1315 for (unsigned i
= 0; i
< ir
->type
->length
; i
++) {
1316 ir
->array_elements
[i
]->accept(this);
1317 fs_reg src_reg
= this->result
;
1319 dst_reg
.type
= src_reg
.type
;
1320 for (unsigned j
= 0; j
< size
; j
++) {
1321 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1322 src_reg
.reg_offset
++;
1323 dst_reg
.reg_offset
++;
1326 } else if (ir
->type
->is_record()) {
1327 foreach_list(node
, &ir
->components
) {
1328 ir_instruction
*const field
= (ir_instruction
*) node
;
1329 const unsigned size
= type_size(field
->type
);
1331 field
->accept(this);
1332 fs_reg src_reg
= this->result
;
1334 dst_reg
.type
= src_reg
.type
;
1335 for (unsigned j
= 0; j
< size
; j
++) {
1336 emit(BRW_OPCODE_MOV
, dst_reg
, src_reg
);
1337 src_reg
.reg_offset
++;
1338 dst_reg
.reg_offset
++;
1342 const unsigned size
= type_size(ir
->type
);
1344 for (unsigned i
= 0; i
< size
; i
++) {
1345 switch (ir
->type
->base_type
) {
1346 case GLSL_TYPE_FLOAT
:
1347 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.f
[i
]));
1349 case GLSL_TYPE_UINT
:
1350 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.u
[i
]));
1353 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg(ir
->value
.i
[i
]));
1355 case GLSL_TYPE_BOOL
:
1356 emit(BRW_OPCODE_MOV
, dst_reg
, fs_reg((int)ir
->value
.b
[i
]));
1359 assert(!"Non-float/uint/int/bool constant");
1361 dst_reg
.reg_offset
++;
1369 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1371 ir_expression
*expr
= ir
->as_expression();
1377 assert(expr
->get_num_operands() <= 2);
1378 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1379 assert(expr
->operands
[i
]->type
->is_scalar());
1381 expr
->operands
[i
]->accept(this);
1382 op
[i
] = this->result
;
1384 resolve_ud_negate(&op
[i
]);
1387 switch (expr
->operation
) {
1388 case ir_unop_logic_not
:
1389 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1));
1390 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1393 case ir_binop_logic_xor
:
1394 inst
= emit(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]);
1395 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1398 case ir_binop_logic_or
:
1399 inst
= emit(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]);
1400 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1403 case ir_binop_logic_and
:
1404 inst
= emit(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]);
1405 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1409 if (intel
->gen
>= 6) {
1410 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0.0f
));
1412 inst
= emit(BRW_OPCODE_MOV
, reg_null_f
, op
[0]);
1414 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1418 if (intel
->gen
>= 6) {
1419 inst
= emit(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0));
1421 inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, op
[0]);
1423 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1426 case ir_binop_greater
:
1427 case ir_binop_gequal
:
1429 case ir_binop_lequal
:
1430 case ir_binop_equal
:
1431 case ir_binop_all_equal
:
1432 case ir_binop_nequal
:
1433 case ir_binop_any_nequal
:
1434 inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, op
[0], op
[1]);
1435 inst
->conditional_mod
=
1436 brw_conditional_for_comparison(expr
->operation
);
1440 assert(!"not reached");
1441 fail("bad cond code\n");
1449 if (intel
->gen
>= 6) {
1450 fs_inst
*inst
= emit(BRW_OPCODE_AND
, reg_null_d
, this->result
, fs_reg(1));
1451 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1453 fs_inst
*inst
= emit(BRW_OPCODE_MOV
, reg_null_d
, this->result
);
1454 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1459 * Emit a gen6 IF statement with the comparison folded into the IF
1463 fs_visitor::emit_if_gen6(ir_if
*ir
)
1465 ir_expression
*expr
= ir
->condition
->as_expression();
1472 assert(expr
->get_num_operands() <= 2);
1473 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1474 assert(expr
->operands
[i
]->type
->is_scalar());
1476 expr
->operands
[i
]->accept(this);
1477 op
[i
] = this->result
;
1480 switch (expr
->operation
) {
1481 case ir_unop_logic_not
:
1482 inst
= emit(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(0));
1483 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1486 case ir_binop_logic_xor
:
1487 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1488 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1491 case ir_binop_logic_or
:
1492 temp
= fs_reg(this, glsl_type::bool_type
);
1493 emit(BRW_OPCODE_OR
, temp
, op
[0], op
[1]);
1494 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1495 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1498 case ir_binop_logic_and
:
1499 temp
= fs_reg(this, glsl_type::bool_type
);
1500 emit(BRW_OPCODE_AND
, temp
, op
[0], op
[1]);
1501 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0));
1502 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1506 inst
= emit(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0));
1507 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1511 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1512 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1515 case ir_binop_greater
:
1516 case ir_binop_gequal
:
1518 case ir_binop_lequal
:
1519 case ir_binop_equal
:
1520 case ir_binop_all_equal
:
1521 case ir_binop_nequal
:
1522 case ir_binop_any_nequal
:
1523 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]);
1524 inst
->conditional_mod
=
1525 brw_conditional_for_comparison(expr
->operation
);
1528 assert(!"not reached");
1529 inst
= emit(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0));
1530 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1531 fail("bad condition\n");
1537 ir
->condition
->accept(this);
1539 fs_inst
*inst
= emit(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0));
1540 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1544 fs_visitor::visit(ir_if
*ir
)
1548 if (intel
->gen
< 6 && c
->dispatch_width
== 16) {
1549 fail("Can't support (non-uniform) control flow on 16-wide\n");
1552 /* Don't point the annotation at the if statement, because then it plus
1553 * the then and else blocks get printed.
1555 this->base_ir
= ir
->condition
;
1557 if (intel
->gen
== 6) {
1560 emit_bool_to_cond_code(ir
->condition
);
1562 inst
= emit(BRW_OPCODE_IF
);
1563 inst
->predicated
= true;
1566 foreach_list(node
, &ir
->then_instructions
) {
1567 ir_instruction
*ir
= (ir_instruction
*)node
;
1573 if (!ir
->else_instructions
.is_empty()) {
1574 emit(BRW_OPCODE_ELSE
);
1576 foreach_list(node
, &ir
->else_instructions
) {
1577 ir_instruction
*ir
= (ir_instruction
*)node
;
1584 emit(BRW_OPCODE_ENDIF
);
1588 fs_visitor::visit(ir_loop
*ir
)
1590 fs_reg counter
= reg_undef
;
1592 if (c
->dispatch_width
== 16) {
1593 fail("Can't support (non-uniform) control flow on 16-wide\n");
1597 this->base_ir
= ir
->counter
;
1598 ir
->counter
->accept(this);
1599 counter
= *(variable_storage(ir
->counter
));
1602 this->base_ir
= ir
->from
;
1603 ir
->from
->accept(this);
1605 emit(BRW_OPCODE_MOV
, counter
, this->result
);
1609 emit(BRW_OPCODE_DO
);
1612 this->base_ir
= ir
->to
;
1613 ir
->to
->accept(this);
1615 fs_inst
*inst
= emit(BRW_OPCODE_CMP
, reg_null_cmp
, counter
, this->result
);
1616 inst
->conditional_mod
= brw_conditional_for_comparison(ir
->cmp
);
1618 inst
= emit(BRW_OPCODE_BREAK
);
1619 inst
->predicated
= true;
1622 foreach_list(node
, &ir
->body_instructions
) {
1623 ir_instruction
*ir
= (ir_instruction
*)node
;
1629 if (ir
->increment
) {
1630 this->base_ir
= ir
->increment
;
1631 ir
->increment
->accept(this);
1632 emit(BRW_OPCODE_ADD
, counter
, counter
, this->result
);
1635 emit(BRW_OPCODE_WHILE
);
1639 fs_visitor::visit(ir_loop_jump
*ir
)
1642 case ir_loop_jump::jump_break
:
1643 emit(BRW_OPCODE_BREAK
);
1645 case ir_loop_jump::jump_continue
:
1646 emit(BRW_OPCODE_CONTINUE
);
1652 fs_visitor::visit(ir_call
*ir
)
1654 assert(!"FINISHME");
1658 fs_visitor::visit(ir_return
*ir
)
1660 assert(!"FINISHME");
1664 fs_visitor::visit(ir_function
*ir
)
1666 /* Ignore function bodies other than main() -- we shouldn't see calls to
1667 * them since they should all be inlined before we get to ir_to_mesa.
1669 if (strcmp(ir
->name
, "main") == 0) {
1670 const ir_function_signature
*sig
;
1673 sig
= ir
->matching_signature(&empty
);
1677 foreach_list(node
, &sig
->body
) {
1678 ir_instruction
*ir
= (ir_instruction
*)node
;
1687 fs_visitor::visit(ir_function_signature
*ir
)
1689 assert(!"not reached");
1694 fs_visitor::emit(fs_inst inst
)
1696 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1699 if (force_uncompressed_stack
> 0)
1700 list_inst
->force_uncompressed
= true;
1701 else if (force_sechalf_stack
> 0)
1702 list_inst
->force_sechalf
= true;
1704 list_inst
->annotation
= this->current_annotation
;
1705 list_inst
->ir
= this->base_ir
;
1707 this->instructions
.push_tail(list_inst
);
1712 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1714 fs_visitor::emit_dummy_fs()
1716 /* Everyone's favorite color. */
1717 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 2), fs_reg(1.0f
));
1718 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 3), fs_reg(0.0f
));
1719 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 4), fs_reg(1.0f
));
1720 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, 5), fs_reg(0.0f
));
1723 write
= emit(FS_OPCODE_FB_WRITE
, fs_reg(0), fs_reg(0));
1724 write
->base_mrf
= 2;
1727 /* The register location here is relative to the start of the URB
1728 * data. It will get adjusted to be a real location before
1729 * generate_code() time.
1732 fs_visitor::interp_reg(int location
, int channel
)
1734 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1735 int stride
= (channel
& 1) * 4;
1737 assert(urb_setup
[location
] != -1);
1739 return brw_vec1_grf(regnr
, stride
);
1742 /** Emits the interpolation for the varying inputs. */
1744 fs_visitor::emit_interpolation_setup_gen4()
1746 this->current_annotation
= "compute pixel centers";
1747 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1748 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1749 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1750 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1752 emit(FS_OPCODE_PIXEL_X
, this->pixel_x
);
1753 emit(FS_OPCODE_PIXEL_Y
, this->pixel_y
);
1755 this->current_annotation
= "compute pixel deltas from v0";
1757 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1758 fs_reg(this, glsl_type::vec2_type
);
1759 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1760 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
];
1761 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
].reg_offset
++;
1763 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1764 fs_reg(this, glsl_type::float_type
);
1765 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
] =
1766 fs_reg(this, glsl_type::float_type
);
1768 emit(BRW_OPCODE_ADD
, this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1769 this->pixel_x
, fs_reg(negate(brw_vec1_grf(1, 0))));
1770 emit(BRW_OPCODE_ADD
, this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1771 this->pixel_y
, fs_reg(negate(brw_vec1_grf(1, 1))));
1773 this->current_annotation
= "compute pos.w and 1/pos.w";
1774 /* Compute wpos.w. It's always in our setup, since it's needed to
1775 * interpolate the other attributes.
1777 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1778 emit(FS_OPCODE_LINTERP
, wpos_w
,
1779 this->delta_x
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1780 this->delta_y
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1781 interp_reg(FRAG_ATTRIB_WPOS
, 3));
1782 /* Compute the pixel 1/W value from wpos.w. */
1783 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1784 emit_math(SHADER_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1785 this->current_annotation
= NULL
;
1788 /** Emits the interpolation for the varying inputs. */
1790 fs_visitor::emit_interpolation_setup_gen6()
1792 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1794 /* If the pixel centers end up used, the setup is the same as for gen4. */
1795 this->current_annotation
= "compute pixel centers";
1796 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1797 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1798 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1799 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1800 emit(BRW_OPCODE_ADD
,
1802 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1803 fs_reg(brw_imm_v(0x10101010)));
1804 emit(BRW_OPCODE_ADD
,
1806 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1807 fs_reg(brw_imm_v(0x11001100)));
1809 /* As of gen6, we can no longer mix float and int sources. We have
1810 * to turn the integer pixel centers into floats for their actual
1813 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1814 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1815 emit(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
);
1816 emit(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
);
1818 this->current_annotation
= "compute pos.w";
1819 this->pixel_w
= fs_reg(brw_vec8_grf(c
->source_w_reg
, 0));
1820 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1821 emit_math(SHADER_OPCODE_RCP
, this->wpos_w
, this->pixel_w
);
1823 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
1824 uint8_t reg
= c
->barycentric_coord_reg
[i
];
1825 this->delta_x
[i
] = fs_reg(brw_vec8_grf(reg
, 0));
1826 this->delta_y
[i
] = fs_reg(brw_vec8_grf(reg
+ 1, 0));
1829 this->current_annotation
= NULL
;
1833 fs_visitor::emit_color_write(int index
, int first_color_mrf
, fs_reg color
)
1835 int reg_width
= c
->dispatch_width
/ 8;
1838 if (c
->dispatch_width
== 8 || intel
->gen
>= 6) {
1839 /* SIMD8 write looks like:
1845 * gen6 SIMD16 DP write looks like:
1855 inst
= emit(BRW_OPCODE_MOV
,
1856 fs_reg(MRF
, first_color_mrf
+ index
* reg_width
),
1858 inst
->saturate
= c
->key
.clamp_fragment_color
;
1860 /* pre-gen6 SIMD16 single source DP write looks like:
1870 if (brw
->has_compr4
) {
1871 /* By setting the high bit of the MRF register number, we
1872 * indicate that we want COMPR4 mode - instead of doing the
1873 * usual destination + 1 for the second half we get
1876 inst
= emit(BRW_OPCODE_MOV
,
1877 fs_reg(MRF
, BRW_MRF_COMPR4
+ first_color_mrf
+ index
),
1879 inst
->saturate
= c
->key
.clamp_fragment_color
;
1881 push_force_uncompressed();
1882 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
),
1884 inst
->saturate
= c
->key
.clamp_fragment_color
;
1885 pop_force_uncompressed();
1887 push_force_sechalf();
1888 color
.sechalf
= true;
1889 inst
= emit(BRW_OPCODE_MOV
, fs_reg(MRF
, first_color_mrf
+ index
+ 4),
1891 inst
->saturate
= c
->key
.clamp_fragment_color
;
1892 pop_force_sechalf();
1893 color
.sechalf
= false;
1899 fs_visitor::emit_fb_writes()
1901 this->current_annotation
= "FB write header";
1902 bool header_present
= true;
1905 int reg_width
= c
->dispatch_width
/ 8;
1907 if (intel
->gen
>= 6 &&
1908 !this->kill_emitted
&&
1909 c
->key
.nr_color_regions
== 1) {
1910 header_present
= false;
1913 if (header_present
) {
1918 if (c
->aa_dest_stencil_reg
) {
1919 push_force_uncompressed();
1920 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1921 fs_reg(brw_vec8_grf(c
->aa_dest_stencil_reg
, 0)));
1922 pop_force_uncompressed();
1925 /* Reserve space for color. It'll be filled in per MRT below. */
1927 nr
+= 4 * reg_width
;
1929 if (c
->source_depth_to_render_target
) {
1930 if (intel
->gen
== 6 && c
->dispatch_width
== 16) {
1931 /* For outputting oDepth on gen6, SIMD8 writes have to be
1932 * used. This would require 8-wide moves of each half to
1933 * message regs, kind of like pre-gen5 SIMD16 FB writes.
1934 * Just bail on doing so for now.
1936 fail("Missing support for simd16 depth writes on gen6\n");
1939 if (c
->computes_depth
) {
1940 /* Hand over gl_FragDepth. */
1941 assert(this->frag_depth
);
1942 fs_reg depth
= *(variable_storage(this->frag_depth
));
1944 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
), depth
);
1946 /* Pass through the payload depth. */
1947 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1948 fs_reg(brw_vec8_grf(c
->source_depth_reg
, 0)));
1953 if (c
->dest_depth_reg
) {
1954 emit(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
),
1955 fs_reg(brw_vec8_grf(c
->dest_depth_reg
, 0)));
1959 fs_reg color
= reg_undef
;
1960 if (this->frag_color
)
1961 color
= *(variable_storage(this->frag_color
));
1962 else if (this->frag_data
) {
1963 color
= *(variable_storage(this->frag_data
));
1964 color
.type
= BRW_REGISTER_TYPE_F
;
1967 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1968 this->current_annotation
= ralloc_asprintf(this->mem_ctx
,
1969 "FB write target %d",
1971 if (this->frag_color
|| this->frag_data
) {
1972 for (int i
= 0; i
< 4; i
++) {
1973 emit_color_write(i
, color_mrf
, color
);
1978 if (this->frag_color
)
1979 color
.reg_offset
-= 4;
1981 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
1982 inst
->target
= target
;
1983 inst
->base_mrf
= base_mrf
;
1984 inst
->mlen
= nr
- base_mrf
;
1985 if (target
== c
->key
.nr_color_regions
- 1)
1987 inst
->header_present
= header_present
;
1990 if (c
->key
.nr_color_regions
== 0) {
1991 if (c
->key
.alpha_test
&& (this->frag_color
|| this->frag_data
)) {
1992 /* If the alpha test is enabled but there's no color buffer,
1993 * we still need to send alpha out the pipeline to our null
1996 color
.reg_offset
+= 3;
1997 emit_color_write(3, color_mrf
, color
);
2000 fs_inst
*inst
= emit(FS_OPCODE_FB_WRITE
);
2001 inst
->base_mrf
= base_mrf
;
2002 inst
->mlen
= nr
- base_mrf
;
2004 inst
->header_present
= header_present
;
2007 this->current_annotation
= NULL
;
2011 fs_visitor::resolve_ud_negate(fs_reg
*reg
)
2013 if (reg
->type
!= BRW_REGISTER_TYPE_UD
||
2017 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
2018 emit(BRW_OPCODE_MOV
, temp
, *reg
);