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i965: Remove never used RSR and RSL opcodes.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_visitor.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_visitor.cpp
25 *
26 * This file supports generating the FS LIR from the GLSL IR. The LIR
27 * makes it easier to do backend-specific optimizations than doing so
28 * in the GLSL IR or in the native code.
29 */
30 extern "C" {
31
32 #include <sys/types.h>
33
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/uniforms.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "program/prog_optimize.h"
40 #include "program/register_allocate.h"
41 #include "program/sampler.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
44 #include "brw_eu.h"
45 #include "brw_wm.h"
46 }
47 #include "brw_fs.h"
48 #include "glsl/glsl_types.h"
49 #include "glsl/ir_optimization.h"
50
51 void
52 fs_visitor::visit(ir_variable *ir)
53 {
54 fs_reg *reg = NULL;
55
56 if (variable_storage(ir))
57 return;
58
59 if (ir->mode == ir_var_shader_in) {
60 if (!strcmp(ir->name, "gl_FragCoord")) {
61 reg = emit_fragcoord_interpolation(ir);
62 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
63 reg = emit_frontfacing_interpolation(ir);
64 } else {
65 reg = emit_general_interpolation(ir);
66 }
67 assert(reg);
68 hash_table_insert(this->variable_ht, reg, ir);
69 return;
70 } else if (ir->mode == ir_var_shader_out) {
71 reg = new(this->mem_ctx) fs_reg(this, ir->type);
72
73 if (ir->index > 0) {
74 assert(ir->location == FRAG_RESULT_DATA0);
75 assert(ir->index == 1);
76 this->dual_src_output = *reg;
77 } else if (ir->location == FRAG_RESULT_COLOR) {
78 /* Writing gl_FragColor outputs to all color regions. */
79 for (unsigned int i = 0; i < MAX2(c->key.nr_color_regions, 1); i++) {
80 this->outputs[i] = *reg;
81 this->output_components[i] = 4;
82 }
83 } else if (ir->location == FRAG_RESULT_DEPTH) {
84 this->frag_depth = *reg;
85 } else {
86 /* gl_FragData or a user-defined FS output */
87 assert(ir->location >= FRAG_RESULT_DATA0 &&
88 ir->location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
89
90 int vector_elements =
91 ir->type->is_array() ? ir->type->fields.array->vector_elements
92 : ir->type->vector_elements;
93
94 /* General color output. */
95 for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
96 int output = ir->location - FRAG_RESULT_DATA0 + i;
97 this->outputs[output] = *reg;
98 this->outputs[output].reg_offset += vector_elements * i;
99 this->output_components[output] = vector_elements;
100 }
101 }
102 } else if (ir->mode == ir_var_uniform) {
103 int param_index = c->prog_data.nr_params;
104
105 /* Thanks to the lower_ubo_reference pass, we will see only
106 * ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
107 * variables, so no need for them to be in variable_ht.
108 */
109 if (ir->is_in_uniform_block())
110 return;
111
112 if (dispatch_width == 16) {
113 if (!variable_storage(ir)) {
114 fail("Failed to find uniform '%s' in 16-wide\n", ir->name);
115 }
116 return;
117 }
118
119 param_size[param_index] = type_size(ir->type);
120 if (!strncmp(ir->name, "gl_", 3)) {
121 setup_builtin_uniform_values(ir);
122 } else {
123 setup_uniform_values(ir);
124 }
125
126 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
127 reg->type = brw_type_for_base_type(ir->type);
128 }
129
130 if (!reg)
131 reg = new(this->mem_ctx) fs_reg(this, ir->type);
132
133 hash_table_insert(this->variable_ht, reg, ir);
134 }
135
136 void
137 fs_visitor::visit(ir_dereference_variable *ir)
138 {
139 fs_reg *reg = variable_storage(ir->var);
140 this->result = *reg;
141 }
142
143 void
144 fs_visitor::visit(ir_dereference_record *ir)
145 {
146 const glsl_type *struct_type = ir->record->type;
147
148 ir->record->accept(this);
149
150 unsigned int offset = 0;
151 for (unsigned int i = 0; i < struct_type->length; i++) {
152 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
153 break;
154 offset += type_size(struct_type->fields.structure[i].type);
155 }
156 this->result.reg_offset += offset;
157 this->result.type = brw_type_for_base_type(ir->type);
158 }
159
160 void
161 fs_visitor::visit(ir_dereference_array *ir)
162 {
163 ir_constant *constant_index;
164 fs_reg src;
165 int element_size = type_size(ir->type);
166
167 constant_index = ir->array_index->as_constant();
168
169 ir->array->accept(this);
170 src = this->result;
171 src.type = brw_type_for_base_type(ir->type);
172
173 if (constant_index) {
174 assert(src.file == UNIFORM || src.file == GRF);
175 src.reg_offset += constant_index->value.i[0] * element_size;
176 } else {
177 /* Variable index array dereference. We attach the variable index
178 * component to the reg as a pointer to a register containing the
179 * offset. Currently only uniform arrays are supported in this patch,
180 * and that reladdr pointer is resolved by
181 * move_uniform_array_access_to_pull_constants(). All other array types
182 * are lowered by lower_variable_index_to_cond_assign().
183 */
184 ir->array_index->accept(this);
185
186 fs_reg index_reg;
187 index_reg = fs_reg(this, glsl_type::int_type);
188 emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
189
190 if (src.reladdr) {
191 emit(BRW_OPCODE_ADD, index_reg, *src.reladdr, index_reg);
192 }
193
194 src.reladdr = ralloc(mem_ctx, fs_reg);
195 memcpy(src.reladdr, &index_reg, sizeof(index_reg));
196 }
197 this->result = src;
198 }
199
200 void
201 fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
202 {
203 if (brw->gen < 6 ||
204 !x.is_valid_3src() ||
205 !y.is_valid_3src() ||
206 !a.is_valid_3src()) {
207 /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
208 fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
209 fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
210 fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
211
212 emit(MUL(y_times_a, y, a));
213
214 a.negate = !a.negate;
215 emit(ADD(one_minus_a, a, fs_reg(1.0f)));
216 emit(MUL(x_times_one_minus_a, x, one_minus_a));
217
218 emit(ADD(dst, x_times_one_minus_a, y_times_a));
219 } else {
220 /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
221 * we need to reorder the operands.
222 */
223 emit(LRP(dst, a, y, x));
224 }
225 }
226
227 void
228 fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
229 fs_reg src0, fs_reg src1)
230 {
231 fs_inst *inst;
232
233 if (brw->gen >= 6) {
234 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
235 inst->conditional_mod = conditionalmod;
236 } else {
237 emit(CMP(reg_null_d, src0, src1, conditionalmod));
238
239 inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
240 inst->predicate = BRW_PREDICATE_NORMAL;
241 }
242 }
243
244 /* Instruction selection: Produce a MOV.sat instead of
245 * MIN(MAX(val, 0), 1) when possible.
246 */
247 bool
248 fs_visitor::try_emit_saturate(ir_expression *ir)
249 {
250 ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
251
252 if (!sat_val)
253 return false;
254
255 fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
256
257 sat_val->accept(this);
258 fs_reg src = this->result;
259
260 fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
261
262 /* If the last instruction from our accept() didn't generate our
263 * src, generate a saturated MOV
264 */
265 fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
266 if (!modify || modify->regs_written != 1) {
267 this->result = fs_reg(this, ir->type);
268 fs_inst *inst = emit(MOV(this->result, src));
269 inst->saturate = true;
270 } else {
271 modify->saturate = true;
272 this->result = src;
273 }
274
275
276 return true;
277 }
278
279 bool
280 fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
281 {
282 /* 3-src instructions were introduced in gen6. */
283 if (brw->gen < 6)
284 return false;
285
286 /* MAD can only handle floating-point data. */
287 if (ir->type != glsl_type::float_type)
288 return false;
289
290 ir_rvalue *nonmul = ir->operands[1 - mul_arg];
291 ir_expression *mul = ir->operands[mul_arg]->as_expression();
292
293 if (!mul || mul->operation != ir_binop_mul)
294 return false;
295
296 if (nonmul->as_constant() ||
297 mul->operands[0]->as_constant() ||
298 mul->operands[1]->as_constant())
299 return false;
300
301 nonmul->accept(this);
302 fs_reg src0 = this->result;
303
304 mul->operands[0]->accept(this);
305 fs_reg src1 = this->result;
306
307 mul->operands[1]->accept(this);
308 fs_reg src2 = this->result;
309
310 this->result = fs_reg(this, ir->type);
311 emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
312
313 return true;
314 }
315
316 void
317 fs_visitor::visit(ir_expression *ir)
318 {
319 unsigned int operand;
320 fs_reg op[3], temp;
321 fs_inst *inst;
322
323 assert(ir->get_num_operands() <= 3);
324
325 if (try_emit_saturate(ir))
326 return;
327 if (ir->operation == ir_binop_add) {
328 if (try_emit_mad(ir, 0) || try_emit_mad(ir, 1))
329 return;
330 }
331
332 for (operand = 0; operand < ir->get_num_operands(); operand++) {
333 ir->operands[operand]->accept(this);
334 if (this->result.file == BAD_FILE) {
335 fail("Failed to get tree for expression operand:\n");
336 ir->operands[operand]->print();
337 printf("\n");
338 }
339 assert(this->result.is_valid_3src());
340 op[operand] = this->result;
341
342 /* Matrix expression operands should have been broken down to vector
343 * operations already.
344 */
345 assert(!ir->operands[operand]->type->is_matrix());
346 /* And then those vector operands should have been broken down to scalar.
347 */
348 assert(!ir->operands[operand]->type->is_vector());
349 }
350
351 /* Storage for our result. If our result goes into an assignment, it will
352 * just get copy-propagated out, so no worries.
353 */
354 this->result = fs_reg(this, ir->type);
355
356 switch (ir->operation) {
357 case ir_unop_logic_not:
358 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
359 * ones complement of the whole register, not just bit 0.
360 */
361 emit(XOR(this->result, op[0], fs_reg(1)));
362 break;
363 case ir_unop_neg:
364 op[0].negate = !op[0].negate;
365 emit(MOV(this->result, op[0]));
366 break;
367 case ir_unop_abs:
368 op[0].abs = true;
369 op[0].negate = false;
370 emit(MOV(this->result, op[0]));
371 break;
372 case ir_unop_sign:
373 temp = fs_reg(this, ir->type);
374
375 emit(MOV(this->result, fs_reg(0.0f)));
376
377 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_G));
378 inst = emit(MOV(this->result, fs_reg(1.0f)));
379 inst->predicate = BRW_PREDICATE_NORMAL;
380
381 emit(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_L));
382 inst = emit(MOV(this->result, fs_reg(-1.0f)));
383 inst->predicate = BRW_PREDICATE_NORMAL;
384
385 break;
386 case ir_unop_rcp:
387 emit_math(SHADER_OPCODE_RCP, this->result, op[0]);
388 break;
389
390 case ir_unop_exp2:
391 emit_math(SHADER_OPCODE_EXP2, this->result, op[0]);
392 break;
393 case ir_unop_log2:
394 emit_math(SHADER_OPCODE_LOG2, this->result, op[0]);
395 break;
396 case ir_unop_exp:
397 case ir_unop_log:
398 assert(!"not reached: should be handled by ir_explog_to_explog2");
399 break;
400 case ir_unop_sin:
401 case ir_unop_sin_reduced:
402 emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
403 break;
404 case ir_unop_cos:
405 case ir_unop_cos_reduced:
406 emit_math(SHADER_OPCODE_COS, this->result, op[0]);
407 break;
408
409 case ir_unop_dFdx:
410 emit(FS_OPCODE_DDX, this->result, op[0]);
411 break;
412 case ir_unop_dFdy:
413 emit(FS_OPCODE_DDY, this->result, op[0]);
414 break;
415
416 case ir_binop_add:
417 emit(ADD(this->result, op[0], op[1]));
418 break;
419 case ir_binop_sub:
420 assert(!"not reached: should be handled by ir_sub_to_add_neg");
421 break;
422
423 case ir_binop_mul:
424 if (ir->type->is_integer()) {
425 /* For integer multiplication, the MUL uses the low 16 bits
426 * of one of the operands (src0 on gen6, src1 on gen7). The
427 * MACH accumulates in the contribution of the upper 16 bits
428 * of that operand.
429 *
430 * FINISHME: Emit just the MUL if we know an operand is small
431 * enough.
432 */
433 if (brw->gen >= 7 && dispatch_width == 16)
434 fail("16-wide explicit accumulator operands unsupported\n");
435
436 struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
437
438 emit(MUL(acc, op[0], op[1]));
439 emit(MACH(reg_null_d, op[0], op[1]));
440 emit(MOV(this->result, fs_reg(acc)));
441 } else {
442 emit(MUL(this->result, op[0], op[1]));
443 }
444 break;
445 case ir_binop_div:
446 /* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
447 assert(ir->type->is_integer());
448 emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
449 break;
450 case ir_binop_mod:
451 /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
452 assert(ir->type->is_integer());
453 emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
454 break;
455
456 case ir_binop_less:
457 case ir_binop_greater:
458 case ir_binop_lequal:
459 case ir_binop_gequal:
460 case ir_binop_equal:
461 case ir_binop_all_equal:
462 case ir_binop_nequal:
463 case ir_binop_any_nequal:
464 resolve_bool_comparison(ir->operands[0], &op[0]);
465 resolve_bool_comparison(ir->operands[1], &op[1]);
466
467 emit(CMP(this->result, op[0], op[1],
468 brw_conditional_for_comparison(ir->operation)));
469 break;
470
471 case ir_binop_logic_xor:
472 emit(XOR(this->result, op[0], op[1]));
473 break;
474
475 case ir_binop_logic_or:
476 emit(OR(this->result, op[0], op[1]));
477 break;
478
479 case ir_binop_logic_and:
480 emit(AND(this->result, op[0], op[1]));
481 break;
482
483 case ir_binop_dot:
484 case ir_unop_any:
485 assert(!"not reached: should be handled by brw_fs_channel_expressions");
486 break;
487
488 case ir_unop_noise:
489 assert(!"not reached: should be handled by lower_noise");
490 break;
491
492 case ir_quadop_vector:
493 assert(!"not reached: should be handled by lower_quadop_vector");
494 break;
495
496 case ir_binop_vector_extract:
497 assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
498 break;
499
500 case ir_triop_vector_insert:
501 assert(!"not reached: should be handled by lower_vector_insert()");
502 break;
503
504 case ir_unop_sqrt:
505 emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
506 break;
507
508 case ir_unop_rsq:
509 emit_math(SHADER_OPCODE_RSQ, this->result, op[0]);
510 break;
511
512 case ir_unop_bitcast_i2f:
513 case ir_unop_bitcast_u2f:
514 op[0].type = BRW_REGISTER_TYPE_F;
515 this->result = op[0];
516 break;
517 case ir_unop_i2u:
518 case ir_unop_bitcast_f2u:
519 op[0].type = BRW_REGISTER_TYPE_UD;
520 this->result = op[0];
521 break;
522 case ir_unop_u2i:
523 case ir_unop_bitcast_f2i:
524 op[0].type = BRW_REGISTER_TYPE_D;
525 this->result = op[0];
526 break;
527 case ir_unop_i2f:
528 case ir_unop_u2f:
529 case ir_unop_f2i:
530 case ir_unop_f2u:
531 emit(MOV(this->result, op[0]));
532 break;
533
534 case ir_unop_b2i:
535 emit(AND(this->result, op[0], fs_reg(1)));
536 break;
537 case ir_unop_b2f:
538 temp = fs_reg(this, glsl_type::int_type);
539 emit(AND(temp, op[0], fs_reg(1)));
540 emit(MOV(this->result, temp));
541 break;
542
543 case ir_unop_f2b:
544 emit(CMP(this->result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
545 break;
546 case ir_unop_i2b:
547 emit(CMP(this->result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
548 break;
549
550 case ir_unop_trunc:
551 emit(RNDZ(this->result, op[0]));
552 break;
553 case ir_unop_ceil:
554 op[0].negate = !op[0].negate;
555 emit(RNDD(this->result, op[0]));
556 this->result.negate = true;
557 break;
558 case ir_unop_floor:
559 emit(RNDD(this->result, op[0]));
560 break;
561 case ir_unop_fract:
562 emit(FRC(this->result, op[0]));
563 break;
564 case ir_unop_round_even:
565 emit(RNDE(this->result, op[0]));
566 break;
567
568 case ir_binop_min:
569 case ir_binop_max:
570 resolve_ud_negate(&op[0]);
571 resolve_ud_negate(&op[1]);
572 emit_minmax(ir->operation == ir_binop_min ?
573 BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
574 this->result, op[0], op[1]);
575 break;
576 case ir_unop_pack_snorm_2x16:
577 case ir_unop_pack_snorm_4x8:
578 case ir_unop_pack_unorm_2x16:
579 case ir_unop_pack_unorm_4x8:
580 case ir_unop_unpack_snorm_2x16:
581 case ir_unop_unpack_snorm_4x8:
582 case ir_unop_unpack_unorm_2x16:
583 case ir_unop_unpack_unorm_4x8:
584 case ir_unop_unpack_half_2x16:
585 case ir_unop_pack_half_2x16:
586 assert(!"not reached: should be handled by lower_packing_builtins");
587 break;
588 case ir_unop_unpack_half_2x16_split_x:
589 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
590 break;
591 case ir_unop_unpack_half_2x16_split_y:
592 emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
593 break;
594 case ir_binop_pow:
595 emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
596 break;
597
598 case ir_unop_bitfield_reverse:
599 emit(BFREV(this->result, op[0]));
600 break;
601 case ir_unop_bit_count:
602 emit(CBIT(this->result, op[0]));
603 break;
604 case ir_unop_find_msb:
605 temp = fs_reg(this, glsl_type::uint_type);
606 emit(FBH(temp, op[0]));
607
608 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
609 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
610 * subtract the result from 31 to convert the MSB count into an LSB count.
611 */
612
613 /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
614 emit(MOV(this->result, temp));
615 emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
616
617 temp.negate = true;
618 inst = emit(ADD(this->result, temp, fs_reg(31)));
619 inst->predicate = BRW_PREDICATE_NORMAL;
620 break;
621 case ir_unop_find_lsb:
622 emit(FBL(this->result, op[0]));
623 break;
624 case ir_triop_bitfield_extract:
625 /* Note that the instruction's argument order is reversed from GLSL
626 * and the IR.
627 */
628 emit(BFE(this->result, op[2], op[1], op[0]));
629 break;
630 case ir_binop_bfm:
631 emit(BFI1(this->result, op[0], op[1]));
632 break;
633 case ir_triop_bfi:
634 emit(BFI2(this->result, op[0], op[1], op[2]));
635 break;
636 case ir_quadop_bitfield_insert:
637 assert(!"not reached: should be handled by "
638 "lower_instructions::bitfield_insert_to_bfm_bfi");
639 break;
640
641 case ir_unop_bit_not:
642 emit(NOT(this->result, op[0]));
643 break;
644 case ir_binop_bit_and:
645 emit(AND(this->result, op[0], op[1]));
646 break;
647 case ir_binop_bit_xor:
648 emit(XOR(this->result, op[0], op[1]));
649 break;
650 case ir_binop_bit_or:
651 emit(OR(this->result, op[0], op[1]));
652 break;
653
654 case ir_binop_lshift:
655 emit(SHL(this->result, op[0], op[1]));
656 break;
657
658 case ir_binop_rshift:
659 if (ir->type->base_type == GLSL_TYPE_INT)
660 emit(ASR(this->result, op[0], op[1]));
661 else
662 emit(SHR(this->result, op[0], op[1]));
663 break;
664 case ir_binop_pack_half_2x16_split:
665 emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
666 break;
667 case ir_binop_ubo_load: {
668 /* This IR node takes a constant uniform block and a constant or
669 * variable byte offset within the block and loads a vector from that.
670 */
671 ir_constant *uniform_block = ir->operands[0]->as_constant();
672 ir_constant *const_offset = ir->operands[1]->as_constant();
673 fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
674 if (const_offset) {
675 fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
676 packed_consts.type = result.type;
677
678 fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
679 emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
680 packed_consts, surf_index, const_offset_reg));
681
682 packed_consts.smear = const_offset->value.u[0] % 16 / 4;
683 for (int i = 0; i < ir->type->vector_elements; i++) {
684 /* UBO bools are any nonzero value. We consider bools to be
685 * values with the low bit set to 1. Convert them using CMP.
686 */
687 if (ir->type->base_type == GLSL_TYPE_BOOL) {
688 emit(CMP(result, packed_consts, fs_reg(0u), BRW_CONDITIONAL_NZ));
689 } else {
690 emit(MOV(result, packed_consts));
691 }
692
693 packed_consts.smear++;
694 result.reg_offset++;
695
696 /* The std140 packing rules don't allow vectors to cross 16-byte
697 * boundaries, and a reg is 32 bytes.
698 */
699 assert(packed_consts.smear < 8);
700 }
701 } else {
702 /* Turn the byte offset into a dword offset. */
703 fs_reg base_offset = fs_reg(this, glsl_type::int_type);
704 emit(SHR(base_offset, op[1], fs_reg(2)));
705
706 for (int i = 0; i < ir->type->vector_elements; i++) {
707 emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
708 base_offset, i));
709
710 if (ir->type->base_type == GLSL_TYPE_BOOL)
711 emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
712
713 result.reg_offset++;
714 }
715 }
716
717 result.reg_offset = 0;
718 break;
719 }
720
721 case ir_triop_fma:
722 /* Note that the instruction's argument order is reversed from GLSL
723 * and the IR.
724 */
725 emit(MAD(this->result, op[2], op[1], op[0]));
726 break;
727
728 case ir_triop_lrp:
729 emit_lrp(this->result, op[0], op[1], op[2]);
730 break;
731 }
732 }
733
734 void
735 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
736 const glsl_type *type, bool predicated)
737 {
738 switch (type->base_type) {
739 case GLSL_TYPE_FLOAT:
740 case GLSL_TYPE_UINT:
741 case GLSL_TYPE_INT:
742 case GLSL_TYPE_BOOL:
743 for (unsigned int i = 0; i < type->components(); i++) {
744 l.type = brw_type_for_base_type(type);
745 r.type = brw_type_for_base_type(type);
746
747 if (predicated || !l.equals(r)) {
748 fs_inst *inst = emit(MOV(l, r));
749 inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
750 }
751
752 l.reg_offset++;
753 r.reg_offset++;
754 }
755 break;
756 case GLSL_TYPE_ARRAY:
757 for (unsigned int i = 0; i < type->length; i++) {
758 emit_assignment_writes(l, r, type->fields.array, predicated);
759 }
760 break;
761
762 case GLSL_TYPE_STRUCT:
763 for (unsigned int i = 0; i < type->length; i++) {
764 emit_assignment_writes(l, r, type->fields.structure[i].type,
765 predicated);
766 }
767 break;
768
769 case GLSL_TYPE_SAMPLER:
770 break;
771
772 case GLSL_TYPE_VOID:
773 case GLSL_TYPE_ERROR:
774 case GLSL_TYPE_INTERFACE:
775 assert(!"not reached");
776 break;
777 }
778 }
779
780 /* If the RHS processing resulted in an instruction generating a
781 * temporary value, and it would be easy to rewrite the instruction to
782 * generate its result right into the LHS instead, do so. This ends
783 * up reliably removing instructions where it can be tricky to do so
784 * later without real UD chain information.
785 */
786 bool
787 fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
788 fs_reg dst,
789 fs_reg src,
790 fs_inst *pre_rhs_inst,
791 fs_inst *last_rhs_inst)
792 {
793 /* Only attempt if we're doing a direct assignment. */
794 if (ir->condition ||
795 !(ir->lhs->type->is_scalar() ||
796 (ir->lhs->type->is_vector() &&
797 ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
798 return false;
799
800 /* Make sure the last instruction generated our source reg. */
801 fs_inst *modify = get_instruction_generating_reg(pre_rhs_inst,
802 last_rhs_inst,
803 src);
804 if (!modify)
805 return false;
806
807 /* If last_rhs_inst wrote a different number of components than our LHS,
808 * we can't safely rewrite it.
809 */
810 if (virtual_grf_sizes[dst.reg] != modify->regs_written)
811 return false;
812
813 /* Success! Rewrite the instruction. */
814 modify->dst = dst;
815
816 return true;
817 }
818
819 void
820 fs_visitor::visit(ir_assignment *ir)
821 {
822 fs_reg l, r;
823 fs_inst *inst;
824
825 /* FINISHME: arrays on the lhs */
826 ir->lhs->accept(this);
827 l = this->result;
828
829 fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
830
831 ir->rhs->accept(this);
832 r = this->result;
833
834 fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
835
836 assert(l.file != BAD_FILE);
837 assert(r.file != BAD_FILE);
838
839 if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
840 return;
841
842 if (ir->condition) {
843 emit_bool_to_cond_code(ir->condition);
844 }
845
846 if (ir->lhs->type->is_scalar() ||
847 ir->lhs->type->is_vector()) {
848 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
849 if (ir->write_mask & (1 << i)) {
850 inst = emit(MOV(l, r));
851 if (ir->condition)
852 inst->predicate = BRW_PREDICATE_NORMAL;
853 r.reg_offset++;
854 }
855 l.reg_offset++;
856 }
857 } else {
858 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
859 }
860 }
861
862 fs_inst *
863 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
864 fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
865 {
866 int mlen;
867 int base_mrf = 1;
868 bool simd16 = false;
869 fs_reg orig_dst;
870
871 /* g0 header. */
872 mlen = 1;
873
874 if (ir->shadow_comparitor) {
875 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
876 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
877 coordinate.reg_offset++;
878 }
879
880 /* gen4's SIMD8 sampler always has the slots for u,v,r present.
881 * the unused slots must be zeroed.
882 */
883 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
884 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
885 }
886 mlen += 3;
887
888 if (ir->op == ir_tex) {
889 /* There's no plain shadow compare message, so we use shadow
890 * compare with a bias of 0.0.
891 */
892 emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
893 mlen++;
894 } else if (ir->op == ir_txb || ir->op == ir_txl) {
895 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
896 mlen++;
897 } else {
898 assert(!"Should not get here.");
899 }
900
901 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
902 mlen++;
903 } else if (ir->op == ir_tex) {
904 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
905 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
906 coordinate.reg_offset++;
907 }
908 /* zero the others. */
909 for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
910 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
911 }
912 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
913 mlen += 3;
914 } else if (ir->op == ir_txd) {
915 fs_reg &dPdx = lod;
916
917 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
918 emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
919 coordinate.reg_offset++;
920 }
921 /* the slots for u and v are always present, but r is optional */
922 mlen += MAX2(ir->coordinate->type->vector_elements, 2);
923
924 /* P = u, v, r
925 * dPdx = dudx, dvdx, drdx
926 * dPdy = dudy, dvdy, drdy
927 *
928 * 1-arg: Does not exist.
929 *
930 * 2-arg: dudx dvdx dudy dvdy
931 * dPdx.x dPdx.y dPdy.x dPdy.y
932 * m4 m5 m6 m7
933 *
934 * 3-arg: dudx dvdx drdx dudy dvdy drdy
935 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
936 * m5 m6 m7 m8 m9 m10
937 */
938 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
939 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
940 dPdx.reg_offset++;
941 }
942 mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
943
944 for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
945 emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
946 dPdy.reg_offset++;
947 }
948 mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
949 } else if (ir->op == ir_txs) {
950 /* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
951 simd16 = true;
952 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
953 mlen += 2;
954 } else {
955 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
956 * instructions. We'll need to do SIMD16 here.
957 */
958 simd16 = true;
959 assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
960
961 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
962 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
963 coordinate));
964 coordinate.reg_offset++;
965 }
966
967 /* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
968 * be necessary for TXF (ld), but seems wise to do for all messages.
969 */
970 for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
971 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
972 }
973
974 /* lod/bias appears after u/v/r. */
975 mlen += 6;
976
977 emit(MOV(fs_reg(MRF, base_mrf + mlen, lod.type), lod));
978 mlen++;
979
980 /* The unused upper half. */
981 mlen++;
982 }
983
984 if (simd16) {
985 /* Now, since we're doing simd16, the return is 2 interleaved
986 * vec4s where the odd-indexed ones are junk. We'll need to move
987 * this weirdness around to the expected layout.
988 */
989 orig_dst = dst;
990 dst = fs_reg(GRF, virtual_grf_alloc(8),
991 (brw->is_g4x ?
992 brw_type_for_base_type(ir->type) :
993 BRW_REGISTER_TYPE_F));
994 }
995
996 fs_inst *inst = NULL;
997 switch (ir->op) {
998 case ir_tex:
999 inst = emit(SHADER_OPCODE_TEX, dst);
1000 break;
1001 case ir_txb:
1002 inst = emit(FS_OPCODE_TXB, dst);
1003 break;
1004 case ir_txl:
1005 inst = emit(SHADER_OPCODE_TXL, dst);
1006 break;
1007 case ir_txd:
1008 inst = emit(SHADER_OPCODE_TXD, dst);
1009 break;
1010 case ir_txs:
1011 inst = emit(SHADER_OPCODE_TXS, dst);
1012 break;
1013 case ir_txf:
1014 inst = emit(SHADER_OPCODE_TXF, dst);
1015 break;
1016 default:
1017 fail("unrecognized texture opcode");
1018 }
1019 inst->base_mrf = base_mrf;
1020 inst->mlen = mlen;
1021 inst->header_present = true;
1022 inst->regs_written = simd16 ? 8 : 4;
1023
1024 if (simd16) {
1025 for (int i = 0; i < 4; i++) {
1026 emit(MOV(orig_dst, dst));
1027 orig_dst.reg_offset++;
1028 dst.reg_offset += 2;
1029 }
1030 }
1031
1032 return inst;
1033 }
1034
1035 /* gen5's sampler has slots for u, v, r, array index, then optional
1036 * parameters like shadow comparitor or LOD bias. If optional
1037 * parameters aren't present, those base slots are optional and don't
1038 * need to be included in the message.
1039 *
1040 * We don't fill in the unnecessary slots regardless, which may look
1041 * surprising in the disassembly.
1042 */
1043 fs_inst *
1044 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1045 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1046 fs_reg sample_index)
1047 {
1048 int mlen = 0;
1049 int base_mrf = 2;
1050 int reg_width = dispatch_width / 8;
1051 bool header_present = false;
1052 const int vector_elements =
1053 ir->coordinate ? ir->coordinate->type->vector_elements : 0;
1054
1055 if (ir->offset != NULL && ir->op == ir_txf) {
1056 /* It appears that the ld instruction used for txf does its
1057 * address bounds check before adding in the offset. To work
1058 * around this, just add the integer offset to the integer texel
1059 * coordinate, and don't put the offset in the header.
1060 */
1061 ir_constant *offset = ir->offset->as_constant();
1062 for (int i = 0; i < vector_elements; i++) {
1063 emit(ADD(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1064 coordinate,
1065 offset->value.i[i]));
1066 coordinate.reg_offset++;
1067 }
1068 } else {
1069 if (ir->offset) {
1070 /* The offsets set up by the ir_texture visitor are in the
1071 * m1 header, so we can't go headerless.
1072 */
1073 header_present = true;
1074 mlen++;
1075 base_mrf--;
1076 }
1077
1078 for (int i = 0; i < vector_elements; i++) {
1079 emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
1080 coordinate));
1081 coordinate.reg_offset++;
1082 }
1083 }
1084 mlen += vector_elements * reg_width;
1085
1086 if (ir->shadow_comparitor) {
1087 mlen = MAX2(mlen, header_present + 4 * reg_width);
1088
1089 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1090 mlen += reg_width;
1091 }
1092
1093 fs_inst *inst = NULL;
1094 switch (ir->op) {
1095 case ir_tex:
1096 inst = emit(SHADER_OPCODE_TEX, dst);
1097 break;
1098 case ir_txb:
1099 mlen = MAX2(mlen, header_present + 4 * reg_width);
1100 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1101 mlen += reg_width;
1102
1103 inst = emit(FS_OPCODE_TXB, dst);
1104 break;
1105 case ir_txl:
1106 mlen = MAX2(mlen, header_present + 4 * reg_width);
1107 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1108 mlen += reg_width;
1109
1110 inst = emit(SHADER_OPCODE_TXL, dst);
1111 break;
1112 case ir_txd: {
1113 mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
1114
1115 /**
1116 * P = u, v, r
1117 * dPdx = dudx, dvdx, drdx
1118 * dPdy = dudy, dvdy, drdy
1119 *
1120 * Load up these values:
1121 * - dudx dudy dvdx dvdy drdx drdy
1122 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
1123 */
1124 for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
1125 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1126 lod.reg_offset++;
1127 mlen += reg_width;
1128
1129 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1130 lod2.reg_offset++;
1131 mlen += reg_width;
1132 }
1133
1134 inst = emit(SHADER_OPCODE_TXD, dst);
1135 break;
1136 }
1137 case ir_txs:
1138 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1139 mlen += reg_width;
1140 inst = emit(SHADER_OPCODE_TXS, dst);
1141 break;
1142 case ir_txf:
1143 mlen = header_present + 4 * reg_width;
1144 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
1145 inst = emit(SHADER_OPCODE_TXF, dst);
1146 break;
1147 case ir_txf_ms:
1148 mlen = header_present + 4 * reg_width;
1149
1150 /* lod */
1151 emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
1152 /* sample index */
1153 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1154 mlen += reg_width;
1155 inst = emit(SHADER_OPCODE_TXF_MS, dst);
1156 break;
1157 case ir_lod:
1158 inst = emit(SHADER_OPCODE_LOD, dst);
1159 break;
1160 }
1161 inst->base_mrf = base_mrf;
1162 inst->mlen = mlen;
1163 inst->header_present = header_present;
1164 inst->regs_written = 4;
1165
1166 if (mlen > 11) {
1167 fail("Message length >11 disallowed by hardware\n");
1168 }
1169
1170 return inst;
1171 }
1172
1173 fs_inst *
1174 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
1175 fs_reg shadow_c, fs_reg lod, fs_reg lod2,
1176 fs_reg sample_index)
1177 {
1178 int mlen = 0;
1179 int base_mrf = 2;
1180 int reg_width = dispatch_width / 8;
1181 bool header_present = false;
1182 int offsets[3];
1183
1184 if (ir->offset && ir->op != ir_txf) {
1185 /* The offsets set up by the ir_texture visitor are in the
1186 * m1 header, so we can't go headerless.
1187 */
1188 header_present = true;
1189 mlen++;
1190 base_mrf--;
1191 }
1192
1193 if (ir->shadow_comparitor) {
1194 emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
1195 mlen += reg_width;
1196 }
1197
1198 /* Set up the LOD info */
1199 switch (ir->op) {
1200 case ir_tex:
1201 case ir_lod:
1202 break;
1203 case ir_txb:
1204 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1205 mlen += reg_width;
1206 break;
1207 case ir_txl:
1208 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1209 mlen += reg_width;
1210 break;
1211 case ir_txd: {
1212 if (dispatch_width == 16)
1213 fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
1214
1215 /* Load dPdx and the coordinate together:
1216 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
1217 */
1218 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1219 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1220 coordinate.reg_offset++;
1221 mlen += reg_width;
1222
1223 /* For cube map array, the coordinate is (u,v,r,ai) but there are
1224 * only derivatives for (u, v, r).
1225 */
1226 if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
1227 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
1228 lod.reg_offset++;
1229 mlen += reg_width;
1230
1231 emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
1232 lod2.reg_offset++;
1233 mlen += reg_width;
1234 }
1235 }
1236 break;
1237 }
1238 case ir_txs:
1239 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
1240 mlen += reg_width;
1241 break;
1242 case ir_txf:
1243 /* It appears that the ld instruction used for txf does its
1244 * address bounds check before adding in the offset. To work
1245 * around this, just add the integer offset to the integer texel
1246 * coordinate, and don't put the offset in the header.
1247 */
1248 if (ir->offset) {
1249 ir_constant *offset = ir->offset->as_constant();
1250 offsets[0] = offset->value.i[0];
1251 offsets[1] = offset->value.i[1];
1252 offsets[2] = offset->value.i[2];
1253 } else {
1254 memset(offsets, 0, sizeof(offsets));
1255 }
1256
1257 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
1258 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1259 coordinate, offsets[0]));
1260 coordinate.reg_offset++;
1261 mlen += reg_width;
1262
1263 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
1264 mlen += reg_width;
1265
1266 for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
1267 emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1268 coordinate, offsets[i]));
1269 coordinate.reg_offset++;
1270 mlen += reg_width;
1271 }
1272 break;
1273 case ir_txf_ms:
1274 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
1275 mlen += reg_width;
1276
1277 /* constant zero MCS; we arrange to never actually have a compressed
1278 * multisample surface here for now. TODO: issue ld_mcs to get this first,
1279 * if we ever support texturing from compressed multisample surfaces
1280 */
1281 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
1282 mlen += reg_width;
1283
1284 /* there is no offsetting for this message; just copy in the integer
1285 * texture coordinates
1286 */
1287 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1288 emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
1289 coordinate));
1290 coordinate.reg_offset++;
1291 mlen += reg_width;
1292 }
1293 break;
1294 }
1295
1296 /* Set up the coordinate (except for cases where it was done above) */
1297 if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) {
1298 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1299 emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
1300 coordinate.reg_offset++;
1301 mlen += reg_width;
1302 }
1303 }
1304
1305 /* Generate the SEND */
1306 fs_inst *inst = NULL;
1307 switch (ir->op) {
1308 case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
1309 case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
1310 case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
1311 case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
1312 case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
1313 case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
1314 case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
1315 case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
1316 }
1317 inst->base_mrf = base_mrf;
1318 inst->mlen = mlen;
1319 inst->header_present = header_present;
1320 inst->regs_written = 4;
1321
1322 if (mlen > 11) {
1323 fail("Message length >11 disallowed by hardware\n");
1324 }
1325
1326 return inst;
1327 }
1328
1329 fs_reg
1330 fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
1331 bool is_rect, int sampler, int texunit)
1332 {
1333 fs_inst *inst = NULL;
1334 bool needs_gl_clamp = true;
1335 fs_reg scale_x, scale_y;
1336
1337 /* The 965 requires the EU to do the normalization of GL rectangle
1338 * texture coordinates. We use the program parameter state
1339 * tracking to get the scaling factor.
1340 */
1341 if (is_rect &&
1342 (brw->gen < 6 ||
1343 (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
1344 c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
1345 struct gl_program_parameter_list *params = fp->Base.Parameters;
1346 int tokens[STATE_LENGTH] = {
1347 STATE_INTERNAL,
1348 STATE_TEXRECT_SCALE,
1349 texunit,
1350 0,
1351 0
1352 };
1353
1354 if (dispatch_width == 16) {
1355 fail("rectangle scale uniform setup not supported on 16-wide\n");
1356 return coordinate;
1357 }
1358
1359 scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1360 scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1361
1362 GLuint index = _mesa_add_state_reference(params,
1363 (gl_state_index *)tokens);
1364 c->prog_data.param[c->prog_data.nr_params++] =
1365 &fp->Base.Parameters->ParameterValues[index][0].f;
1366 c->prog_data.param[c->prog_data.nr_params++] =
1367 &fp->Base.Parameters->ParameterValues[index][1].f;
1368 }
1369
1370 /* The 965 requires the EU to do the normalization of GL rectangle
1371 * texture coordinates. We use the program parameter state
1372 * tracking to get the scaling factor.
1373 */
1374 if (brw->gen < 6 && is_rect) {
1375 fs_reg dst = fs_reg(this, ir->coordinate->type);
1376 fs_reg src = coordinate;
1377 coordinate = dst;
1378
1379 emit(MUL(dst, src, scale_x));
1380 dst.reg_offset++;
1381 src.reg_offset++;
1382 emit(MUL(dst, src, scale_y));
1383 } else if (is_rect) {
1384 /* On gen6+, the sampler handles the rectangle coordinates
1385 * natively, without needing rescaling. But that means we have
1386 * to do GL_CLAMP clamping at the [0, width], [0, height] scale,
1387 * not [0, 1] like the default case below.
1388 */
1389 needs_gl_clamp = false;
1390
1391 for (int i = 0; i < 2; i++) {
1392 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1393 fs_reg chan = coordinate;
1394 chan.reg_offset += i;
1395
1396 inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
1397 inst->conditional_mod = BRW_CONDITIONAL_G;
1398
1399 /* Our parameter comes in as 1.0/width or 1.0/height,
1400 * because that's what people normally want for doing
1401 * texture rectangle handling. We need width or height
1402 * for clamping, but we don't care enough to make a new
1403 * parameter type, so just invert back.
1404 */
1405 fs_reg limit = fs_reg(this, glsl_type::float_type);
1406 emit(MOV(limit, i == 0 ? scale_x : scale_y));
1407 emit(SHADER_OPCODE_RCP, limit, limit);
1408
1409 inst = emit(BRW_OPCODE_SEL, chan, chan, limit);
1410 inst->conditional_mod = BRW_CONDITIONAL_L;
1411 }
1412 }
1413 }
1414
1415 if (ir->coordinate && needs_gl_clamp) {
1416 for (unsigned int i = 0;
1417 i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
1418 if (c->key.tex.gl_clamp_mask[i] & (1 << sampler)) {
1419 fs_reg chan = coordinate;
1420 chan.reg_offset += i;
1421
1422 fs_inst *inst = emit(MOV(chan, chan));
1423 inst->saturate = true;
1424 }
1425 }
1426 }
1427 return coordinate;
1428 }
1429
1430 void
1431 fs_visitor::visit(ir_texture *ir)
1432 {
1433 fs_inst *inst = NULL;
1434
1435 int sampler =
1436 _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
1437 /* FINISHME: We're failing to recompile our programs when the sampler is
1438 * updated. This only matters for the texture rectangle scale parameters
1439 * (pre-gen6, or gen6+ with GL_CLAMP).
1440 */
1441 int texunit = fp->Base.SamplerUnits[sampler];
1442
1443 /* Should be lowered by do_lower_texture_projection */
1444 assert(!ir->projector);
1445
1446 /* Generate code to compute all the subexpression trees. This has to be
1447 * done before loading any values into MRFs for the sampler message since
1448 * generating these values may involve SEND messages that need the MRFs.
1449 */
1450 fs_reg coordinate;
1451 if (ir->coordinate) {
1452 ir->coordinate->accept(this);
1453
1454 coordinate = rescale_texcoord(ir, this->result,
1455 ir->sampler->type->sampler_dimensionality ==
1456 GLSL_SAMPLER_DIM_RECT,
1457 sampler, texunit);
1458 }
1459
1460 fs_reg shadow_comparitor;
1461 if (ir->shadow_comparitor) {
1462 ir->shadow_comparitor->accept(this);
1463 shadow_comparitor = this->result;
1464 }
1465
1466 fs_reg lod, lod2, sample_index;
1467 switch (ir->op) {
1468 case ir_tex:
1469 case ir_lod:
1470 break;
1471 case ir_txb:
1472 ir->lod_info.bias->accept(this);
1473 lod = this->result;
1474 break;
1475 case ir_txd:
1476 ir->lod_info.grad.dPdx->accept(this);
1477 lod = this->result;
1478
1479 ir->lod_info.grad.dPdy->accept(this);
1480 lod2 = this->result;
1481 break;
1482 case ir_txf:
1483 case ir_txl:
1484 case ir_txs:
1485 ir->lod_info.lod->accept(this);
1486 lod = this->result;
1487 break;
1488 case ir_txf_ms:
1489 ir->lod_info.sample_index->accept(this);
1490 sample_index = this->result;
1491 break;
1492 };
1493
1494 /* Writemasking doesn't eliminate channels on SIMD8 texture
1495 * samples, so don't worry about them.
1496 */
1497 fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
1498
1499 if (brw->gen >= 7) {
1500 inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
1501 lod, lod2, sample_index);
1502 } else if (brw->gen >= 5) {
1503 inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
1504 lod, lod2, sample_index);
1505 } else {
1506 inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
1507 lod, lod2);
1508 }
1509
1510 /* The header is set up by generate_tex() when necessary. */
1511 inst->src[0] = reg_undef;
1512
1513 if (ir->offset != NULL && ir->op != ir_txf)
1514 inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
1515
1516 inst->sampler = sampler;
1517
1518 if (ir->shadow_comparitor)
1519 inst->shadow_compare = true;
1520
1521 /* fixup #layers for cube map arrays */
1522 if (ir->op == ir_txs) {
1523 glsl_type const *type = ir->sampler->type;
1524 if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
1525 type->sampler_array) {
1526 fs_reg depth = dst;
1527 depth.reg_offset = 2;
1528 emit_math(SHADER_OPCODE_INT_QUOTIENT, depth, depth, fs_reg(6));
1529 }
1530 }
1531
1532 swizzle_result(ir, dst, sampler);
1533 }
1534
1535 /**
1536 * Swizzle the result of a texture result. This is necessary for
1537 * EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
1538 */
1539 void
1540 fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
1541 {
1542 this->result = orig_val;
1543
1544 if (ir->op == ir_txs || ir->op == ir_lod)
1545 return;
1546
1547 if (ir->type == glsl_type::float_type) {
1548 /* Ignore DEPTH_TEXTURE_MODE swizzling. */
1549 assert(ir->sampler->type->sampler_shadow);
1550 } else if (c->key.tex.swizzles[sampler] != SWIZZLE_NOOP) {
1551 fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
1552
1553 for (int i = 0; i < 4; i++) {
1554 int swiz = GET_SWZ(c->key.tex.swizzles[sampler], i);
1555 fs_reg l = swizzled_result;
1556 l.reg_offset += i;
1557
1558 if (swiz == SWIZZLE_ZERO) {
1559 emit(MOV(l, fs_reg(0.0f)));
1560 } else if (swiz == SWIZZLE_ONE) {
1561 emit(MOV(l, fs_reg(1.0f)));
1562 } else {
1563 fs_reg r = orig_val;
1564 r.reg_offset += GET_SWZ(c->key.tex.swizzles[sampler], i);
1565 emit(MOV(l, r));
1566 }
1567 }
1568 this->result = swizzled_result;
1569 }
1570 }
1571
1572 void
1573 fs_visitor::visit(ir_swizzle *ir)
1574 {
1575 ir->val->accept(this);
1576 fs_reg val = this->result;
1577
1578 if (ir->type->vector_elements == 1) {
1579 this->result.reg_offset += ir->mask.x;
1580 return;
1581 }
1582
1583 fs_reg result = fs_reg(this, ir->type);
1584 this->result = result;
1585
1586 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1587 fs_reg channel = val;
1588 int swiz = 0;
1589
1590 switch (i) {
1591 case 0:
1592 swiz = ir->mask.x;
1593 break;
1594 case 1:
1595 swiz = ir->mask.y;
1596 break;
1597 case 2:
1598 swiz = ir->mask.z;
1599 break;
1600 case 3:
1601 swiz = ir->mask.w;
1602 break;
1603 }
1604
1605 channel.reg_offset += swiz;
1606 emit(MOV(result, channel));
1607 result.reg_offset++;
1608 }
1609 }
1610
1611 void
1612 fs_visitor::visit(ir_discard *ir)
1613 {
1614 assert(ir->condition == NULL); /* FINISHME */
1615
1616 /* We track our discarded pixels in f0.1. By predicating on it, we can
1617 * update just the flag bits that aren't yet discarded. By emitting a
1618 * CMP of g0 != g0, all our currently executing channels will get turned
1619 * off.
1620 */
1621 fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
1622 BRW_REGISTER_TYPE_UW));
1623 fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
1624 BRW_CONDITIONAL_NZ));
1625 cmp->predicate = BRW_PREDICATE_NORMAL;
1626 cmp->flag_subreg = 1;
1627
1628 if (brw->gen >= 6) {
1629 /* For performance, after a discard, jump to the end of the shader.
1630 * However, many people will do foliage by discarding based on a
1631 * texture's alpha mask, and then continue on to texture with the
1632 * remaining pixels. To avoid trashing the derivatives for those
1633 * texture samples, we'll only jump if all of the pixels in the subspan
1634 * have been discarded.
1635 */
1636 fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
1637 discard_jump->flag_subreg = 1;
1638 discard_jump->predicate = BRW_PREDICATE_ALIGN1_ANY4H;
1639 discard_jump->predicate_inverse = true;
1640 }
1641 }
1642
1643 void
1644 fs_visitor::visit(ir_constant *ir)
1645 {
1646 /* Set this->result to reg at the bottom of the function because some code
1647 * paths will cause this visitor to be applied to other fields. This will
1648 * cause the value stored in this->result to be modified.
1649 *
1650 * Make reg constant so that it doesn't get accidentally modified along the
1651 * way. Yes, I actually had this problem. :(
1652 */
1653 const fs_reg reg(this, ir->type);
1654 fs_reg dst_reg = reg;
1655
1656 if (ir->type->is_array()) {
1657 const unsigned size = type_size(ir->type->fields.array);
1658
1659 for (unsigned i = 0; i < ir->type->length; i++) {
1660 ir->array_elements[i]->accept(this);
1661 fs_reg src_reg = this->result;
1662
1663 dst_reg.type = src_reg.type;
1664 for (unsigned j = 0; j < size; j++) {
1665 emit(MOV(dst_reg, src_reg));
1666 src_reg.reg_offset++;
1667 dst_reg.reg_offset++;
1668 }
1669 }
1670 } else if (ir->type->is_record()) {
1671 foreach_list(node, &ir->components) {
1672 ir_constant *const field = (ir_constant *) node;
1673 const unsigned size = type_size(field->type);
1674
1675 field->accept(this);
1676 fs_reg src_reg = this->result;
1677
1678 dst_reg.type = src_reg.type;
1679 for (unsigned j = 0; j < size; j++) {
1680 emit(MOV(dst_reg, src_reg));
1681 src_reg.reg_offset++;
1682 dst_reg.reg_offset++;
1683 }
1684 }
1685 } else {
1686 const unsigned size = type_size(ir->type);
1687
1688 for (unsigned i = 0; i < size; i++) {
1689 switch (ir->type->base_type) {
1690 case GLSL_TYPE_FLOAT:
1691 emit(MOV(dst_reg, fs_reg(ir->value.f[i])));
1692 break;
1693 case GLSL_TYPE_UINT:
1694 emit(MOV(dst_reg, fs_reg(ir->value.u[i])));
1695 break;
1696 case GLSL_TYPE_INT:
1697 emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
1698 break;
1699 case GLSL_TYPE_BOOL:
1700 emit(MOV(dst_reg, fs_reg((int)ir->value.b[i])));
1701 break;
1702 default:
1703 assert(!"Non-float/uint/int/bool constant");
1704 }
1705 dst_reg.reg_offset++;
1706 }
1707 }
1708
1709 this->result = reg;
1710 }
1711
1712 void
1713 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1714 {
1715 ir_expression *expr = ir->as_expression();
1716
1717 if (expr) {
1718 fs_reg op[2];
1719 fs_inst *inst;
1720
1721 assert(expr->get_num_operands() <= 2);
1722 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1723 assert(expr->operands[i]->type->is_scalar());
1724
1725 expr->operands[i]->accept(this);
1726 op[i] = this->result;
1727
1728 resolve_ud_negate(&op[i]);
1729 }
1730
1731 switch (expr->operation) {
1732 case ir_unop_logic_not:
1733 inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
1734 inst->conditional_mod = BRW_CONDITIONAL_Z;
1735 break;
1736
1737 case ir_binop_logic_xor:
1738 case ir_binop_logic_or:
1739 case ir_binop_logic_and:
1740 goto out;
1741
1742 case ir_unop_f2b:
1743 if (brw->gen >= 6) {
1744 emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
1745 } else {
1746 inst = emit(MOV(reg_null_f, op[0]));
1747 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1748 }
1749 break;
1750
1751 case ir_unop_i2b:
1752 if (brw->gen >= 6) {
1753 emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1754 } else {
1755 inst = emit(MOV(reg_null_d, op[0]));
1756 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1757 }
1758 break;
1759
1760 case ir_binop_greater:
1761 case ir_binop_gequal:
1762 case ir_binop_less:
1763 case ir_binop_lequal:
1764 case ir_binop_equal:
1765 case ir_binop_all_equal:
1766 case ir_binop_nequal:
1767 case ir_binop_any_nequal:
1768 resolve_bool_comparison(expr->operands[0], &op[0]);
1769 resolve_bool_comparison(expr->operands[1], &op[1]);
1770
1771 emit(CMP(reg_null_d, op[0], op[1],
1772 brw_conditional_for_comparison(expr->operation)));
1773 break;
1774
1775 default:
1776 assert(!"not reached");
1777 fail("bad cond code\n");
1778 break;
1779 }
1780 return;
1781 }
1782
1783 out:
1784 ir->accept(this);
1785
1786 fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
1787 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1788 }
1789
1790 /**
1791 * Emit a gen6 IF statement with the comparison folded into the IF
1792 * instruction.
1793 */
1794 void
1795 fs_visitor::emit_if_gen6(ir_if *ir)
1796 {
1797 ir_expression *expr = ir->condition->as_expression();
1798
1799 if (expr) {
1800 fs_reg op[2];
1801 fs_inst *inst;
1802 fs_reg temp;
1803
1804 assert(expr->get_num_operands() <= 2);
1805 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1806 assert(expr->operands[i]->type->is_scalar());
1807
1808 expr->operands[i]->accept(this);
1809 op[i] = this->result;
1810 }
1811
1812 switch (expr->operation) {
1813 case ir_unop_logic_not:
1814 case ir_binop_logic_xor:
1815 case ir_binop_logic_or:
1816 case ir_binop_logic_and:
1817 /* For operations on bool arguments, only the low bit of the bool is
1818 * valid, and the others are undefined. Fall back to the condition
1819 * code path.
1820 */
1821 break;
1822
1823 case ir_unop_f2b:
1824 inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
1825 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1826 return;
1827
1828 case ir_unop_i2b:
1829 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1830 return;
1831
1832 case ir_binop_greater:
1833 case ir_binop_gequal:
1834 case ir_binop_less:
1835 case ir_binop_lequal:
1836 case ir_binop_equal:
1837 case ir_binop_all_equal:
1838 case ir_binop_nequal:
1839 case ir_binop_any_nequal:
1840 resolve_bool_comparison(expr->operands[0], &op[0]);
1841 resolve_bool_comparison(expr->operands[1], &op[1]);
1842
1843 emit(IF(op[0], op[1],
1844 brw_conditional_for_comparison(expr->operation)));
1845 return;
1846 default:
1847 assert(!"not reached");
1848 emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
1849 fail("bad condition\n");
1850 return;
1851 }
1852 }
1853
1854 emit_bool_to_cond_code(ir->condition);
1855 fs_inst *inst = emit(BRW_OPCODE_IF);
1856 inst->predicate = BRW_PREDICATE_NORMAL;
1857 }
1858
1859 /**
1860 * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
1861 *
1862 * Many GLSL shaders contain the following pattern:
1863 *
1864 * x = condition ? foo : bar
1865 *
1866 * The compiler emits an ir_if tree for this, since each subexpression might be
1867 * a complex tree that could have side-effects or short-circuit logic.
1868 *
1869 * However, the common case is to simply select one of two constants or
1870 * variable values---which is exactly what SEL is for. In this case, the
1871 * assembly looks like:
1872 *
1873 * (+f0) IF
1874 * MOV dst src0
1875 * ELSE
1876 * MOV dst src1
1877 * ENDIF
1878 *
1879 * which can be easily translated into:
1880 *
1881 * (+f0) SEL dst src0 src1
1882 *
1883 * If src0 is an immediate value, we promote it to a temporary GRF.
1884 */
1885 void
1886 fs_visitor::try_replace_with_sel()
1887 {
1888 fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
1889 assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
1890
1891 /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
1892 int opcodes[] = {
1893 BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
1894 };
1895
1896 fs_inst *match = (fs_inst *) endif_inst->prev;
1897 for (int i = 0; i < 4; i++) {
1898 if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
1899 return;
1900 match = (fs_inst *) match->prev;
1901 }
1902
1903 /* The opcodes match; it looks like the right sequence of instructions. */
1904 fs_inst *else_mov = (fs_inst *) endif_inst->prev;
1905 fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
1906 fs_inst *if_inst = (fs_inst *) then_mov->prev;
1907
1908 /* Check that the MOVs are the right form. */
1909 if (then_mov->dst.equals(else_mov->dst) &&
1910 !then_mov->is_partial_write() &&
1911 !else_mov->is_partial_write()) {
1912
1913 /* Remove the matched instructions; we'll emit a SEL to replace them. */
1914 while (!if_inst->next->is_tail_sentinel())
1915 if_inst->next->remove();
1916 if_inst->remove();
1917
1918 /* Only the last source register can be a constant, so if the MOV in
1919 * the "then" clause uses a constant, we need to put it in a temporary.
1920 */
1921 fs_reg src0(then_mov->src[0]);
1922 if (src0.file == IMM) {
1923 src0 = fs_reg(this, glsl_type::float_type);
1924 src0.type = then_mov->src[0].type;
1925 emit(MOV(src0, then_mov->src[0]));
1926 }
1927
1928 fs_inst *sel;
1929 if (if_inst->conditional_mod) {
1930 /* Sandybridge-specific IF with embedded comparison */
1931 emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
1932 if_inst->conditional_mod));
1933 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1934 sel->predicate = BRW_PREDICATE_NORMAL;
1935 } else {
1936 /* Separate CMP and IF instructions */
1937 sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
1938 sel->predicate = if_inst->predicate;
1939 sel->predicate_inverse = if_inst->predicate_inverse;
1940 }
1941 }
1942 }
1943
1944 void
1945 fs_visitor::visit(ir_if *ir)
1946 {
1947 if (brw->gen < 6 && dispatch_width == 16) {
1948 fail("Can't support (non-uniform) control flow on 16-wide\n");
1949 }
1950
1951 /* Don't point the annotation at the if statement, because then it plus
1952 * the then and else blocks get printed.
1953 */
1954 this->base_ir = ir->condition;
1955
1956 if (brw->gen == 6) {
1957 emit_if_gen6(ir);
1958 } else {
1959 emit_bool_to_cond_code(ir->condition);
1960
1961 emit(IF(BRW_PREDICATE_NORMAL));
1962 }
1963
1964 foreach_list(node, &ir->then_instructions) {
1965 ir_instruction *ir = (ir_instruction *)node;
1966 this->base_ir = ir;
1967
1968 ir->accept(this);
1969 }
1970
1971 if (!ir->else_instructions.is_empty()) {
1972 emit(BRW_OPCODE_ELSE);
1973
1974 foreach_list(node, &ir->else_instructions) {
1975 ir_instruction *ir = (ir_instruction *)node;
1976 this->base_ir = ir;
1977
1978 ir->accept(this);
1979 }
1980 }
1981
1982 emit(BRW_OPCODE_ENDIF);
1983
1984 try_replace_with_sel();
1985 }
1986
1987 void
1988 fs_visitor::visit(ir_loop *ir)
1989 {
1990 fs_reg counter = reg_undef;
1991
1992 if (brw->gen < 6 && dispatch_width == 16) {
1993 fail("Can't support (non-uniform) control flow on 16-wide\n");
1994 }
1995
1996 if (ir->counter) {
1997 this->base_ir = ir->counter;
1998 ir->counter->accept(this);
1999 counter = *(variable_storage(ir->counter));
2000
2001 if (ir->from) {
2002 this->base_ir = ir->from;
2003 ir->from->accept(this);
2004
2005 emit(MOV(counter, this->result));
2006 }
2007 }
2008
2009 this->base_ir = NULL;
2010 emit(BRW_OPCODE_DO);
2011
2012 if (ir->to) {
2013 this->base_ir = ir->to;
2014 ir->to->accept(this);
2015
2016 emit(CMP(reg_null_d, counter, this->result,
2017 brw_conditional_for_comparison(ir->cmp)));
2018
2019 fs_inst *inst = emit(BRW_OPCODE_BREAK);
2020 inst->predicate = BRW_PREDICATE_NORMAL;
2021 }
2022
2023 foreach_list(node, &ir->body_instructions) {
2024 ir_instruction *ir = (ir_instruction *)node;
2025
2026 this->base_ir = ir;
2027 ir->accept(this);
2028 }
2029
2030 if (ir->increment) {
2031 this->base_ir = ir->increment;
2032 ir->increment->accept(this);
2033 emit(ADD(counter, counter, this->result));
2034 }
2035
2036 this->base_ir = NULL;
2037 emit(BRW_OPCODE_WHILE);
2038 }
2039
2040 void
2041 fs_visitor::visit(ir_loop_jump *ir)
2042 {
2043 switch (ir->mode) {
2044 case ir_loop_jump::jump_break:
2045 emit(BRW_OPCODE_BREAK);
2046 break;
2047 case ir_loop_jump::jump_continue:
2048 emit(BRW_OPCODE_CONTINUE);
2049 break;
2050 }
2051 }
2052
2053 void
2054 fs_visitor::visit(ir_call *ir)
2055 {
2056 assert(!"FINISHME");
2057 }
2058
2059 void
2060 fs_visitor::visit(ir_return *ir)
2061 {
2062 assert(!"FINISHME");
2063 }
2064
2065 void
2066 fs_visitor::visit(ir_function *ir)
2067 {
2068 /* Ignore function bodies other than main() -- we shouldn't see calls to
2069 * them since they should all be inlined before we get to ir_to_mesa.
2070 */
2071 if (strcmp(ir->name, "main") == 0) {
2072 const ir_function_signature *sig;
2073 exec_list empty;
2074
2075 sig = ir->matching_signature(&empty);
2076
2077 assert(sig);
2078
2079 foreach_list(node, &sig->body) {
2080 ir_instruction *ir = (ir_instruction *)node;
2081 this->base_ir = ir;
2082
2083 ir->accept(this);
2084 }
2085 }
2086 }
2087
2088 void
2089 fs_visitor::visit(ir_function_signature *ir)
2090 {
2091 assert(!"not reached");
2092 (void)ir;
2093 }
2094
2095 void
2096 fs_visitor::visit(ir_emit_vertex *)
2097 {
2098 assert(!"not reached");
2099 }
2100
2101 void
2102 fs_visitor::visit(ir_end_primitive *)
2103 {
2104 assert(!"not reached");
2105 }
2106
2107 fs_inst *
2108 fs_visitor::emit(fs_inst inst)
2109 {
2110 fs_inst *list_inst = new(mem_ctx) fs_inst;
2111 *list_inst = inst;
2112 emit(list_inst);
2113 return list_inst;
2114 }
2115
2116 fs_inst *
2117 fs_visitor::emit(fs_inst *inst)
2118 {
2119 if (force_uncompressed_stack > 0)
2120 inst->force_uncompressed = true;
2121 else if (force_sechalf_stack > 0)
2122 inst->force_sechalf = true;
2123
2124 inst->annotation = this->current_annotation;
2125 inst->ir = this->base_ir;
2126
2127 this->instructions.push_tail(inst);
2128
2129 return inst;
2130 }
2131
2132 void
2133 fs_visitor::emit(exec_list list)
2134 {
2135 foreach_list_safe(node, &list) {
2136 fs_inst *inst = (fs_inst *)node;
2137 inst->remove();
2138 emit(inst);
2139 }
2140 }
2141
2142 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
2143 void
2144 fs_visitor::emit_dummy_fs()
2145 {
2146 int reg_width = dispatch_width / 8;
2147
2148 /* Everyone's favorite color. */
2149 emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
2150 emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
2151 emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
2152 emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
2153
2154 fs_inst *write;
2155 write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
2156 write->base_mrf = 2;
2157 write->mlen = 4 * reg_width;
2158 write->eot = true;
2159 }
2160
2161 /* The register location here is relative to the start of the URB
2162 * data. It will get adjusted to be a real location before
2163 * generate_code() time.
2164 */
2165 struct brw_reg
2166 fs_visitor::interp_reg(int location, int channel)
2167 {
2168 int regnr = urb_setup[location] * 2 + channel / 2;
2169 int stride = (channel & 1) * 4;
2170
2171 assert(urb_setup[location] != -1);
2172
2173 return brw_vec1_grf(regnr, stride);
2174 }
2175
2176 /** Emits the interpolation for the varying inputs. */
2177 void
2178 fs_visitor::emit_interpolation_setup_gen4()
2179 {
2180 this->current_annotation = "compute pixel centers";
2181 this->pixel_x = fs_reg(this, glsl_type::uint_type);
2182 this->pixel_y = fs_reg(this, glsl_type::uint_type);
2183 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
2184 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
2185
2186 emit(FS_OPCODE_PIXEL_X, this->pixel_x);
2187 emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
2188
2189 this->current_annotation = "compute pixel deltas from v0";
2190 if (brw->has_pln) {
2191 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2192 fs_reg(this, glsl_type::vec2_type);
2193 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2194 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
2195 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
2196 } else {
2197 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2198 fs_reg(this, glsl_type::float_type);
2199 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
2200 fs_reg(this, glsl_type::float_type);
2201 }
2202 emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2203 this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
2204 emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2205 this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
2206
2207 this->current_annotation = "compute pos.w and 1/pos.w";
2208 /* Compute wpos.w. It's always in our setup, since it's needed to
2209 * interpolate the other attributes.
2210 */
2211 this->wpos_w = fs_reg(this, glsl_type::float_type);
2212 emit(FS_OPCODE_LINTERP, wpos_w,
2213 this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2214 this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
2215 interp_reg(VARYING_SLOT_POS, 3));
2216 /* Compute the pixel 1/W value from wpos.w. */
2217 this->pixel_w = fs_reg(this, glsl_type::float_type);
2218 emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
2219 this->current_annotation = NULL;
2220 }
2221
2222 /** Emits the interpolation for the varying inputs. */
2223 void
2224 fs_visitor::emit_interpolation_setup_gen6()
2225 {
2226 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
2227
2228 /* If the pixel centers end up used, the setup is the same as for gen4. */
2229 this->current_annotation = "compute pixel centers";
2230 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
2231 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
2232 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
2233 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
2234 emit(ADD(int_pixel_x,
2235 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
2236 fs_reg(brw_imm_v(0x10101010))));
2237 emit(ADD(int_pixel_y,
2238 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
2239 fs_reg(brw_imm_v(0x11001100))));
2240
2241 /* As of gen6, we can no longer mix float and int sources. We have
2242 * to turn the integer pixel centers into floats for their actual
2243 * use.
2244 */
2245 this->pixel_x = fs_reg(this, glsl_type::float_type);
2246 this->pixel_y = fs_reg(this, glsl_type::float_type);
2247 emit(MOV(this->pixel_x, int_pixel_x));
2248 emit(MOV(this->pixel_y, int_pixel_y));
2249
2250 this->current_annotation = "compute pos.w";
2251 this->pixel_w = fs_reg(brw_vec8_grf(c->source_w_reg, 0));
2252 this->wpos_w = fs_reg(this, glsl_type::float_type);
2253 emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
2254
2255 for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
2256 uint8_t reg = c->barycentric_coord_reg[i];
2257 this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
2258 this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
2259 }
2260
2261 this->current_annotation = NULL;
2262 }
2263
2264 void
2265 fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
2266 {
2267 int reg_width = dispatch_width / 8;
2268 fs_inst *inst;
2269 fs_reg color = outputs[target];
2270 fs_reg mrf;
2271
2272 /* If there's no color data to be written, skip it. */
2273 if (color.file == BAD_FILE)
2274 return;
2275
2276 color.reg_offset += index;
2277
2278 if (dispatch_width == 8 || brw->gen >= 6) {
2279 /* SIMD8 write looks like:
2280 * m + 0: r0
2281 * m + 1: r1
2282 * m + 2: g0
2283 * m + 3: g1
2284 *
2285 * gen6 SIMD16 DP write looks like:
2286 * m + 0: r0
2287 * m + 1: r1
2288 * m + 2: g0
2289 * m + 3: g1
2290 * m + 4: b0
2291 * m + 5: b1
2292 * m + 6: a0
2293 * m + 7: a1
2294 */
2295 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
2296 color.type),
2297 color));
2298 inst->saturate = c->key.clamp_fragment_color;
2299 } else {
2300 /* pre-gen6 SIMD16 single source DP write looks like:
2301 * m + 0: r0
2302 * m + 1: g0
2303 * m + 2: b0
2304 * m + 3: a0
2305 * m + 4: r1
2306 * m + 5: g1
2307 * m + 6: b1
2308 * m + 7: a1
2309 */
2310 if (brw->has_compr4) {
2311 /* By setting the high bit of the MRF register number, we
2312 * indicate that we want COMPR4 mode - instead of doing the
2313 * usual destination + 1 for the second half we get
2314 * destination + 4.
2315 */
2316 inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
2317 color.type),
2318 color));
2319 inst->saturate = c->key.clamp_fragment_color;
2320 } else {
2321 push_force_uncompressed();
2322 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
2323 color));
2324 inst->saturate = c->key.clamp_fragment_color;
2325 pop_force_uncompressed();
2326
2327 push_force_sechalf();
2328 color.sechalf = true;
2329 inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
2330 color));
2331 inst->saturate = c->key.clamp_fragment_color;
2332 pop_force_sechalf();
2333 color.sechalf = false;
2334 }
2335 }
2336 }
2337
2338 void
2339 fs_visitor::emit_fb_writes()
2340 {
2341 this->current_annotation = "FB write header";
2342 bool header_present = true;
2343 /* We can potentially have a message length of up to 15, so we have to set
2344 * base_mrf to either 0 or 1 in order to fit in m0..m15.
2345 */
2346 int base_mrf = 1;
2347 int nr = base_mrf;
2348 int reg_width = dispatch_width / 8;
2349 bool do_dual_src = this->dual_src_output.file != BAD_FILE;
2350 bool src0_alpha_to_render_target = false;
2351
2352 if (dispatch_width == 16 && do_dual_src) {
2353 fail("GL_ARB_blend_func_extended not yet supported in 16-wide.");
2354 do_dual_src = false;
2355 }
2356
2357 /* From the Sandy Bridge PRM, volume 4, page 198:
2358 *
2359 * "Dispatched Pixel Enables. One bit per pixel indicating
2360 * which pixels were originally enabled when the thread was
2361 * dispatched. This field is only required for the end-of-
2362 * thread message and on all dual-source messages."
2363 */
2364 if (brw->gen >= 6 &&
2365 !this->fp->UsesKill &&
2366 !do_dual_src &&
2367 c->key.nr_color_regions == 1) {
2368 header_present = false;
2369 }
2370
2371 if (header_present) {
2372 src0_alpha_to_render_target = brw->gen >= 6 &&
2373 !do_dual_src &&
2374 c->key.replicate_alpha;
2375 /* m2, m3 header */
2376 nr += 2;
2377 }
2378
2379 if (c->aa_dest_stencil_reg) {
2380 push_force_uncompressed();
2381 emit(MOV(fs_reg(MRF, nr++),
2382 fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0))));
2383 pop_force_uncompressed();
2384 }
2385
2386 /* Reserve space for color. It'll be filled in per MRT below. */
2387 int color_mrf = nr;
2388 nr += 4 * reg_width;
2389 if (do_dual_src)
2390 nr += 4;
2391 if (src0_alpha_to_render_target)
2392 nr += reg_width;
2393
2394 if (c->source_depth_to_render_target) {
2395 if (brw->gen == 6 && dispatch_width == 16) {
2396 /* For outputting oDepth on gen6, SIMD8 writes have to be
2397 * used. This would require 8-wide moves of each half to
2398 * message regs, kind of like pre-gen5 SIMD16 FB writes.
2399 * Just bail on doing so for now.
2400 */
2401 fail("Missing support for simd16 depth writes on gen6\n");
2402 }
2403
2404 if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
2405 /* Hand over gl_FragDepth. */
2406 assert(this->frag_depth.file != BAD_FILE);
2407 emit(MOV(fs_reg(MRF, nr), this->frag_depth));
2408 } else {
2409 /* Pass through the payload depth. */
2410 emit(MOV(fs_reg(MRF, nr),
2411 fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
2412 }
2413 nr += reg_width;
2414 }
2415
2416 if (c->dest_depth_reg) {
2417 emit(MOV(fs_reg(MRF, nr),
2418 fs_reg(brw_vec8_grf(c->dest_depth_reg, 0))));
2419 nr += reg_width;
2420 }
2421
2422 if (do_dual_src) {
2423 fs_reg src0 = this->outputs[0];
2424 fs_reg src1 = this->dual_src_output;
2425
2426 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2427 "FB write src0");
2428 for (int i = 0; i < 4; i++) {
2429 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
2430 src0.reg_offset++;
2431 inst->saturate = c->key.clamp_fragment_color;
2432 }
2433
2434 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2435 "FB write src1");
2436 for (int i = 0; i < 4; i++) {
2437 fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
2438 src1));
2439 src1.reg_offset++;
2440 inst->saturate = c->key.clamp_fragment_color;
2441 }
2442
2443 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2444 emit_shader_time_end();
2445
2446 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2447 inst->target = 0;
2448 inst->base_mrf = base_mrf;
2449 inst->mlen = nr - base_mrf;
2450 inst->eot = true;
2451 inst->header_present = header_present;
2452
2453 c->prog_data.dual_src_blend = true;
2454 this->current_annotation = NULL;
2455 return;
2456 }
2457
2458 for (int target = 0; target < c->key.nr_color_regions; target++) {
2459 this->current_annotation = ralloc_asprintf(this->mem_ctx,
2460 "FB write target %d",
2461 target);
2462 /* If src0_alpha_to_render_target is true, include source zero alpha
2463 * data in RenderTargetWrite message for targets > 0.
2464 */
2465 int write_color_mrf = color_mrf;
2466 if (src0_alpha_to_render_target && target != 0) {
2467 fs_inst *inst;
2468 fs_reg color = outputs[0];
2469 color.reg_offset += 3;
2470
2471 inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
2472 color));
2473 inst->saturate = c->key.clamp_fragment_color;
2474 write_color_mrf = color_mrf + reg_width;
2475 }
2476
2477 for (unsigned i = 0; i < this->output_components[target]; i++)
2478 emit_color_write(target, i, write_color_mrf);
2479
2480 bool eot = false;
2481 if (target == c->key.nr_color_regions - 1) {
2482 eot = true;
2483
2484 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2485 emit_shader_time_end();
2486 }
2487
2488 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2489 inst->target = target;
2490 inst->base_mrf = base_mrf;
2491 if (src0_alpha_to_render_target && target == 0)
2492 inst->mlen = nr - base_mrf - reg_width;
2493 else
2494 inst->mlen = nr - base_mrf;
2495 inst->eot = eot;
2496 inst->header_present = header_present;
2497 }
2498
2499 if (c->key.nr_color_regions == 0) {
2500 /* Even if there's no color buffers enabled, we still need to send
2501 * alpha out the pipeline to our null renderbuffer to support
2502 * alpha-testing, alpha-to-coverage, and so on.
2503 */
2504 emit_color_write(0, 3, color_mrf);
2505
2506 if (INTEL_DEBUG & DEBUG_SHADER_TIME)
2507 emit_shader_time_end();
2508
2509 fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
2510 inst->base_mrf = base_mrf;
2511 inst->mlen = nr - base_mrf;
2512 inst->eot = true;
2513 inst->header_present = header_present;
2514 }
2515
2516 this->current_annotation = NULL;
2517 }
2518
2519 void
2520 fs_visitor::resolve_ud_negate(fs_reg *reg)
2521 {
2522 if (reg->type != BRW_REGISTER_TYPE_UD ||
2523 !reg->negate)
2524 return;
2525
2526 fs_reg temp = fs_reg(this, glsl_type::uint_type);
2527 emit(MOV(temp, *reg));
2528 *reg = temp;
2529 }
2530
2531 void
2532 fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
2533 {
2534 if (rvalue->type != glsl_type::bool_type)
2535 return;
2536
2537 fs_reg temp = fs_reg(this, glsl_type::bool_type);
2538 emit(AND(temp, *reg, fs_reg(1)));
2539 *reg = temp;
2540 }
2541
2542 fs_visitor::fs_visitor(struct brw_context *brw,
2543 struct brw_wm_compile *c,
2544 struct gl_shader_program *shader_prog,
2545 struct gl_fragment_program *fp,
2546 unsigned dispatch_width)
2547 : dispatch_width(dispatch_width)
2548 {
2549 this->c = c;
2550 this->brw = brw;
2551 this->fp = fp;
2552 this->shader_prog = shader_prog;
2553 this->ctx = &brw->ctx;
2554 this->mem_ctx = ralloc_context(NULL);
2555 if (shader_prog)
2556 shader = (struct brw_shader *)
2557 shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
2558 else
2559 shader = NULL;
2560 this->failed = false;
2561 this->variable_ht = hash_table_ctor(0,
2562 hash_table_pointer_hash,
2563 hash_table_pointer_compare);
2564
2565 memset(this->outputs, 0, sizeof(this->outputs));
2566 memset(this->output_components, 0, sizeof(this->output_components));
2567 this->first_non_payload_grf = 0;
2568 this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
2569
2570 this->current_annotation = NULL;
2571 this->base_ir = NULL;
2572
2573 this->virtual_grf_sizes = NULL;
2574 this->virtual_grf_count = 0;
2575 this->virtual_grf_array_size = 0;
2576 this->virtual_grf_start = NULL;
2577 this->virtual_grf_end = NULL;
2578 this->live_intervals_valid = false;
2579
2580 this->params_remap = NULL;
2581 this->nr_params_remap = 0;
2582
2583 this->force_uncompressed_stack = 0;
2584 this->force_sechalf_stack = 0;
2585
2586 memset(&this->param_size, 0, sizeof(this->param_size));
2587 }
2588
2589 fs_visitor::~fs_visitor()
2590 {
2591 ralloc_free(this->mem_ctx);
2592 hash_table_dtor(this->variable_ht);
2593 }